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ulp: document peripherals accessible using RD_REG and WR_REG

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This commit is contained in:
Ivan Grokhotkov 2016-12-16 20:32:34 +08:00
parent 7a527896dc
commit b62f8b42d4
1 changed files with 13 additions and 5 deletions
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18
components/ulp/include/esp32/ulp.h
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@ -49,7 +49,7 @@ extern "C" {
#define RD_REG_PERIPH_RTC_CNTL 0 /*!< Identifier of RTC_CNTL peripheral for RD_REG and WR_REG instructions */ #define RD_REG_PERIPH_RTC_CNTL 0 /*!< Identifier of RTC_CNTL peripheral for RD_REG and WR_REG instructions */
#define RD_REG_PERIPH_RTC_IO 1 /*!< Identifier of RTC_IO peripheral for RD_REG and WR_REG instructions */ #define RD_REG_PERIPH_RTC_IO 1 /*!< Identifier of RTC_IO peripheral for RD_REG and WR_REG instructions */
#define RD_REG_PERIPH_SARADC 2 /*!< Identifier of SARADC peripheral for RD_REG and WR_REG instructions */ #define RD_REG_PERIPH_SENS 2 /*!< Identifier of SARADC peripheral for RD_REG and WR_REG instructions */
#define OPCODE_I2C 3 /*!< Instruction: read/write I2C (not implemented yet) */ #define OPCODE_I2C 3 /*!< Instruction: read/write I2C (not implemented yet) */
@ -277,17 +277,23 @@ _Static_assert(sizeof(ulp_insn_t) == 4, "ULP coprocessor instruction size should
.unused = 0, \ .unused = 0, \
.opcode = OPCODE_HALT } } .opcode = OPCODE_HALT } }
/**
* Map SoC peripheral register to periph_sel field of RD_REG and WR_REG
* instructions.
*
* @param reg peripheral register in RTC_CNTL_, RTC_IO_, SENS_ peripherals.
* @return periph_sel value for the peripheral to which this register belongs.
*/
static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) { static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
uint32_t ret = 3; uint32_t ret = 3;
if (reg < DR_REG_RTCCNTL_BASE) { if (reg < DR_REG_RTCCNTL_BASE) {
assert(0 && "invalid register base"); assert(0 && "invalid register base");
} else if (reg < DR_REG_RTCIO_BASE) { } else if (reg < DR_REG_RTCIO_BASE) {
ret = 0; ret = RD_REG_PERIPH_RTC_CNTL;
} else if (reg < DR_REG_SENS_BASE) { } else if (reg < DR_REG_SENS_BASE) {
ret = 1; ret = RD_REG_PERIPH_RTC_IO;
} else if (reg < DR_REG_RTCMEM0_BASE){ } else if (reg < DR_REG_RTCMEM0_BASE){
ret = 2; ret = RD_REG_PERIPH_SENS;
} else { } else {
assert(0 && "invalid register base"); assert(0 && "invalid register base");
} }
@ -298,6 +304,7 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
* Write literal value to a peripheral register * Write literal value to a peripheral register
* *
* reg[high_bit : low_bit] = val * reg[high_bit : low_bit] = val
* This instruction can access RTC_CNTL_, RTC_IO_, and SENS_ peripheral registers.
*/ */
#define I_WR_REG(reg, low_bit, high_bit, val) {.wr_reg = {\ #define I_WR_REG(reg, low_bit, high_bit, val) {.wr_reg = {\
.addr = reg & 0xff, \ .addr = reg & 0xff, \
@ -311,6 +318,7 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
* Read from peripheral register into R0 * Read from peripheral register into R0
* *
* R0 = reg[high_bit : low_bit] * R0 = reg[high_bit : low_bit]
* This instruction can access RTC_CNTL_, RTC_IO_, and SENS_ peripheral registers.
*/ */
#define I_RD_REG(reg, low_bit, high_bit, val) {.wr_reg = {\ #define I_RD_REG(reg, low_bit, high_bit, val) {.wr_reg = {\
.addr = reg & 0xff, \ .addr = reg & 0xff, \