From b6113eb73b18ee7e826d3c8cf7e72be7d2c91104 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Mon, 3 Sep 2018 18:15:20 +0800 Subject: [PATCH] bootloader: account for load address when mapping cache pages Bootloader used to calculate the number of cache pages assuming that load address was aligned, while in reality load address for DROM and IROM was offset by 0x20 bytes from the start of 64kB page. This caused the bootloader to map one less page if the size of the image was 0x4..0x1c less than a multiple of 64kB. Reported in https://esp32.com/viewtopic.php?f=13&t=6952. --- .../subproject/main/bootloader_start.c | 43 +++++++++++++------ .../include_priv/bootloader_flash.h | 17 ++++++++ .../bootloader_support/src/bootloader_flash.c | 7 ++- 3 files changed, 49 insertions(+), 18 deletions(-) diff --git a/components/bootloader/subproject/main/bootloader_start.c b/components/bootloader/subproject/main/bootloader_start.c index eed030984..9cdddf4c6 100644 --- a/components/bootloader/subproject/main/bootloader_start.c +++ b/components/bootloader/subproject/main/bootloader_start.c @@ -599,6 +599,7 @@ static void set_cache_and_start_app( uint32_t irom_size, uint32_t entry_addr) { + int rc; ESP_LOGD(TAG, "configure drom and irom and start"); Cache_Read_Disable( 0 ); Cache_Flush( 0 ); @@ -610,20 +611,34 @@ static void set_cache_and_start_app( DPORT_PRO_FLASH_MMU_TABLE[i] = DPORT_FLASH_MMU_TABLE_INVALID_VAL; } - uint32_t drom_page_count = (drom_size + 64*1024 - 1) / (64*1024); // round up to 64k - ESP_LOGV(TAG, "d mmu set paddr=%08x vaddr=%08x size=%d n=%d", drom_addr & 0xffff0000, drom_load_addr & 0xffff0000, drom_size, drom_page_count ); - int rc = cache_flash_mmu_set( 0, 0, drom_load_addr & 0xffff0000, drom_addr & 0xffff0000, 64, drom_page_count ); - ESP_LOGV(TAG, "rc=%d", rc ); - rc = cache_flash_mmu_set( 1, 0, drom_load_addr & 0xffff0000, drom_addr & 0xffff0000, 64, drom_page_count ); - ESP_LOGV(TAG, "rc=%d", rc ); - uint32_t irom_page_count = (irom_size + 64*1024 - 1) / (64*1024); // round up to 64k - ESP_LOGV(TAG, "i mmu set paddr=%08x vaddr=%08x size=%d n=%d", irom_addr & 0xffff0000, irom_load_addr & 0xffff0000, irom_size, irom_page_count ); - rc = cache_flash_mmu_set( 0, 0, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count ); - ESP_LOGV(TAG, "rc=%d", rc ); - rc = cache_flash_mmu_set( 1, 0, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count ); - ESP_LOGV(TAG, "rc=%d", rc ); - DPORT_REG_CLR_BIT( DPORT_PRO_CACHE_CTRL1_REG, (DPORT_PRO_CACHE_MASK_IRAM0) | (DPORT_PRO_CACHE_MASK_IRAM1 & 0) | (DPORT_PRO_CACHE_MASK_IROM0 & 0) | DPORT_PRO_CACHE_MASK_DROM0 | DPORT_PRO_CACHE_MASK_DRAM1 ); - DPORT_REG_CLR_BIT( DPORT_APP_CACHE_CTRL1_REG, (DPORT_APP_CACHE_MASK_IRAM0) | (DPORT_APP_CACHE_MASK_IRAM1 & 0) | (DPORT_APP_CACHE_MASK_IROM0 & 0) | DPORT_APP_CACHE_MASK_DROM0 | DPORT_APP_CACHE_MASK_DRAM1 ); + uint32_t drom_load_addr_aligned = drom_load_addr & MMU_FLASH_MASK; + uint32_t drom_page_count = bootloader_cache_pages_to_map(drom_size, drom_load_addr); + ESP_LOGV(TAG, "d mmu set paddr=%08x vaddr=%08x size=%d n=%d", + drom_addr & MMU_FLASH_MASK, drom_load_addr_aligned, drom_size, drom_page_count); + rc = cache_flash_mmu_set(0, 0, drom_load_addr_aligned, drom_addr & MMU_FLASH_MASK, 64, drom_page_count); + ESP_LOGV(TAG, "rc=%d", rc); + rc = cache_flash_mmu_set(1, 0, drom_load_addr_aligned, drom_addr & MMU_FLASH_MASK, 64, drom_page_count); + ESP_LOGV(TAG, "rc=%d", rc); + + uint32_t irom_load_addr_aligned = irom_load_addr & MMU_FLASH_MASK; + uint32_t irom_page_count = bootloader_cache_pages_to_map(irom_size, irom_load_addr); + ESP_LOGV(TAG, "i mmu set paddr=%08x vaddr=%08x size=%d n=%d", + irom_addr & MMU_FLASH_MASK, irom_load_addr_aligned, irom_size, irom_page_count); + rc = cache_flash_mmu_set(0, 0, irom_load_addr_aligned, irom_addr & MMU_FLASH_MASK, 64, irom_page_count); + ESP_LOGV(TAG, "rc=%d", rc); + rc = cache_flash_mmu_set(1, 0, irom_load_addr_aligned, irom_addr & MMU_FLASH_MASK, 64, irom_page_count); + ESP_LOGV(TAG, "rc=%d", rc); + + DPORT_REG_CLR_BIT( DPORT_PRO_CACHE_CTRL1_REG, + (DPORT_PRO_CACHE_MASK_IRAM0) | (DPORT_PRO_CACHE_MASK_IRAM1 & 0) | + (DPORT_PRO_CACHE_MASK_IROM0 & 0) | DPORT_PRO_CACHE_MASK_DROM0 | + DPORT_PRO_CACHE_MASK_DRAM1 ); + + DPORT_REG_CLR_BIT( DPORT_APP_CACHE_CTRL1_REG, + (DPORT_APP_CACHE_MASK_IRAM0) | (DPORT_APP_CACHE_MASK_IRAM1 & 0) | + (DPORT_APP_CACHE_MASK_IROM0 & 0) | DPORT_APP_CACHE_MASK_DROM0 | + DPORT_APP_CACHE_MASK_DRAM1 ); + Cache_Read_Enable( 0 ); // Application will need to do Cache_Flush(1) and Cache_Read_Enable(1) diff --git a/components/bootloader_support/include_priv/bootloader_flash.h b/components/bootloader_support/include_priv/bootloader_flash.h index 763136e03..9f19b4b69 100644 --- a/components/bootloader_support/include_priv/bootloader_flash.h +++ b/components/bootloader_support/include_priv/bootloader_flash.h @@ -100,4 +100,21 @@ esp_err_t bootloader_flash_write(size_t dest_addr, void *src, size_t size, bool */ esp_err_t bootloader_flash_erase_sector(size_t sector); +/* Cache MMU block size */ +#define MMU_BLOCK_SIZE 0x00010000 + +/* Cache MMU address mask (MMU tables ignore bits which are zero) */ +#define MMU_FLASH_MASK (~(MMU_BLOCK_SIZE - 1)) + +/** + * @brief Calculate the number of cache pages to map + * @param size size of data to map + * @param vaddr virtual address where data will be mapped + * @return number of cache MMU pages required to do the mapping + */ +static inline uint32_t bootloader_cache_pages_to_map(uint32_t size, uint32_t vaddr) +{ + return (size + (vaddr - (vaddr & MMU_FLASH_MASK)) + MMU_BLOCK_SIZE - 1) / MMU_BLOCK_SIZE; +} + #endif diff --git a/components/bootloader_support/src/bootloader_flash.c b/components/bootloader_support/src/bootloader_flash.c index a7a6f6e61..1c45890f0 100644 --- a/components/bootloader_support/src/bootloader_flash.c +++ b/components/bootloader_support/src/bootloader_flash.c @@ -86,8 +86,6 @@ static const char *TAG = "bootloader_flash"; */ #define MMU_BLOCK0_VADDR 0x3f400000 #define MMU_BLOCK50_VADDR 0x3f720000 -#define MMU_FLASH_MASK 0xffff0000 -#define MMU_BLOCK_SIZE 0x00010000 static bool mapped; @@ -107,10 +105,11 @@ const void *bootloader_mmap(uint32_t src_addr, uint32_t size) } uint32_t src_addr_aligned = src_addr & MMU_FLASH_MASK; - uint32_t count = (size + (src_addr - src_addr_aligned) + 0xffff) / MMU_BLOCK_SIZE; + uint32_t count = bootloader_cache_pages_to_map(size, src_addr); Cache_Read_Disable(0); Cache_Flush(0); - ESP_LOGD(TAG, "mmu set paddr=%08x count=%d", src_addr_aligned, count ); + ESP_LOGD(TAG, "mmu set paddr=%08x count=%d size=%x src_addr=%x src_addr_aligned=%x", + src_addr & MMU_FLASH_MASK, count, size, src_addr, src_addr_aligned ); int e = cache_flash_mmu_set(0, 0, MMU_BLOCK0_VADDR, src_addr_aligned, 64, count); if (e != 0) { ESP_LOGE(TAG, "cache_flash_mmu_set failed: %d\n", e);