soc/rtc_clk: don’t clear DPORT_CPUPERIOD_SEL when switching to XTAL
This is not necessary since RTC_CNTL_SOC_CLK_SEL is set before this.
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1 changed files with 0 additions and 2 deletions
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@ -395,7 +395,6 @@ void rtc_clk_cpu_freq_to_xtal(int freq, int div)
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REG_WRITE(APB_CTRL_XTAL_TICK_CONF_REG, freq * MHZ / REF_CLK_FREQ - 1);
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REG_WRITE(APB_CTRL_XTAL_TICK_CONF_REG, freq * MHZ / REF_CLK_FREQ - 1);
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/* switch clock source */
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/* switch clock source */
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REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_XTL);
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REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_XTL);
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DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, 0); /* clear DPORT_CPUPERIOD_SEL */
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rtc_clk_apb_freq_update(freq * MHZ);
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rtc_clk_apb_freq_update(freq * MHZ);
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/* lower the voltage */
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/* lower the voltage */
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if (freq <= 2) {
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if (freq <= 2) {
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@ -411,7 +410,6 @@ static void rtc_clk_cpu_freq_to_8m()
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REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL);
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REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL);
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REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, 0);
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REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, 0);
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REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_8M);
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REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_8M);
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DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, 0); // clear DPORT_CPUPERIOD_SEL
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rtc_clk_apb_freq_update(RTC_FAST_CLK_FREQ_8M);
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rtc_clk_apb_freq_update(RTC_FAST_CLK_FREQ_8M);
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}
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}
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