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Merge branch 'bugfix/fix_i2s_comm_format_unclear_description_bug' into 'master'

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Bugfix(I2S):  Fix i2s_comm_format_t configuration parameter does not match the TRM bug

Closes IDFGH-3040, IDFGH-2913, IDFGH-578, IDFGH-2408, and IDFGH-3117

See merge request espressif/esp-idf!8339
This commit is contained in:
Michael (XIAO Xufeng) 2020-05-25 15:00:10 +08:00
parent b82d91fc39 b35d9002f3
commit b3587ff88c
15 changed files with 591 additions and 523 deletions
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33
components/driver/i2s.c
View file

@ -25,6 +25,7 @@
#include "esp32/rom/lldesc.h"
#include "driver/gpio.h"
#include "driver/i2s.h"
#if SOC_I2S_SUPPORTS_ADC_DAC
#include "driver/dac.h"
#include "hal/i2s_hal.h"
@ -351,10 +352,9 @@ esp_err_t i2s_set_clk(i2s_port_t i2s_num, uint32_t rate, i2s_bits_per_sample_t b
if (bits != p_i2s_obj[i2s_num]->bits_per_sample) {
p_i2s_obj[i2s_num]->bits_per_sample = bits;
p_i2s_obj[i2s_num]->bytes_per_sample = p_i2s_obj[i2s_num]->bits_per_sample / 8;
// Round bytes_per_sample up to next multiple of 16 bits
int halfwords_per_sample = (p_i2s_obj[i2s_num]->bits_per_sample + 15) / 16;
int halfwords_per_sample = (bits + 15) / 16;
p_i2s_obj[i2s_num]->bytes_per_sample = halfwords_per_sample * 2;
// Because limited of DMA buffer is 4092 bytes
@ -827,18 +827,31 @@ esp_err_t i2s_set_pdm_rx_down_sample(i2s_port_t i2s_num, i2s_pdm_dsr_t dsr)
}
#endif
static esp_err_t i2s_check_cfg_static(i2s_port_t i2s_num, const i2s_config_t *cfg)
{
#if SOC_I2S_SUPPORTS_ADC_DAC
//We only check if the I2S number is invalid when set to build in ADC and DAC mode.
I2S_CHECK(!((cfg->mode & I2S_MODE_ADC_BUILT_IN) && (i2s_num != I2S_NUM_0)), "I2S ADC built-in only support on I2S0", ESP_ERR_INVALID_ARG);
I2S_CHECK(!((cfg->mode & I2S_MODE_DAC_BUILT_IN) && (i2s_num != I2S_NUM_0)), "I2S DAC built-in only support on I2S0", ESP_ERR_INVALID_ARG);
return ESP_OK;
#endif
#if SOC_I2S_SUPPORTS_PDM
//We only check if the I2S number is invalid when set to PDM mode.
I2S_CHECK(!((cfg->mode & I2S_MODE_PDM) && (i2s_num != I2S_NUM_0)), "I2S DAC PDM only support on I2S0", ESP_ERR_INVALID_ARG);
return ESP_OK;
#endif
I2S_CHECK(cfg->communication_format && (cfg->communication_format < I2S_COMM_FORMAT_STAND_MAX), "invalid communication formats", ESP_ERR_INVALID_ARG);
I2S_CHECK(!((cfg->communication_format & I2S_COMM_FORMAT_STAND_MSB) && (cfg->communication_format & I2S_COMM_FORMAT_STAND_PCM_LONG)), "multiple communication formats specified", ESP_ERR_INVALID_ARG);
return ESP_OK;
}
static esp_err_t i2s_param_config(i2s_port_t i2s_num, const i2s_config_t *i2s_config)
{
I2S_CHECK((i2s_num < I2S_NUM_MAX), "i2s_num error", ESP_ERR_INVALID_ARG);
I2S_CHECK((i2s_config), "param null", ESP_ERR_INVALID_ARG);
#if SOC_I2S_SUPPORTS_ADC_DAC
I2S_CHECK(!((i2s_config->mode & I2S_MODE_ADC_BUILT_IN) && (i2s_num != I2S_NUM_0)), "I2S ADC built-in only support on I2S0", ESP_ERR_INVALID_ARG);
I2S_CHECK(!((i2s_config->mode & I2S_MODE_DAC_BUILT_IN) && (i2s_num != I2S_NUM_0)), "I2S DAC built-in only support on I2S0", ESP_ERR_INVALID_ARG);
#endif
I2S_CHECK(((i2s_config->communication_format & I2S_COMM_FORMAT_I2S) || (i2s_config->communication_format & I2S_COMM_FORMAT_PCM)), "I2S communication format invalid.", ESP_ERR_INVALID_ARG);
#if SOC_I2S_SUPPORTS_PDM
I2S_CHECK(!((i2s_config->mode & I2S_MODE_PDM) && (i2s_num != I2S_NUM_0)), "I2S DAC PDM only support on I2S0", ESP_ERR_INVALID_ARG);
#endif
I2S_CHECK((i2s_check_cfg_static(i2s_num, i2s_config) == ESP_OK), "param check error", ESP_ERR_INVALID_ARG);
periph_module_enable(i2s_periph_signal[i2s_num].module);
#if SOC_I2S_SUPPORTS_ADC_DAC

6
components/driver/include/driver/i2s.h
View file

@ -1,4 +1,4 @@
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -33,6 +33,8 @@
extern "C" {
#endif
#define I2S_PIN_NO_CHANGE (-1) /*!< Use in i2s_pin_config_t for pins which should not be changed */
typedef intr_handle_t i2s_isr_handle_t;
/**
@ -194,7 +196,7 @@ esp_err_t i2s_write_expand(i2s_port_t i2s_num, const void *src, size_t size, siz
*
* @param ticks_to_wait RX buffer wait timeout in RTOS ticks. If this many ticks pass without bytes becoming available in the DMA receive buffer, then the function will return (note that if data is read from the DMA buffer in pieces, the overall operation may still take longer than this timeout.) Pass portMAX_DELAY for no timeout.
*
* @note If the built-in ADC mode is enabled, we should call i2s_adc_start and i2s_adc_stop around the whole reading process,
* @note If the built-in ADC mode is enabled, we should call i2s_adc_enable and i2s_adc_disable around the whole reading process,
* to prevent the data getting corrupted.
*
* @return

1
components/driver/test/adc_dma_test/test_esp32.c
View file

@ -79,7 +79,6 @@ static void example_i2s_init(void)
.mode = I2S_MODE_MASTER | I2S_MODE_RX | I2S_MODE_TX | I2S_MODE_DAC_BUILT_IN | I2S_MODE_ADC_BUILT_IN,
.sample_rate = EXAMPLE_I2S_SAMPLE_RATE,
.bits_per_sample = EXAMPLE_I2S_SAMPLE_BITS,
.communication_format = I2S_COMM_FORMAT_PCM,
.channel_format = EXAMPLE_I2S_FORMAT,
.intr_alloc_flags = 0,
.dma_buf_count = 2,

1
components/driver/test/dac_dma_test/test_esp32.c
View file

@ -75,7 +75,6 @@ static void example_i2s_init(void)
.mode = I2S_MODE_MASTER | I2S_MODE_RX | I2S_MODE_TX | I2S_MODE_DAC_BUILT_IN | I2S_MODE_ADC_BUILT_IN,
.sample_rate = EXAMPLE_I2S_SAMPLE_RATE,
.bits_per_sample = EXAMPLE_I2S_SAMPLE_BITS,
.communication_format = I2S_COMM_FORMAT_PCM,
.channel_format = EXAMPLE_I2S_FORMAT,
.intr_alloc_flags = 0,
.dma_buf_count = 2,

17
components/driver/test/test_i2s.c
View file

@ -102,7 +102,7 @@ TEST_CASE("I2S basic driver install, uninstall, set pin test", "[i2s]")
.sample_rate = SAMPLE_RATE,
.bits_per_sample = SAMPLE_BITS,
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
.communication_format = I2S_COMM_FORMAT_I2S | I2S_COMM_FORMAT_I2S_MSB,
.communication_format = I2S_COMM_FORMAT_STAND_I2S,
.dma_buf_count = 6,
.dma_buf_len = 60,
.use_apll = 0,
@ -147,7 +147,7 @@ TEST_CASE("I2S Loopback test(master tx and rx)", "[i2s]")
.sample_rate = SAMPLE_RATE,
.bits_per_sample = SAMPLE_BITS,
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
.communication_format = I2S_COMM_FORMAT_I2S | I2S_COMM_FORMAT_I2S_MSB,
.communication_format = I2S_COMM_FORMAT_STAND_I2S,
.dma_buf_count = 6,
.dma_buf_len = 100,
.use_apll = 0,
@ -212,7 +212,6 @@ TEST_CASE("I2S adc test", "[i2s]")
.mode = I2S_MODE_MASTER | I2S_MODE_RX | I2S_MODE_ADC_BUILT_IN,
.sample_rate = SAMPLE_RATE,
.bits_per_sample = SAMPLE_BITS,
.communication_format = I2S_COMM_FORMAT_PCM,
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
.intr_alloc_flags = 0,
.dma_buf_count = 2,
@ -268,7 +267,7 @@ TEST_CASE("I2S write and read test(master tx and slave rx)", "[i2s]")
.sample_rate = SAMPLE_RATE,
.bits_per_sample = SAMPLE_BITS,
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
.communication_format = I2S_COMM_FORMAT_I2S | I2S_COMM_FORMAT_I2S_MSB,
.communication_format = I2S_COMM_FORMAT_STAND_I2S,
.dma_buf_count = 6,
.dma_buf_len = 100,
.use_apll = 0,
@ -290,7 +289,7 @@ TEST_CASE("I2S write and read test(master tx and slave rx)", "[i2s]")
.sample_rate = SAMPLE_RATE,
.bits_per_sample = SAMPLE_BITS,
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
.communication_format = I2S_COMM_FORMAT_I2S | I2S_COMM_FORMAT_I2S_MSB,
.communication_format = I2S_COMM_FORMAT_STAND_I2S,
.dma_buf_count = 6,
.dma_buf_len = 100,
.use_apll = 0,
@ -353,7 +352,7 @@ TEST_CASE("I2S write and read test(master rx and slave tx)", "[i2s]")
.sample_rate = SAMPLE_RATE,
.bits_per_sample = SAMPLE_BITS,
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
.communication_format = I2S_COMM_FORMAT_I2S | I2S_COMM_FORMAT_I2S_MSB,
.communication_format = I2S_COMM_FORMAT_STAND_I2S,
.dma_buf_count = 6,
.dma_buf_len = 100,
.use_apll = 1,
@ -375,7 +374,7 @@ TEST_CASE("I2S write and read test(master rx and slave tx)", "[i2s]")
.sample_rate = SAMPLE_RATE,
.bits_per_sample = SAMPLE_BITS,
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT, //2-channels
.communication_format = I2S_COMM_FORMAT_I2S | I2S_COMM_FORMAT_I2S_MSB,
.communication_format = I2S_COMM_FORMAT_STAND_I2S,
.dma_buf_count = 6,
.dma_buf_len = 100,
.use_apll = 1,
@ -438,7 +437,7 @@ TEST_CASE("I2S memory leaking test", "[i2s]")
.sample_rate = SAMPLE_RATE,
.bits_per_sample = SAMPLE_BITS,
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
.communication_format = I2S_COMM_FORMAT_I2S | I2S_COMM_FORMAT_I2S_MSB,
.communication_format = I2S_COMM_FORMAT_STAND_I2S,
.dma_buf_count = 6,
.dma_buf_len = 100,
.use_apll = 0,
@ -485,7 +484,7 @@ TEST_CASE("I2S APLL clock variation test", "[i2s]")
.sample_rate = SAMPLE_RATE,
.bits_per_sample = SAMPLE_BITS,
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
.communication_format = I2S_COMM_FORMAT_I2S,
.communication_format = I2S_COMM_FORMAT_STAND_I2S,
.dma_buf_count = 6,
.dma_buf_len = 60,
.use_apll = true,

78
components/soc/include/hal/i2s_types.h
View file

@ -1,4 +1,4 @@
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -34,9 +34,6 @@ typedef enum {
I2S_NUM_MAX, /*!< I2S port max */
} i2s_port_t;
#define I2S_PIN_NO_CHANGE (-1) /*!< Use in i2s_pin_config_t for pins which should not be changed */
/**
* @brief I2S bit width per sample.
*
@ -62,14 +59,21 @@ typedef enum {
*
*/
typedef enum {
I2S_COMM_FORMAT_I2S = 0x01, /*!< I2S communication format I2S*/
I2S_COMM_FORMAT_I2S_MSB = 0x02, /*!< I2S format MSB*/
I2S_COMM_FORMAT_I2S_LSB = 0x04, /*!< I2S format LSB*/
I2S_COMM_FORMAT_PCM = 0x08, /*!< I2S communication format PCM*/
I2S_COMM_FORMAT_PCM_SHORT = 0x10, /*!< PCM Short*/
I2S_COMM_FORMAT_PCM_LONG = 0x20, /*!< PCM Long*/
} i2s_comm_format_t;
// In order to keep compatibility, remain the old definitions and introduce new definitions,
I2S_COMM_FORMAT_STAND_I2S = 0X01, /*!< I2S communication I2S Philips standard, data launch at second BCK*/
I2S_COMM_FORMAT_STAND_MSB = 0X03, /*!< I2S communication MSB alignment standard, data launch at first BCK*/
I2S_COMM_FORMAT_STAND_PCM_SHORT = 0x04, /*!< PCM Short standard*/
I2S_COMM_FORMAT_STAND_PCM_LONG = 0x0C, /*!< PCM Long standard*/
I2S_COMM_FORMAT_STAND_MAX, /*!< standard max*/
//old definition will be removed in the future.
I2S_COMM_FORMAT_I2S __attribute__((deprecated)) = 0x01, /*!< I2S communication format I2S, correspond to `I2S_COMM_FORMAT_STAND_I2S`*/
I2S_COMM_FORMAT_I2S_MSB __attribute__((deprecated)) = 0x01, /*!< I2S format MSB, (I2S_COMM_FORMAT_I2S |I2S_COMM_FORMAT_I2S_MSB) correspond to `I2S_COMM_FORMAT_STAND_I2S`*/
I2S_COMM_FORMAT_I2S_LSB __attribute__((deprecated)) = 0x02, /*!< I2S format LSB, (I2S_COMM_FORMAT_I2S |I2S_COMM_FORMAT_I2S_LSB) correspond to `I2S_COMM_FORMAT_STAND_MSB`*/
I2S_COMM_FORMAT_PCM __attribute__((deprecated)) = 0x04, /*!< I2S communication format PCM, correspond to `I2S_COMM_FORMAT_STAND_PCM_SHORT`*/
I2S_COMM_FORMAT_PCM_SHORT __attribute__((deprecated)) = 0x04, /*!< PCM Short, (I2S_COMM_FORMAT_PCM | I2S_COMM_FORMAT_PCM_SHORT) correspond to `I2S_COMM_FORMAT_STAND_PCM_SHORT`*/
I2S_COMM_FORMAT_PCM_LONG __attribute__((deprecated)) = 0x08, /*!< PCM Long, (I2S_COMM_FORMAT_PCM | I2S_COMM_FORMAT_PCM_LONG) correspond to `I2S_COMM_FORMAT_STAND_PCM_LONG`*/
} i2s_comm_format_t;
/**
* @brief I2S channel format type
@ -82,26 +86,6 @@ typedef enum {
I2S_CHANNEL_FMT_ONLY_LEFT,
} i2s_channel_fmt_t;
#if SOC_I2S_SUPPORTS_PDM
/**
* @brief PDM sample rate ratio, measured in Hz.
*
*/
typedef enum {
PDM_SAMPLE_RATE_RATIO_64,
PDM_SAMPLE_RATE_RATIO_128,
} pdm_sample_rate_ratio_t;
/**
* @brief PDM PCM convter enable/disable.
*
*/
typedef enum {
PDM_PCM_CONV_ENABLE,
PDM_PCM_CONV_DISABLE,
} pdm_pcm_conv_t;
#endif
/**
* @brief I2S Mode, defaut is I2S_MODE_MASTER | I2S_MODE_TX
*
@ -109,19 +93,29 @@ typedef enum {
*
*/
typedef enum {
I2S_MODE_MASTER = 1,
I2S_MODE_SLAVE = 2,
I2S_MODE_TX = 4,
I2S_MODE_RX = 8,
I2S_MODE_MASTER = 1, /*!< Master mode*/
I2S_MODE_SLAVE = 2, /*!< Slave mode*/
I2S_MODE_TX = 4, /*!< TX mode*/
I2S_MODE_RX = 8, /*!< RX mode*/
#if SOC_I2S_SUPPORTS_ADC_DAC
I2S_MODE_DAC_BUILT_IN = 16, /*!< Output I2S data to built-in DAC, no matter the data format is 16bit or 32 bit, the DAC module will only take the 8bits from MSB*/
I2S_MODE_ADC_BUILT_IN = 32, /*!< Input I2S data from built-in ADC, each data can be 12-bit width at most*/
#endif
#if SOC_I2S_SUPPORTS_PDM
I2S_MODE_PDM = 64,
I2S_MODE_PDM = 64, /*!< PDM mode*/
#endif
} i2s_mode_t;
/**
* @brief I2S source clock
*
*/
typedef enum {
I2S_CLK_D2CLK = 0, /*!< Clock from PLL_D2_CLK(160M)*/
I2S_CLK_APLL, /*!< Clock from APLL*/
} i2s_clock_src_t;
/**
* @brief I2S configuration parameters for i2s_param_config function
*
@ -193,12 +187,16 @@ typedef enum {
I2S_PDM_DSR_16S, /*!< downsampling number is 16 for PDM RX mode*/
I2S_PDM_DSR_MAX,
} i2s_pdm_dsr_t;
#endif
/**
* @brief PDM PCM convter enable/disable.
*
*/
typedef enum {
I2S_CLK_D2CLK = 0,
I2S_CLK_APLL,
} i2s_clock_src_t;
PDM_PCM_CONV_ENABLE, /*!< Enable PDM PCM convert*/
PDM_PCM_CONV_DISABLE, /*!< Disable PDM PCM convert*/
} pdm_pcm_conv_t;
#endif
#ifdef __cplusplus

524
components/soc/soc/esp32s2/include/soc/i2s_struct.h
View file

@ -1,9 +1,9 @@
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
@ -22,33 +22,33 @@ typedef volatile struct {
uint32_t reserved_4;
union {
struct {
uint32_t tx_reset: 1; /*Set this bit to reset transmitter*/
uint32_t rx_reset: 1; /*Set this bit to reset receiver*/
uint32_t tx_fifo_reset: 1; /*Set this bit to reset txFIFO*/
uint32_t rx_fifo_reset: 1; /*Set this bit to reset rxFIFO*/
uint32_t tx_start: 1; /*Set this bit to start transmitting data*/
uint32_t rx_start: 1; /*Set this bit to start receiving data*/
uint32_t tx_slave_mod: 1; /*Set this bit to enable slave transmitter mode*/
uint32_t rx_slave_mod: 1; /*Set this bit to enable slave receiver mode*/
uint32_t tx_right_first: 1; /*Set this bit to transmit right channel data first*/
uint32_t rx_right_first: 1; /*Set this bit to receive right channel data first*/
uint32_t tx_msb_shift: 1; /*Set this bit to enable transmitter in Phillips standard mode*/
uint32_t rx_msb_shift: 1; /*Set this bit to enable receiver in Phillips standard mode*/
uint32_t tx_short_sync: 1; /*Set this bit to enable transmitter in PCM standard mode*/
uint32_t rx_short_sync: 1; /*Set this bit to enable receiver in PCM standard mode*/
uint32_t tx_mono: 1; /*Set this bit to enable transmitter in mono mode*/
uint32_t rx_mono: 1; /*Set this bit to enable receiver in mono mode*/
uint32_t tx_msb_right: 1; /*Set this bit to place right channel data at the MSB in the transmit FIFO.*/
uint32_t rx_msb_right: 1; /*Set this bit to place right channel data at the MSB in the receive FIFO.*/
uint32_t tx_lsb_first_dma: 1; /*1:the data in DMA/APB transform from low bits*/
uint32_t rx_lsb_first_dma: 1; /*1:the data in DMA/APB transform from low bits*/
uint32_t sig_loopback: 1; /*Enable signal loopback mode with transmitter module and receiver module sharing the same WS and BCK signals.*/
uint32_t tx_fifo_reset_st: 1; /*1:i2s_tx_fifo reset is not ok 0:i2s_tx_fifo_reset is ok*/
uint32_t rx_fifo_reset_st: 1; /*1:i2s_rx_fifo_reset is not ok 0:i2s_rx_fifo reset is ok*/
uint32_t tx_reset_st: 1; /*1: i2s_tx_reset is not ok 0: i2s_tx_reset is ok*/
uint32_t tx_dma_equal: 1; /*1:data in left channel is equal to data in right channel*/
uint32_t rx_dma_equal: 1; /*1:data in left channel is equal to data in right channel*/
uint32_t pre_req_en: 1; /*set this bit to enable i2s to prepare data earlier*/
uint32_t tx_reset: 1; /*Set this bit to reset transmitter*/
uint32_t rx_reset: 1; /*Set this bit to reset receiver*/
uint32_t tx_fifo_reset: 1; /*Set this bit to reset txFIFO*/
uint32_t rx_fifo_reset: 1; /*Set this bit to reset rxFIFO*/
uint32_t tx_start: 1; /*Set this bit to start transmitting data*/
uint32_t rx_start: 1; /*Set this bit to start receiving data*/
uint32_t tx_slave_mod: 1; /*Set this bit to enable slave transmitter mode*/
uint32_t rx_slave_mod: 1; /*Set this bit to enable slave receiver mode*/
uint32_t tx_right_first: 1; /*Set this bit to transmit right channel data first*/
uint32_t rx_right_first: 1; /*Set this bit to receive right channel data first*/
uint32_t tx_msb_shift: 1; /*Set this bit to enable transmitter in Phillips standard mode*/
uint32_t rx_msb_shift: 1; /*Set this bit to enable receiver in Phillips standard mode*/
uint32_t tx_short_sync: 1; /*Set this bit to enable transmitter in PCM standard mode*/
uint32_t rx_short_sync: 1; /*Set this bit to enable receiver in PCM standard mode*/
uint32_t tx_mono: 1; /*Set this bit to enable transmitter in mono mode*/
uint32_t rx_mono: 1; /*Set this bit to enable receiver in mono mode*/
uint32_t tx_msb_right: 1; /*Set this bit to place right channel data at the MSB in the transmit FIFO.*/
uint32_t rx_msb_right: 1; /*Set this bit to place right channel data at the MSB in the receive FIFO.*/
uint32_t tx_lsb_first_dma: 1; /*1:the data in DMA/APB transform from low bits*/
uint32_t rx_lsb_first_dma: 1; /*1:the data in DMA/APB transform from low bits*/
uint32_t sig_loopback: 1; /*Enable signal loopback mode with transmitter module and receiver module sharing the same WS and BCK signals.*/
uint32_t tx_fifo_reset_st: 1; /*1:i2s_tx_fifo reset is not ok 0:i2s_tx_fifo_reset is ok*/
uint32_t rx_fifo_reset_st: 1; /*1:i2s_rx_fifo_reset is not ok 0:i2s_rx_fifo reset is ok*/
uint32_t tx_reset_st: 1; /*1: i2s_tx_reset is not ok 0: i2s_tx_reset is ok*/
uint32_t tx_dma_equal: 1; /*1:data in left channel is equal to data in right channel*/
uint32_t rx_dma_equal: 1; /*1:data in left channel is equal to data in right channel*/
uint32_t pre_req_en: 1; /*set this bit to enable i2s to prepare data earlier*/
uint32_t tx_big_endian: 1;
uint32_t rx_big_endian: 1;
uint32_t rx_reset_st: 1;
@ -58,167 +58,171 @@ typedef volatile struct {
} conf;
union {
struct {
uint32_t rx_take_data: 1; /*The raw interrupt status bit for the i2s_rx_take_data_int interrupt*/
uint32_t tx_put_data: 1; /*The raw interrupt status bit for the i2s_tx_put_data_int interrupt*/
uint32_t rx_wfull: 1; /*The raw interrupt status bit for the i2s_rx_wfull_int interrupt*/
uint32_t rx_rempty: 1; /*The raw interrupt status bit for the i2s_rx_rempty_int interrupt*/
uint32_t tx_wfull: 1; /*The raw interrupt status bit for the i2s_tx_wfull_int interrupt*/
uint32_t tx_rempty: 1; /*The raw interrupt status bit for the i2s_tx_rempty_int interrupt*/
uint32_t rx_hung: 1; /*The raw interrupt status bit for the i2s_rx_hung_int interrupt*/
uint32_t tx_hung: 1; /*The raw interrupt status bit for the i2s_tx_hung_int interrupt*/
uint32_t in_done: 1; /*The raw interrupt status bit for the i2s_in_done_int interrupt*/
uint32_t in_suc_eof: 1; /*The raw interrupt status bit for the i2s_in_suc_eof_int interrupt*/
uint32_t in_err_eof: 1; /*don't use*/
uint32_t out_done: 1; /*The raw interrupt status bit for the i2s_out_done_int interrupt*/
uint32_t out_eof: 1; /*The raw interrupt status bit for the i2s_out_eof_int interrupt*/
uint32_t in_dscr_err: 1; /*The raw interrupt status bit for the i2s_in_dscr_err_int interrupt*/
uint32_t out_dscr_err: 1; /*The raw interrupt status bit for the i2s_out_dscr_err_int interrupt*/
uint32_t in_dscr_empty: 1; /*The raw interrupt status bit for the i2s_in_dscr_empty_int interrupt*/
uint32_t out_total_eof: 1; /*The raw interrupt status bit for the i2s_out_total_eof_int interrupt*/
uint32_t reserved17: 15;
uint32_t rx_take_data: 1; /*The raw interrupt status bit for the i2s_rx_take_data_int interrupt*/
uint32_t tx_put_data: 1; /*The raw interrupt status bit for the i2s_tx_put_data_int interrupt*/
uint32_t rx_wfull: 1; /*The raw interrupt status bit for the i2s_rx_wfull_int interrupt*/
uint32_t rx_rempty: 1; /*The raw interrupt status bit for the i2s_rx_rempty_int interrupt*/
uint32_t tx_wfull: 1; /*The raw interrupt status bit for the i2s_tx_wfull_int interrupt*/
uint32_t tx_rempty: 1; /*The raw interrupt status bit for the i2s_tx_rempty_int interrupt*/
uint32_t rx_hung: 1; /*The raw interrupt status bit for the i2s_rx_hung_int interrupt*/
uint32_t tx_hung: 1; /*The raw interrupt status bit for the i2s_tx_hung_int interrupt*/
uint32_t in_done: 1; /*The raw interrupt status bit for the i2s_in_done_int interrupt*/
uint32_t in_suc_eof: 1; /*The raw interrupt status bit for the i2s_in_suc_eof_int interrupt*/
uint32_t in_err_eof: 1; /*don't use*/
uint32_t out_done: 1; /*The raw interrupt status bit for the i2s_out_done_int interrupt*/
uint32_t out_eof: 1; /*The raw interrupt status bit for the i2s_out_eof_int interrupt*/
uint32_t in_dscr_err: 1; /*The raw interrupt status bit for the i2s_in_dscr_err_int interrupt*/
uint32_t out_dscr_err: 1; /*The raw interrupt status bit for the i2s_out_dscr_err_int interrupt*/
uint32_t in_dscr_empty: 1; /*The raw interrupt status bit for the i2s_in_dscr_empty_int interrupt*/
uint32_t out_total_eof: 1; /*The raw interrupt status bit for the i2s_out_total_eof_int interrupt*/
uint32_t v_sync: 1; /*The raw interrupt status bit for the i2s_v_sync_int interrupt*/
uint32_t reserved18: 14;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t rx_take_data: 1; /*The masked interrupt status bit for the i2s_rx_take_data_int interrupt*/
uint32_t tx_put_data: 1; /*The masked interrupt status bit for the i2s_tx_put_data_int interrupt*/
uint32_t rx_wfull: 1; /*The masked interrupt status bit for the i2s_rx_wfull_int interrupt*/
uint32_t rx_rempty: 1; /*The masked interrupt status bit for the i2s_rx_rempty_int interrupt*/
uint32_t tx_wfull: 1; /*The masked interrupt status bit for the i2s_tx_wfull_int interrupt*/
uint32_t tx_rempty: 1; /*The masked interrupt status bit for the i2s_tx_rempty_int interrupt*/
uint32_t rx_hung: 1; /*The masked interrupt status bit for the i2s_rx_hung_int interrupt*/
uint32_t tx_hung: 1; /*The masked interrupt status bit for the i2s_tx_hung_int interrupt*/
uint32_t in_done: 1; /*The masked interrupt status bit for the i2s_in_done_int interrupt*/
uint32_t in_suc_eof: 1; /*The masked interrupt status bit for the i2s_in_suc_eof_int interrupt*/
uint32_t in_err_eof: 1; /*don't use*/
uint32_t out_done: 1; /*The masked interrupt status bit for the i2s_out_done_int interrupt*/
uint32_t out_eof: 1; /*The masked interrupt status bit for the i2s_out_eof_int interrupt*/
uint32_t in_dscr_err: 1; /*The masked interrupt status bit for the i2s_in_dscr_err_int interrupt*/
uint32_t out_dscr_err: 1; /*The masked interrupt status bit for the i2s_out_dscr_err_int interrupt*/
uint32_t in_dscr_empty: 1; /*The masked interrupt status bit for the i2s_in_dscr_empty_int interrupt*/
uint32_t out_total_eof: 1; /*The masked interrupt status bit for the i2s_out_total_eof_int interrupt*/
uint32_t reserved17: 15;
uint32_t rx_take_data: 1; /*The masked interrupt status bit for the i2s_rx_take_data_int interrupt*/
uint32_t tx_put_data: 1; /*The masked interrupt status bit for the i2s_tx_put_data_int interrupt*/
uint32_t rx_wfull: 1; /*The masked interrupt status bit for the i2s_rx_wfull_int interrupt*/
uint32_t rx_rempty: 1; /*The masked interrupt status bit for the i2s_rx_rempty_int interrupt*/
uint32_t tx_wfull: 1; /*The masked interrupt status bit for the i2s_tx_wfull_int interrupt*/
uint32_t tx_rempty: 1; /*The masked interrupt status bit for the i2s_tx_rempty_int interrupt*/
uint32_t rx_hung: 1; /*The masked interrupt status bit for the i2s_rx_hung_int interrupt*/
uint32_t tx_hung: 1; /*The masked interrupt status bit for the i2s_tx_hung_int interrupt*/
uint32_t in_done: 1; /*The masked interrupt status bit for the i2s_in_done_int interrupt*/
uint32_t in_suc_eof: 1; /*The masked interrupt status bit for the i2s_in_suc_eof_int interrupt*/
uint32_t in_err_eof: 1; /*don't use*/
uint32_t out_done: 1; /*The masked interrupt status bit for the i2s_out_done_int interrupt*/
uint32_t out_eof: 1; /*The masked interrupt status bit for the i2s_out_eof_int interrupt*/
uint32_t in_dscr_err: 1; /*The masked interrupt status bit for the i2s_in_dscr_err_int interrupt*/
uint32_t out_dscr_err: 1; /*The masked interrupt status bit for the i2s_out_dscr_err_int interrupt*/
uint32_t in_dscr_empty: 1; /*The masked interrupt status bit for the i2s_in_dscr_empty_int interrupt*/
uint32_t out_total_eof: 1; /*The masked interrupt status bit for the i2s_out_total_eof_int interrupt*/
uint32_t v_sync: 1; /*The masked interrupt status bit for the i2s_v_sync_int interrupt*/
uint32_t reserved18: 14;
};
uint32_t val;
} int_st;
union {
struct {
uint32_t rx_take_data: 1; /*The interrupt enable bit for the i2s_rx_take_data_int interrupt*/
uint32_t tx_put_data: 1; /*The interrupt enable bit for the i2s_tx_put_data_int interrupt*/
uint32_t rx_wfull: 1; /*The interrupt enable bit for the i2s_rx_wfull_int interrupt*/
uint32_t rx_rempty: 1; /*The interrupt enable bit for the i2s_rx_rempty_int interrupt*/
uint32_t tx_wfull: 1; /*The interrupt enable bit for the i2s_tx_wfull_int interrupt*/
uint32_t tx_rempty: 1; /*The interrupt enable bit for the i2s_tx_rempty_int interrupt*/
uint32_t rx_hung: 1; /*The interrupt enable bit for the i2s_rx_hung_int interrupt*/
uint32_t tx_hung: 1; /*The interrupt enable bit for the i2s_tx_hung_int interrupt*/
uint32_t in_done: 1; /*The interrupt enable bit for the i2s_in_done_int interrupt*/
uint32_t in_suc_eof: 1; /*The interrupt enable bit for the i2s_in_suc_eof_int interrupt*/
uint32_t in_err_eof: 1; /*don't use*/
uint32_t out_done: 1; /*The interrupt enable bit for the i2s_out_done_int interrupt*/
uint32_t out_eof: 1; /*The interrupt enable bit for the i2s_out_eof_int interrupt*/
uint32_t in_dscr_err: 1; /*The interrupt enable bit for the i2s_in_dscr_err_int interrupt*/
uint32_t out_dscr_err: 1; /*The interrupt enable bit for the i2s_out_dscr_err_int interrupt*/
uint32_t in_dscr_empty: 1; /*The interrupt enable bit for the i2s_in_dscr_empty_int interrupt*/
uint32_t out_total_eof: 1; /*The interrupt enable bit for the i2s_out_total_eof_int interrupt*/
uint32_t reserved17: 15;
uint32_t rx_take_data: 1; /*The interrupt enable bit for the i2s_rx_take_data_int interrupt*/
uint32_t tx_put_data: 1; /*The interrupt enable bit for the i2s_tx_put_data_int interrupt*/
uint32_t rx_wfull: 1; /*The interrupt enable bit for the i2s_rx_wfull_int interrupt*/
uint32_t rx_rempty: 1; /*The interrupt enable bit for the i2s_rx_rempty_int interrupt*/
uint32_t tx_wfull: 1; /*The interrupt enable bit for the i2s_tx_wfull_int interrupt*/
uint32_t tx_rempty: 1; /*The interrupt enable bit for the i2s_tx_rempty_int interrupt*/
uint32_t rx_hung: 1; /*The interrupt enable bit for the i2s_rx_hung_int interrupt*/
uint32_t tx_hung: 1; /*The interrupt enable bit for the i2s_tx_hung_int interrupt*/
uint32_t in_done: 1; /*The interrupt enable bit for the i2s_in_done_int interrupt*/
uint32_t in_suc_eof: 1; /*The interrupt enable bit for the i2s_in_suc_eof_int interrupt*/
uint32_t in_err_eof: 1; /*don't use*/
uint32_t out_done: 1; /*The interrupt enable bit for the i2s_out_done_int interrupt*/
uint32_t out_eof: 1; /*The interrupt enable bit for the i2s_out_eof_int interrupt*/
uint32_t in_dscr_err: 1; /*The interrupt enable bit for the i2s_in_dscr_err_int interrupt*/
uint32_t out_dscr_err: 1; /*The interrupt enable bit for the i2s_out_dscr_err_int interrupt*/
uint32_t in_dscr_empty: 1; /*The interrupt enable bit for the i2s_in_dscr_empty_int interrupt*/
uint32_t out_total_eof: 1; /*The interrupt enable bit for the i2s_out_total_eof_int interrupt*/
uint32_t v_sync: 1; /*The interrupt enable bit for the i2s_v_sync_int interrupt*/
uint32_t reserved18: 14;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t take_data: 1; /*Set this bit to clear the i2s_rx_take_data_int interrupt*/
uint32_t put_data: 1; /*Set this bit to clear the i2s_tx_put_data_int interrupt*/
uint32_t rx_wfull: 1; /*Set this bit to clear the i2s_rx_wfull_int interrupt*/
uint32_t rx_rempty: 1; /*Set this bit to clear the i2s_rx_rempty_int interrupt*/
uint32_t tx_wfull: 1; /*Set this bit to clear the i2s_tx_wfull_int interrupt*/
uint32_t tx_rempty: 1; /*Set this bit to clear the i2s_tx_rempty_int interrupt*/
uint32_t rx_hung: 1; /*Set this bit to clear the i2s_rx_hung_int interrupt*/
uint32_t tx_hung: 1; /*Set this bit to clear the i2s_tx_hung_int interrupt*/
uint32_t in_done: 1; /*Set this bit to clear the i2s_in_done_int interrupt*/
uint32_t in_suc_eof: 1; /*Set this bit to clear the i2s_in_suc_eof_int interrupt*/
uint32_t in_err_eof: 1; /*don't use*/
uint32_t out_done: 1; /*Set this bit to clear the i2s_out_done_int interrupt*/
uint32_t out_eof: 1; /*Set this bit to clear the i2s_out_eof_int interrupt*/
uint32_t in_dscr_err: 1; /*Set this bit to clear the i2s_in_dscr_err_int interrupt*/
uint32_t out_dscr_err: 1; /*Set this bit to clear the i2s_out_dscr_err_int interrupt*/
uint32_t in_dscr_empty: 1; /*Set this bit to clear the i2s_in_dscr_empty_int interrupt*/
uint32_t out_total_eof: 1; /*Set this bit to clear the i2s_out_total_eof_int interrupt*/
uint32_t reserved17: 15;
uint32_t take_data: 1; /*Set this bit to clear the i2s_rx_take_data_int interrupt*/
uint32_t put_data: 1; /*Set this bit to clear the i2s_tx_put_data_int interrupt*/
uint32_t rx_wfull: 1; /*Set this bit to clear the i2s_rx_wfull_int interrupt*/
uint32_t rx_rempty: 1; /*Set this bit to clear the i2s_rx_rempty_int interrupt*/
uint32_t tx_wfull: 1; /*Set this bit to clear the i2s_tx_wfull_int interrupt*/
uint32_t tx_rempty: 1; /*Set this bit to clear the i2s_tx_rempty_int interrupt*/
uint32_t rx_hung: 1; /*Set this bit to clear the i2s_rx_hung_int interrupt*/
uint32_t tx_hung: 1; /*Set this bit to clear the i2s_tx_hung_int interrupt*/
uint32_t in_done: 1; /*Set this bit to clear the i2s_in_done_int interrupt*/
uint32_t in_suc_eof: 1; /*Set this bit to clear the i2s_in_suc_eof_int interrupt*/
uint32_t in_err_eof: 1; /*don't use*/
uint32_t out_done: 1; /*Set this bit to clear the i2s_out_done_int interrupt*/
uint32_t out_eof: 1; /*Set this bit to clear the i2s_out_eof_int interrupt*/
uint32_t in_dscr_err: 1; /*Set this bit to clear the i2s_in_dscr_err_int interrupt*/
uint32_t out_dscr_err: 1; /*Set this bit to clear the i2s_out_dscr_err_int interrupt*/
uint32_t in_dscr_empty: 1; /*Set this bit to clear the i2s_in_dscr_empty_int interrupt*/
uint32_t out_total_eof: 1; /*Set this bit to clear the i2s_out_total_eof_int interrupt*/
uint32_t v_sync: 1; /*Set this bit to clear the i2s_v_sync_int interrupt*/
uint32_t reserved18: 14;
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t tx_bck_in_delay: 2; /*Number of delay cycles for BCK into the transmitter*/
uint32_t tx_ws_in_delay: 2; /*Number of delay cycles for WS into the transmitter*/
uint32_t rx_bck_in_delay: 2; /*Number of delay cycles for BCK into the receiver*/
uint32_t rx_ws_in_delay: 2; /*Number of delay cycles for WS into the receiver*/
uint32_t rx_sd_in_delay: 2; /*Number of delay cycles for SD into the receiver*/
uint32_t tx_bck_out_delay: 2; /*Number of delay cycles for BCK out of the transmitter*/
uint32_t tx_ws_out_delay: 2; /*Number of delay cycles for WS out of the transmitter*/
uint32_t tx_sd_out_delay: 2; /*Number of delay cycles for SD out of the transmitter*/
uint32_t rx_ws_out_delay: 2; /*Number of delay cycles for WS out of the receiver*/
uint32_t rx_bck_out_delay: 2; /*Number of delay cycles for BCK out of the receiver*/
uint32_t tx_dsync_sw: 1; /*Set this bit to synchronize signals with the double sync method into the transmitter*/
uint32_t rx_dsync_sw: 1; /*Set this bit to synchronize signals with the double sync method into the receiver*/
uint32_t data_enable_delay: 2; /*Number of delay cycles for data valid flag.*/
uint32_t tx_bck_in_inv: 1; /*Set this bit to invert BCK signal input to the slave transmitter*/
uint32_t tx_bck_in_delay: 2; /*Number of delay cycles for BCK into the transmitter*/
uint32_t tx_ws_in_delay: 2; /*Number of delay cycles for WS into the transmitter*/
uint32_t rx_bck_in_delay: 2; /*Number of delay cycles for BCK into the receiver*/
uint32_t rx_ws_in_delay: 2; /*Number of delay cycles for WS into the receiver*/
uint32_t rx_sd_in_delay: 2; /*Number of delay cycles for SD into the receiver*/
uint32_t tx_bck_out_delay: 2; /*Number of delay cycles for BCK out of the transmitter*/
uint32_t tx_ws_out_delay: 2; /*Number of delay cycles for WS out of the transmitter*/
uint32_t tx_sd_out_delay: 2; /*Number of delay cycles for SD out of the transmitter*/
uint32_t rx_ws_out_delay: 2; /*Number of delay cycles for WS out of the receiver*/
uint32_t rx_bck_out_delay: 2; /*Number of delay cycles for BCK out of the receiver*/
uint32_t tx_dsync_sw: 1; /*Set this bit to synchronize signals with the double sync method into the transmitter*/
uint32_t rx_dsync_sw: 1; /*Set this bit to synchronize signals with the double sync method into the receiver*/
uint32_t data_enable_delay: 2; /*Number of delay cycles for data valid flag.*/
uint32_t tx_bck_in_inv: 1; /*Set this bit to invert BCK signal input to the slave transmitter*/
uint32_t reserved25: 7;
};
uint32_t val;
} timing;
union {
struct {
uint32_t rx_data_num: 6; /*Threshold of data length in receiver FIFO*/
uint32_t tx_data_num: 6; /*Threshold of data length in transmitter FIFO*/
uint32_t dscr_en: 1; /*Set this bit to enable I2S DMA mode*/
uint32_t tx_fifo_mod: 3; /*Transmitter FIFO mode configuration bits*/
uint32_t rx_fifo_mod: 3; /*Receiver FIFO mode configuration bits*/
uint32_t tx_fifo_mod_force_en: 1; /*The bit should always be set to 1*/
uint32_t rx_fifo_mod_force_en: 1; /*The bit should always be set to 1*/
uint32_t rx_fifo_sync: 1; /*force write back rx data to memory*/
uint32_t rx_24msb_en: 1; /*Only useful in rx 24bit mode. 1: the high 24 bits are effective in i2s fifo 0: the low 24 bits are effective in i2s fifo*/
uint32_t tx_24msb_en: 1; /*Only useful in tx 24bit mode. 1: the high 24 bits are effective in i2s fifo 0: the low 24 bits are effective in i2s fifo*/
uint32_t rx_data_num: 6; /*Threshold of data length in receiver FIFO*/
uint32_t tx_data_num: 6; /*Threshold of data length in transmitter FIFO*/
uint32_t dscr_en: 1; /*Set this bit to enable I2S DMA mode*/
uint32_t tx_fifo_mod: 3; /*Transmitter FIFO mode configuration bits*/
uint32_t rx_fifo_mod: 3; /*Receiver FIFO mode configuration bits*/
uint32_t tx_fifo_mod_force_en: 1; /*The bit should always be set to 1*/
uint32_t rx_fifo_mod_force_en: 1; /*The bit should always be set to 1*/
uint32_t rx_fifo_sync: 1; /*force write back rx data to memory*/
uint32_t rx_24msb_en: 1; /*Only useful in rx 24bit mode. 1: the high 24 bits are effective in i2s fifo 0: the low 24 bits are effective in i2s fifo*/
uint32_t tx_24msb_en: 1; /*Only useful in tx 24bit mode. 1: the high 24 bits are effective in i2s fifo 0: the low 24 bits are effective in i2s fifo*/
uint32_t reserved24: 8;
};
uint32_t val;
} fifo_conf;
uint32_t rx_eof_num; /*the length of data to be received. It will trigger i2s_in_suc_eof_int.*/
uint32_t conf_single_data; /*the right channel or left channel put out constant value stored in this register according to tx_chan_mod and reg_tx_msb_right*/
uint32_t rx_eof_num; /*the length of data to be received. It will trigger i2s_in_suc_eof_int.*/
uint32_t conf_single_data; /*the right channel or left channel put out constant value stored in this register according to tx_chan_mod and reg_tx_msb_right*/
union {
struct {
uint32_t tx_chan_mod: 3; /*I2S transmitter channel mode configuration bits.*/
uint32_t rx_chan_mod: 2; /*I2S receiver channel mode configuration bits.*/
uint32_t tx_chan_mod: 3; /*I2S transmitter channel mode configuration bits.*/
uint32_t rx_chan_mod: 2; /*I2S receiver channel mode configuration bits.*/
uint32_t reserved5: 27;
};
uint32_t val;
} conf_chan;
union {
struct {
uint32_t addr: 20; /*The address of first outlink descriptor*/
uint32_t addr: 20; /*The address of first outlink descriptor*/
uint32_t reserved20: 8;
uint32_t stop: 1; /*Set this bit to stop outlink descriptor*/
uint32_t start: 1; /*Set this bit to start outlink descriptor*/
uint32_t restart: 1; /*Set this bit to restart outlink descriptor*/
uint32_t stop: 1; /*Set this bit to stop outlink descriptor*/
uint32_t start: 1; /*Set this bit to start outlink descriptor*/
uint32_t restart: 1; /*Set this bit to restart outlink descriptor*/
uint32_t park: 1;
};
uint32_t val;
} out_link;
union {
struct {
uint32_t addr: 20; /*The address of first inlink descriptor*/
uint32_t addr: 20; /*The address of first inlink descriptor*/
uint32_t reserved20: 8;
uint32_t stop: 1; /*Set this bit to stop inlink descriptor*/
uint32_t start: 1; /*Set this bit to start inlink descriptor*/
uint32_t restart: 1; /*Set this bit to restart inlink descriptor*/
uint32_t stop: 1; /*Set this bit to stop inlink descriptor*/
uint32_t start: 1; /*Set this bit to start inlink descriptor*/
uint32_t restart: 1; /*Set this bit to restart inlink descriptor*/
uint32_t park: 1;
};
uint32_t val;
} in_link;
uint32_t out_eof_des_addr; /*The address of outlink descriptor that produces EOF*/
uint32_t in_eof_des_addr; /*The address of inlink descriptor that produces EOF*/
uint32_t out_eof_bfr_des_addr; /*The address of buffer relative to the outlink descriptor that produces EOF*/
uint32_t out_eof_des_addr; /*The address of outlink descriptor that produces EOF*/
uint32_t in_eof_des_addr; /*The address of inlink descriptor that produces EOF*/
uint32_t out_eof_bfr_des_addr; /*The address of buffer relative to the outlink descriptor that produces EOF*/
union {
struct {
uint32_t mode: 3;
@ -228,29 +232,29 @@ typedef volatile struct {
};
uint32_t val;
} ahb_test;
uint32_t in_link_dscr; /*The address of current inlink descriptor*/
uint32_t in_link_dscr_bf0; /*The address of next inlink descriptor*/
uint32_t in_link_dscr_bf1; /*The address of next inlink data buffer*/
uint32_t out_link_dscr; /*The address of current outlink descriptor*/
uint32_t out_link_dscr_bf0; /*The address of next outlink descriptor*/
uint32_t out_link_dscr_bf1; /*The address of next outlink data buffer*/
uint32_t in_link_dscr; /*The address of current inlink descriptor*/
uint32_t in_link_dscr_bf0; /*The address of next inlink descriptor*/
uint32_t in_link_dscr_bf1; /*The address of next inlink data buffer*/
uint32_t out_link_dscr; /*The address of current outlink descriptor*/
uint32_t out_link_dscr_bf0; /*The address of next outlink descriptor*/
uint32_t out_link_dscr_bf1; /*The address of next outlink data buffer*/
union {
struct {
uint32_t in_rst: 1; /*Set this bit to reset in dma FSM*/
uint32_t out_rst: 1; /*Set this bit to reset out dma FSM*/
uint32_t ahbm_fifo_rst: 1; /*Set this bit to reset ahb interface cmdFIFO of DMA*/
uint32_t ahbm_rst: 1; /*Set this bit to reset ahb interface of DMA*/
uint32_t out_loop_test: 1; /*Set this bit to loop test inlink*/
uint32_t in_loop_test: 1; /*Set this bit to loop test outlink*/
uint32_t out_auto_wrback: 1; /*Set this bit to enable outlink-written-back automatically when out buffer is transmitted done.*/
uint32_t out_no_restart_clr: 1; /*don't use*/
uint32_t out_eof_mode: 1; /*DMA out EOF flag generation mode . 1: when dma has popped all data from the FIFO 0:when ahb has pushed all data to the FIFO*/
uint32_t outdscr_burst_en: 1; /*DMA outlink descriptor transfer mode configuration bit. 1: to prepare outlink descriptor with burst mode 0: to prepare outlink descriptor with byte mode*/
uint32_t indscr_burst_en: 1; /*DMA inlink descriptor transfer mode configuration bit. 1: to prepare inlink descriptor with burst mode 0: to prepare inlink descriptor with byte mode*/
uint32_t out_data_burst_en: 1; /*Transmitter data transfer mode configuration bit. 1: to prepare out data with burst mode 0: to prepare out data with byte mode*/
uint32_t check_owner: 1; /*Set this bit to enable check owner bit by hardware*/
uint32_t mem_trans_en: 1; /*don't use*/
uint32_t ext_mem_bk_size: 2; /*DMA access external memory block size. 0: 16 bytes 1: 32 bytes 2:64 bytes 3:reserved*/
uint32_t in_rst: 1; /*Set this bit to reset in dma FSM*/
uint32_t out_rst: 1; /*Set this bit to reset out dma FSM*/
uint32_t ahbm_fifo_rst: 1; /*Set this bit to reset ahb interface cmdFIFO of DMA*/
uint32_t ahbm_rst: 1; /*Set this bit to reset ahb interface of DMA*/
uint32_t out_loop_test: 1; /*Set this bit to loop test inlink*/
uint32_t in_loop_test: 1; /*Set this bit to loop test outlink*/
uint32_t out_auto_wrback: 1; /*Set this bit to enable outlink-written-back automatically when out buffer is transmitted done.*/
uint32_t out_no_restart_clr: 1; /*don't use*/
uint32_t out_eof_mode: 1; /*DMA out EOF flag generation mode . 1: when dma has popped all data from the FIFO 0:when ahb has pushed all data to the FIFO*/
uint32_t outdscr_burst_en: 1; /*DMA outlink descriptor transfer mode configuration bit. 1: to prepare outlink descriptor with burst mode 0: to prepare outlink descriptor with byte mode*/
uint32_t indscr_burst_en: 1; /*DMA inlink descriptor transfer mode configuration bit. 1: to prepare inlink descriptor with burst mode 0: to prepare inlink descriptor with byte mode*/
uint32_t out_data_burst_en: 1; /*Transmitter data transfer mode configuration bit. 1: to prepare out data with burst mode 0: to prepare out data with byte mode*/
uint32_t check_owner: 1; /*Set this bit to enable check owner bit by hardware*/
uint32_t mem_trans_en: 1; /*don't use*/
uint32_t ext_mem_bk_size: 2; /*DMA access external memory block size. 0: 16 bytes 1: 32 bytes 2:64 bytes 3:reserved*/
uint32_t reserved16: 16;
};
uint32_t val;
@ -280,7 +284,7 @@ typedef volatile struct {
uint32_t out_state: 3;
uint32_t cnt: 7;
uint32_t out_full: 1;
uint32_t out_empty: 1; /*DMA transmitter status register*/
uint32_t out_empty: 1; /*DMA transmitter status register*/
};
uint32_t val;
} lc_state0;
@ -291,134 +295,66 @@ typedef volatile struct {
uint32_t in_state: 3;
uint32_t cnt_debug: 7;
uint32_t in_full: 1;
uint32_t in_empty: 1; /*DMA receiver status register*/
uint32_t in_empty: 1; /*DMA receiver status register*/
};
uint32_t val;
} lc_state1;
union {
struct {
uint32_t fifo_timeout: 8; /*the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value*/
uint32_t fifo_timeout_shift: 3; /*The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift*/
uint32_t fifo_timeout_ena: 1; /*The enable bit for FIFO timeout*/
uint32_t fifo_timeout: 8; /*the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value*/
uint32_t fifo_timeout_shift: 3; /*The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift*/
uint32_t fifo_timeout_ena: 1; /*The enable bit for FIFO timeout*/
uint32_t reserved12: 20;
};
uint32_t val;
} lc_hung_conf;
uint32_t reserved_78;
uint32_t reserved_7c;
uint32_t reserved_80;
uint32_t reserved_84;
uint32_t reserved_88;
uint32_t reserved_8c;
uint32_t reserved_90;
uint32_t reserved_94;
uint32_t reserved_98;
uint32_t reserved_9c;
union {
struct {
uint32_t y_max: 16; /*don't use*/
uint32_t y_min: 16; /*don't use*/
};
uint32_t val;
} cvsd_conf0;
union {
struct {
uint32_t sigma_max: 16; /*don't use*/
uint32_t sigma_min: 16; /*don't use*/
};
uint32_t val;
} cvsd_conf1;
union {
struct {
uint32_t cvsd_k: 3; /*don't use*/
uint32_t cvsd_j: 3; /*don't use*/
uint32_t cvsd_beta: 10; /*don't use*/
uint32_t cvsd_h: 3; /*don't use*/
uint32_t reserved19:13; /*don't use*/
};
uint32_t val;
} cvsd_conf2;
union {
struct {
uint32_t good_pack_max: 6; /*don't use*/
uint32_t n_err_seg: 3; /*don't use*/
uint32_t shift_rate: 3; /*don't use*/
uint32_t max_slide_sample: 8; /*don't use*/
uint32_t pack_len_8k: 5; /*don't use*/
uint32_t n_min_err: 3; /*don't use*/
uint32_t reserved28: 4; /*don't use*/
};
uint32_t val;
} plc_conf0;
union {
struct {
uint32_t bad_cef_atten_para: 8; /*don't use*/
uint32_t bad_cef_atten_para_shift: 4; /*don't use*/
uint32_t bad_ola_win2_para_shift: 4; /*don't use*/
uint32_t bad_ola_win2_para: 8; /*don't use*/
uint32_t slide_win_len: 8; /*don't use*/
};
uint32_t val;
} plc_conf1;
union {
struct {
uint32_t cvsd_seg_mod: 2; /*don't use*/
uint32_t min_period: 5; /*don't use*/
uint32_t reserved7: 25; /*don't use*/
};
uint32_t val;
} plc_conf2;
union {
struct {
uint32_t en: 1; /*don't use*/
uint32_t chan_mod: 1; /*don't use*/
uint32_t cvsd_dec_pack_err: 1; /*don't use*/
uint32_t cvsd_pack_len_8k: 5; /*don't use*/
uint32_t cvsd_inf_en: 1; /*don't use*/
uint32_t cvsd_dec_start: 1; /*don't use*/
uint32_t cvsd_dec_reset: 1; /*don't use*/
uint32_t plc_en: 1; /*don't use*/
uint32_t plc2dma_en: 1; /*don't use*/
uint32_t reserved13: 19; /*don't use*/
};
uint32_t val;
} esco_conf0;
union {
struct {
uint32_t with_en: 1; /*don't use*/
uint32_t no_en: 1; /*don't use*/
uint32_t cvsd_enc_start: 1; /*don't use*/
uint32_t cvsd_enc_reset: 1; /*don't use*/
uint32_t reserved4: 28; /*don't use*/
};
uint32_t val;
} sco_conf0;
union {
struct {
uint32_t tx_pcm_conf: 3; /*Compress/Decompress module configuration bits. 0: decompress transmitted data 1:compress transmitted data*/
uint32_t tx_pcm_bypass: 1; /*Set this bit to bypass Compress/Decompress module for transmitted data.*/
uint32_t rx_pcm_conf: 3; /*Compress/Decompress module configuration bits. 0: decompress received data 1:compress received data*/
uint32_t rx_pcm_bypass: 1; /*Set this bit to bypass Compress/Decompress module for received data.*/
uint32_t tx_stop_en: 1; /*Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy*/
uint32_t tx_zeros_rm_en: 1; /*don't use*/
uint32_t tx_pcm_conf: 3; /*Compress/Decompress module configuration bits. 0: decompress transmitted data 1:compress transmitted data*/
uint32_t tx_pcm_bypass: 1; /*Set this bit to bypass Compress/Decompress module for transmitted data.*/
uint32_t rx_pcm_conf: 3; /*Compress/Decompress module configuration bits. 0: decompress received data 1:compress received data*/
uint32_t rx_pcm_bypass: 1; /*Set this bit to bypass Compress/Decompress module for received data.*/
uint32_t tx_stop_en: 1; /*Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy*/
uint32_t tx_zeros_rm_en: 1; /*don't use*/
uint32_t reserved10: 22;
};
uint32_t val;
} conf1;
union {
struct {
uint32_t fifo_force_pd: 1; /*Force FIFO power-down*/
uint32_t fifo_force_pu: 1; /*Force FIFO power-up*/
uint32_t fifo_force_pd: 1; /*Force FIFO power-down*/
uint32_t fifo_force_pu: 1; /*Force FIFO power-up*/
uint32_t plc_mem_force_pd: 1;
uint32_t plc_mem_force_pu: 1;
uint32_t reserved4: 28;
uint32_t dma_ram_force_pd: 1;
uint32_t dma_ram_force_pu: 1;
uint32_t dma_ram_clk_fo: 1;
uint32_t reserved7: 25;
};
uint32_t val;
} pd_conf;
union {
struct {
uint32_t camera_en: 1; /*Set this bit to enable camera mode*/
uint32_t lcd_tx_wrx2_en: 1; /*LCD WR double for one datum.*/
uint32_t lcd_tx_sdx2_en: 1; /*Set this bit to duplicate data pairs (Frame Form 2) in LCD mode.*/
uint32_t data_enable_test_en: 1; /*for debug camera mode enable*/
uint32_t data_enable: 1; /*for debug camera mode enable*/
uint32_t lcd_en: 1; /*Set this bit to enable LCD mode*/
uint32_t ext_adc_start_en: 1; /*Set this bit to enable the function that ADC mode is triggered by external signal.*/
uint32_t inter_valid_en: 1; /*Set this bit to enable camera internal valid*/
uint32_t cam_sync_fifo_reset: 1; /*Set this bit to reset cam_sync_fifo*/
uint32_t cam_clk_loopback: 1; /*Set this bit to loopback cam_clk from i2s_rx*/
uint32_t camera_en: 1; /*Set this bit to enable camera mode*/
uint32_t lcd_tx_wrx2_en: 1; /*LCD WR double for one datum.*/
uint32_t lcd_tx_sdx2_en: 1; /*Set this bit to duplicate data pairs (Frame Form 2) in LCD mode.*/
uint32_t data_enable_test_en: 1; /*for debug camera mode enable*/
uint32_t data_enable: 1; /*for debug camera mode enable*/
uint32_t lcd_en: 1; /*Set this bit to enable LCD mode*/
uint32_t ext_adc_start_en: 1; /*Set this bit to enable the function that ADC mode is triggered by external signal.*/
uint32_t inter_valid_en: 1; /*Set this bit to enable camera internal valid*/
uint32_t cam_sync_fifo_reset: 1; /*Set this bit to reset cam_sync_fifo*/
uint32_t cam_clk_loopback: 1; /*Set this bit to loopback cam_clk from i2s_rx*/
uint32_t i_v_sync_filter_en: 1;
uint32_t i_v_sync_filter_thres: 3;
uint32_t reserved14: 18;
@ -427,57 +363,31 @@ typedef volatile struct {
} conf2;
union {
struct {
uint32_t clkm_div_num: 8; /*Integral I2S clock divider value*/
uint32_t clkm_div_b: 6; /*Fractional clock divider numerator value*/
uint32_t clkm_div_a: 6; /*Fractional clock divider denominator value*/
uint32_t clk_en: 1; /*Set this bit to enable clk gate*/
uint32_t clk_sel: 2; /*Set this bit to enable clk_apll*/
uint32_t clkm_div_num: 8; /*Integral I2S clock divider value*/
uint32_t clkm_div_b: 6; /*Fractional clock divider numerator value*/
uint32_t clkm_div_a: 6; /*Fractional clock divider denominator value*/
uint32_t clk_en: 1; /*Set this bit to enable clk gate*/
uint32_t clk_sel: 2; /*Set this bit to enable clk_apll*/
uint32_t reserved23: 9;
};
uint32_t val;
} clkm_conf;
union {
struct {
uint32_t tx_bck_div_num: 6; /*Bit clock configuration bits in transmitter mode.*/
uint32_t rx_bck_div_num: 6; /*Bit clock configuration bits in receiver mode.*/
uint32_t tx_bits_mod: 6; /*Set the bits to configure bit length of I2S transmitter channel.*/
uint32_t rx_bits_mod: 6; /*Set the bits to configure bit length of I2S receiver channel.*/
uint32_t tx_bck_div_num: 6; /*Bit clock configuration bits in transmitter mode.*/
uint32_t rx_bck_div_num: 6; /*Bit clock configuration bits in receiver mode.*/
uint32_t tx_bits_mod: 6; /*Set the bits to configure bit length of I2S transmitter channel.*/
uint32_t rx_bits_mod: 6; /*Set the bits to configure bit length of I2S receiver channel.*/
uint32_t reserved24: 8;
};
uint32_t val;
} sample_rate_conf;
uint32_t reserved_b4;
uint32_t reserved_b8;
union {
struct {
uint32_t tx_pdm_en: 1; /*Set this bit to enable transmitter PDM mode*/
uint32_t rx_pdm_en: 1; /*Set this bit to enable receiver PDM mode*/
uint32_t pcm2pdm_conv_en: 1; /*Set this bit to enable PCM-to-PDM converter*/
uint32_t pdm2pcm_conv_en: 1; /*Set this bit to enable PDM-to-PCM converter*/
uint32_t tx_sinc_osr2: 4; /*upsample rate = 64 * reg_tx_pdm_sinc_osr2*/
uint32_t tx_prescale: 8; /*set to 0*/
uint32_t tx_hp_in_shift: 2; /*Adjust size of input signal to filter module. 0: divided by 2 1:multiplied by 1 2:multiplied by 2 3:multiplied by 4*/
uint32_t tx_lp_in_shift: 2; /*Adjust size of input signal to filter module. 0: divided by 2 1:multiplied by 1 2:multiplied by 2 3:multiplied by 4*/
uint32_t tx_sinc_in_shift: 2; /*Adjust size of input signal to filter module. 0: divided by 2 1:multiplied by 1 2:multiplied by 2 3:multiplied by 4*/
uint32_t tx_sigmadelta_in_shift: 2; /*Adjust size of input signal to filter module. 0: divided by 2 1:multiplied by 1 2:multiplied by 2 3:multiplied by 4*/
uint32_t rx_sinc_dsr_16_en: 1; /*PDM down-sampling rate for filter group1 in receiver mode. 0: downsample rate = 64 1:downsample rate = 128*/
uint32_t txhp_bypass: 1; /*Set this bit to enable tx pdm hp filter bypass*/
uint32_t tx_chan_mod: 2; /*pdm tx channel mode*/
uint32_t tx_way_mode: 2; /*0/1 pdm rx use one-way*/
uint32_t rx_way_mode: 2; /*0/1 pdm rx use one-way*/
};
uint32_t val;
} pdm_conf;
union {
struct {
uint32_t tx_pdm_fs: 10; /*PCM-to-PDM converter PCM frequency parameter*/
uint32_t tx_pdm_fp: 10; /*PCM-to-PDM converter PDM frequency parameter*/
uint32_t reserved20:12;
};
uint32_t val;
} pdm_freq_conf;
union {
struct {
uint32_t tx_idle: 1; /*1: i2s_tx is idle state*/
uint32_t reserved1: 31;
uint32_t tx_idle: 1;
uint32_t reserved1: 31; /*1: i2s_tx is idle state*/
};
uint32_t val;
} state;
@ -496,12 +406,14 @@ typedef volatile struct {
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t date; /**/
uint32_t date; /**/
} i2s_dev_t;
extern i2s_dev_t I2S0;
extern i2s_dev_t I2S1;
_Static_assert(sizeof(i2s_dev_t)==0x100, "invalid i2s_dev_t size");
#ifdef __cplusplus
}
#endif
#endif /* _SOC_I2S_STRUCT_H_ */
#endif /* _SOC_I2S_STRUCT_H_ */

188
components/soc/src/esp32/include/hal/i2s_ll.h
View file

@ -621,50 +621,6 @@ static inline void i2s_ll_set_tx_pdm_en(i2s_dev_t *hw, bool val)
hw->pdm_conf.tx_pdm_en = val;
}
/**
* @brief Set I2S tx msb shift
*
* @param hw Peripheral I2S hardware instance address.
* @param val value to set tx msb shift
*/
static inline void i2s_ll_set_tx_msb_shift(i2s_dev_t *hw, uint32_t val)
{
hw->conf.tx_msb_shift = val;
}
/**
* @brief Set I2S rx msb shift
*
* @param hw Peripheral I2S hardware instance address.
* @param val value to set rx msb shift
*/
static inline void i2s_ll_set_rx_msb_shift(i2s_dev_t *hw, uint32_t val)
{
hw->conf.rx_msb_shift = val;
}
/**
* @brief Set I2S tx short sync
*
* @param hw Peripheral I2S hardware instance address.
* @param val value to set tx short sync
*/
static inline void i2s_ll_set_tx_short_sync(i2s_dev_t *hw, uint32_t val)
{
hw->conf.tx_short_sync = val;
}
/**
* @brief Set I2S rx short sync
*
* @param hw Peripheral I2S hardware instance address.
* @param val value to set rx short sync
*/
static inline void i2s_ll_set_rx_short_sync(i2s_dev_t *hw, uint32_t val)
{
hw->conf.rx_short_sync = val;
}
/**
* @brief Set I2S tx fifo mod force en
*
@ -819,6 +775,150 @@ static inline void i2s_ll_set_sig_loopback(i2s_dev_t *hw, uint32_t val)
hw->conf.sig_loopback = val;
}
/**
* @brief Set I2S TX to philip standard
*
* @param hw Peripheral I2S hardware instance address.
*/
static inline void i2s_ll_set_tx_format_philip(i2s_dev_t *hw)
{
hw->conf.tx_short_sync = 0;
hw->conf.tx_msb_shift = 1;
}
/**
* @brief Set I2S RX to philip standard
*
* @param hw Peripheral I2S hardware instance address.
*/
static inline void i2s_ll_set_rx_format_philip(i2s_dev_t *hw)
{
hw->conf.rx_short_sync = 0;
hw->conf.rx_msb_shift = 1;
}
/**
* @brief Set I2S TX to MSB Alignment Standard
*
* @param hw Peripheral I2S hardware instance address.
*/
static inline void i2s_ll_set_tx_format_msb_align(i2s_dev_t *hw)
{
hw->conf.tx_short_sync = 0;
hw->conf.tx_msb_shift = 0;
}
/**
* @brief Set I2S RX to MSB Alignment Standard
*
* @param hw Peripheral I2S hardware instance address.
*/
static inline void i2s_ll_set_rx_format_msb_align(i2s_dev_t *hw)
{
hw->conf.rx_short_sync = 0;
hw->conf.rx_msb_shift = 0;
}
/**
* @brief Set I2S TX to PCM short standard
*
* @param hw Peripheral I2S hardware instance address.
*/
static inline void i2s_ll_set_tx_pcm_short(i2s_dev_t *hw)
{
hw->conf.tx_short_sync = 1;
hw->conf.tx_msb_shift = 0;
}
/**
* @brief Set I2S RX to PCM short standard
*
* @param hw Peripheral I2S hardware instance address.
*/
static inline void i2s_ll_set_rx_pcm_short(i2s_dev_t *hw)
{
hw->conf.rx_short_sync = 1;
hw->conf.rx_msb_shift = 0;
}
/**
* @brief Set I2S TX to PCM long standard
*
* @param hw Peripheral I2S hardware instance address.
*/
static inline void i2s_ll_set_tx_pcm_long(i2s_dev_t *hw)
{
hw->conf.tx_short_sync = 0;
hw->conf.tx_msb_shift = 0;
}
/**
* @brief Set I2S RX to PCM long standard
*
* @param hw Peripheral I2S hardware instance address.
*/
static inline void i2s_ll_set_rx_pcm_long(i2s_dev_t *hw)
{
hw->conf.rx_short_sync = 0;
hw->conf.rx_msb_shift = 0;
}
/**
* @brief Configure I2S TX pdm
*
* @param sample_rate The sample rate to be set.
* @param hw Peripheral I2S hardware instance address.
*/
static inline void i2s_ll_tx_pdm_cfg(i2s_dev_t *hw, uint32_t sample_rate)
{
uint32_t fp = 96;
uint32_t fs = sample_rate / 1000 * 10;
hw->pdm_freq_conf.tx_pdm_fp = fp;
hw->pdm_freq_conf.tx_pdm_fs = fs;
hw->pdm_conf.tx_sinc_osr2 = fp/fs;
hw->pdm_conf.pcm2pdm_conv_en = 1;
hw->pdm_conf.tx_pdm_en = 1;
}
/**
* @brief Configure I2S TX pdm
*
* @param hw Peripheral I2S hardware instance address.
*/
static inline void i2s_ll_rx_pdm_cfg(i2s_dev_t *hw)
{
hw->pdm_conf.rx_sinc_dsr_16_en = 0;
hw->pdm_conf.pdm2pcm_conv_en = 1;
hw->pdm_conf.rx_pdm_en = 1;
}
/**
* @brief Enable I2S build in ADC mode
*
* @param hw Peripheral I2S hardware instance address.
*/
static inline void i2s_ll_build_in_adc_ena(i2s_dev_t *hw)
{
hw->conf2.lcd_en = 1;
hw->conf2.camera_en = 0;
hw->conf.rx_msb_shift = 0;
hw->conf.rx_short_sync = 0;
}
/**
* @brief Enable I2S build in DAC mode
*
* @param hw Peripheral I2S hardware instance address.
*/
static inline void i2s_ll_build_in_dac_ena(i2s_dev_t *hw)
{
hw->conf2.lcd_en = 1;
hw->conf2.camera_en = 0;
hw->conf.tx_right_first = 1;
hw->conf.tx_msb_shift = 0;
hw->conf.tx_short_sync = 0;
}
#ifdef __cplusplus
}
#endif

132
components/soc/src/esp32s2/include/hal/i2s_ll.h
View file

@ -529,50 +529,6 @@ static inline void i2s_ll_set_camera_en(i2s_dev_t *hw, bool val)
hw->conf2.camera_en = val;
}
/**
* @brief Set I2S tx msb shift
*
* @param hw Peripheral I2S hardware instance address.
* @param val value to set tx msb shift
*/
static inline void i2s_ll_set_tx_msb_shift(i2s_dev_t *hw, uint32_t val)
{
hw->conf.tx_msb_shift = val;
}
/**
* @brief Set I2S rx msb shift
*
* @param hw Peripheral I2S hardware instance address.
* @param val value to set rx msb shift
*/
static inline void i2s_ll_set_rx_msb_shift(i2s_dev_t *hw, uint32_t val)
{
hw->conf.rx_msb_shift = val;
}
/**
* @brief Set I2S tx short sync
*
* @param hw Peripheral I2S hardware instance address.
* @param val value to set tx short sync
*/
static inline void i2s_ll_set_tx_short_sync(i2s_dev_t *hw, uint32_t val)
{
hw->conf.tx_short_sync = val;
}
/**
* @brief Set I2S rx short sync
*
* @param hw Peripheral I2S hardware instance address.
* @param val value to set rx short sync
*/
static inline void i2s_ll_set_rx_short_sync(i2s_dev_t *hw, uint32_t val)
{
hw->conf.rx_short_sync = val;
}
/**
* @brief Set I2S tx fifo mod force en
*
@ -716,6 +672,94 @@ static inline void i2s_ll_set_sig_loopback(i2s_dev_t *hw, uint32_t val)
hw->conf.sig_loopback = val;
}
/**
* @brief Set I2S TX to philip standard
*
* @param hw Peripheral I2S hardware instance address.
*/
static inline void i2s_ll_set_tx_format_philip(i2s_dev_t *hw)
{
hw->conf.tx_short_sync = 0;
hw->conf.tx_msb_shift = 1;
}
/**
* @brief Set I2S RX to philip standard
*
* @param hw Peripheral I2S hardware instance address.
*/
static inline void i2s_ll_set_rx_format_philip(i2s_dev_t *hw)
{
hw->conf.rx_short_sync = 0;
hw->conf.rx_msb_shift = 1;
}
/**
* @brief Set I2S TX to MSB Alignment Standard
*
* @param hw Peripheral I2S hardware instance address.
*/
static inline void i2s_ll_set_tx_format_msb_align(i2s_dev_t *hw)
{
hw->conf.tx_short_sync = 0;
hw->conf.tx_msb_shift = 0;
}
/**
* @brief Set I2S RX to MSB Alignment Standard
*
* @param hw Peripheral I2S hardware instance address.
*/
static inline void i2s_ll_set_rx_format_msb_align(i2s_dev_t *hw)
{
hw->conf.rx_short_sync = 0;
hw->conf.rx_msb_shift = 0;
}
/**
* @brief Set I2S TX to PCM short standard
*
* @param hw Peripheral I2S hardware instance address.
*/
static inline void i2s_ll_set_tx_pcm_short(i2s_dev_t *hw)
{
hw->conf.tx_short_sync = 1;
hw->conf.tx_msb_shift = 0;
}
/**
* @brief Set I2S RX to PCM short standard
*
* @param hw Peripheral I2S hardware instance address.
*/
static inline void i2s_ll_set_rx_pcm_short(i2s_dev_t *hw)
{
hw->conf.rx_short_sync = 1;
hw->conf.rx_msb_shift = 0;
}
/**
* @brief Set I2S TX to PCM long standard
*
* @param hw Peripheral I2S hardware instance address.
*/
static inline void i2s_ll_set_tx_pcm_long(i2s_dev_t *hw)
{
hw->conf.tx_short_sync = 0;
hw->conf.tx_msb_shift = 0;
}
/**
* @brief Set I2S RX to PCM long standard
*
* @param hw Peripheral I2S hardware instance address.
*/
static inline void i2s_ll_set_rx_pcm_long(i2s_dev_t *hw)
{
hw->conf.rx_short_sync = 0;
hw->conf.rx_msb_shift = 0;
}
#ifdef __cplusplus
}
#endif

119
components/soc/src/hal/i2s_hal.c
View file

@ -15,7 +15,6 @@
// The HAL layer for I2S (common part)
#include "soc/soc.h"
#include "esp_log.h"
#include "hal/i2s_hal.h"
void i2s_hal_reset_fifo(i2s_hal_context_t *hal)
@ -115,6 +114,44 @@ void i2s_hal_stop_rx(i2s_hal_context_t *hal)
i2s_ll_stop_rx(hal->dev);
}
void i2s_hal_format_config(i2s_hal_context_t *hal, const i2s_config_t *i2s_config)
{
switch (i2s_config->communication_format) {
case I2S_COMM_FORMAT_STAND_MSB:
if (i2s_config->mode & I2S_MODE_TX) {
i2s_ll_set_tx_format_msb_align(hal->dev);
}
if (i2s_config->mode & I2S_MODE_RX) {
i2s_ll_set_rx_format_msb_align(hal->dev);
}
break;
case I2S_COMM_FORMAT_STAND_PCM_SHORT:
if (i2s_config->mode & I2S_MODE_TX) {
i2s_ll_set_tx_pcm_long(hal->dev);
}
if (i2s_config->mode & I2S_MODE_RX) {
i2s_ll_set_rx_pcm_long(hal->dev);
}
break;
case I2S_COMM_FORMAT_STAND_PCM_LONG:
if (i2s_config->mode & I2S_MODE_TX) {
i2s_ll_set_tx_pcm_short(hal->dev);
}
if (i2s_config->mode & I2S_MODE_RX) {
i2s_ll_set_rx_pcm_short(hal->dev);
}
break;
default: //I2S_COMM_FORMAT_STAND_I2S
if (i2s_config->mode & I2S_MODE_TX) {
i2s_ll_set_tx_format_philip(hal->dev);
}
if (i2s_config->mode & I2S_MODE_RX) {
i2s_ll_set_rx_format_philip(hal->dev);
}
break;
}
}
void i2s_hal_config_param(i2s_hal_context_t *hal, const i2s_config_t *i2s_config)
{
//reset i2s
@ -129,10 +166,6 @@ void i2s_hal_config_param(i2s_hal_context_t *hal, const i2s_config_t *i2s_config
i2s_ll_set_lcd_en(hal->dev, 0);
i2s_ll_set_camera_en(hal->dev, 0);
#if SOC_I2S_SUPPORTS_PDM
i2s_ll_set_pcm2pdm_conv_en(hal->dev, 0);
i2s_ll_set_pdm2pcm_conv_en(hal->dev, 0);
#endif
i2s_ll_set_dscr_en(hal->dev, 0);
@ -172,66 +205,36 @@ void i2s_hal_config_param(i2s_hal_context_t *hal, const i2s_config_t *i2s_config
}
}
#if SOC_I2S_SUPPORTS_ADC_DAC
if (i2s_config->mode & (I2S_MODE_DAC_BUILT_IN | I2S_MODE_ADC_BUILT_IN)) {
i2s_ll_set_lcd_en(hal->dev, 1);
i2s_ll_set_tx_right_first(hal->dev, 1);
i2s_ll_set_camera_en(hal->dev, 0);
}
#endif
#if SOC_I2S_SUPPORTS_PDM
if (i2s_config->mode & I2S_MODE_PDM) {
i2s_ll_set_rx_fifo_mod_force_en(hal->dev, 1);
i2s_ll_set_tx_fifo_mod_force_en(hal->dev, 1);
i2s_ll_set_tx_pdm_fp(hal->dev, 960);
i2s_ll_set_tx_pdm_fs(hal->dev, i2s_config->sample_rate / 1000 * 10);
uint32_t fp, fs;
i2s_ll_get_tx_pdm_fp(hal->dev, &fp);
i2s_ll_get_tx_pdm_fs(hal->dev, &fs);
i2s_ll_set_tx_sinc_osr2(hal->dev, fp / fs);
i2s_ll_set_rx_sinc_dsr_16_en(hal->dev, 0);
i2s_ll_set_rx_pdm_en(hal->dev, 1);
i2s_ll_set_tx_pdm_en(hal->dev, 1);
i2s_ll_set_pcm2pdm_conv_en(hal->dev, 1);
i2s_ll_set_pdm2pcm_conv_en(hal->dev, 1);
} else {
if (!(i2s_config->mode & I2S_MODE_PDM)) {
i2s_ll_set_rx_pdm_en(hal->dev, 0);
i2s_ll_set_tx_pdm_en(hal->dev, 0);
} else {
if (i2s_config->mode & I2S_MODE_TX) {
i2s_ll_tx_pdm_cfg(hal->dev, i2s_config->sample_rate);
}
if(i2s_config->mode & I2S_MODE_RX) {
i2s_ll_rx_pdm_cfg(hal->dev);
}
// PDM mode have nothing to do with communication format configuration.
return;
}
#endif
if (i2s_config->communication_format & I2S_COMM_FORMAT_I2S) {
i2s_ll_set_tx_short_sync(hal->dev, 0);
i2s_ll_set_rx_short_sync(hal->dev, 0);
i2s_ll_set_tx_msb_shift(hal->dev, 1);
i2s_ll_set_rx_msb_shift(hal->dev, 1);
if (i2s_config->communication_format & I2S_COMM_FORMAT_I2S_LSB) {
if (i2s_config->mode & I2S_MODE_TX) {
i2s_ll_set_tx_msb_shift(hal->dev, 0);
}
if (i2s_config->mode & I2S_MODE_RX) {
i2s_ll_set_rx_msb_shift(hal->dev, 0);
}
}
}
if (i2s_config->communication_format & I2S_COMM_FORMAT_PCM) {
i2s_ll_set_tx_msb_shift(hal->dev, 0);
i2s_ll_set_rx_msb_shift(hal->dev, 0);
i2s_ll_set_tx_short_sync(hal->dev, 0);
i2s_ll_set_rx_short_sync(hal->dev, 0);
if (i2s_config->communication_format & I2S_COMM_FORMAT_PCM_SHORT) {
if (i2s_config->mode & I2S_MODE_TX) {
i2s_ll_set_tx_short_sync(hal->dev, 1);
}
if (i2s_config->mode & I2S_MODE_RX) {
i2s_ll_set_rx_short_sync(hal->dev, 1);
}
}
#if SOC_I2S_SUPPORTS_ADC_DAC
if (i2s_config->mode & (I2S_MODE_DAC_BUILT_IN | I2S_MODE_ADC_BUILT_IN)) {
if (i2s_config->mode & I2S_MODE_DAC_BUILT_IN) {
i2s_ll_build_in_dac_ena(hal->dev);
}
if (i2s_config->mode & I2S_MODE_ADC_BUILT_IN) {
i2s_ll_build_in_adc_ena(hal->dev);
}
// Buildin ADC and DAC have nothing to do with communication format configuration.
return;
}
#endif
i2s_hal_format_config(hal, i2s_config);
}
void i2s_hal_enable_master_mode(i2s_hal_context_t *hal)

5
docs/en/api-reference/peripherals/i2s.rst
View file

@ -73,7 +73,7 @@ Configuration example:
.sample_rate = 44100,
.bits_per_sample = 16,
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
.communication_format = I2S_COMM_FORMAT_I2S | I2S_COMM_FORMAT_I2S_MSB,
.communication_format = I2S_COMM_FORMAT_STAND_I2S,
.intr_alloc_flags = 0, // default interrupt priority
.dma_buf_count = 8,
.dma_buf_len = 64,
@ -152,7 +152,7 @@ I2S configuration
.sample_rate = 44100,
.bits_per_sample = 16,
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
.communication_format = I2S_COMM_FORMAT_I2S | I2S_COMM_FORMAT_I2S_MSB,
.communication_format = I2S_COMM_FORMAT_STAND_I2S,
.intr_alloc_flags = 0, // default interrupt priority
.dma_buf_count = 8,
.dma_buf_len = 64,
@ -192,7 +192,6 @@ Configuring I2S to use internal DAC for analog output
.sample_rate = 44100,
.bits_per_sample = 16, /* the DAC module will only take the 8bits from MSB */
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
.communication_format = I2S_COMM_FORMAT_I2S_MSB,
.intr_alloc_flags = 0, // default interrupt priority
.dma_buf_count = 8,
.dma_buf_len = 64,

2
examples/bluetooth/bluedroid/classic_bt/a2dp_sink/main/main.c
View file

@ -61,7 +61,7 @@ void app_main(void)
.sample_rate = 44100,
.bits_per_sample = 16,
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT, //2-channels
.communication_format = I2S_COMM_FORMAT_I2S_MSB,
.communication_format = I2S_COMM_FORMAT_STAND_MSB,
.dma_buf_count = 6,
.dma_buf_len = 60,
.intr_alloc_flags = 0, //Default interrupt priority

3
examples/bluetooth/bluedroid/coex/a2dp_gatts_coex/main/main.c
View file

@ -682,11 +682,10 @@ void app_main(void)
i2s_config_t i2s_config = {
#ifdef CONFIG_EXAMPLE_A2DP_SINK_OUTPUT_INTERNAL_DAC
.mode = I2S_MODE_MASTER | I2S_MODE_TX | I2S_MODE_DAC_BUILT_IN,
.communication_format = I2S_COMM_FORMAT_PCM,
#else
.mode = I2S_MODE_MASTER | I2S_MODE_TX, // Only TX
.communication_format = I2S_COMM_FORMAT_I2S | I2S_COMM_FORMAT_I2S_MSB,
#endif
.communication_format = I2S_COMM_FORMAT_STAND_MSB,
.sample_rate = 44100,
.bits_per_sample = 16,
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT, //2-channels

3
examples/peripherals/i2s/main/i2s_example_main.c
View file

@ -13,6 +13,7 @@
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "driver/i2s.h"
#include "driver/gpio.h"
#include "esp_system.h"
#include <math.h>
@ -90,7 +91,7 @@ void app_main(void)
.sample_rate = SAMPLE_RATE,
.bits_per_sample = 16,
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT, //2-channels
.communication_format = I2S_COMM_FORMAT_I2S | I2S_COMM_FORMAT_I2S_MSB,
.communication_format = I2S_COMM_FORMAT_STAND_MSB,
.dma_buf_count = 6,
.dma_buf_len = 60,
.use_apll = false,

2
examples/peripherals/i2s_adc_dac/main/app_main.c
View file

@ -65,7 +65,7 @@ void example_i2s_init(void)
.mode = I2S_MODE_MASTER | I2S_MODE_RX | I2S_MODE_TX | I2S_MODE_DAC_BUILT_IN | I2S_MODE_ADC_BUILT_IN,
.sample_rate = EXAMPLE_I2S_SAMPLE_RATE,
.bits_per_sample = EXAMPLE_I2S_SAMPLE_BITS,
.communication_format = I2S_COMM_FORMAT_PCM,
.communication_format = I2S_COMM_FORMAT_STAND_MSB,
.channel_format = EXAMPLE_I2S_FORMAT,
.intr_alloc_flags = 0,
.dma_buf_count = 2,