Merge branch 'bugfix/external_rtc_start_fail' into 'master'
Bugfix/external rtc start fail See merge request idf/esp-idf!4374
This commit is contained in:
commit
ae585b6615
4 changed files with 64 additions and 7 deletions
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@ -775,6 +775,19 @@ menu "ESP32-specific"
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bool "Internal 8.5MHz oscillator, divided by 256 (~33kHz)"
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bool "Internal 8.5MHz oscillator, divided by 256 (~33kHz)"
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endchoice
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endchoice
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config ESP32_RTC_EXTERNAL_CRYSTAL_ADDITIONAL_CURRENT
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bool "Additional current for external 32kHz crystal"
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depends on ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL
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default "n"
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help
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Choose which additional current is used for rtc external crystal.
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- With some 32kHz crystal configurations, the X32N and X32P pins may not
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have enough drive strength to keep the crystal oscillating during deep sleep.
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If this option is enabled, additional current from touchpad 9 is provided
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internally to drive the 32kHz crystal. If this option is enabled, deep sleep current
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is slightly higher (4-5uA) and the touchpad and ULP wakeup sources are not available.
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config ESP32_RTC_CLK_CAL_CYCLES
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config ESP32_RTC_CLK_CAL_CYCLES
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int "Number of cycles for RTC_SLOW_CLK calibration"
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int "Number of cycles for RTC_SLOW_CLK calibration"
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default 3000 if ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL
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default 3000 if ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL
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@ -95,6 +95,7 @@ esp_err_t esp_sleep_disable_wakeup_source(esp_sleep_source_t source);
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* source is used.
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* source is used.
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* @return
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* @return
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* - ESP_OK on success
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* - ESP_OK on success
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* - ESP_ERR_NOT_SUPPORTED if additional current by touch (CONFIG_ESP32_RTC_EXTERNAL_CRYSTAL_ADDITIONAL_CURRENT) is enabled.
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* - ESP_ERR_INVALID_STATE if ULP co-processor is not enabled or if wakeup triggers conflict
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* - ESP_ERR_INVALID_STATE if ULP co-processor is not enabled or if wakeup triggers conflict
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*/
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*/
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esp_err_t esp_sleep_enable_ulp_wakeup();
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esp_err_t esp_sleep_enable_ulp_wakeup();
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@ -121,6 +122,7 @@ esp_err_t esp_sleep_enable_timer_wakeup(uint64_t time_in_us);
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*
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*
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* @return
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* @return
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* - ESP_OK on success
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* - ESP_OK on success
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* - ESP_ERR_NOT_SUPPORTED if additional current by touch (CONFIG_ESP32_RTC_EXTERNAL_CRYSTAL_ADDITIONAL_CURRENT) is enabled.
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* - ESP_ERR_INVALID_STATE if wakeup triggers conflict
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* - ESP_ERR_INVALID_STATE if wakeup triggers conflict
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*/
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*/
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esp_err_t esp_sleep_enable_touchpad_wakeup();
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esp_err_t esp_sleep_enable_touchpad_wakeup();
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@ -403,6 +403,9 @@ esp_err_t esp_sleep_disable_wakeup_source(esp_sleep_source_t source)
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esp_err_t esp_sleep_enable_ulp_wakeup()
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esp_err_t esp_sleep_enable_ulp_wakeup()
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{
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{
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#ifdef CONFIG_ESP32_RTC_EXTERNAL_CRYSTAL_ADDITIONAL_CURRENT
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return ESP_ERR_NOT_SUPPORTED;
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#endif
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#ifdef CONFIG_ULP_COPROC_ENABLED
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#ifdef CONFIG_ULP_COPROC_ENABLED
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if(s_config.wakeup_triggers & RTC_EXT0_TRIG_EN) {
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if(s_config.wakeup_triggers & RTC_EXT0_TRIG_EN) {
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ESP_LOGE(TAG, "Conflicting wake-up trigger: ext0");
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ESP_LOGE(TAG, "Conflicting wake-up trigger: ext0");
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@ -436,6 +439,9 @@ static void timer_wakeup_prepare()
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esp_err_t esp_sleep_enable_touchpad_wakeup()
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esp_err_t esp_sleep_enable_touchpad_wakeup()
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{
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{
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#ifdef CONFIG_ESP32_RTC_EXTERNAL_CRYSTAL_ADDITIONAL_CURRENT
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return ESP_ERR_NOT_SUPPORTED;
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#endif
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if (s_config.wakeup_triggers & (RTC_EXT0_TRIG_EN)) {
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if (s_config.wakeup_triggers & (RTC_EXT0_TRIG_EN)) {
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ESP_LOGE(TAG, "Conflicting wake-up trigger: ext0");
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ESP_LOGE(TAG, "Conflicting wake-up trigger: ext0");
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return ESP_ERR_INVALID_STATE;
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return ESP_ERR_INVALID_STATE;
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@ -695,6 +701,13 @@ static uint32_t get_power_down_flags()
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if (s_config.pd_options[ESP_PD_DOMAIN_XTAL] != ESP_PD_OPTION_ON) {
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if (s_config.pd_options[ESP_PD_DOMAIN_XTAL] != ESP_PD_OPTION_ON) {
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pd_flags |= RTC_SLEEP_PD_XTAL;
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pd_flags |= RTC_SLEEP_PD_XTAL;
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}
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}
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if ((s_config.wakeup_triggers & (RTC_TOUCH_TRIG_EN | RTC_ULP_TRIG_EN)) == 0) {
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// If enabled EXT1 only and enable the additional current by touch, should be keep RTC_PERIPH power on.
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#if ((defined CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL) && (defined CONFIG_ESP32_RTC_EXTERNAL_CRYSTAL_ADDITIONAL_CURRENT))
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pd_flags &= ~RTC_SLEEP_PD_RTC_PERIPH;
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#endif
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}
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return pd_flags;
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return pd_flags;
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}
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}
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@ -58,7 +58,7 @@
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#define APLL_CAL_DELAY_2 0x3f
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#define APLL_CAL_DELAY_2 0x3f
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#define APLL_CAL_DELAY_3 0x1f
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#define APLL_CAL_DELAY_3 0x1f
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#define XTAL_32K_DAC_VAL 1
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#define XTAL_32K_DAC_VAL 3
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#define XTAL_32K_DRES_VAL 3
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#define XTAL_32K_DRES_VAL 3
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#define XTAL_32K_DBIAS_VAL 0
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#define XTAL_32K_DBIAS_VAL 0
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@ -85,7 +85,7 @@
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/* Core voltage needs to be increased in two cases:
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/* Core voltage needs to be increased in two cases:
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* 1. running at 240 MHz
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* 1. running at 240 MHz
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* 2. running with 80MHz Flash frequency
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* 2. running with 80MHz Flash frequency
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*
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*
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* There is a record in efuse which indicates the proper voltage for these two cases.
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* There is a record in efuse which indicates the proper voltage for these two cases.
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*/
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*/
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#define RTC_CNTL_DBIAS_HP_VOLT (RTC_CNTL_DBIAS_1V25 - (REG_GET_FIELD(EFUSE_BLK0_RDATA5_REG, EFUSE_RD_VOL_LEVEL_HP_INV)))
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#define RTC_CNTL_DBIAS_HP_VOLT (RTC_CNTL_DBIAS_1V25 - (REG_GET_FIELD(EFUSE_BLK0_RDATA5_REG, EFUSE_RD_VOL_LEVEL_HP_INV)))
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@ -114,14 +114,36 @@ static const char* TAG = "rtc_clk";
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static void rtc_clk_32k_enable_common(int dac, int dres, int dbias)
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static void rtc_clk_32k_enable_common(int dac, int dres, int dbias)
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{
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{
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SET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32N_MUX_SEL | RTC_IO_X32P_MUX_SEL);
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CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG,
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CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG,
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RTC_IO_X32P_RDE | RTC_IO_X32P_RUE | RTC_IO_X32N_RUE |
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RTC_IO_X32P_RDE | RTC_IO_X32P_RUE | RTC_IO_X32N_RUE |
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RTC_IO_X32N_RDE | RTC_IO_X32N_MUX_SEL | RTC_IO_X32P_MUX_SEL);
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RTC_IO_X32N_RDE | RTC_IO_X32N_FUN_IE | RTC_IO_X32P_FUN_IE);
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SET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32N_MUX_SEL | RTC_IO_X32P_MUX_SEL);
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/* Set the parameters of xtal
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dac --> current
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dres --> resistance
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dbias --> bais voltage
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*/
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REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DAC_XTAL_32K, dac);
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REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DAC_XTAL_32K, dac);
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REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DRES_XTAL_32K, dres);
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REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DRES_XTAL_32K, dres);
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REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DBIAS_XTAL_32K, dbias);
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REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DBIAS_XTAL_32K, dbias);
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SET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K);
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#ifdef CONFIG_ESP32_RTC_EXTERNAL_CRYSTAL_ADDITIONAL_CURRENT
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/* TOUCH sensor can provide additional current to external XTAL.
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In some case, X32N and X32P PAD don't have enough drive capability to start XTAL */
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SET_PERI_REG_MASK(RTC_IO_TOUCH_CFG_REG, RTC_IO_TOUCH_XPD_BIAS_M);
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/* Tie PAD Touch8 to VDD
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NOTE: TOUCH8 and TOUCH9 register settings are reversed except for DAC, so we set RTC_IO_TOUCH_PAD9_REG here instead
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*/
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SET_PERI_REG_MASK(RTC_IO_TOUCH_PAD9_REG, RTC_IO_TOUCH_PAD9_TIE_OPT_M);
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/* Set the current used to compensate TOUCH PAD8 */
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SET_PERI_REG_BITS(RTC_IO_TOUCH_PAD8_REG, RTC_IO_TOUCH_PAD8_DAC, 4, RTC_IO_TOUCH_PAD8_DAC_S);
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/* Power up TOUCH8
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So the Touch DAC start to drive some current from VDD to TOUCH8(which is also XTAL-N)
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*/
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SET_PERI_REG_MASK(RTC_IO_TOUCH_PAD9_REG, RTC_IO_TOUCH_PAD9_XPD_M);
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#endif // CONFIG_ESP32_RTC_EXTERNAL_CRYSTAL_ADDITIONAL_CURRENT
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/* Power up external xtal */
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SET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K_M);
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}
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}
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void rtc_clk_32k_enable(bool enable)
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void rtc_clk_32k_enable(bool enable)
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@ -129,7 +151,14 @@ void rtc_clk_32k_enable(bool enable)
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if (enable) {
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if (enable) {
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rtc_clk_32k_enable_common(XTAL_32K_DAC_VAL, XTAL_32K_DRES_VAL, XTAL_32K_DBIAS_VAL);
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rtc_clk_32k_enable_common(XTAL_32K_DAC_VAL, XTAL_32K_DRES_VAL, XTAL_32K_DBIAS_VAL);
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} else {
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} else {
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CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K);
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/* Disable X32N and X32P pad drive external xtal */
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CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K_M);
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CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32N_MUX_SEL | RTC_IO_X32P_MUX_SEL);
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#ifdef CONFIG_ESP32_RTC_EXTERNAL_CRYSTAL_ADDITIONAL_CURRENT
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/* Power down TOUCH */
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CLEAR_PERI_REG_MASK(RTC_IO_TOUCH_PAD9_REG, RTC_IO_TOUCH_PAD9_XPD_M);
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#endif // CONFIG_ESP32_RTC_EXTERNAL_CRYSTAL_ADDITIONAL_CURRENT
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}
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}
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}
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}
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