esp32: Use package identifier to look up SPI flash/PSRAM WP Pin, unless overridden
Allows booting in QIO/QOUT mode or with PSRAM on ESP32-PICO-V3 and ESP32-PICO-V3-O2 without any config changes. Custom WP pins (needed for fully custom circuit boards) should still be compatible.
This commit is contained in:
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55a1bd0fb6
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a94685a222
6 changed files with 103 additions and 61 deletions
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@ -53,20 +53,34 @@ menu "Bootloader config"
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default 4 if BOOTLOADER_LOG_LEVEL_DEBUG
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default 4 if BOOTLOADER_LOG_LEVEL_DEBUG
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default 5 if BOOTLOADER_LOG_LEVEL_VERBOSE
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default 5 if BOOTLOADER_LOG_LEVEL_VERBOSE
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config BOOTLOADER_SPI_CUSTOM_WP_PIN
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bool "Use custom SPI Flash WP Pin when flash pins set in eFuse (read help)"
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depends on IDF_TARGET_ESP32 && (ESPTOOLPY_FLASHMODE_QIO || ESPTOOLPY_FLASHMODE_QOUT)
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default y if BOOTLOADER_SPI_WP_PIN != 7 # backwards compatibility, can remove in IDF 5
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default n
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help
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This setting is only used if the SPI flash pins have been overridden by setting the eFuses
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SPI_PAD_CONFIG_xxx, and the SPI flash mode is QIO or QOUT.
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When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka
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ESP32 pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. The same pin is also used
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for external SPIRAM if it is enabled.
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If this config item is set to N (default), the correct WP pin will be automatically used for any
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Espressif chip or module with integrated flash. If a custom setting is needed, set this config item to
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Y and specify the GPIO number connected to the WP.
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config BOOTLOADER_SPI_WP_PIN
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config BOOTLOADER_SPI_WP_PIN
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int "SPI Flash WP Pin when customising pins via eFuse (read help)"
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int "Custom SPI Flash WP Pin"
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range 0 33
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range 0 33
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default 7
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default 7
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depends on ESPTOOLPY_FLASHMODE_QIO || ESPTOOLPY_FLASHMODE_QOUT
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depends on IDF_TARGET_ESP32 && (ESPTOOLPY_FLASHMODE_QIO || ESPTOOLPY_FLASHMODE_QOUT)
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#depends on BOOTLOADER_SPI_CUSTOM_WP_PIN # backwards compatibility, can uncomment in IDF 5
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help
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help
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This value is ignored unless flash mode is set to QIO or QOUT *and* the SPI flash pins have been
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The option "Use custom SPI Flash WP Pin" must be set or this value is ignored
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overriden by setting the eFuses SPI_PAD_CONFIG_xxx.
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When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka ESP32
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If burning a customized set of SPI flash pins in eFuse and using QIO or QOUT mode for flash, set this
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pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. That pin number is compiled into the
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value to the GPIO number of the SPI flash WP pin.
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bootloader instead.
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The default value (GPIO 7) is correct for WP pin on ESP32-D2WD integrated flash.
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choice BOOTLOADER_VDDSDIO_BOOST
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choice BOOTLOADER_VDDSDIO_BOOST
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bool "VDDSDIO LDO voltage"
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bool "VDDSDIO LDO voltage"
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@ -14,6 +14,7 @@
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#pragma once
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#pragma once
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#include "sdkconfig.h"
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#include "esp_image_format.h"
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#include "esp_image_format.h"
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#ifdef __cplusplus
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#ifdef __cplusplus
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@ -66,6 +67,22 @@ void bootloader_flash_gpio_config(const esp_image_header_t* pfhdr);
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*/
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*/
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void bootloader_flash_dummy_config(const esp_image_header_t* pfhdr);
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void bootloader_flash_dummy_config(const esp_image_header_t* pfhdr);
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#ifdef CONFIG_IDF_TARGET_ESP32
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/**
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* @brief Return the pin number used for custom SPI flash and/or SPIRAM WP pin
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*
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* Can be determined by eFuse values in most cases, or overriden in configuration
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*
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* This value is only meaningful if the other SPI flash pins are overriden via eFuse.
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*
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* This value is only meaningful if flash is set to QIO or QOUT mode, or if
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* SPIRAM is enabled.
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*
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* @return Pin number to use, or -1 if the default should be kept
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*/
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int bootloader_flash_get_wp_pin(void);
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#endif
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#ifdef __cplusplus
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#ifdef __cplusplus
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}
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}
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#endif
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#endif
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@ -25,6 +25,7 @@
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#include "soc/spi_reg.h"
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#include "soc/spi_reg.h"
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#include "soc/spi_caps.h"
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#include "soc/spi_caps.h"
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#include "flash_qio_mode.h"
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#include "flash_qio_mode.h"
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#include "bootloader_common.h"
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#include "bootloader_flash_config.h"
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#include "bootloader_flash_config.h"
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void bootloader_flash_update_id(void)
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void bootloader_flash_update_id(void)
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@ -157,3 +158,32 @@ void IRAM_ATTR bootloader_flash_dummy_config(const esp_image_header_t* pfhdr)
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SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + g_rom_spiflash_dummy_len_plus[0],
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SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + g_rom_spiflash_dummy_len_plus[0],
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SPI_USR_DUMMY_CYCLELEN_S);
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SPI_USR_DUMMY_CYCLELEN_S);
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}
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}
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#define ESP32_D2WD_WP_GPIO 7 /* ESP32-D2WD & ESP32-PICO-D4 has this GPIO wired to WP pin of flash */
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#define ESP32_PICO_V3_GPIO 18 /* ESP32-PICO-V3* use this GPIO for WP pin of flash */
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int bootloader_flash_get_wp_pin(void)
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{
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#if CONFIG_BOOTLOADER_SPI_CUSTOM_WP_PIN
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return CONFIG_BOOTLOADER_SPI_WP_PIN; // can be set for bootloader when QIO or QOUT config in use
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#elif CONFIG_SPIRAM_CUSTOM_SPIWP_SD3_PIN
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return CONFIG_SPIRAM_SPIWP_SD3_PIN; // can be set for app when DIO or DOUT config used for PSRAM only
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#else
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// no custom value, find it based on the package eFuse value
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uint8_t chip_ver;
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uint32_t pkg_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG);
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switch(pkg_ver) {
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case EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5:
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return ESP32_D2WD_WP_GPIO;
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case EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2:
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case EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4:
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/* Same package IDs are used for ESP32-PICO-V3 and ESP32-PICO-D4, silicon version differentiates */
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chip_ver = bootloader_common_get_chip_revision();
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return (chip_ver < 3) ? ESP32_D2WD_WP_GPIO : ESP32_PICO_V3_GPIO;
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case EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302:
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return ESP32_PICO_V3_GPIO;
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default:
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return SPI_WP_GPIO_NUM;
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}
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#endif
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}
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@ -13,6 +13,7 @@
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// limitations under the License.
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// limitations under the License.
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#include <stddef.h>
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#include <stddef.h>
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#include <stdint.h>
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#include <stdint.h>
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#include "bootloader_flash_config.h"
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#include "flash_qio_mode.h"
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#include "flash_qio_mode.h"
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#include "esp_log.h"
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#include "esp_log.h"
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#include "esp_err.h"
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#include "esp_err.h"
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@ -84,12 +85,6 @@ static unsigned read_status_8b_xmc25qu64a(void);
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/* Write 8 bit status of XM25QU64A */
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/* Write 8 bit status of XM25QU64A */
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static void write_status_8b_xmc25qu64a(unsigned new_status);
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static void write_status_8b_xmc25qu64a(unsigned new_status);
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#define ESP32_D2WD_WP_GPIO 7 /* ESP32-D2WD has this GPIO wired to WP pin of flash */
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#ifndef CONFIG_BOOTLOADER_SPI_WP_PIN // Set in menuconfig if SPI flasher config is set to a quad mode
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#define CONFIG_BOOTLOADER_SPI_WP_PIN ESP32_D2WD_WP_GPIO
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#endif
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/* Array of known flash chips and data to enable Quad I/O mode
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/* Array of known flash chips and data to enable Quad I/O mode
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Manufacturer & flash ID can be tested by running "esptool.py
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Manufacturer & flash ID can be tested by running "esptool.py
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@ -224,25 +219,6 @@ static esp_err_t enable_qio_mode(read_status_fn_t read_status_fn,
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uint32_t status;
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uint32_t status;
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const uint32_t spiconfig = ets_efuse_get_spiconfig();
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const uint32_t spiconfig = ets_efuse_get_spiconfig();
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#if CONFIG_IDF_TARGET_ESP32
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if (spiconfig != EFUSE_SPICONFIG_SPI_DEFAULTS && spiconfig != EFUSE_SPICONFIG_HSPI_DEFAULTS) {
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// spiconfig specifies a custom efuse pin configuration. This config defines all pins -except- WP,
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// which is compiled into the bootloader instead.
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//
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// Most commonly an overriden pin mapping means ESP32-D2WD or ESP32-PICO series.
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//Warn if chip is ESP32-D2WD/ESP32-PICO series but someone has changed the WP pin
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//assignment from that chip's WP pin.
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uint32_t pkg_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG);
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if (CONFIG_BOOTLOADER_SPI_WP_PIN != ESP32_D2WD_WP_GPIO &&
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(pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 ||
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pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 ||
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pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 ||
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pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302)) {
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ESP_LOGW(TAG, "Chip is ESP32-D2WD/ESP32-PICO series, but flash WP pin is different value to internal flash");
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}
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}
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#endif
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esp_rom_spiflash_wait_idle(&g_rom_flashchip);
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esp_rom_spiflash_wait_idle(&g_rom_flashchip);
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status = read_status_fn();
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status = read_status_fn();
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@ -277,13 +253,10 @@ static esp_err_t enable_qio_mode(read_status_fn_t read_status_fn,
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esp_rom_spiflash_config_readmode(mode);
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esp_rom_spiflash_config_readmode(mode);
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#if CONFIG_IDF_TARGET_ESP32
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#if CONFIG_IDF_TARGET_ESP32
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esp_rom_spiflash_select_qio_pins(CONFIG_BOOTLOADER_SPI_WP_PIN, spiconfig);
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int wp_pin = bootloader_flash_get_wp_pin();
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esp_rom_spiflash_select_qio_pins(wp_pin, spiconfig);
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#elif CONFIG_IDF_TARGET_ESP32S2
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#elif CONFIG_IDF_TARGET_ESP32S2
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if (ets_efuse_get_wp_pad() <= MAX_PAD_GPIO_NUM) {
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esp_rom_spiflash_select_qio_pins(ets_efuse_get_wp_pad(), spiconfig);
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esp_rom_spiflash_select_qio_pins(ets_efuse_get_wp_pad(), spiconfig);
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} else {
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esp_rom_spiflash_select_qio_pins(CONFIG_BOOTLOADER_SPI_WP_PIN, spiconfig);
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}
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#endif
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#endif
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return ESP_OK;
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return ESP_OK;
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}
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}
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@ -283,23 +283,37 @@ menu "ESP32-specific"
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endmenu
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endmenu
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config SPIRAM_CUSTOM_SPIWP_SD3_PIN
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bool "Use custom SPI PSRAM WP(SD3) Pin when flash pins set in eFuse (read help)"
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depends on IDF_TARGET_ESP32 && (ESPTOOLPY_FLASHMODE_DIO || ESPTOOLPY_FLASHMODE_DOUT)
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default y if SPIRAM_SPIWP_SD3_PIN != 7 # backwards compatibility, can remove in IDF 5
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default n
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help
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This setting is only used if the SPI flash pins have been overridden by setting the eFuses
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SPI_PAD_CONFIG_xxx, and the SPI flash mode is DIO or DOUT.
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When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka
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ESP32 pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. The psram only has QPI
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mode, so a WP pin setting is necessary.
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If this config item is set to N (default), the correct WP pin will be automatically used for any
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Espressif chip or module with integrated flash. If a custom setting is needed, set this config item
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to Y and specify the GPIO number connected to the WP pin.
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When flash mode is set to QIO or QOUT, the PSRAM WP pin will be set the same as the SPI Flash WP pin
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configured in the bootloader.
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config SPIRAM_SPIWP_SD3_PIN
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config SPIRAM_SPIWP_SD3_PIN
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int "SPI PSRAM WP(SD3) Pin when customising pins via eFuse (read help)"
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int "Custom SPI PSRAM WP(SD3) Pin"
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depends on ESPTOOLPY_FLASHMODE_DIO || ESPTOOLPY_FLASHMODE_DOUT
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depends on IDF_TARGET_ESP32 && (ESPTOOLPY_FLASHMODE_DIO || ESPTOOLPY_FLASHMODE_DOUT)
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#depends on SPIRAM_CUSTOM_SPIWP_SD3_PIN # backwards compatibility, can uncomment in IDF 5
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range 0 33
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range 0 33
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default 7
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default 7
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help
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help
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This value is ignored unless flash mode is set to DIO or DOUT and the SPI flash pins have been
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The option "Use custom SPI PSRAM WP(SD3) pin" must be set or this value is ignored
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overriden by setting the eFuses SPI_PAD_CONFIG_xxx.
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When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka
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If burning a customized set of SPI flash pins in eFuse and using DIO or DOUT mode for flash, set this
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ESP32 pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. And the psram only has QPI
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value to the GPIO number of the SPIRAM WP pin.
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mode, the WP pin is necessary, so we need to configure this value here.
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When flash mode is set to QIO or QOUT, the PSRAM WP pin will be set as the value configured in
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bootloader.
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For ESP32-PICO chip, the default value of this config should be 7.
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config SPIRAM_2T_MODE
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config SPIRAM_2T_MODE
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bool "Enable SPI PSRAM 2T mode"
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bool "Enable SPI PSRAM 2T mode"
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@ -36,6 +36,7 @@
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#include "driver/spi_common_internal.h"
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#include "driver/spi_common_internal.h"
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#include "driver/periph_ctrl.h"
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#include "driver/periph_ctrl.h"
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#include "bootloader_common.h"
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#include "bootloader_common.h"
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#include "bootloader_flash_config.h"
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#if CONFIG_SPIRAM
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#if CONFIG_SPIRAM
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#include "soc/rtc.h"
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#include "soc/rtc.h"
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@ -864,14 +865,7 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad
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psram_io.psram_spiq_sd0_io = EFUSE_SPICONFIG_RET_SPIQ(spiconfig);
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psram_io.psram_spiq_sd0_io = EFUSE_SPICONFIG_RET_SPIQ(spiconfig);
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psram_io.psram_spid_sd1_io = EFUSE_SPICONFIG_RET_SPID(spiconfig);
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psram_io.psram_spid_sd1_io = EFUSE_SPICONFIG_RET_SPID(spiconfig);
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psram_io.psram_spihd_sd2_io = EFUSE_SPICONFIG_RET_SPIHD(spiconfig);
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psram_io.psram_spihd_sd2_io = EFUSE_SPICONFIG_RET_SPIHD(spiconfig);
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psram_io.psram_spiwp_sd3_io = bootloader_flash_get_wp_pin();
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// If flash mode is set to QIO or QOUT, the WP pin is equal the value configured in bootloader.
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// If flash mode is set to DIO or DOUT, the WP pin should config it via menuconfig.
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#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_FLASHMODE_QOUT
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psram_io.psram_spiwp_sd3_io = CONFIG_BOOTLOADER_SPI_WP_PIN;
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#else
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psram_io.psram_spiwp_sd3_io = CONFIG_SPIRAM_SPIWP_SD3_PIN;
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#endif
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}
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}
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assert(mode < PSRAM_CACHE_MAX && "we don't support any other mode for now.");
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assert(mode < PSRAM_CACHE_MAX && "we don't support any other mode for now.");
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