From a8e3ad6bd9150c68264b84d97f3df1064d198ca2 Mon Sep 17 00:00:00 2001
From: Ivan Grokhotkov <ivan@espressif.com>
Date: Tue, 5 Nov 2019 14:42:43 +0100
Subject: [PATCH] bootloader: revert support for booting dual-core apps on
 single-core bootloader

---
 components/bootloader_support/CMakeLists.txt    |  3 +--
 .../bootloader_support/src/bootloader_init.c    | 17 -----------------
 .../bootloader_support/src/bootloader_utility.c |  6 +-----
 3 files changed, 2 insertions(+), 24 deletions(-)

diff --git a/components/bootloader_support/CMakeLists.txt b/components/bootloader_support/CMakeLists.txt
index 311dad0e2..e56a8803e 100644
--- a/components/bootloader_support/CMakeLists.txt
+++ b/components/bootloader_support/CMakeLists.txt
@@ -18,8 +18,7 @@ endif()
 
 if(BOOTLOADER_BUILD)
     set(include_dirs "include" "include_bootloader")
-    # freertos is included just for the CONFIG_FREERTOS_UNICORE macro
-    set(priv_requires micro-ecc spi_flash efuse freertos)
+    set(priv_requires micro-ecc spi_flash efuse)
     list(APPEND srcs
         "src/bootloader_init.c"
         "src/${IDF_TARGET}/bootloader_sha.c"
diff --git a/components/bootloader_support/src/bootloader_init.c b/components/bootloader_support/src/bootloader_init.c
index 45118aa95..5da6712e0 100644
--- a/components/bootloader_support/src/bootloader_init.c
+++ b/components/bootloader_support/src/bootloader_init.c
@@ -115,19 +115,13 @@ esp_err_t bootloader_init(void)
        (in case serial bootloader was running) */
 #if CONFIG_IDF_TARGET_ESP32
     Cache_Read_Disable(0);
-#if !CONFIG_FREERTOS_UNICORE
     Cache_Read_Disable(1);
-#endif
     Cache_Flush(0);
-#if !CONFIG_FREERTOS_UNICORE
     Cache_Flush(1);
-#endif
     mmu_init(0);
-#if !CONFIG_FREERTOS_UNICORE
     DPORT_REG_SET_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
     mmu_init(1);
     DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
-#endif
 #elif CONFIG_IDF_TARGET_ESP32S2BETA
     //TODO, save the autoload value
     Cache_Suspend_ICache();
@@ -146,9 +140,7 @@ esp_err_t bootloader_init(void)
     */
 #if CONFIG_IDF_TARGET_ESP32
     DPORT_REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MASK_DROM0);
-#if !CONFIG_FREERTOS_UNICORE
     DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DROM0);
-#endif
 #elif CONFIG_IDF_TARGET_ESP32S2BETA
     DPORT_REG_CLR_BIT(DPORT_PRO_ICACHE_CTRL1_REG, DPORT_PRO_ICACHE_MASK_DROM0);
 #endif
@@ -193,9 +185,6 @@ static esp_err_t bootloader_main(void)
     ESP_LOGI(TAG, "ESP-IDF %s 2nd stage bootloader", IDF_VER);
 
     ESP_LOGI(TAG, "compile time " __TIME__ );
-#if !CONFIG_FREERTOS_UNICORE
-    ets_set_appcpu_boot_addr(0);
-#endif
 
 #ifdef CONFIG_BOOTLOADER_WDT_ENABLE
     ESP_LOGD(TAG, "Enabling RTCWDT(%d ms)", CONFIG_BOOTLOADER_WDT_TIME_MS);
@@ -456,9 +445,7 @@ static void wdt_reset_info_dump(int cpu)
         lsstat  = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_REG);
         lsaddr  = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG);
         lsdata  = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG);
-
     } else {
-#if !CONFIG_FREERTOS_UNICORE
         stat    = DPORT_REG_READ(DPORT_APP_CPU_RECORD_STATUS_REG);
         pid     = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PID_REG);
         inst    = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGINST_REG);
@@ -468,10 +455,6 @@ static void wdt_reset_info_dump(int cpu)
         lsstat  = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGLS0STAT_REG);
         lsaddr  = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGLS0ADDR_REG);
         lsdata  = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGLS0DATA_REG);
-#else
-        ESP_LOGE(TAG, "WDT reset info: &s CPU not support!\n", cpu_name);
-        return;
-#endif
     }
 #elif CONFIG_IDF_TARGET_ESP32S2BETA
     stat    = 0xdeadbeef;
diff --git a/components/bootloader_support/src/bootloader_utility.c b/components/bootloader_support/src/bootloader_utility.c
index 613d5aa0d..16c534e63 100644
--- a/components/bootloader_support/src/bootloader_utility.c
+++ b/components/bootloader_support/src/bootloader_utility.c
@@ -700,7 +700,7 @@ static void set_cache_and_start_app(
                                 64, drom_page_count, 0);
 #endif
     ESP_LOGV(TAG, "rc=%d", rc);
-#if CONFIG_IDF_TARGET_ESP32 && !CONFIG_FREERTOS_UNICORE
+#if CONFIG_IDF_TARGET_ESP32
     rc = cache_flash_mmu_set(1, 0, drom_load_addr_aligned, drom_addr & MMU_FLASH_MASK, 64, drom_page_count);
     ESP_LOGV(TAG, "rc=%d", rc);
 #endif
@@ -734,20 +734,16 @@ static void set_cache_and_start_app(
 #endif
     ESP_LOGV(TAG, "rc=%d", rc);
 #if CONFIG_IDF_TARGET_ESP32
-#if !CONFIG_FREERTOS_UNICORE
     rc = cache_flash_mmu_set(1, 0, irom_load_addr_aligned, irom_addr & MMU_FLASH_MASK, 64, irom_page_count);
     ESP_LOGV(TAG, "rc=%d", rc);
-#endif
     DPORT_REG_CLR_BIT( DPORT_PRO_CACHE_CTRL1_REG,
                        (DPORT_PRO_CACHE_MASK_IRAM0) | (DPORT_PRO_CACHE_MASK_IRAM1 & 0) |
                        (DPORT_PRO_CACHE_MASK_IROM0 & 0) | DPORT_PRO_CACHE_MASK_DROM0 |
                        DPORT_PRO_CACHE_MASK_DRAM1 );
-#if !CONFIG_FREERTOS_UNICORE
     DPORT_REG_CLR_BIT( DPORT_APP_CACHE_CTRL1_REG,
                        (DPORT_APP_CACHE_MASK_IRAM0) | (DPORT_APP_CACHE_MASK_IRAM1 & 0) |
                        (DPORT_APP_CACHE_MASK_IROM0 & 0) | DPORT_APP_CACHE_MASK_DROM0 |
                        DPORT_APP_CACHE_MASK_DRAM1 );
-#endif
 #elif CONFIG_IDF_TARGET_ESP32S2BETA
     DPORT_REG_CLR_BIT( DPORT_PRO_ICACHE_CTRL1_REG, (DPORT_PRO_ICACHE_MASK_IRAM0) | (DPORT_PRO_ICACHE_MASK_IRAM1 & 0) | (DPORT_PRO_ICACHE_MASK_IROM0 & 0) | DPORT_PRO_ICACHE_MASK_DROM0 );
 #endif