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Merge branch 'bugfix/clean_up_WIFI_CLK_EN_settings' into 'master'

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refactor WIFI_CLK_EN settings

See merge request !1463
This commit is contained in:
Jiang Jiang Jian 2017-11-02 15:44:37 +08:00
parent da178e446d 42cefc173f
commit a77912fbdd
8 changed files with 45 additions and 12 deletions
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5
components/bt/bt.c
View file

@ -36,6 +36,7 @@
#include "esp_log.h"
#include "esp_pm.h"
#include "esp_ipc.h"
#include "driver/periph_ctrl.h"
#if CONFIG_BT_ENABLED
@ -482,6 +483,8 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
btdm_controller_mem_init();
periph_module_enable(PERIPH_BT_MODULE);
btdm_cfg_mask = btdm_config_mask_load();
ret = btdm_controller_init(btdm_cfg_mask, cfg);
@ -507,6 +510,8 @@ esp_err_t esp_bt_controller_deinit(void)
return ESP_ERR_NO_MEM;
}
periph_module_disable(PERIPH_BT_MODULE);
btdm_controller_status = ESP_BT_CONTROLLER_STATUS_IDLE;
#ifdef CONFIG_PM_ENABLE

2
components/bt/lib

@ -1 +1 @@
Subproject commit 9a8e4ee159e59bb7308f3b5f6fcb89049da48777
Subproject commit 8e62573de3dd9565b2209a3e8fe19a9900320b77

4
components/driver/include/driver/periph_ctrl.h
View file

@ -49,6 +49,10 @@ typedef enum {
PERIPH_SDIO_SLAVE_MODULE,
PERIPH_CAN_MODULE,
PERIPH_EMAC_MODULE,
PERIPH_RNG_MODULE,
PERIPH_WIFI_MODULE,
PERIPH_BT_MODULE,
PERIPH_WIFI_BT_COMMON_MODULE,
} periph_module_t;
/**

22
components/driver/periph_ctrl.c
View file

@ -106,6 +106,14 @@ static uint32_t get_clk_en_mask(periph_module_t periph)
return DPORT_CAN_CLK_EN;
case PERIPH_EMAC_MODULE:
return DPORT_WIFI_CLK_EMAC_EN;
case PERIPH_RNG_MODULE:
return DPORT_WIFI_CLK_RNG_EN;
case PERIPH_WIFI_MODULE:
return DPORT_WIFI_CLK_WIFI_EN_M;
case PERIPH_BT_MODULE:
return DPORT_WIFI_CLK_BT_EN_M;
case PERIPH_WIFI_BT_COMMON_MODULE:
return DPORT_WIFI_CLK_WIFI_BT_COMMON_M;
default:
return 0;
}
@ -159,13 +167,17 @@ static uint32_t get_rst_en_mask(periph_module_t periph)
case PERIPH_SPI_DMA_MODULE:
return DPORT_SPI_DMA_RST;
case PERIPH_SDMMC_MODULE:
return DPORT_WIFI_CLK_SDIO_HOST_EN;
return DPORT_SDIO_HOST_RST;
case PERIPH_SDIO_SLAVE_MODULE:
return DPORT_WIFI_CLK_SDIOSLAVE_EN;
return DPORT_SDIO_RST;
case PERIPH_CAN_MODULE:
return DPORT_CAN_RST;
case PERIPH_EMAC_MODULE:
return DPORT_WIFI_CLK_EMAC_EN;
return DPORT_EMAC_RST;
case PERIPH_WIFI_MODULE:
case PERIPH_BT_MODULE:
case PERIPH_WIFI_BT_COMMON_MODULE:
return 0;
default:
return 0;
}
@ -179,6 +191,10 @@ static bool is_wifi_clk_peripheral(periph_module_t periph)
case PERIPH_SDMMC_MODULE:
case PERIPH_SDIO_SLAVE_MODULE:
case PERIPH_EMAC_MODULE:
case PERIPH_RNG_MODULE:
case PERIPH_WIFI_MODULE:
case PERIPH_BT_MODULE:
case PERIPH_WIFI_BT_COMMON_MODULE:
return true;
default:
return false;

4
components/esp32/clk.c
View file

@ -29,6 +29,7 @@
#include "soc/rtc_cntl_reg.h"
#include "soc/dport_reg.h"
#include "soc/i2s_reg.h"
#include "driver/periph_ctrl.h"
#include "xtensa/core-macros.h"
/* Number of cycles to wait from the 32k XTAL oscillator to consider it running.
@ -236,4 +237,7 @@ void esp_perip_clk_init(void)
/* Disable WiFi/BT/SDIO clocks. */
DPORT_CLEAR_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, wifi_bt_sdio_clk);
/* Enable RNG clock. */
periph_module_enable(PERIPH_RNG_MODULE);
}

2
components/esp32/lib

@ -1 +1 @@
Subproject commit 4d59fe9623f5a7cab7ef4b0b4cda1772d4795631
Subproject commit f5733f50ce43bf54d18328499f3cf8cf61c7087d

9
components/esp32/phy_init.c
View file

@ -35,6 +35,7 @@
#include "phy.h"
#include "phy_init_data.h"
#include "esp_coexist.h"
#include "driver/periph_ctrl.h"
static const char* TAG = "phy_init";
@ -50,8 +51,8 @@ esp_err_t esp_phy_rf_init(const esp_phy_init_data_t* init_data,
_lock_acquire(&s_phy_rf_init_lock);
if (s_phy_rf_init_count == 0) {
// Enable WiFi peripheral clock
DPORT_SET_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_WIFI_EN | DPORT_WIFI_CLK_RNG_EN);
// Enable WiFi/BT common peripheral clock
periph_module_enable(PERIPH_WIFI_BT_COMMON_MODULE);
ESP_LOGV(TAG, "register_chipv7_phy, init_data=%p, cal_data=%p, mode=%d",
init_data, calibration_data, mode);
phy_set_wifi_mode_only(0);
@ -75,8 +76,8 @@ esp_err_t esp_phy_rf_deinit(void)
if (s_phy_rf_init_count == 1) {
// Disable PHY and RF.
phy_close_rf();
// Disable WiFi peripheral clock. Do not disable clock for hardware RNG
DPORT_CLEAR_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_WIFI_EN);
// Disable WiFi/BT common peripheral clock. Do not disable clock for hardware RNG
periph_module_disable(PERIPH_WIFI_BT_COMMON_MODULE);
} else {
#if CONFIG_SW_COEXIST_ENABLE
coex_deinit();

9
components/soc/esp32/include/soc/dport_reg.h
View file

@ -1043,16 +1043,19 @@
#define DPORT_WIFI_CLK_EN_V 0xFFFFFFFF
#define DPORT_WIFI_CLK_EN_S 0
/* Mask for all Wifi clock bits - 0, 1, 2, 3, 6, 7, 8, 9, 10, 15 */
#define DPORT_WIFI_CLK_WIFI_EN 0x000007cf
/* Mask for all Wifi clock bits - 1, 2, 10 */
#define DPORT_WIFI_CLK_WIFI_EN 0x00000406
#define DPORT_WIFI_CLK_WIFI_EN_M ((DPORT_WIFI_CLK_WIFI_EN_V)<<(DPORT_WIFI_CLK_WIFI_EN_S))
#define DPORT_WIFI_CLK_WIFI_EN_V 0x1FF
#define DPORT_WIFI_CLK_WIFI_EN_V 0x406
#define DPORT_WIFI_CLK_WIFI_EN_S 0
/* Mask for all Bluetooth clock bits - 11, 16, 17 */
#define DPORT_WIFI_CLK_BT_EN 0x61
#define DPORT_WIFI_CLK_BT_EN_M ((DPORT_WIFI_CLK_BT_EN_V)<<(DPORT_WIFI_CLK_BT_EN_S))
#define DPORT_WIFI_CLK_BT_EN_V 0x61
#define DPORT_WIFI_CLK_BT_EN_S 11
/* Mask for clock bits used by both WIFI and Bluetooth, bit 0, 3, 6, 7, 8, 9 */
#define DPORT_WIFI_CLK_WIFI_BT_COMMON_M 0x000003c9
/* Remaining single bit clock masks */
#define DPORT_WIFI_CLK_SDIOSLAVE_EN BIT(4)
#define DPORT_WIFI_CLK_UNUSED_BIT5 BIT(5)