From a6f990ffb91795d9168d099806b0cd431c0b7095 Mon Sep 17 00:00:00 2001 From: chenjianqiang Date: Mon, 20 May 2019 15:26:52 +0800 Subject: [PATCH] bugfix(flash): improve flash dio read timing When flash work in DIO Mode, in order to ensure the fast read mode of flash is a fixed value, we merged the mode bits into address part, and the fast read mode value is 0 (the default value). --- components/bootloader_support/src/bootloader_init.c | 5 +++-- components/esp32/include/rom/spi_flash.h | 3 ++- components/esp32/spiram_psram.c | 6 ++++-- components/spi_flash/spi_flash_rom_patch.c | 1 + 4 files changed, 10 insertions(+), 5 deletions(-) diff --git a/components/bootloader_support/src/bootloader_init.c b/components/bootloader_support/src/bootloader_init.c index 5ae8a5e81..520629bdd 100644 --- a/components/bootloader_support/src/bootloader_init.c +++ b/components/bootloader_support/src/bootloader_init.c @@ -320,10 +320,11 @@ static void IRAM_ATTR flash_gpio_configure(const esp_image_header_t* pfhdr) int drv = 2; switch (pfhdr->spi_mode) { case ESP_IMAGE_SPI_MODE_QIO: - spi_cache_dummy = SPI0_R_DIO_DUMMY_CYCLELEN; + spi_cache_dummy = SPI0_R_QIO_DUMMY_CYCLELEN; break; case ESP_IMAGE_SPI_MODE_DIO: - spi_cache_dummy = SPI0_R_DIO_DUMMY_CYCLELEN; //qio 3 + spi_cache_dummy = SPI0_R_DIO_DUMMY_CYCLELEN; + SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_ADDR_BITLEN_V, SPI0_R_DIO_ADDR_BITSLEN, SPI_USR_ADDR_BITLEN_S); break; case ESP_IMAGE_SPI_MODE_QOUT: case ESP_IMAGE_SPI_MODE_DOUT: diff --git a/components/esp32/include/rom/spi_flash.h b/components/esp32/include/rom/spi_flash.h index cc9856f45..165aaefe6 100644 --- a/components/esp32/include/rom/spi_flash.h +++ b/components/esp32/include/rom/spi_flash.h @@ -86,7 +86,8 @@ extern "C" { #define SPI0_R_QIO_DUMMY_CYCLELEN 3 #define SPI0_R_QIO_ADDR_BITSLEN 31 #define SPI0_R_FAST_DUMMY_CYCLELEN 7 -#define SPI0_R_DIO_DUMMY_CYCLELEN 3 +#define SPI0_R_DIO_DUMMY_CYCLELEN 1 +#define SPI0_R_DIO_ADDR_BITSLEN 27 #define SPI0_R_FAST_ADDR_BITSLEN 23 #define SPI0_R_SIO_ADDR_BITSLEN 23 diff --git a/components/esp32/spiram_psram.c b/components/esp32/spiram_psram.c index cbc25b09e..2e8e0a8c0 100644 --- a/components/esp32/spiram_psram.c +++ b/components/esp32/spiram_psram.c @@ -516,9 +516,11 @@ static void IRAM_ATTR psram_gpio_config(psram_io_t psram_io, psram_cache_mode_t { int spi_cache_dummy = 0; uint32_t rd_mode_reg = READ_PERI_REG(SPI_CTRL_REG(0)); - if (rd_mode_reg & (SPI_FREAD_QIO_M | SPI_FREAD_DIO_M)) { + if (rd_mode_reg & SPI_FREAD_QIO_M) { spi_cache_dummy = SPI0_R_QIO_DUMMY_CYCLELEN; - } else if (rd_mode_reg & (SPI_FREAD_QUAD_M | SPI_FREAD_DUAL_M)) { + } else if (rd_mode_reg & SPI_FREAD_DIO_M) { + spi_cache_dummy = SPI0_R_DIO_DUMMY_CYCLELEN; + } else if (rd_mode_reg & (SPI_FREAD_QUAD_M | SPI_FREAD_DUAL_M)) { spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN; } else { spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN; diff --git a/components/spi_flash/spi_flash_rom_patch.c b/components/spi_flash/spi_flash_rom_patch.c index ec59a1ff1..2d585ba44 100644 --- a/components/spi_flash/spi_flash_rom_patch.c +++ b/components/spi_flash/spi_flash_rom_patch.c @@ -322,6 +322,7 @@ static void spi_cache_mode_switch(uint32_t modebit) REG_SET_FIELD(SPI_USER2_REG(0), SPI_USR_COMMAND_VALUE, 0x6B); REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN, SPI0_R_FAST_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]); } else if ((modebit & SPI_FREAD_DIO)) { + REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_ADDR_BITLEN, SPI0_R_DIO_ADDR_BITSLEN); REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN, SPI0_R_DIO_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]); REG_SET_FIELD(SPI_USER2_REG(0), SPI_USR_COMMAND_VALUE, 0xBB); } else if ((modebit & SPI_FREAD_DUAL)) {