From 4132834faa15bf2ed9b3d02dddbdd869e2d0816c Mon Sep 17 00:00:00 2001
From: "Michael (XIAO Xufeng)" <xiaoxufeng@espressif.com>
Date: Wed, 31 Oct 2018 16:51:09 +0800
Subject: [PATCH] test: fix the unit test fail issue under single_core config

Introduced in 97e35429477b9877378ce9c4ec943ccc34318d42.

The previous commit frees the IRAM part when single core, but doesn't
change the memory layout functions. The unit test mallocs IRAM memory
from the heap, accidently into the new-released region, which doesn't
match the memory layout function.

This commit update the memory layout function to fix this.
---
 components/soc/esp32/include/soc/soc.h         | 4 ++++
 components/soc/esp32/soc_memory_layout.c       | 4 ++--
 components/soc/include/soc/soc_memory_layout.h | 4 ++++
 3 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/components/soc/esp32/include/soc/soc.h b/components/soc/esp32/include/soc/soc.h
index 15b77a363..c3cb55db8 100644
--- a/components/soc/esp32/include/soc/soc.h
+++ b/components/soc/esp32/include/soc/soc.h
@@ -286,6 +286,10 @@
 #define SOC_DROM_HIGH   0x3F800000
 #define SOC_IROM_LOW    0x400D0000
 #define SOC_IROM_HIGH   0x40400000
+#define SOC_CACHE_PRO_LOW   0x40070000
+#define SOC_CACHE_PRO_HIGH  0x40078000
+#define SOC_CACHE_APP_LOW   0x40078000
+#define SOC_CACHE_APP_HIGH  0x40080000
 #define SOC_IRAM_LOW    0x40080000
 #define SOC_IRAM_HIGH   0x400A0000
 #define SOC_RTC_IRAM_LOW  0x400C0000
diff --git a/components/soc/esp32/soc_memory_layout.c b/components/soc/esp32/soc_memory_layout.c
index de884cd45..b3adc08b8 100644
--- a/components/soc/esp32/soc_memory_layout.c
+++ b/components/soc/esp32/soc_memory_layout.c
@@ -130,9 +130,9 @@ const size_t soc_memory_region_count = sizeof(soc_memory_regions)/sizeof(soc_mem
 
    These are removed from the soc_memory_regions array when heaps are created.
  */
-SOC_RESERVE_MEMORY_REGION(0x40070000, 0x40078000, cpu0_cache);
+SOC_RESERVE_MEMORY_REGION(SOC_CACHE_PRO_LOW, SOC_CACHE_PRO_HIGH, cpu0_cache);
 #ifndef CONFIG_FREERTOS_UNICORE
-SOC_RESERVE_MEMORY_REGION(0x40078000, 0x40080000, cpu1_cache);
+SOC_RESERVE_MEMORY_REGION(SOC_CACHE_APP_LOW, SOC_CACHE_APP_HIGH, cpu1_cache);
 #endif
 
     /* Warning: The ROM stack is located in the 0x3ffe0000 area. We do not specifically disable that area here because
diff --git a/components/soc/include/soc/soc_memory_layout.h b/components/soc/include/soc/soc_memory_layout.h
index 8c9640483..68c87623c 100644
--- a/components/soc/include/soc/soc_memory_layout.h
+++ b/components/soc/include/soc/soc_memory_layout.h
@@ -175,7 +175,11 @@ inline static bool IRAM_ATTR esp_ptr_external_ram(const void *p) {
 }
 
 inline static bool IRAM_ATTR esp_ptr_in_iram(const void *p) {
+#ifndef CONFIG_FREERTOS_UNICORE
     return ((intptr_t)p >= SOC_IRAM_LOW && (intptr_t)p < SOC_IRAM_HIGH);
+#else
+    return ((intptr_t)p >= SOC_CACHE_APP_LOW && (intptr_t)p < SOC_IRAM_HIGH);
+#endif
 }
 
 inline static bool IRAM_ATTR esp_ptr_in_drom(const void *p) {