Merge branch 'feat/spi_caps_control_dummy' into 'master'
spi_flash: add caps for dummy output control See merge request espressif/esp-idf!7534
This commit is contained in:
commit
a3c9a864ab
6 changed files with 54 additions and 28 deletions
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@ -60,4 +60,9 @@
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//#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS
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//#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS
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//#define SOC_SPI_SUPPORT_CD_SIG
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//#define SOC_SPI_SUPPORT_CD_SIG
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#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(SPI_HOST) true
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// Peripheral supports DIO, DOUT, QIO, or QOUT
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#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(spi_dev) 1
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// Peripheral doesn't support output given level during its "dummy phase"
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#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT(spi_dev) 0
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@ -45,5 +45,21 @@
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#define SOC_SPI_SUPPORT_CD_SIG 1
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#define SOC_SPI_SUPPORT_CD_SIG 1
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#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1
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#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1
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#ifdef __cplusplus
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extern "C" {
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#endif
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struct spi_dev_s;
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extern volatile struct spi_dev_s GPSPI3;
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struct spi_mem_dev_s;
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extern volatile struct spi_mem_dev_s SPIMEM1;
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#ifdef __cplusplus
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}
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#endif
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// Peripheral supports DIO, DOUT, QIO, or QOUT
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// Peripheral supports DIO, DOUT, QIO, or QOUT
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#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(spi_dev) (!((void*)spi_dev == (void*)&GPSPI3))
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#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(spi_dev) (!((void*)spi_dev == (void*)&GPSPI3))
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// Peripheral supports output given level during its "dummy phase"
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#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT(spi_dev) ((void*)spi_dev == (void*)&SPIMEM1)
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@ -17,7 +17,7 @@
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extern "C" {
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extern "C" {
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#endif
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#endif
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typedef volatile struct {
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typedef volatile struct spi_mem_dev_s {
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union {
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union {
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struct {
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struct {
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uint32_t reserved0: 17; /*reserved*/
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uint32_t reserved0: 17; /*reserved*/
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@ -17,7 +17,7 @@
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extern "C" {
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extern "C" {
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#endif
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#endif
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typedef volatile struct {
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typedef volatile struct spi_dev_s {
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union {
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union {
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struct {
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struct {
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uint32_t conf_bitlen:23; /*Define the spi_clk cycles of SPI_CONF state. Can be configured in CONF state.*/
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uint32_t conf_bitlen:23; /*Define the spi_clk cycles of SPI_CONF state. Can be configured in CONF state.*/
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@ -55,12 +55,32 @@ esp_err_t spi_flash_hal_configure_host_io_mode(
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if (!SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(dev) && io_mode > SPI_FLASH_FASTRD) {
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if (!SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(dev) && io_mode > SPI_FLASH_FASTRD) {
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return ESP_ERR_NOT_SUPPORTED;
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return ESP_ERR_NOT_SUPPORTED;
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}
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}
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if (addr_bitlen > 24 && SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT(dev)) {
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/*
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* The extra address bits (24-addr_bitlen) are used to control the M7-M0 bits right after
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* the address field, to avoid the flash going into continuous read mode.
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*
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* On ESP32-S2 the MEMSPI (that SUPPORT_CONTROL_DUMMY_OUTPUT), the least significant
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* addr_bitlen bits of the address will be used, instead of the MSBs. The driver is
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* required to set the address according to the extra address bits.
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*
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* To reduce the time consuming for the read() function to calculate the shift of address,
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* the addr_bitlen is kept to 24 bits. And the CONTROL_DUMMY_OUTPUT feature is used to
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* control those bits instead.
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*/
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//This block is only reached when SPI_FLASH_QIO or SPI_FLASH_DIO
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assert(io_mode == SPI_FLASH_DIO || io_mode == SPI_FLASH_QIO);
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int line_width = (io_mode == SPI_FLASH_DIO? 2: 4);
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dummy_cyclelen_base += (addr_bitlen - 24) / line_width;
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addr_bitlen = 24;
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spi_flash_ll_set_dummy_out(dev, 1, 1);
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}
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spi_flash_ll_set_command8(dev, command);
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spi_flash_ll_set_command8(dev, command);
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spi_flash_ll_set_addr_bitlen(dev, addr_bitlen);
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spi_flash_ll_set_addr_bitlen(dev, addr_bitlen);
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// Add dummy cycles to compensate for latency of GPIO matrix and external delay, if necessary...
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// Add dummy cycles to compensate for latency of GPIO matrix and external delay, if necessary...
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spi_flash_ll_set_dummy(dev, COMPUTE_DUMMY_CYCLELEN(host, dummy_cyclelen_base));
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spi_flash_ll_set_dummy(dev, COMPUTE_DUMMY_CYCLELEN(host, dummy_cyclelen_base));
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spi_flash_ll_set_dummy_out(dev, 1, 1);
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//disable all data phases, enable them later if needed
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//disable all data phases, enable them later if needed
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spi_flash_ll_set_miso_bitlen(dev, 0);
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spi_flash_ll_set_miso_bitlen(dev, 0);
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spi_flash_ll_set_mosi_bitlen(dev, 0);
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spi_flash_ll_set_mosi_bitlen(dev, 0);
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@ -42,30 +42,15 @@
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#define CMD_RST_EN 0x66
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#define CMD_RST_EN 0x66
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#define CMD_RST_DEV 0x99
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#define CMD_RST_DEV 0x99
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#ifdef CONFIG_IDF_TARGET_ESP32S2
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#define SPI_FLASH_DIO_ADDR_BITLEN (24+4)
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#define SPI_FLASH_DIO_ADDR_BITLEN 24
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#define SPI_FLASH_DIO_DUMMY_BITLEN 2
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#define SPI_FLASH_DIO_DUMMY_BITLEN 4
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#define SPI_FLASH_QIO_ADDR_BITLEN (24+8)
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#define SPI_FLASH_QIO_ADDR_BITLEN 24
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#define SPI_FLASH_QIO_DUMMY_BITLEN 4
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#define SPI_FLASH_QIO_DUMMY_BITLEN 6
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#define SPI_FLASH_QOUT_ADDR_BITLEN 24
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#define SPI_FLASH_QOUT_ADDR_BITLEN 24
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#define SPI_FLASH_QOUT_DUMMY_BITLEN 8
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#define SPI_FLASH_QOUT_DUMMY_BITLEN 8
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#define SPI_FLASH_DOUT_ADDR_BITLEN 24
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#define SPI_FLASH_DOUT_ADDR_BITLEN 24
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#define SPI_FLASH_DOUT_DUMMY_BITLEN 8
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#define SPI_FLASH_DOUT_DUMMY_BITLEN 8
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#define SPI_FLASH_FASTRD_ADDR_BITLEN 24
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#define SPI_FLASH_FASTRD_ADDR_BITLEN 24
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#define SPI_FLASH_FASTRD_DUMMY_BITLEN 8
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#define SPI_FLASH_FASTRD_DUMMY_BITLEN 8
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#define SPI_FLASH_SLOWRD_ADDR_BITLEN 24
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#define SPI_FLASH_SLOWRD_ADDR_BITLEN 24
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#define SPI_FLASH_SLOWRD_DUMMY_BITLEN 0
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#define SPI_FLASH_SLOWRD_DUMMY_BITLEN 0
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#else
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#define SPI_FLASH_DIO_ADDR_BITLEN 28
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#define SPI_FLASH_DIO_DUMMY_BITLEN 2
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#define SPI_FLASH_QIO_ADDR_BITLEN 32
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#define SPI_FLASH_QIO_DUMMY_BITLEN 4
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#define SPI_FLASH_QOUT_ADDR_BITLEN 24
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#define SPI_FLASH_QOUT_DUMMY_BITLEN 8
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#define SPI_FLASH_DOUT_ADDR_BITLEN 24
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#define SPI_FLASH_DOUT_DUMMY_BITLEN 8
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#define SPI_FLASH_FASTRD_ADDR_BITLEN 24
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#define SPI_FLASH_FASTRD_DUMMY_BITLEN 8
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#define SPI_FLASH_SLOWRD_ADDR_BITLEN 24
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#define SPI_FLASH_SLOWRD_DUMMY_BITLEN 0
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#endif
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