diff --git a/components/esp32/clk.c b/components/esp32/clk.c
index 02a8caa17..7d17b4347 100644
--- a/components/esp32/clk.c
+++ b/components/esp32/clk.c
@@ -136,7 +136,7 @@ void esp_clk_init(void)
     rtc_clk_cpu_freq_set_config(&new_config);
 
     // Re calculate the ccount to make time calculation correct.
-    XTHAL_SET_CCOUNT( XTHAL_GET_CCOUNT() * new_freq_mhz / old_freq_mhz );
+    XTHAL_SET_CCOUNT( (uint64_t)XTHAL_GET_CCOUNT() * new_freq_mhz / old_freq_mhz );
 }
 
 int IRAM_ATTR esp_clk_cpu_freq(void)
diff --git a/components/soc/esp32/rtc_clk_init.c b/components/soc/esp32/rtc_clk_init.c
index ef1485311..4c0cddd02 100644
--- a/components/soc/esp32/rtc_clk_init.c
+++ b/components/soc/esp32/rtc_clk_init.c
@@ -128,7 +128,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
     REG_WRITE(APB_CTRL_PLL_TICK_CONF_REG, APB_CLK_FREQ / MHZ - 1); /* Under PLL, APB frequency is always 80MHz */
 
     /* Re-calculate the ccount to make time calculation correct. */
-    XTHAL_SET_CCOUNT( XTHAL_GET_CCOUNT() * cfg.cpu_freq_mhz / freq_before );
+    XTHAL_SET_CCOUNT( (uint64_t)XTHAL_GET_CCOUNT() * cfg.cpu_freq_mhz / freq_before );
 
     /* Slow & fast clocks setup */
     if (cfg.slow_freq == RTC_SLOW_FREQ_32K_XTAL) {