Fix up tests for stack not in psram on flash, add small testcase
This commit is contained in:
parent
05237496c2
commit
9f86a00fc3
9 changed files with 184 additions and 16 deletions
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@ -141,6 +141,7 @@ config MEMMAP_SPIRAM_TEST
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config MEMMAP_SPIRAM_ENABLE_MALLOC
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config MEMMAP_SPIRAM_ENABLE_MALLOC
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bool "malloc() can also allocate in SPI SRAM"
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bool "malloc() can also allocate in SPI SRAM"
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depends on !MEMMAP_SPIRAM_NO_HEAPALLOC
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default "n"
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default "n"
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help
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help
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If enabled, malloc() will return pointers to both internal as well as external
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If enabled, malloc() will return pointers to both internal as well as external
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@ -149,6 +149,30 @@ void heap_alloc_enable_nonos_stack_tag()
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nonos_stack_in_use=false;
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nonos_stack_in_use=false;
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}
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}
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bool esp32_ptr_has_memory_caps(void *ptr, int caps) {
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int tag=-1;
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//Look up region tag of pointer
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for (int i=0; regions[i].xSizeInBytes!=0; i++) {
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if (regions[i].xTag != -1 &&
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(uint8_t*)ptr >= regions[i].pucStartAddress &&
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(uint8_t*)ptr < regions[i].pucStartAddress+regions[i].xSizeInBytes) {
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tag=regions[i].xTag;
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break;
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}
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}
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if (tag==-1) return false;
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//Mask off all the caps the tag does have. What should remain is the caps the tag does not have.
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for (int i=0; i<NO_PRIOS; i++) caps&=~(tag_desc[tag].prio[i]);
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//If any remain, ptr does not have all given caps.
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return (caps==0);
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}
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bool esp32_task_stack_is_internal() {
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int i;
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return esp32_ptr_has_memory_caps(&i, MALLOC_CAP_INTERNAL);
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}
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//Modify regions array to disable the given range of memory.
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//Modify regions array to disable the given range of memory.
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static void disable_mem_region(void *from, void *to) {
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static void disable_mem_region(void *from, void *to) {
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int i;
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int i;
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@ -86,6 +86,26 @@ size_t xPortGetFreeHeapSizeCaps( uint32_t caps );
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*/
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*/
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size_t xPortGetMinimumEverFreeHeapSizeCaps( uint32_t caps );
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size_t xPortGetMinimumEverFreeHeapSizeCaps( uint32_t caps );
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/**
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* @brief Checks if a memory address resides in a memory region satisfying the given capabilities
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*
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* Given a pointer, this routine will look up the region it resides in. If the region
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* has _all_ the capabilities given in caps, it will return true. If this is not the case,
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* or the pointer address is unknown , false is returned.
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*
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* @param ptr Pointer to be investigated
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* @param caps Bitwise OR of MALLOC_CAP_* flags
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*
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* @return True if pointer region has all the given capabilities
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*/
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bool esp32_ptr_has_memory_caps(void *ptr, int caps);
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/**
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* @brief Convenience function to check if stack of currently-running task resides in internal memory
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*
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* @returns true if stack is in internal memory
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*/
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bool esp32_task_stack_is_internal();
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#endif
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#endif
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110
components/esp32/test/test_psram_cache_flush.c
Normal file
110
components/esp32/test/test_psram_cache_flush.c
Normal file
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@ -0,0 +1,110 @@
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/*
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This code triggers a psram-related silicon bug in rev0 silicon. The bug is fixed in rev1 silicon.
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*/
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#include <esp_types.h>
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#include <stdio.h>
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#include "rom/ets_sys.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/semphr.h"
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#include "freertos/queue.h"
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#include "freertos/xtensa_api.h"
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#include "unity.h"
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#include "soc/dport_reg.h"
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#include "soc/io_mux_reg.h"
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#include <stdint.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include "rom/ets_sys.h"
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#include "esp_heap_alloc_caps.h"
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#include "esp_spi_flash.h"
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#define TSTSZ (16*1024)
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volatile static int res[2];
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void tstMem(void *arg) {
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volatile unsigned char *mem=(volatile unsigned char*)arg;
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int p=0;
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while(1) {
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for (int i=0; i<TSTSZ; i++) {
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mem[i]=(i^p);
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}
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// vTaskDelay(1);
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for (int i=0; i<TSTSZ; i++) {
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if (mem[i]!=((i^p)&0xff)) {
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printf("Core %d mem err! Got %x espected %x at addr %p\n", xPortGetCoreID(), mem[i], (i^p)&0xff, &mem[i]);
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}
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}
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p++;
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res[xPortGetCoreID()]++;
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}
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}
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TEST_CASE("PSram cache flush on mmap", "[psram][ignore]")
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{
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void *mem[2];
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res[0]=0; res[1]=0;
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mem[0]=pvPortMallocCaps(TSTSZ, MALLOC_CAP_SPIRAM);
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mem[1]=pvPortMallocCaps(TSTSZ, MALLOC_CAP_SPIRAM);
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TaskHandle_t th[2];
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printf("Creating tasks\n");
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xTaskCreatePinnedToCore(tstMem , "tskone" , 2048, mem[0], 3, &th[0], 0);
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xTaskCreatePinnedToCore(tstMem , "tsktwo" , 2048, mem[1], 3, &th[1], 1);
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char buf[512];
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for (int i=0; i<4*1024*1024; i+=512) {
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spi_flash_read(i, buf, 512);
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vTaskDelay(1);
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}
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printf("Checked memory %d and %d times.\n", res[0], res[1]);
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vTaskDelete(th[0]);
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vTaskDelete(th[1]);
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free(mem[0]);
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free(mem[1]);
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}
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#define FLASHPOS (2*1024*1024-512)
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#define CYCLES 1024
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TEST_CASE("PSram cache flush on write/read", "[psram][ignore]")
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{
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void *mem[2];
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res[0]=0; res[1]=0;
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mem[0]=pvPortMallocCaps(TSTSZ, MALLOC_CAP_SPIRAM);
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mem[1]=pvPortMallocCaps(TSTSZ, MALLOC_CAP_SPIRAM);
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TaskHandle_t th[2];
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printf("Creating tasks\n");
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xTaskCreatePinnedToCore(tstMem , "tskone" , 2048, mem[0], 3, &th[0], 0);
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xTaskCreatePinnedToCore(tstMem , "tsktwo" , 2048, mem[1], 3, &th[1], 1);
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char buf[512];
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printf("Erasing sector...\n");
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spi_flash_erase_sector(FLASHPOS/4096);
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printf("Erased.\n");
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for (int i=0; i<CYCLES; i++) {
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printf("%d/%d\n", i, CYCLES);
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spi_flash_write(FLASHPOS, buf, 512);
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spi_flash_read(i, buf, 512);
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vTaskDelay(1);
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//if ((i%31)==0)
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}
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printf("Checked memory %d and %d times.\n", res[0], res[1]);
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vTaskDelete(th[0]);
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vTaskDelete(th[1]);
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free(mem[0]);
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free(mem[1]);
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}
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@ -510,7 +510,7 @@ static int vfs_fat_closedir(void* ctx, DIR* pdir)
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static struct dirent* vfs_fat_readdir(void* ctx, DIR* pdir)
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static struct dirent* vfs_fat_readdir(void* ctx, DIR* pdir)
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{
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{
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vfs_fat_dir_t* fat_dir = (vfs_fat_dir_t*) pdir;
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vfs_fat_dir_t* fat_dir = (vfs_fat_dir_t*) pdir;
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struct dirent* out_dirent;
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struct dirent* out_dirent=NULL;
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int err = vfs_fat_readdir_r(ctx, pdir, &fat_dir->cur_dirent, &out_dirent);
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int err = vfs_fat_readdir_r(ctx, pdir, &fat_dir->cur_dirent, &out_dirent);
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if (err != 0) {
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if (err != 0) {
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errno = err;
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errno = err;
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@ -31,7 +31,6 @@
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#include "esp_spi_flash.h"
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#include "esp_spi_flash.h"
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#include "esp_log.h"
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#include "esp_log.h"
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static void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t* saved_state);
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static void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t* saved_state);
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static void IRAM_ATTR spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_state);
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static void IRAM_ATTR spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_state);
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@ -32,6 +32,7 @@
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#include "esp_log.h"
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#include "esp_log.h"
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#include "cache_utils.h"
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#include "cache_utils.h"
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#include "esp_psram.h"
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#include "esp_psram.h"
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#include "esp_heap_alloc_caps.h"
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#ifndef NDEBUG
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#ifndef NDEBUG
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// Enable built-in checks in queue.h in debug builds
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// Enable built-in checks in queue.h in debug builds
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@ -31,6 +31,7 @@
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#include "esp_spi_flash.h"
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#include "esp_spi_flash.h"
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#include "esp_log.h"
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#include "esp_log.h"
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#include "cache_utils.h"
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#include "cache_utils.h"
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#include "esp_heap_alloc_caps.h"
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/* bytes erased by SPIEraseBlock() ROM function */
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/* bytes erased by SPIEraseBlock() ROM function */
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#define BLOCK_ERASE_SIZE 65536
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#define BLOCK_ERASE_SIZE 65536
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@ -102,6 +103,7 @@ size_t IRAM_ATTR spi_flash_get_chip_size()
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static inline void IRAM_ATTR spi_flash_guard_start()
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static inline void IRAM_ATTR spi_flash_guard_start()
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{
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{
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assert(esp32_task_stack_is_internal() && "SPI operation called from task which has its stack in external memory");
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if (s_flash_guard_ops && s_flash_guard_ops->start) {
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if (s_flash_guard_ops && s_flash_guard_ops->start) {
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s_flash_guard_ops->start();
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s_flash_guard_ops->start();
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}
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}
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@ -21,12 +21,10 @@ CONFIG_LOG_BOOTLOADER_LEVEL_WARN=y
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CONFIG_LOG_BOOTLOADER_LEVEL=2
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CONFIG_LOG_BOOTLOADER_LEVEL=2
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#
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#
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# Secure boot configuration
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# Security features
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#
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#
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CONFIG_SECURE_BOOTLOADER_DISABLED=y
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# CONFIG_SECURE_BOOT_ENABLED is not set
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# CONFIG_SECURE_BOOTLOADER_ONE_TIME_FLASH is not set
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# CONFIG_FLASH_ENCRYPTION_ENABLED is not set
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# CONFIG_SECURE_BOOTLOADER_REFLASHABLE is not set
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# CONFIG_SECURE_BOOTLOADER_ENABLED is not set
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#
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#
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# Serial flasher config
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# Serial flasher config
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@ -100,14 +98,12 @@ CONFIG_AWS_IOT_MQTT_PORT=8883
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CONFIG_BT_RESERVE_DRAM=0
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CONFIG_BT_RESERVE_DRAM=0
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#
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#
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# ESP32-specific config
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# ESP32-specific
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#
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#
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# CONFIG_ESP32_DEFAULT_CPU_FREQ_80 is not set
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# CONFIG_ESP32_DEFAULT_CPU_FREQ_80 is not set
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# CONFIG_ESP32_DEFAULT_CPU_FREQ_160 is not set
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# CONFIG_ESP32_DEFAULT_CPU_FREQ_160 is not set
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CONFIG_ESP32_DEFAULT_CPU_FREQ_240=y
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CONFIG_ESP32_DEFAULT_CPU_FREQ_240=y
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CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ=240
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CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ=240
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# CONFIG_ESP32_ENABLE_STACK_WIFI is not set
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# CONFIG_ESP32_ENABLE_STACK_BT is not set
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CONFIG_MEMMAP_SMP=y
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CONFIG_MEMMAP_SMP=y
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# CONFIG_MEMMAP_TRACEMEM is not set
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# CONFIG_MEMMAP_TRACEMEM is not set
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CONFIG_TRACEMEM_RESERVE_DRAM=0x0
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CONFIG_TRACEMEM_RESERVE_DRAM=0x0
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@ -115,14 +111,16 @@ CONFIG_TRACEMEM_RESERVE_DRAM=0x0
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# CONFIG_ESP32_ENABLE_COREDUMP_TO_UART is not set
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# CONFIG_ESP32_ENABLE_COREDUMP_TO_UART is not set
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CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE=y
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CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE=y
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# CONFIG_ESP32_ENABLE_COREDUMP is not set
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# CONFIG_ESP32_ENABLE_COREDUMP is not set
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CONFIG_MEMMAP_SPIRAM_ENABLE=y
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CONFIG_MEMMAP_SPIRAM_TYPE_ESPPSRAM32=y
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CONFIG_MEMMAP_SPIRAM_SIZE=4194304
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# CONFIG_MEMMAP_SPIRAM_NO_HEAPALLOC is not set
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CONFIG_MEMMAP_SPIRAM_TEST=y
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CONFIG_MEMMAP_SPIRAM_ENABLE_MALLOC=y
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CONFIG_MEMMAP_SPIRAM_ALLOC_LIMIT_INTERNAL=40960
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# CONFIG_TWO_MAC_ADDRESS_FROM_EFUSE is not set
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# CONFIG_TWO_MAC_ADDRESS_FROM_EFUSE is not set
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CONFIG_FOUR_MAC_ADDRESS_FROM_EFUSE=y
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CONFIG_FOUR_MAC_ADDRESS_FROM_EFUSE=y
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CONFIG_NUMBER_OF_MAC_ADDRESS_GENERATED_FROM_EFUSE=4
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CONFIG_NUMBER_OF_MAC_ADDRESS_GENERATED_FROM_EFUSE=4
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CONFIG_MEMMAP_SPIRAM_ENABLE=y
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CONFIG_MEMMAP_SPIRAM_TYPE_ESPPSRAM32=y
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CONFIG_MEMMAP_SPIRAM_TEST=y
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CONFIG_MEMMAP_SPIRAM_ENABLE_MALLOC=y
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CONFIG_MEMMAP_SPIRAM_ALLOC_LIMIT_INTERNAL=1024
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CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32
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CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32
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CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2048
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CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2048
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CONFIG_MAIN_TASK_STACK_SIZE=4096
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CONFIG_MAIN_TASK_STACK_SIZE=4096
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@ -163,6 +161,7 @@ CONFIG_PHY_ENABLED=y
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#
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#
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CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y
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CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y
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# CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION is not set
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# CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION is not set
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CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20
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CONFIG_ESP32_PHY_MAX_TX_POWER=20
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CONFIG_ESP32_PHY_MAX_TX_POWER=20
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# CONFIG_ETHERNET is not set
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# CONFIG_ETHERNET is not set
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@ -172,7 +171,6 @@ CONFIG_ESP32_PHY_MAX_TX_POWER=20
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# CONFIG_FREERTOS_UNICORE is not set
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# CONFIG_FREERTOS_UNICORE is not set
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CONFIG_FREERTOS_CORETIMER_0=y
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CONFIG_FREERTOS_CORETIMER_0=y
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# CONFIG_FREERTOS_CORETIMER_1 is not set
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# CONFIG_FREERTOS_CORETIMER_1 is not set
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# CONFIG_FREERTOS_CORETIMER_2 is not set
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CONFIG_FREERTOS_HZ=1000
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CONFIG_FREERTOS_HZ=1000
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CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION=y
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CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION=y
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# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE is not set
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# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE is not set
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@ -209,7 +207,13 @@ CONFIG_LOG_COLORS=y
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CONFIG_LWIP_MAX_SOCKETS=4
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CONFIG_LWIP_MAX_SOCKETS=4
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CONFIG_LWIP_THREAD_LOCAL_STORAGE_INDEX=0
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CONFIG_LWIP_THREAD_LOCAL_STORAGE_INDEX=0
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# CONFIG_LWIP_SO_REUSE is not set
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# CONFIG_LWIP_SO_REUSE is not set
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# CONFIG_LWIP_SO_RCVBUF is not set
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CONFIG_LWIP_DHCP_MAX_NTP_SERVERS=1
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CONFIG_LWIP_DHCP_MAX_NTP_SERVERS=1
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# CONFIG_LWIP_IP_FRAG is not set
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# CONFIG_LWIP_IP_REASSEMBLY is not set
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CONFIG_TCP_MAXRTX=12
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CONFIG_TCP_SYNMAXRTX=6
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CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y
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#
|
#
|
||||||
# mbedTLS
|
# mbedTLS
|
||||||
|
@ -223,6 +227,13 @@ CONFIG_MBEDTLS_HARDWARE_SHA=y
|
||||||
CONFIG_MBEDTLS_HAVE_TIME=y
|
CONFIG_MBEDTLS_HAVE_TIME=y
|
||||||
# CONFIG_MBEDTLS_HAVE_TIME_DATE is not set
|
# CONFIG_MBEDTLS_HAVE_TIME_DATE is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# OpenSSL
|
||||||
|
#
|
||||||
|
# CONFIG_OPENSSL_DEBUG is not set
|
||||||
|
CONFIG_OPENSSL_ASSERT_DO_NOTHING=y
|
||||||
|
# CONFIG_OPENSSL_ASSERT_EXIT is not set
|
||||||
|
|
||||||
#
|
#
|
||||||
# SPI Flash driver
|
# SPI Flash driver
|
||||||
#
|
#
|
||||||
|
|
Loading…
Reference in a new issue