From 724673be8359473b84222aa62cb0253738f9c06e Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Thu, 23 Mar 2017 15:20:05 +0800 Subject: [PATCH 1/5] soc: add apb_ctrl, struct headers for rtc_cntl and rtc_io --- components/esp32/include/soc/apb_ctrl_reg.h | 294 ++++++++++ .../esp32/include/soc/apb_ctrl_struct.h | 120 ++++ .../esp32/include/soc/rtc_cntl_struct.h | 553 ++++++++++++++++++ components/esp32/include/soc/rtc_io_struct.h | 280 +++++++++ components/esp32/include/soc/soc.h | 1 + 5 files changed, 1248 insertions(+) create mode 100644 components/esp32/include/soc/apb_ctrl_reg.h create mode 100644 components/esp32/include/soc/apb_ctrl_struct.h create mode 100644 components/esp32/include/soc/rtc_cntl_struct.h create mode 100644 components/esp32/include/soc/rtc_io_struct.h diff --git a/components/esp32/include/soc/apb_ctrl_reg.h b/components/esp32/include/soc/apb_ctrl_reg.h new file mode 100644 index 000000000..2e5ea54c4 --- /dev/null +++ b/components/esp32/include/soc/apb_ctrl_reg.h @@ -0,0 +1,294 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_APB_CTRL_REG_H_ +#define _SOC_APB_CTRL_REG_H_ + +#include "soc.h" +#define APB_CTRL_SYSCLK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x0) +/* APB_CTRL_QUICK_CLK_CHNG : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: */ +#define APB_CTRL_QUICK_CLK_CHNG (BIT(13)) +#define APB_CTRL_QUICK_CLK_CHNG_M (BIT(13)) +#define APB_CTRL_QUICK_CLK_CHNG_V 0x1 +#define APB_CTRL_QUICK_CLK_CHNG_S 13 +/* APB_CTRL_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define APB_CTRL_RST_TICK_CNT (BIT(12)) +#define APB_CTRL_RST_TICK_CNT_M (BIT(12)) +#define APB_CTRL_RST_TICK_CNT_V 0x1 +#define APB_CTRL_RST_TICK_CNT_S 12 +/* APB_CTRL_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define APB_CTRL_CLK_EN (BIT(11)) +#define APB_CTRL_CLK_EN_M (BIT(11)) +#define APB_CTRL_CLK_EN_V 0x1 +#define APB_CTRL_CLK_EN_S 11 +/* APB_CTRL_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define APB_CTRL_CLK_320M_EN (BIT(10)) +#define APB_CTRL_CLK_320M_EN_M (BIT(10)) +#define APB_CTRL_CLK_320M_EN_V 0x1 +#define APB_CTRL_CLK_320M_EN_S 10 +/* APB_CTRL_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: */ +#define APB_CTRL_PRE_DIV_CNT 0x000003FF +#define APB_CTRL_PRE_DIV_CNT_M ((APB_CTRL_PRE_DIV_CNT_V)<<(APB_CTRL_PRE_DIV_CNT_S)) +#define APB_CTRL_PRE_DIV_CNT_V 0x3FF +#define APB_CTRL_PRE_DIV_CNT_S 0 + +#define APB_CTRL_XTAL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x4) +/* APB_CTRL_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */ +/*description: */ +#define APB_CTRL_XTAL_TICK_NUM 0x000000FF +#define APB_CTRL_XTAL_TICK_NUM_M ((APB_CTRL_XTAL_TICK_NUM_V)<<(APB_CTRL_XTAL_TICK_NUM_S)) +#define APB_CTRL_XTAL_TICK_NUM_V 0xFF +#define APB_CTRL_XTAL_TICK_NUM_S 0 + +#define APB_CTRL_PLL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x8) +/* APB_CTRL_PLL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd79 ; */ +/*description: */ +#define APB_CTRL_PLL_TICK_NUM 0x000000FF +#define APB_CTRL_PLL_TICK_NUM_M ((APB_CTRL_PLL_TICK_NUM_V)<<(APB_CTRL_PLL_TICK_NUM_S)) +#define APB_CTRL_PLL_TICK_NUM_V 0xFF +#define APB_CTRL_PLL_TICK_NUM_S 0 + +#define APB_CTRL_CK8M_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0xC) +/* APB_CTRL_CK8M_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd11 ; */ +/*description: */ +#define APB_CTRL_CK8M_TICK_NUM 0x000000FF +#define APB_CTRL_CK8M_TICK_NUM_M ((APB_CTRL_CK8M_TICK_NUM_V)<<(APB_CTRL_CK8M_TICK_NUM_S)) +#define APB_CTRL_CK8M_TICK_NUM_V 0xFF +#define APB_CTRL_CK8M_TICK_NUM_S 0 + +#define APB_CTRL_APB_SARADC_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x10) +/* APB_CTRL_SARADC_DATA_TO_I2S : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: 1: I2S input data is from SAR ADC (for DMA) 0: I2S input data + is from GPIO matrix*/ +#define APB_CTRL_SARADC_DATA_TO_I2S (BIT(26)) +#define APB_CTRL_SARADC_DATA_TO_I2S_M (BIT(26)) +#define APB_CTRL_SARADC_DATA_TO_I2S_V 0x1 +#define APB_CTRL_SARADC_DATA_TO_I2S_S 26 +/* APB_CTRL_SARADC_DATA_SAR_SEL : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: 1: sar_sel will be coded by the MSB of the 16-bit output data + in this case the resolution should not be larger than 11 bits.*/ +#define APB_CTRL_SARADC_DATA_SAR_SEL (BIT(25)) +#define APB_CTRL_SARADC_DATA_SAR_SEL_M (BIT(25)) +#define APB_CTRL_SARADC_DATA_SAR_SEL_V 0x1 +#define APB_CTRL_SARADC_DATA_SAR_SEL_S 25 +/* APB_CTRL_SARADC_SAR2_PATT_P_CLEAR : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: clear the pointer of pattern table for DIG ADC2 CTRL*/ +#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR (BIT(24)) +#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_M (BIT(24)) +#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_V 0x1 +#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_S 24 +/* APB_CTRL_SARADC_SAR1_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */ +/*description: clear the pointer of pattern table for DIG ADC1 CTRL*/ +#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR (BIT(23)) +#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_M (BIT(23)) +#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_V 0x1 +#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_S 23 +/* APB_CTRL_SARADC_SAR2_PATT_LEN : R/W ;bitpos:[22:19] ;default: 4'd15 ; */ +/*description: 0 ~ 15 means length 1 ~ 16*/ +#define APB_CTRL_SARADC_SAR2_PATT_LEN 0x0000000F +#define APB_CTRL_SARADC_SAR2_PATT_LEN_M ((APB_CTRL_SARADC_SAR2_PATT_LEN_V)<<(APB_CTRL_SARADC_SAR2_PATT_LEN_S)) +#define APB_CTRL_SARADC_SAR2_PATT_LEN_V 0xF +#define APB_CTRL_SARADC_SAR2_PATT_LEN_S 19 +/* APB_CTRL_SARADC_SAR1_PATT_LEN : R/W ;bitpos:[18:15] ;default: 4'd15 ; */ +/*description: 0 ~ 15 means length 1 ~ 16*/ +#define APB_CTRL_SARADC_SAR1_PATT_LEN 0x0000000F +#define APB_CTRL_SARADC_SAR1_PATT_LEN_M ((APB_CTRL_SARADC_SAR1_PATT_LEN_V)<<(APB_CTRL_SARADC_SAR1_PATT_LEN_S)) +#define APB_CTRL_SARADC_SAR1_PATT_LEN_V 0xF +#define APB_CTRL_SARADC_SAR1_PATT_LEN_S 15 +/* APB_CTRL_SARADC_SAR_CLK_DIV : R/W ;bitpos:[14:7] ;default: 8'd4 ; */ +/*description: SAR clock divider*/ +#define APB_CTRL_SARADC_SAR_CLK_DIV 0x000000FF +#define APB_CTRL_SARADC_SAR_CLK_DIV_M ((APB_CTRL_SARADC_SAR_CLK_DIV_V)<<(APB_CTRL_SARADC_SAR_CLK_DIV_S)) +#define APB_CTRL_SARADC_SAR_CLK_DIV_V 0xFF +#define APB_CTRL_SARADC_SAR_CLK_DIV_S 7 +/* APB_CTRL_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: */ +#define APB_CTRL_SARADC_SAR_CLK_GATED (BIT(6)) +#define APB_CTRL_SARADC_SAR_CLK_GATED_M (BIT(6)) +#define APB_CTRL_SARADC_SAR_CLK_GATED_V 0x1 +#define APB_CTRL_SARADC_SAR_CLK_GATED_S 6 +/* APB_CTRL_SARADC_SAR_SEL : R/W ;bitpos:[5] ;default: 1'd0 ; */ +/*description: 0: SAR1 1: SAR2 only work for single SAR mode*/ +#define APB_CTRL_SARADC_SAR_SEL (BIT(5)) +#define APB_CTRL_SARADC_SAR_SEL_M (BIT(5)) +#define APB_CTRL_SARADC_SAR_SEL_V 0x1 +#define APB_CTRL_SARADC_SAR_SEL_S 5 +/* APB_CTRL_SARADC_WORK_MODE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */ +/*description: 0: single mode 1: double mode 2: alternate mode*/ +#define APB_CTRL_SARADC_WORK_MODE 0x00000003 +#define APB_CTRL_SARADC_WORK_MODE_M ((APB_CTRL_SARADC_WORK_MODE_V)<<(APB_CTRL_SARADC_WORK_MODE_S)) +#define APB_CTRL_SARADC_WORK_MODE_V 0x3 +#define APB_CTRL_SARADC_WORK_MODE_S 3 +/* APB_CTRL_SARADC_SAR2_MUX : R/W ;bitpos:[2] ;default: 1'd0 ; */ +/*description: 1: SAR ADC2 is controlled by DIG ADC2 CTRL 0: SAR ADC2 is controlled + by PWDET CTRL*/ +#define APB_CTRL_SARADC_SAR2_MUX (BIT(2)) +#define APB_CTRL_SARADC_SAR2_MUX_M (BIT(2)) +#define APB_CTRL_SARADC_SAR2_MUX_V 0x1 +#define APB_CTRL_SARADC_SAR2_MUX_S 2 +/* APB_CTRL_SARADC_START : R/W ;bitpos:[1] ;default: 1'd0 ; */ +/*description: */ +#define APB_CTRL_SARADC_START (BIT(1)) +#define APB_CTRL_SARADC_START_M (BIT(1)) +#define APB_CTRL_SARADC_START_V 0x1 +#define APB_CTRL_SARADC_START_S 1 +/* APB_CTRL_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define APB_CTRL_SARADC_START_FORCE (BIT(0)) +#define APB_CTRL_SARADC_START_FORCE_M (BIT(0)) +#define APB_CTRL_SARADC_START_FORCE_V 0x1 +#define APB_CTRL_SARADC_START_FORCE_S 0 + +#define APB_CTRL_APB_SARADC_CTRL2_REG (DR_REG_APB_CTRL_BASE + 0x14) +/* APB_CTRL_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: 1: data to DIG ADC2 CTRL is inverted otherwise not*/ +#define APB_CTRL_SARADC_SAR2_INV (BIT(10)) +#define APB_CTRL_SARADC_SAR2_INV_M (BIT(10)) +#define APB_CTRL_SARADC_SAR2_INV_V 0x1 +#define APB_CTRL_SARADC_SAR2_INV_S 10 +/* APB_CTRL_SARADC_SAR1_INV : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: 1: data to DIG ADC1 CTRL is inverted otherwise not*/ +#define APB_CTRL_SARADC_SAR1_INV (BIT(9)) +#define APB_CTRL_SARADC_SAR1_INV_M (BIT(9)) +#define APB_CTRL_SARADC_SAR1_INV_V 0x1 +#define APB_CTRL_SARADC_SAR1_INV_S 9 +/* APB_CTRL_SARADC_MAX_MEAS_NUM : R/W ;bitpos:[8:1] ;default: 8'd255 ; */ +/*description: max conversion number*/ +#define APB_CTRL_SARADC_MAX_MEAS_NUM 0x000000FF +#define APB_CTRL_SARADC_MAX_MEAS_NUM_M ((APB_CTRL_SARADC_MAX_MEAS_NUM_V)<<(APB_CTRL_SARADC_MAX_MEAS_NUM_S)) +#define APB_CTRL_SARADC_MAX_MEAS_NUM_V 0xFF +#define APB_CTRL_SARADC_MAX_MEAS_NUM_S 1 +/* APB_CTRL_SARADC_MEAS_NUM_LIMIT : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define APB_CTRL_SARADC_MEAS_NUM_LIMIT (BIT(0)) +#define APB_CTRL_SARADC_MEAS_NUM_LIMIT_M (BIT(0)) +#define APB_CTRL_SARADC_MEAS_NUM_LIMIT_V 0x1 +#define APB_CTRL_SARADC_MEAS_NUM_LIMIT_S 0 + +#define APB_CTRL_APB_SARADC_FSM_REG (DR_REG_APB_CTRL_BASE + 0x18) +/* APB_CTRL_SARADC_SAMPLE_CYCLE : R/W ;bitpos:[31:24] ;default: 8'd2 ; */ +/*description: sample cycles*/ +#define APB_CTRL_SARADC_SAMPLE_CYCLE 0x000000FF +#define APB_CTRL_SARADC_SAMPLE_CYCLE_M ((APB_CTRL_SARADC_SAMPLE_CYCLE_V)<<(APB_CTRL_SARADC_SAMPLE_CYCLE_S)) +#define APB_CTRL_SARADC_SAMPLE_CYCLE_V 0xFF +#define APB_CTRL_SARADC_SAMPLE_CYCLE_S 24 +/* APB_CTRL_SARADC_START_WAIT : R/W ;bitpos:[23:16] ;default: 8'd8 ; */ +/*description: */ +#define APB_CTRL_SARADC_START_WAIT 0x000000FF +#define APB_CTRL_SARADC_START_WAIT_M ((APB_CTRL_SARADC_START_WAIT_V)<<(APB_CTRL_SARADC_START_WAIT_S)) +#define APB_CTRL_SARADC_START_WAIT_V 0xFF +#define APB_CTRL_SARADC_START_WAIT_S 16 +/* APB_CTRL_SARADC_STANDBY_WAIT : R/W ;bitpos:[15:8] ;default: 8'd255 ; */ +/*description: */ +#define APB_CTRL_SARADC_STANDBY_WAIT 0x000000FF +#define APB_CTRL_SARADC_STANDBY_WAIT_M ((APB_CTRL_SARADC_STANDBY_WAIT_V)<<(APB_CTRL_SARADC_STANDBY_WAIT_S)) +#define APB_CTRL_SARADC_STANDBY_WAIT_V 0xFF +#define APB_CTRL_SARADC_STANDBY_WAIT_S 8 +/* APB_CTRL_SARADC_RSTB_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */ +/*description: */ +#define APB_CTRL_SARADC_RSTB_WAIT 0x000000FF +#define APB_CTRL_SARADC_RSTB_WAIT_M ((APB_CTRL_SARADC_RSTB_WAIT_V)<<(APB_CTRL_SARADC_RSTB_WAIT_S)) +#define APB_CTRL_SARADC_RSTB_WAIT_V 0xFF +#define APB_CTRL_SARADC_RSTB_WAIT_S 0 + +#define APB_CTRL_APB_SARADC_SAR1_PATT_TAB1_REG (DR_REG_APB_CTRL_BASE + 0x1C) +/* APB_CTRL_SARADC_SAR1_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: item 0 ~ 3 for pattern table 1 (each item one byte)*/ +#define APB_CTRL_SARADC_SAR1_PATT_TAB1 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR1_PATT_TAB1_M ((APB_CTRL_SARADC_SAR1_PATT_TAB1_V)<<(APB_CTRL_SARADC_SAR1_PATT_TAB1_S)) +#define APB_CTRL_SARADC_SAR1_PATT_TAB1_V 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR1_PATT_TAB1_S 0 + +#define APB_CTRL_APB_SARADC_SAR1_PATT_TAB2_REG (DR_REG_APB_CTRL_BASE + 0x20) +/* APB_CTRL_SARADC_SAR1_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: Item 4 ~ 7 for pattern table 1 (each item one byte)*/ +#define APB_CTRL_SARADC_SAR1_PATT_TAB2 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR1_PATT_TAB2_M ((APB_CTRL_SARADC_SAR1_PATT_TAB2_V)<<(APB_CTRL_SARADC_SAR1_PATT_TAB2_S)) +#define APB_CTRL_SARADC_SAR1_PATT_TAB2_V 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR1_PATT_TAB2_S 0 + +#define APB_CTRL_APB_SARADC_SAR1_PATT_TAB3_REG (DR_REG_APB_CTRL_BASE + 0x24) +/* APB_CTRL_SARADC_SAR1_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: Item 8 ~ 11 for pattern table 1 (each item one byte)*/ +#define APB_CTRL_SARADC_SAR1_PATT_TAB3 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR1_PATT_TAB3_M ((APB_CTRL_SARADC_SAR1_PATT_TAB3_V)<<(APB_CTRL_SARADC_SAR1_PATT_TAB3_S)) +#define APB_CTRL_SARADC_SAR1_PATT_TAB3_V 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR1_PATT_TAB3_S 0 + +#define APB_CTRL_APB_SARADC_SAR1_PATT_TAB4_REG (DR_REG_APB_CTRL_BASE + 0x28) +/* APB_CTRL_SARADC_SAR1_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: Item 12 ~ 15 for pattern table 1 (each item one byte)*/ +#define APB_CTRL_SARADC_SAR1_PATT_TAB4 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR1_PATT_TAB4_M ((APB_CTRL_SARADC_SAR1_PATT_TAB4_V)<<(APB_CTRL_SARADC_SAR1_PATT_TAB4_S)) +#define APB_CTRL_SARADC_SAR1_PATT_TAB4_V 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR1_PATT_TAB4_S 0 + +#define APB_CTRL_APB_SARADC_SAR2_PATT_TAB1_REG (DR_REG_APB_CTRL_BASE + 0x2C) +/* APB_CTRL_SARADC_SAR2_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: item 0 ~ 3 for pattern table 2 (each item one byte)*/ +#define APB_CTRL_SARADC_SAR2_PATT_TAB1 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR2_PATT_TAB1_M ((APB_CTRL_SARADC_SAR2_PATT_TAB1_V)<<(APB_CTRL_SARADC_SAR2_PATT_TAB1_S)) +#define APB_CTRL_SARADC_SAR2_PATT_TAB1_V 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR2_PATT_TAB1_S 0 + +#define APB_CTRL_APB_SARADC_SAR2_PATT_TAB2_REG (DR_REG_APB_CTRL_BASE + 0x30) +/* APB_CTRL_SARADC_SAR2_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: Item 4 ~ 7 for pattern table 2 (each item one byte)*/ +#define APB_CTRL_SARADC_SAR2_PATT_TAB2 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR2_PATT_TAB2_M ((APB_CTRL_SARADC_SAR2_PATT_TAB2_V)<<(APB_CTRL_SARADC_SAR2_PATT_TAB2_S)) +#define APB_CTRL_SARADC_SAR2_PATT_TAB2_V 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR2_PATT_TAB2_S 0 + +#define APB_CTRL_APB_SARADC_SAR2_PATT_TAB3_REG (DR_REG_APB_CTRL_BASE + 0x34) +/* APB_CTRL_SARADC_SAR2_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: Item 8 ~ 11 for pattern table 2 (each item one byte)*/ +#define APB_CTRL_SARADC_SAR2_PATT_TAB3 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR2_PATT_TAB3_M ((APB_CTRL_SARADC_SAR2_PATT_TAB3_V)<<(APB_CTRL_SARADC_SAR2_PATT_TAB3_S)) +#define APB_CTRL_SARADC_SAR2_PATT_TAB3_V 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR2_PATT_TAB3_S 0 + +#define APB_CTRL_APB_SARADC_SAR2_PATT_TAB4_REG (DR_REG_APB_CTRL_BASE + 0x38) +/* APB_CTRL_SARADC_SAR2_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: Item 12 ~ 15 for pattern table 2 (each item one byte)*/ +#define APB_CTRL_SARADC_SAR2_PATT_TAB4 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR2_PATT_TAB4_M ((APB_CTRL_SARADC_SAR2_PATT_TAB4_V)<<(APB_CTRL_SARADC_SAR2_PATT_TAB4_S)) +#define APB_CTRL_SARADC_SAR2_PATT_TAB4_V 0xFFFFFFFF +#define APB_CTRL_SARADC_SAR2_PATT_TAB4_S 0 + +#define APB_CTRL_APLL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x3C) +/* APB_CTRL_APLL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd99 ; */ +/*description: */ +#define APB_CTRL_APLL_TICK_NUM 0x000000FF +#define APB_CTRL_APLL_TICK_NUM_M ((APB_CTRL_APLL_TICK_NUM_V)<<(APB_CTRL_APLL_TICK_NUM_S)) +#define APB_CTRL_APLL_TICK_NUM_V 0xFF +#define APB_CTRL_APLL_TICK_NUM_S 0 + +#define APB_CTRL_DATE_REG (DR_REG_APB_CTRL_BASE + 0x7C) +/* APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h16042000 ; */ +/*description: */ +#define APB_CTRL_DATE 0xFFFFFFFF +#define APB_CTRL_DATE_M ((APB_CTRL_DATE_V)<<(APB_CTRL_DATE_S)) +#define APB_CTRL_DATE_V 0xFFFFFFFF +#define APB_CTRL_DATE_S 0 + + + + +#endif /*_SOC_APB_CTRL_REG_H_ */ + + diff --git a/components/esp32/include/soc/apb_ctrl_struct.h b/components/esp32/include/soc/apb_ctrl_struct.h new file mode 100644 index 000000000..d25967838 --- /dev/null +++ b/components/esp32/include/soc/apb_ctrl_struct.h @@ -0,0 +1,120 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_APB_CTRL_STRUCT_H_ +#define _SOC_APB_CTRL_STRUCT_H_ +typedef struct { + union { + struct { + volatile uint32_t pre_div: 10; + volatile uint32_t clk_320m_en: 1; + volatile uint32_t clk_en: 1; + volatile uint32_t rst_tick: 1; + volatile uint32_t quick_clk_chng: 1; + volatile uint32_t reserved14: 18; + }; + volatile uint32_t val; + }clk_conf; + union { + struct { + volatile uint32_t xtal_tick: 8; + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }xtal_tick_conf; + union { + struct { + volatile uint32_t pll_tick: 8; + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }pll_tick_conf; + union { + struct { + volatile uint32_t ck8m_tick: 8; + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }ck8m_tick_conf; + union { + struct { + volatile uint32_t start_force: 1; + volatile uint32_t start: 1; + volatile uint32_t sar2_mux: 1; /*1: SAR ADC2 is controlled by DIG ADC2 CTRL 0: SAR ADC2 is controlled by PWDET CTRL*/ + volatile uint32_t work_mode: 2; /*0: single mode 1: double mode 2: alternate mode*/ + volatile uint32_t sar_sel: 1; /*0: SAR1 1: SAR2 only work for single SAR mode*/ + volatile uint32_t sar_clk_gated: 1; + volatile uint32_t sar_clk_div: 8; /*SAR clock divider*/ + volatile uint32_t sar1_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/ + volatile uint32_t sar2_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/ + volatile uint32_t sar1_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC1 CTRL*/ + volatile uint32_t sar2_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC2 CTRL*/ + volatile uint32_t data_sar_sel: 1; /*1: sar_sel will be coded by the MSB of the 16-bit output data in this case the resolution should not be larger than 11 bits.*/ + volatile uint32_t data_to_i2s: 1; /*1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix*/ + volatile uint32_t reserved27: 5; + }; + volatile uint32_t val; + }saradc_ctrl; + union { + struct { + volatile uint32_t meas_num_limit: 1; + volatile uint32_t max_meas_num: 8; /*max conversion number*/ + volatile uint32_t sar1_inv: 1; /*1: data to DIG ADC1 CTRL is inverted otherwise not*/ + volatile uint32_t sar2_inv: 1; /*1: data to DIG ADC2 CTRL is inverted otherwise not*/ + volatile uint32_t reserved11: 21; + }; + volatile uint32_t val; + }saradc_ctrl2; + union { + struct { + volatile uint32_t rstb_wait: 8; + volatile uint32_t standby_wait: 8; + volatile uint32_t start_wait: 8; + volatile uint32_t sample_cycle: 8; /*sample cycles*/ + }; + volatile uint32_t val; + }saradc_fsm; + volatile uint32_t saradc_sar1_patt_tab1; /*item 0 ~ 3 for pattern table 1 (each item one byte)*/ + volatile uint32_t saradc_sar1_patt_tab2; /*Item 4 ~ 7 for pattern table 1 (each item one byte)*/ + volatile uint32_t saradc_sar1_patt_tab3; /*Item 8 ~ 11 for pattern table 1 (each item one byte)*/ + volatile uint32_t saradc_sar1_patt_tab4; /*Item 12 ~ 15 for pattern table 1 (each item one byte)*/ + volatile uint32_t saradc_sar2_patt_tab1; /*item 0 ~ 3 for pattern table 2 (each item one byte)*/ + volatile uint32_t saradc_sar2_patt_tab2; /*Item 4 ~ 7 for pattern table 2 (each item one byte)*/ + volatile uint32_t saradc_sar2_patt_tab3; /*Item 8 ~ 11 for pattern table 2 (each item one byte)*/ + volatile uint32_t saradc_sar2_patt_tab4; /*Item 12 ~ 15 for pattern table 2 (each item one byte)*/ + union { + struct { + volatile uint32_t apll_tick: 8; + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }apll_tick_conf; + volatile uint32_t reserved_40; + volatile uint32_t reserved_44; + volatile uint32_t reserved_48; + volatile uint32_t reserved_4c; + volatile uint32_t reserved_50; + volatile uint32_t reserved_54; + volatile uint32_t reserved_58; + volatile uint32_t reserved_5c; + volatile uint32_t reserved_60; + volatile uint32_t reserved_64; + volatile uint32_t reserved_68; + volatile uint32_t reserved_6c; + volatile uint32_t reserved_70; + volatile uint32_t reserved_74; + volatile uint32_t reserved_78; + volatile uint32_t date; /**/ +} apb_ctrl_dev_t; + +#endif /* _SOC_APB_CTRL_STRUCT_H_ */ diff --git a/components/esp32/include/soc/rtc_cntl_struct.h b/components/esp32/include/soc/rtc_cntl_struct.h new file mode 100644 index 000000000..acb12432b --- /dev/null +++ b/components/esp32/include/soc/rtc_cntl_struct.h @@ -0,0 +1,553 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_RTC_CNTL_STRUCT_H_ +#define _SOC_RTC_CNTL_STRUCT_H_ +typedef volatile struct { + union { + struct { + uint32_t sw_stall_appcpu_c0: 2; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/ + uint32_t sw_stall_procpu_c0: 2; /*{reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU*/ + uint32_t sw_appcpu_rst: 1; /*APP CPU SW reset*/ + uint32_t sw_procpu_rst: 1; /*PRO CPU SW reset*/ + uint32_t bb_i2c_force_pd: 1; /*BB_I2C force power down*/ + uint32_t bb_i2c_force_pu: 1; /*BB_I2C force power up*/ + uint32_t bbpll_i2c_force_pd: 1; /*BB_PLL _I2C force power down*/ + uint32_t bbpll_i2c_force_pu: 1; /*BB_PLL_I2C force power up*/ + uint32_t bbpll_force_pd: 1; /*BB_PLL force power down*/ + uint32_t bbpll_force_pu: 1; /*BB_PLL force power up*/ + uint32_t xtl_force_pd: 1; /*crystall force power down*/ + uint32_t xtl_force_pu: 1; /*crystall force power up*/ + uint32_t bias_sleep_folw_8m: 1; /*BIAS_SLEEP follow CK8M*/ + uint32_t bias_force_sleep: 1; /*BIAS_SLEEP force sleep*/ + uint32_t bias_force_nosleep: 1; /*BIAS_SLEEP force no sleep*/ + uint32_t bias_i2c_folw_8m: 1; /*BIAS_I2C follow CK8M*/ + uint32_t bias_i2c_force_pd: 1; /*BIAS_I2C force power down*/ + uint32_t bias_i2c_force_pu: 1; /*BIAS_I2C force power up*/ + uint32_t bias_core_folw_8m: 1; /*BIAS_CORE follow CK8M*/ + uint32_t bias_core_force_pd: 1; /*BIAS_CORE force power down*/ + uint32_t bias_core_force_pu: 1; /*BIAS_CORE force power up*/ + uint32_t xtl_force_iso: 1; + uint32_t pll_force_iso: 1; + uint32_t analog_force_iso: 1; + uint32_t xtl_force_noiso: 1; + uint32_t pll_force_noiso: 1; + uint32_t analog_force_noiso: 1; + uint32_t dg_wrap_force_rst: 1; /*digital wrap force reset in deep sleep*/ + uint32_t dg_wrap_force_norst: 1; /*digital core force no reset in deep sleep*/ + uint32_t sw_sys_rst: 1; /*SW system reset*/ + }; + uint32_t val; + } options0; + uint32_t slp_timer0; /*RTC sleep timer low 32 bits*/ + union { + struct { + uint32_t slp_val_hi: 16; /*RTC sleep timer high 16 bits*/ + uint32_t main_timer_alarm_en: 1; /*timer alarm enable bit*/ + uint32_t reserved17: 15; + }; + uint32_t val; + } slp_timer1; + union { + struct { + uint32_t reserved0: 30; + uint32_t valid: 1; /*To indicate the register is updated*/ + uint32_t update: 1; /*Set 1: to update register with RTC timer*/ + }; + uint32_t val; + } time_update; + uint32_t time0; /*RTC timer low 32 bits*/ + union { + struct { + uint32_t time_hi:16; /*RTC timer high 16 bits*/ + uint32_t reserved16: 16; + }; + uint32_t val; + } time1; + union { + struct { + uint32_t reserved0: 20; + uint32_t touch_wakeup_force_en: 1; /*touch controller force wake up*/ + uint32_t ulp_cp_wakeup_force_en: 1; /*ULP-coprocessor force wake up*/ + uint32_t apb2rtc_bridge_sel: 1; /*1: APB to RTC using bridge 0: APB to RTC using sync*/ + uint32_t touch_slp_timer_en: 1; /*touch timer enable bit*/ + uint32_t ulp_cp_slp_timer_en: 1; /*ULP-coprocessor timer enable bit*/ + uint32_t reserved25: 3; + uint32_t sdio_active_ind: 1; /*SDIO active indication*/ + uint32_t slp_wakeup: 1; /*sleep wakeup bit*/ + uint32_t slp_reject: 1; /*sleep reject bit*/ + uint32_t sleep_en: 1; /*sleep enable bit*/ + }; + uint32_t val; + } state0; + union { + struct { + uint32_t cpu_stall_en: 1; /*CPU stall enable bit*/ + uint32_t cpu_stall_wait: 5; /*CPU stall wait cycles in fast_clk_rtc*/ + uint32_t ck8m_wait: 8; /*CK8M wait cycles in slow_clk_rtc*/ + uint32_t xtl_buf_wait: 10; /*XTAL wait cycles in slow_clk_rtc*/ + uint32_t pll_buf_wait: 8; /*PLL wait cycles in slow_clk_rtc*/ + }; + uint32_t val; + } timer1; + union { + struct { + uint32_t reserved0: 15; + uint32_t ulpcp_touch_start_wait: 9; /*wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller start to work*/ + uint32_t min_time_ck8m_off: 8; /*minimal cycles in slow_clk_rtc for CK8M in power down state*/ + }; + uint32_t val; + } timer2; + union { + struct { + uint32_t wifi_wait_timer: 9; + uint32_t wifi_powerup_timer: 7; + uint32_t rom_ram_wait_timer: 9; + uint32_t rom_ram_powerup_timer: 7; + }; + uint32_t val; + } timer3; + union { + struct { + uint32_t rtc_wait_timer: 9; + uint32_t rtc_powerup_timer: 7; + uint32_t dg_wrap_wait_timer: 9; + uint32_t dg_wrap_powerup_timer: 7; + }; + uint32_t val; + } timer4; + union { + struct { + uint32_t ulp_cp_subtimer_prediv: 8; + uint32_t min_slp_val: 8; /*minimal sleep cycles in slow_clk_rtc*/ + uint32_t rtcmem_wait_timer: 9; + uint32_t rtcmem_powerup_timer: 7; + }; + uint32_t val; + } timer5; + union { + struct { + uint32_t reserved0: 23; + uint32_t plla_force_pd: 1; /*PLLA force power down*/ + uint32_t plla_force_pu: 1; /*PLLA force power up*/ + uint32_t bbpll_cal_slp_start: 1; /*start BBPLL calibration during sleep*/ + uint32_t pvtmon_pu: 1; /*1: PVTMON power up otherwise power down*/ + uint32_t txrf_i2c_pu: 1; /*1: TXRF_I2C power up otherwise power down*/ + uint32_t rfrx_pbus_pu: 1; /*1: RFRX_PBUS power up otherwise power down*/ + uint32_t reserved29: 1; + uint32_t ckgen_i2c_pu: 1; /*1: CKGEN_I2C power up otherwise power down*/ + uint32_t pll_i2c_pu: 1; /*1: PLL_I2C power up otherwise power down*/ + }; + uint32_t val; + } ana_conf; + union { + struct { + uint32_t reset_cause_procpu: 6; /*reset cause of PRO CPU*/ + uint32_t reset_cause_appcpu: 6; /*reset cause of APP CPU*/ + uint32_t appcpu_stat_vector_sel: 1; /*APP CPU state vector sel*/ + uint32_t procpu_stat_vector_sel: 1; /*PRO CPU state vector sel*/ + uint32_t reserved14: 18; + }; + uint32_t val; + } reset_state; + union { + struct { + uint32_t wakeup_cause: 11; /*wakeup cause*/ + uint32_t rtc_wakeup_ena: 11; /*wakeup enable bitmap*/ + uint32_t gpio_wakeup_filter: 1; /*enable filter for gpio wakeup event*/ + uint32_t reserved23: 9; + }; + uint32_t val; + } wakeup_state; + union { + struct { + uint32_t slp_wakeup: 1; /*enable sleep wakeup interrupt*/ + uint32_t slp_reject: 1; /*enable sleep reject interrupt*/ + uint32_t sdio_idle: 1; /*enable SDIO idle interrupt*/ + uint32_t rtc_wdt: 1; /*enable RTC WDT interrupt*/ + uint32_t rtc_time_valid: 1; /*enable RTC time valid interrupt*/ + uint32_t rtc_ulp_cp: 1; /*enable ULP-coprocessor interrupt*/ + uint32_t rtc_touch: 1; /*enable touch interrupt*/ + uint32_t rtc_brown_out: 1; /*enable brown out interrupt*/ + uint32_t rtc_main_timer: 1; /*enable RTC main timer interrupt*/ + uint32_t reserved9: 23; + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t slp_wakeup: 1; /*sleep wakeup interrupt raw*/ + uint32_t slp_reject: 1; /*sleep reject interrupt raw*/ + uint32_t sdio_idle: 1; /*SDIO idle interrupt raw*/ + uint32_t rtc_wdt: 1; /*RTC WDT interrupt raw*/ + uint32_t rtc_time_valid: 1; /*RTC time valid interrupt raw*/ + uint32_t rtc_ulp_cp: 1; /*ULP-coprocessor interrupt raw*/ + uint32_t rtc_touch: 1; /*touch interrupt raw*/ + uint32_t rtc_brown_out: 1; /*brown out interrupt raw*/ + uint32_t rtc_main_timer: 1; /*RTC main timer interrupt raw*/ + uint32_t reserved9: 23; + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t slp_wakeup: 1; /*sleep wakeup interrupt state*/ + uint32_t slp_reject: 1; /*sleep reject interrupt state*/ + uint32_t sdio_idle: 1; /*SDIO idle interrupt state*/ + uint32_t rtc_wdt: 1; /*RTC WDT interrupt state*/ + uint32_t rtc_time_valid: 1; /*RTC time valid interrupt state*/ + uint32_t rtc_sar: 1; /*ULP-coprocessor interrupt state*/ + uint32_t rtc_touch: 1; /*touch interrupt state*/ + uint32_t rtc_brown_out: 1; /*brown out interrupt state*/ + uint32_t rtc_main_timer: 1; /*RTC main timer interrupt state*/ + uint32_t reserved9: 23; + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t slp_wakeup: 1; /*Clear sleep wakeup interrupt state*/ + uint32_t slp_reject: 1; /*Clear sleep reject interrupt state*/ + uint32_t sdio_idle: 1; /*Clear SDIO idle interrupt state*/ + uint32_t rtc_wdt: 1; /*Clear RTC WDT interrupt state*/ + uint32_t rtc_time_valid: 1; /*Clear RTC time valid interrupt state*/ + uint32_t rtc_sar: 1; /*Clear ULP-coprocessor interrupt state*/ + uint32_t rtc_touch: 1; /*Clear touch interrupt state*/ + uint32_t rtc_brown_out: 1; /*Clear brown out interrupt state*/ + uint32_t rtc_main_timer: 1; /*Clear RTC main timer interrupt state*/ + uint32_t reserved9: 23; + }; + uint32_t val; + } int_clr; + uint32_t rtc_store0; /*32-bit general purpose retention register*/ + uint32_t rtc_store1; /*32-bit general purpose retention register*/ + uint32_t rtc_store2; /*32-bit general purpose retention register*/ + uint32_t rtc_store3; /*32-bit general purpose retention register*/ + union { + struct { + uint32_t reserved0: 30; + uint32_t ctr_lv: 1; /*0: power down XTAL at high level 1: power down XTAL at low level*/ + uint32_t ctr_en: 1; /*enable control XTAL by external pads*/ + }; + uint32_t val; + } ext_xtl_conf; + union { + struct { + uint32_t reserved0: 30; + uint32_t wakeup0_lv: 1; /*0: external wakeup at low level 1: external wakeup at high level*/ + uint32_t wakeup1_lv: 1; /*0: external wakeup at low level 1: external wakeup at high level*/ + }; + uint32_t val; + } ext_wakeup_conf; + union { + struct { + uint32_t reserved0: 24; + uint32_t gpio_reject_en: 1; /*enable GPIO reject*/ + uint32_t sdio_reject_en: 1; /*enable SDIO reject*/ + uint32_t light_slp_reject_en: 1; /*enable reject for light sleep*/ + uint32_t deep_slp_reject_en: 1; /*enable reject for deep sleep*/ + uint32_t reject_cause: 4; /*sleep reject cause*/ + }; + uint32_t val; + } slp_reject_conf; + union { + struct { + uint32_t reserved0: 29; + uint32_t cpusel_conf: 1; /*CPU sel option*/ + uint32_t cpuperiod_sel: 2; /*CPU period sel*/ + }; + uint32_t val; + } cpu_period_conf; + union { + struct { + uint32_t reserved0: 22; + uint32_t sdio_act_dnum:10; + }; + uint32_t val; + } sdio_act_conf; + union { + struct { + uint32_t reserved0: 4; + uint32_t ck8m_div: 2; /*CK8M_D256_OUT divider. 00: div128 01: div256 10: div512 11: div1024.*/ + uint32_t enb_ck8m: 1; /*disable CK8M and CK8M_D256_OUT*/ + uint32_t enb_ck8m_div: 1; /*1: CK8M_D256_OUT is actually CK8M 0: CK8M_D256_OUT is CK8M divided by 256*/ + uint32_t dig_xtal32k_en: 1; /*enable CK_XTAL_32K for digital core (no relationship with RTC core)*/ + uint32_t dig_clk8m_d256_en: 1; /*enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/ + uint32_t dig_clk8m_en: 1; /*enable CK8M for digital core (no relationship with RTC core)*/ + uint32_t ck8m_dfreq_force: 1; + uint32_t ck8m_div_sel: 3; /*divider = reg_ck8m_div_sel + 1*/ + uint32_t xtal_force_nogating: 1; /*XTAL force no gating during sleep*/ + uint32_t ck8m_force_nogating: 1; /*CK8M force no gating during sleep*/ + uint32_t ck8m_dfreq: 8; /*CK8M_DFREQ*/ + uint32_t ck8m_force_pd: 1; /*CK8M force power down*/ + uint32_t ck8m_force_pu: 1; /*CK8M force power up*/ + uint32_t soc_clk_sel: 2; /*SOC clock sel. 0: XTAL 1: PLL 2: CK8M 3: APLL*/ + uint32_t fast_clk_rtc_sel: 1; /*fast_clk_rtc sel. 0: XTAL div 4 1: CK8M*/ + uint32_t ana_clk_rtc_sel: 2; /*slow_clk_rtc sel. 0: SLOW_CK 1: CK_XTAL_32K 2: CK8M_D256_OUT*/ + }; + uint32_t val; + } clk_conf; + union { + struct { + uint32_t reserved0: 21; + uint32_t sdio_pd_en: 1; /*power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/ + uint32_t sdio_force: 1; /*1: use SW option to control SDIO_REG 0: use state machine*/ + uint32_t sdio_tieh: 1; /*SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/ + uint32_t reg1p8_ready: 1; /*read only register for REG1P8_READY*/ + uint32_t drefl_sdio: 2; /*SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/ + uint32_t drefm_sdio: 2; /*SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/ + uint32_t drefh_sdio: 2; /*SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/ + uint32_t xpd_sdio: 1; /*SW option for XPD_SDIO_REG. Only active when reg_sdio_force = 1*/ + }; + uint32_t val; + } sdio_conf; + union { + struct { + uint32_t reserved0: 24; + uint32_t dbg_atten: 2; /*DBG_ATTEN*/ + uint32_t enb_sck_xtal: 1; /*ENB_SCK_XTAL*/ + uint32_t inc_heartbeat_refresh: 1; /*INC_HEARTBEAT_REFRESH*/ + uint32_t dec_heartbeat_period: 1; /*DEC_HEARTBEAT_PERIOD*/ + uint32_t inc_heartbeat_period: 1; /*INC_HEARTBEAT_PERIOD*/ + uint32_t dec_heartbeat_width: 1; /*DEC_HEARTBEAT_WIDTH*/ + uint32_t rst_bias_i2c: 1; /*RST_BIAS_I2C*/ + }; + uint32_t val; + } bias_conf; + union { + struct { + uint32_t reserved0: 7; + uint32_t sck_dcap_force: 1; /*N/A*/ + uint32_t dig_dbias_slp: 3; /*DIG_REG_DBIAS during sleep*/ + uint32_t dig_dbias_wak: 3; /*DIG_REG_DBIAS during wakeup*/ + uint32_t sck_dcap: 8; /*SCK_DCAP*/ + uint32_t rtc_dbias_slp: 3; /*RTC_DBIAS during sleep*/ + uint32_t rtc_dbias_wak: 3; /*RTC_DBIAS during wakeup*/ + uint32_t rtc_dboost_force_pd: 1; /*RTC_DBOOST force power down*/ + uint32_t rtc_dboost_force_pu: 1; /*RTC_DBOOST force power up*/ + uint32_t rtc_force_pd: 1; /*RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )*/ + uint32_t rtc_force_pu: 1; /*RTC_REG force power up*/ + }; + uint32_t val; + } rtc; + union { + struct { + uint32_t fastmem_force_noiso: 1; /*Fast RTC memory force no ISO*/ + uint32_t fastmem_force_iso: 1; /*Fast RTC memory force ISO*/ + uint32_t slowmem_force_noiso: 1; /*RTC memory force no ISO*/ + uint32_t slowmem_force_iso: 1; /*RTC memory force ISO*/ + uint32_t rtc_force_iso: 1; /*rtc_peri force ISO*/ + uint32_t force_noiso: 1; /*rtc_peri force no ISO*/ + uint32_t fastmem_folw_cpu: 1; /*1: Fast RTC memory PD following CPU 0: fast RTC memory PD following RTC state machine*/ + uint32_t fastmem_force_lpd: 1; /*Fast RTC memory force PD*/ + uint32_t fastmem_force_lpu: 1; /*Fast RTC memory force no PD*/ + uint32_t slowmem_folw_cpu: 1; /*1: RTC memory PD following CPU 0: RTC memory PD following RTC state machine*/ + uint32_t slowmem_force_lpd: 1; /*RTC memory force PD*/ + uint32_t slowmem_force_lpu: 1; /*RTC memory force no PD*/ + uint32_t fastmem_force_pd: 1; /*Fast RTC memory force power down*/ + uint32_t fastmem_force_pu: 1; /*Fast RTC memory force power up*/ + uint32_t fastmem_pd_en: 1; /*enable power down fast RTC memory in sleep*/ + uint32_t slowmem_force_pd: 1; /*RTC memory force power down*/ + uint32_t slowmem_force_pu: 1; /*RTC memory force power up*/ + uint32_t slowmem_pd_en: 1; /*enable power down RTC memory in sleep*/ + uint32_t pwc_force_pd: 1; /*rtc_peri force power down*/ + uint32_t pwc_force_pu: 1; /*rtc_peri force power up*/ + uint32_t pd_en: 1; /*enable power down rtc_peri in sleep*/ + uint32_t reserved21: 11; + }; + uint32_t val; + } rtc_pwc; + union { + struct { + uint32_t reserved0: 3; + uint32_t lslp_mem_force_pd: 1; /*memories in digital core force PD in sleep*/ + uint32_t lslp_mem_force_pu: 1; /*memories in digital core force no PD in sleep*/ + uint32_t rom0_force_pd: 1; /*ROM force power down*/ + uint32_t rom0_force_pu: 1; /*ROM force power up*/ + uint32_t inter_ram0_force_pd: 1; /*internal SRAM 0 force power down*/ + uint32_t inter_ram0_force_pu: 1; /*internal SRAM 0 force power up*/ + uint32_t inter_ram1_force_pd: 1; /*internal SRAM 1 force power down*/ + uint32_t inter_ram1_force_pu: 1; /*internal SRAM 1 force power up*/ + uint32_t inter_ram2_force_pd: 1; /*internal SRAM 2 force power down*/ + uint32_t inter_ram2_force_pu: 1; /*internal SRAM 2 force power up*/ + uint32_t inter_ram3_force_pd: 1; /*internal SRAM 3 force power down*/ + uint32_t inter_ram3_force_pu: 1; /*internal SRAM 3 force power up*/ + uint32_t inter_ram4_force_pd: 1; /*internal SRAM 4 force power down*/ + uint32_t inter_ram4_force_pu: 1; /*internal SRAM 4 force power up*/ + uint32_t wifi_force_pd: 1; /*wifi force power down*/ + uint32_t wifi_force_pu: 1; /*wifi force power up*/ + uint32_t dg_wrap_force_pd: 1; /*digital core force power down*/ + uint32_t dg_wrap_force_pu: 1; /*digital core force power up*/ + uint32_t reserved21: 3; + uint32_t rom0_pd_en: 1; /*enable power down ROM in sleep*/ + uint32_t inter_ram0_pd_en: 1; /*enable power down internal SRAM 0 in sleep*/ + uint32_t inter_ram1_pd_en: 1; /*enable power down internal SRAM 1 in sleep*/ + uint32_t inter_ram2_pd_en: 1; /*enable power down internal SRAM 2 in sleep*/ + uint32_t inter_ram3_pd_en: 1; /*enable power down internal SRAM 3 in sleep*/ + uint32_t inter_ram4_pd_en: 1; /*enable power down internal SRAM 4 in sleep*/ + uint32_t wifi_pd_en: 1; /*enable power down wifi in sleep*/ + uint32_t dg_wrap_pd_en: 1; /*enable power down digital core in sleep*/ + }; + uint32_t val; + } dig_pwc; + union { + struct { + uint32_t reserved0: 7; + uint32_t dig_iso_force_off: 1; + uint32_t dig_iso_force_on: 1; + uint32_t dg_pad_autohold: 1; /*read only register to indicate digital pad auto-hold status*/ + uint32_t clr_dg_pad_autohold: 1; /*wtite only register to clear digital pad auto-hold*/ + uint32_t dg_pad_autohold_en: 1; /*digital pad enable auto-hold*/ + uint32_t dg_pad_force_noiso: 1; /*digital pad force no ISO*/ + uint32_t dg_pad_force_iso: 1; /*digital pad force ISO*/ + uint32_t dg_pad_force_unhold: 1; /*digital pad force un-hold*/ + uint32_t dg_pad_force_hold: 1; /*digital pad force hold*/ + uint32_t rom0_force_iso: 1; /*ROM force ISO*/ + uint32_t rom0_force_noiso: 1; /*ROM force no ISO*/ + uint32_t inter_ram0_force_iso: 1; /*internal SRAM 0 force ISO*/ + uint32_t inter_ram0_force_noiso: 1; /*internal SRAM 0 force no ISO*/ + uint32_t inter_ram1_force_iso: 1; /*internal SRAM 1 force ISO*/ + uint32_t inter_ram1_force_noiso: 1; /*internal SRAM 1 force no ISO*/ + uint32_t inter_ram2_force_iso: 1; /*internal SRAM 2 force ISO*/ + uint32_t inter_ram2_force_noiso: 1; /*internal SRAM 2 force no ISO*/ + uint32_t inter_ram3_force_iso: 1; /*internal SRAM 3 force ISO*/ + uint32_t inter_ram3_force_noiso: 1; /*internal SRAM 3 force no ISO*/ + uint32_t inter_ram4_force_iso: 1; /*internal SRAM 4 force ISO*/ + uint32_t inter_ram4_force_noiso: 1; /*internal SRAM 4 force no ISO*/ + uint32_t wifi_force_iso: 1; /*wifi force ISO*/ + uint32_t wifi_force_noiso: 1; /*wifi force no ISO*/ + uint32_t dg_wrap_force_iso: 1; /*digital core force ISO*/ + uint32_t dg_wrap_force_noiso: 1; /*digital core force no ISO*/ + }; + uint32_t val; + } dig_iso; + union { + struct { + uint32_t reserved0: 7; + uint32_t pause_in_slp: 1; /*pause WDT in sleep*/ + uint32_t appcpu_reset_en: 1; /*enable WDT reset APP CPU*/ + uint32_t procpu_reset_en: 1; /*enable WDT reset PRO CPU*/ + uint32_t flashboot_mod_en: 1; /*enable WDT in flash boot*/ + uint32_t sys_reset_length: 3; /*system reset counter length*/ + uint32_t cpu_reset_length: 3; /*CPU reset counter length*/ + uint32_t level_int_en: 1; /*N/A*/ + uint32_t edge_int_en: 1; /*N/A*/ + uint32_t stg3: 3; /*1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en*/ + uint32_t stg2: 3; /*1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en*/ + uint32_t stg1: 3; /*1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en*/ + uint32_t stg0: 3; /*1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en*/ + uint32_t en: 1; /*enable RTC WDT*/ + }; + uint32_t val; + } wdt_config0; + uint32_t wdt_config1; /**/ + uint32_t wdt_config2; /**/ + uint32_t wdt_config3; /**/ + uint32_t wdt_config4; /**/ + union { + struct { + uint32_t reserved0: 31; + uint32_t feed: 1; + }; + uint32_t val; + } wdt_feed; + uint32_t wdt_wprotect; /**/ + union { + struct { + uint32_t reserved0: 29; + uint32_t ent_rtc: 1; /*ENT_RTC*/ + uint32_t dtest_rtc: 2; /*DTEST_RTC*/ + }; + uint32_t val; + } test_mux; + union { + struct { + uint32_t reserved0: 20; + uint32_t appcpu_c1: 6; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/ + uint32_t procpu_c1: 6; /*{reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU*/ + }; + uint32_t val; + } sw_cpu_stall; + uint32_t store4; /*32-bit general purpose retention register*/ + uint32_t store5; /*32-bit general purpose retention register*/ + uint32_t store6; /*32-bit general purpose retention register*/ + uint32_t store7; /*32-bit general purpose retention register*/ + uint32_t diag0; /**/ + uint32_t diag1; /**/ + union { + struct { + uint32_t adc1_hold_force: 1; + uint32_t adc2_hold_force: 1; + uint32_t pdac1_hold_force: 1; + uint32_t pdac2_hold_force: 1; + uint32_t sense1_hold_force: 1; + uint32_t sense2_hold_force: 1; + uint32_t sense3_hold_force: 1; + uint32_t sense4_hold_force: 1; + uint32_t touch_pad0_hold_force: 1; + uint32_t touch_pad1_hold_force: 1; + uint32_t touch_pad2_hold_force: 1; + uint32_t touch_pad3_hold_force: 1; + uint32_t touch_pad4_hold_force: 1; + uint32_t touch_pad5_hold_force: 1; + uint32_t touch_pad6_hold_force: 1; + uint32_t touch_pad7_hold_force: 1; + uint32_t x32p_hold_force: 1; + uint32_t x32n_hold_force: 1; + uint32_t reserved18: 14; + }; + uint32_t val; + } hold_force; + union { + struct { + uint32_t ext_wakeup1_sel: 18; /*Bitmap to select RTC pads for ext wakeup1*/ + uint32_t ext_wakeup1_status_clr: 1; /*clear ext wakeup1 status*/ + uint32_t reserved19: 13; + }; + uint32_t val; + } ext_wakeup1; + union { + struct { + uint32_t ext_wakeup1_status:18; /*ext wakeup1 status*/ + uint32_t reserved18: 14; + }; + uint32_t val; + } ext_wakeup1_status; + union { + struct { + uint32_t reserved0: 14; + uint32_t close_flash_ena: 1; /*enable close flash when brown out happens*/ + uint32_t pd_rf_ena: 1; /*enable power down RF when brown out happens*/ + uint32_t rst_wait: 10; /*brown out reset wait cycles*/ + uint32_t rst_ena: 1; /*enable brown out reset*/ + uint32_t thres: 3; /*brown out threshold*/ + uint32_t ena: 1; /*enable brown out*/ + uint32_t det: 1; /*brown out detect*/ + }; + uint32_t val; + } brown_out; + uint32_t reserved_39; + uint32_t reserved_3d; + uint32_t reserved_41; + uint32_t reserved_45; + uint32_t reserved_49; + uint32_t reserved_4d; + union { + struct { + uint32_t date: 28; + uint32_t reserved28: 4; + }; + uint32_t val; + } date; +} rtc_cntl_dev_t; +#endif /* _SOC_RTC_CNTL_STRUCT_H_ */ diff --git a/components/esp32/include/soc/rtc_io_struct.h b/components/esp32/include/soc/rtc_io_struct.h new file mode 100644 index 000000000..da27078c8 --- /dev/null +++ b/components/esp32/include/soc/rtc_io_struct.h @@ -0,0 +1,280 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_RTC_IO_STRUCT_H_ +#define _SOC_RTC_IO_STRUCT_H_ +typedef volatile struct { + union { + struct { + uint32_t reserved0: 14; + uint32_t data:18; /*GPIO0~17 output value*/ + }; + uint32_t val; + } out; + union { + struct { + uint32_t reserved0: 14; + uint32_t w1ts:18; /*GPIO0~17 output value write 1 to set*/ + }; + uint32_t val; + } out_w1ts; + union { + struct { + uint32_t reserved0: 14; + uint32_t w1tc:18; /*GPIO0~17 output value write 1 to clear*/ + }; + uint32_t val; + } out_w1tc; + union { + struct { + uint32_t reserved0: 14; + uint32_t enable:18; /*GPIO0~17 output enable*/ + }; + uint32_t val; + } enable; + union { + struct { + uint32_t reserved0: 14; + uint32_t w1ts:18; /*GPIO0~17 output enable write 1 to set*/ + }; + uint32_t val; + } enable_w1ts; + union { + struct { + uint32_t reserved0: 14; + uint32_t w1tc:18; /*GPIO0~17 output enable write 1 to clear*/ + }; + uint32_t val; + } enable_w1tc; + union { + struct { + uint32_t reserved0: 14; + uint32_t status:18; /*GPIO0~17 interrupt status*/ + }; + uint32_t val; + } status; + union { + struct { + uint32_t reserved0: 14; + uint32_t w1ts:18; /*GPIO0~17 interrupt status write 1 to set*/ + }; + uint32_t val; + } status_w1ts; + union { + struct { + uint32_t reserved0: 14; + uint32_t w1tc:18; /*GPIO0~17 interrupt status write 1 to clear*/ + }; + uint32_t val; + } status_w1tc; + union { + struct { + uint32_t reserved0: 14; + uint32_t in:18; /*GPIO0~17 input value*/ + }; + uint32_t val; + } in_val; + union { + struct { + uint32_t reserved0: 2; + uint32_t pad_driver: 1; /*if set to 0: normal output if set to 1: open drain*/ + uint32_t reserved3: 4; + uint32_t int_type: 3; /*if set to 0: GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ + uint32_t wakeup_enable: 1; /*GPIO wake up enable only available in light sleep*/ + uint32_t reserved11: 21; + }; + uint32_t val; + } pin[18]; + union { + struct { + uint32_t sel0: 5; + uint32_t sel1: 5; + uint32_t sel2: 5; + uint32_t sel3: 5; + uint32_t sel4: 5; + uint32_t no_gating_12m: 1; + uint32_t reserved26: 6; + }; + uint32_t val; + } debug_sel; + uint32_t dig_pad_hold; /*select the digital pad hold value.*/ + union { + struct { + uint32_t reserved0: 30; + uint32_t hall_phase: 1; /*Reverse phase of hall sensor*/ + uint32_t xpd_hall: 1; /*Power on hall sensor and connect to VP and VN*/ + }; + uint32_t val; + } hall_sens; + union { + struct { + uint32_t reserved0: 4; + uint32_t sense4_fun_ie: 1; /*the input enable of the pad*/ + uint32_t sense4_slp_ie: 1; /*the input enable of the pad in sleep status*/ + uint32_t sense4_slp_sel: 1; /*the sleep status selection signal of the pad*/ + uint32_t sense4_fun_sel: 2; /*the functional selection signal of the pad*/ + uint32_t sense3_fun_ie: 1; /*the input enable of the pad*/ + uint32_t sense3_slp_ie: 1; /*the input enable of the pad in sleep status*/ + uint32_t sense3_slp_sel: 1; /*the sleep status selection signal of the pad*/ + uint32_t sense3_fun_sel: 2; /*the functional selection signal of the pad*/ + uint32_t sense2_fun_ie: 1; /*the input enable of the pad*/ + uint32_t sense2_slp_ie: 1; /*the input enable of the pad in sleep status*/ + uint32_t sense2_slp_sel: 1; /*the sleep status selection signal of the pad*/ + uint32_t sense2_fun_sel: 2; /*the functional selection signal of the pad*/ + uint32_t sense1_fun_ie: 1; /*the input enable of the pad*/ + uint32_t sense1_slp_ie: 1; /*the input enable of the pad in sleep status*/ + uint32_t sense1_slp_sel: 1; /*the sleep status selection signal of the pad*/ + uint32_t sense1_fun_sel: 2; /*the functional selection signal of the pad*/ + uint32_t sense4_mux_sel: 1; /*�1� select the digital function �0�slection the rtc function*/ + uint32_t sense3_mux_sel: 1; /*�1� select the digital function �0�slection the rtc function*/ + uint32_t sense2_mux_sel: 1; /*�1� select the digital function �0�slection the rtc function*/ + uint32_t sense1_mux_sel: 1; /*�1� select the digital function �0�slection the rtc function*/ + uint32_t sense4_hold: 1; /*hold the current value of the output when setting the hold to �1�*/ + uint32_t sense3_hold: 1; /*hold the current value of the output when setting the hold to �1�*/ + uint32_t sense2_hold: 1; /*hold the current value of the output when setting the hold to �1�*/ + uint32_t sense1_hold: 1; /*hold the current value of the output when setting the hold to �1�*/ + }; + uint32_t val; + } sensor_pads; + union { + struct { + uint32_t reserved0: 18; + uint32_t adc2_fun_ie: 1; /*the input enable of the pad*/ + uint32_t adc2_slp_ie: 1; /*the input enable of the pad in sleep status*/ + uint32_t adc2_slp_sel: 1; /*the sleep status selection signal of the pad*/ + uint32_t adc2_fun_sel: 2; /*the functional selection signal of the pad*/ + uint32_t adc1_fun_ie: 1; /*the input enable of the pad*/ + uint32_t adc1_slp_ie: 1; /*the input enable of the pad in sleep status*/ + uint32_t adc1_slp_sel: 1; /*the sleep status selection signal of the pad*/ + uint32_t adc1_fun_sel: 2; /*the functional selection signal of the pad*/ + uint32_t adc2_mux_sel: 1; /*�1� select the digital function �0�slection the rtc function*/ + uint32_t adc1_mux_sel: 1; /*�1� select the digital function �0�slection the rtc function*/ + uint32_t adc2_hold: 1; /*hold the current value of the output when setting the hold to �1�*/ + uint32_t adc1_hold: 1; /*hold the current value of the output when setting the hold to �1�*/ + }; + uint32_t val; + } adc_pad; + union { + struct { + uint32_t reserved0: 10; + uint32_t dac_xpd_force: 1; /*Power on DAC1. Usually we need to tristate PDAC1 if we power on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/ + uint32_t fun_ie: 1; /*the input enable of the pad*/ + uint32_t slp_oe: 1; /*the output enable of the pad in sleep status*/ + uint32_t slp_ie: 1; /*the input enable of the pad in sleep status*/ + uint32_t slp_sel: 1; /*the sleep status selection signal of the pad*/ + uint32_t fun_sel: 2; /*the functional selection signal of the pad*/ + uint32_t mux_sel: 1; /*�1� select the digital function �0�slection the rtc function*/ + uint32_t xpd_dac: 1; /*Power on DAC1. Usually we need to tristate PDAC1 if we power on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/ + uint32_t dac: 8; /*PAD DAC1 control code.*/ + uint32_t rue: 1; /*the pull up enable of the pad*/ + uint32_t rde: 1; /*the pull down enable of the pad*/ + uint32_t hold: 1; /*hold the current value of the output when setting the hold to �1�*/ + uint32_t drv: 2; /*the driver strength of the pad*/ + }; + uint32_t val; + } pad_dac[2]; + union { + struct { + uint32_t reserved0: 1; + uint32_t dbias_xtal_32k: 2; /*32K XTAL self-bias reference control.*/ + uint32_t dres_xtal_32k: 2; /*32K XTAL resistor bias control.*/ + uint32_t x32p_fun_ie: 1; /*the input enable of the pad*/ + uint32_t x32p_slp_oe: 1; /*the output enable of the pad in sleep status*/ + uint32_t x32p_slp_ie: 1; /*the input enable of the pad in sleep status*/ + uint32_t x32p_slp_sel: 1; /*the sleep status selection signal of the pad*/ + uint32_t x32p_fun_sel: 2; /*the functional selection signal of the pad*/ + uint32_t x32n_fun_ie: 1; /*the input enable of the pad*/ + uint32_t x32n_slp_oe: 1; /*the output enable of the pad in sleep status*/ + uint32_t x32n_slp_ie: 1; /*the input enable of the pad in sleep status*/ + uint32_t x32n_slp_sel: 1; /*the sleep status selection signal of the pad*/ + uint32_t x32n_fun_sel: 2; /*the functional selection signal of the pad*/ + uint32_t x32p_mux_sel: 1; /*�1� select the digital function �0�slection the rtc function*/ + uint32_t x32n_mux_sel: 1; /*�1� select the digital function �0�slection the rtc function*/ + uint32_t xpd_xtal_32k: 1; /*Power up 32kHz crystal oscillator*/ + uint32_t dac_xtal_32k: 2; /*32K XTAL bias current DAC.*/ + uint32_t x32p_rue: 1; /*the pull up enable of the pad*/ + uint32_t x32p_rde: 1; /*the pull down enable of the pad*/ + uint32_t x32p_hold: 1; /*hold the current value of the output when setting the hold to �1�*/ + uint32_t x32p_drv: 2; /*the driver strength of the pad*/ + uint32_t x32n_rue: 1; /*the pull up enable of the pad*/ + uint32_t x32n_rde: 1; /*the pull down enable of the pad*/ + uint32_t x32n_hold: 1; /*hold the current value of the output when setting the hold to �1�*/ + uint32_t x32n_drv: 2; /*the driver strength of the pad*/ + }; + uint32_t val; + } xtal_32k_pad; + union { + struct { + uint32_t reserved0: 23; + uint32_t dcur: 2; /*touch sensor bias current. Should have option to tie with BIAS_SLEEP(When BIAS_SLEEP this setting is available*/ + uint32_t drange: 2; /*touch sensor saw wave voltage range.*/ + uint32_t drefl: 2; /*touch sensor saw wave bottom voltage.*/ + uint32_t drefh: 2; /*touch sensor saw wave top voltage.*/ + uint32_t xpd_bias: 1; /*touch sensor bias power on.*/ + }; + uint32_t val; + } touch_cfg; + union { + struct { + uint32_t reserved0: 12; + uint32_t to_gpio: 1; /*connect the rtc pad input to digital pad input �0� is availbale GPIO4*/ + uint32_t fun_ie: 1; /*the input enable of the pad*/ + uint32_t slp_oe: 1; /*the output enable of the pad in sleep status*/ + uint32_t slp_ie: 1; /*the input enable of the pad in sleep status*/ + uint32_t slp_sel: 1; /*the sleep status selection signal of the pad*/ + uint32_t fun_sel: 2; /*the functional selection signal of the pad*/ + uint32_t mux_sel: 1; /*�1� select the digital function �0�slection the rtc function*/ + uint32_t xpd: 1; /*touch sensor power on.*/ + uint32_t tie_opt: 1; /*default touch sensor tie option. 0: tie low 1: tie high.*/ + uint32_t start: 1; /*start touch sensor.*/ + uint32_t dac: 3; /*touch sensor slope control. 3-bit for each touch panel default 100.*/ + uint32_t reserved26: 1; + uint32_t rue: 1; /*the pull up enable of the pad*/ + uint32_t rde: 1; /*the pull down enable of the pad*/ + uint32_t drv: 2; /*the driver strength of the pad*/ + uint32_t hold: 1; /*hold the current value of the output when setting the hold to �1�*/ + }; + uint32_t val; + } touch_pad[10]; + union { + struct { + uint32_t reserved0: 27; + uint32_t sel: 5; /*select the wakeup source �0� select GPIO0 �1� select GPIO2 ...�17� select GPIO17*/ + }; + uint32_t val; + } ext_wakeup0; + union { + struct { + uint32_t reserved0: 27; + uint32_t sel: 5; /*select the external xtl power source �0� select GPIO0 �1� select GPIO2 ...�17� select GPIO17*/ + }; + uint32_t val; + } xtl_ext_ctr; + union { + struct { + uint32_t reserved0: 23; + uint32_t debug_bit_sel: 5; + uint32_t scl_sel: 2; /*�0� using TOUCH_PAD[0] as i2c clk �1� using TOUCH_PAD[2] as i2c clk*/ + uint32_t sda_sel: 2; /*�0� using TOUCH_PAD[1] as i2c sda �1� using TOUCH_PAD[3] as i2c sda*/ + }; + uint32_t val; + } sar_i2c_io; + union { + struct { + uint32_t date: 28; /*date*/ + uint32_t reserved28: 4; + }; + uint32_t val; + } date; +} rtc_io_dev_t; +#endif /* _SOC_RTC_IO_STRUCT_H_ */ diff --git a/components/esp32/include/soc/soc.h b/components/esp32/include/soc/soc.h index 9b0c82fc1..c17df3858 100755 --- a/components/esp32/include/soc/soc.h +++ b/components/esp32/include/soc/soc.h @@ -184,6 +184,7 @@ #define DR_REG_TIMERGROUP1_BASE 0x3ff60000 #define DR_REG_SPI2_BASE 0x3ff64000 #define DR_REG_SPI3_BASE 0x3ff65000 +#define DR_REG_APB_CTRL_BASE 0x3ff66000 #define DR_REG_I2C1_EXT_BASE 0x3ff67000 #define DR_REG_SDMMC_BASE 0x3ff68000 #define DR_REG_EMAC_BASE 0x3ff69000 From d6dbf15a1fb2bbfbeed953ad8ca90f2e141c19d1 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Tue, 28 Mar 2017 14:05:27 +0800 Subject: [PATCH 2/5] soc: move header files into soc component --- components/{ => soc}/esp32/include/soc/apb_ctrl_reg.h | 0 components/{ => soc}/esp32/include/soc/apb_ctrl_struct.h | 0 components/{ => soc}/esp32/include/soc/bb_reg.h | 0 components/{ => soc}/esp32/include/soc/boot_mode.h | 0 components/{ => soc}/esp32/include/soc/cpu.h | 0 components/{ => soc}/esp32/include/soc/dport_reg.h | 0 components/{ => soc}/esp32/include/soc/efuse_reg.h | 0 components/{ => soc}/esp32/include/soc/emac_ex_reg.h | 0 components/{ => soc}/esp32/include/soc/emac_reg_v2.h | 0 components/{ => soc}/esp32/include/soc/frc_timer_reg.h | 0 components/{ => soc}/esp32/include/soc/gpio_reg.h | 0 components/{ => soc}/esp32/include/soc/gpio_sd_reg.h | 0 components/{ => soc}/esp32/include/soc/gpio_sd_struct.h | 0 components/{ => soc}/esp32/include/soc/gpio_sig_map.h | 0 components/{ => soc}/esp32/include/soc/gpio_struct.h | 0 components/{ => soc}/esp32/include/soc/hwcrypto_reg.h | 0 components/{ => soc}/esp32/include/soc/i2c_reg.h | 0 components/{ => soc}/esp32/include/soc/i2c_struct.h | 0 components/{ => soc}/esp32/include/soc/i2s_reg.h | 0 components/{ => soc}/esp32/include/soc/i2s_struct.h | 0 components/{ => soc}/esp32/include/soc/io_mux_reg.h | 0 components/{ => soc}/esp32/include/soc/ledc_reg.h | 0 components/{ => soc}/esp32/include/soc/ledc_struct.h | 0 components/{ => soc}/esp32/include/soc/pcnt_reg.h | 0 components/{ => soc}/esp32/include/soc/pcnt_struct.h | 0 components/{ => soc}/esp32/include/soc/pid.h | 0 components/{ => soc}/esp32/include/soc/rmt_reg.h | 0 components/{ => soc}/esp32/include/soc/rmt_struct.h | 0 components/{ => soc}/esp32/include/soc/rtc_cntl_reg.h | 0 components/{ => soc}/esp32/include/soc/rtc_cntl_struct.h | 0 components/{ => soc}/esp32/include/soc/rtc_io_reg.h | 0 components/{ => soc}/esp32/include/soc/rtc_io_struct.h | 0 components/{ => soc}/esp32/include/soc/sdmmc_reg.h | 0 components/{ => soc}/esp32/include/soc/sdmmc_struct.h | 0 components/{ => soc}/esp32/include/soc/sens_reg.h | 0 components/{ => soc}/esp32/include/soc/soc.h | 0 components/{ => soc}/esp32/include/soc/soc_ulp.h | 0 components/{ => soc}/esp32/include/soc/spi_reg.h | 0 components/{ => soc}/esp32/include/soc/spi_struct.h | 0 components/{ => soc}/esp32/include/soc/syscon_reg.h | 0 components/{ => soc}/esp32/include/soc/syscon_struct.h | 0 components/{ => soc}/esp32/include/soc/timer_group_reg.h | 0 components/{ => soc}/esp32/include/soc/timer_group_struct.h | 0 components/{ => soc}/esp32/include/soc/uart_reg.h | 0 components/{ => soc}/esp32/include/soc/uart_struct.h | 0 components/{ => soc}/esp32/include/soc/uhci_reg.h | 0 components/{ => soc}/esp32/include/soc/uhci_struct.h | 0 components/{ => soc}/esp32/include/soc/wdev_reg.h | 0 48 files changed, 0 insertions(+), 0 deletions(-) rename components/{ => soc}/esp32/include/soc/apb_ctrl_reg.h (100%) rename components/{ => soc}/esp32/include/soc/apb_ctrl_struct.h (100%) rename components/{ => soc}/esp32/include/soc/bb_reg.h (100%) rename components/{ => soc}/esp32/include/soc/boot_mode.h (100%) rename components/{ => soc}/esp32/include/soc/cpu.h (100%) rename components/{ => soc}/esp32/include/soc/dport_reg.h (100%) rename components/{ => soc}/esp32/include/soc/efuse_reg.h (100%) rename components/{ => soc}/esp32/include/soc/emac_ex_reg.h (100%) rename components/{ => soc}/esp32/include/soc/emac_reg_v2.h (100%) rename components/{ => soc}/esp32/include/soc/frc_timer_reg.h (100%) rename components/{ => soc}/esp32/include/soc/gpio_reg.h (100%) rename components/{ => soc}/esp32/include/soc/gpio_sd_reg.h (100%) rename components/{ => soc}/esp32/include/soc/gpio_sd_struct.h (100%) rename components/{ => soc}/esp32/include/soc/gpio_sig_map.h (100%) rename components/{ => soc}/esp32/include/soc/gpio_struct.h (100%) rename components/{ => soc}/esp32/include/soc/hwcrypto_reg.h (100%) rename components/{ => soc}/esp32/include/soc/i2c_reg.h (100%) rename components/{ => soc}/esp32/include/soc/i2c_struct.h (100%) rename components/{ => soc}/esp32/include/soc/i2s_reg.h (100%) rename components/{ => soc}/esp32/include/soc/i2s_struct.h (100%) rename components/{ => soc}/esp32/include/soc/io_mux_reg.h (100%) rename components/{ => soc}/esp32/include/soc/ledc_reg.h (100%) rename components/{ => soc}/esp32/include/soc/ledc_struct.h (100%) rename components/{ => soc}/esp32/include/soc/pcnt_reg.h (100%) rename components/{ => soc}/esp32/include/soc/pcnt_struct.h (100%) rename components/{ => soc}/esp32/include/soc/pid.h (100%) rename components/{ => soc}/esp32/include/soc/rmt_reg.h (100%) rename components/{ => soc}/esp32/include/soc/rmt_struct.h (100%) rename components/{ => soc}/esp32/include/soc/rtc_cntl_reg.h (100%) rename components/{ => soc}/esp32/include/soc/rtc_cntl_struct.h (100%) rename components/{ => soc}/esp32/include/soc/rtc_io_reg.h (100%) rename components/{ => soc}/esp32/include/soc/rtc_io_struct.h (100%) rename components/{ => soc}/esp32/include/soc/sdmmc_reg.h (100%) rename components/{ => soc}/esp32/include/soc/sdmmc_struct.h (100%) rename components/{ => soc}/esp32/include/soc/sens_reg.h (100%) rename components/{ => soc}/esp32/include/soc/soc.h (100%) rename components/{ => soc}/esp32/include/soc/soc_ulp.h (100%) rename components/{ => soc}/esp32/include/soc/spi_reg.h (100%) rename components/{ => soc}/esp32/include/soc/spi_struct.h (100%) rename components/{ => soc}/esp32/include/soc/syscon_reg.h (100%) rename components/{ => soc}/esp32/include/soc/syscon_struct.h (100%) rename components/{ => soc}/esp32/include/soc/timer_group_reg.h (100%) rename components/{ => soc}/esp32/include/soc/timer_group_struct.h (100%) rename components/{ => soc}/esp32/include/soc/uart_reg.h (100%) rename components/{ => soc}/esp32/include/soc/uart_struct.h (100%) rename components/{ => soc}/esp32/include/soc/uhci_reg.h (100%) rename components/{ => soc}/esp32/include/soc/uhci_struct.h (100%) rename components/{ => soc}/esp32/include/soc/wdev_reg.h (100%) diff --git a/components/esp32/include/soc/apb_ctrl_reg.h b/components/soc/esp32/include/soc/apb_ctrl_reg.h similarity index 100% rename from components/esp32/include/soc/apb_ctrl_reg.h rename to components/soc/esp32/include/soc/apb_ctrl_reg.h diff --git a/components/esp32/include/soc/apb_ctrl_struct.h b/components/soc/esp32/include/soc/apb_ctrl_struct.h similarity index 100% rename from components/esp32/include/soc/apb_ctrl_struct.h rename to components/soc/esp32/include/soc/apb_ctrl_struct.h diff --git a/components/esp32/include/soc/bb_reg.h b/components/soc/esp32/include/soc/bb_reg.h similarity index 100% rename from components/esp32/include/soc/bb_reg.h rename to components/soc/esp32/include/soc/bb_reg.h diff --git a/components/esp32/include/soc/boot_mode.h b/components/soc/esp32/include/soc/boot_mode.h similarity index 100% rename from components/esp32/include/soc/boot_mode.h rename to components/soc/esp32/include/soc/boot_mode.h diff --git a/components/esp32/include/soc/cpu.h b/components/soc/esp32/include/soc/cpu.h similarity index 100% rename from components/esp32/include/soc/cpu.h rename to components/soc/esp32/include/soc/cpu.h diff --git a/components/esp32/include/soc/dport_reg.h b/components/soc/esp32/include/soc/dport_reg.h similarity index 100% rename from components/esp32/include/soc/dport_reg.h rename to components/soc/esp32/include/soc/dport_reg.h diff --git a/components/esp32/include/soc/efuse_reg.h b/components/soc/esp32/include/soc/efuse_reg.h similarity index 100% rename from components/esp32/include/soc/efuse_reg.h rename to components/soc/esp32/include/soc/efuse_reg.h diff --git a/components/esp32/include/soc/emac_ex_reg.h b/components/soc/esp32/include/soc/emac_ex_reg.h similarity index 100% rename from components/esp32/include/soc/emac_ex_reg.h rename to components/soc/esp32/include/soc/emac_ex_reg.h diff --git a/components/esp32/include/soc/emac_reg_v2.h b/components/soc/esp32/include/soc/emac_reg_v2.h similarity index 100% rename from components/esp32/include/soc/emac_reg_v2.h rename to components/soc/esp32/include/soc/emac_reg_v2.h diff --git a/components/esp32/include/soc/frc_timer_reg.h b/components/soc/esp32/include/soc/frc_timer_reg.h similarity index 100% rename from components/esp32/include/soc/frc_timer_reg.h rename to components/soc/esp32/include/soc/frc_timer_reg.h diff --git a/components/esp32/include/soc/gpio_reg.h b/components/soc/esp32/include/soc/gpio_reg.h similarity index 100% rename from components/esp32/include/soc/gpio_reg.h rename to components/soc/esp32/include/soc/gpio_reg.h diff --git a/components/esp32/include/soc/gpio_sd_reg.h b/components/soc/esp32/include/soc/gpio_sd_reg.h similarity index 100% rename from components/esp32/include/soc/gpio_sd_reg.h rename to components/soc/esp32/include/soc/gpio_sd_reg.h diff --git a/components/esp32/include/soc/gpio_sd_struct.h b/components/soc/esp32/include/soc/gpio_sd_struct.h similarity index 100% rename from components/esp32/include/soc/gpio_sd_struct.h rename to components/soc/esp32/include/soc/gpio_sd_struct.h diff --git a/components/esp32/include/soc/gpio_sig_map.h b/components/soc/esp32/include/soc/gpio_sig_map.h similarity index 100% rename from components/esp32/include/soc/gpio_sig_map.h rename to components/soc/esp32/include/soc/gpio_sig_map.h diff --git a/components/esp32/include/soc/gpio_struct.h b/components/soc/esp32/include/soc/gpio_struct.h similarity index 100% rename from components/esp32/include/soc/gpio_struct.h rename to components/soc/esp32/include/soc/gpio_struct.h diff --git a/components/esp32/include/soc/hwcrypto_reg.h b/components/soc/esp32/include/soc/hwcrypto_reg.h similarity index 100% rename from components/esp32/include/soc/hwcrypto_reg.h rename to components/soc/esp32/include/soc/hwcrypto_reg.h diff --git a/components/esp32/include/soc/i2c_reg.h b/components/soc/esp32/include/soc/i2c_reg.h similarity index 100% rename from components/esp32/include/soc/i2c_reg.h rename to components/soc/esp32/include/soc/i2c_reg.h diff --git a/components/esp32/include/soc/i2c_struct.h b/components/soc/esp32/include/soc/i2c_struct.h similarity index 100% rename from components/esp32/include/soc/i2c_struct.h rename to components/soc/esp32/include/soc/i2c_struct.h diff --git a/components/esp32/include/soc/i2s_reg.h b/components/soc/esp32/include/soc/i2s_reg.h similarity index 100% rename from components/esp32/include/soc/i2s_reg.h rename to components/soc/esp32/include/soc/i2s_reg.h diff --git a/components/esp32/include/soc/i2s_struct.h b/components/soc/esp32/include/soc/i2s_struct.h similarity index 100% rename from components/esp32/include/soc/i2s_struct.h rename to components/soc/esp32/include/soc/i2s_struct.h diff --git a/components/esp32/include/soc/io_mux_reg.h b/components/soc/esp32/include/soc/io_mux_reg.h similarity index 100% rename from components/esp32/include/soc/io_mux_reg.h rename to components/soc/esp32/include/soc/io_mux_reg.h diff --git a/components/esp32/include/soc/ledc_reg.h b/components/soc/esp32/include/soc/ledc_reg.h similarity index 100% rename from components/esp32/include/soc/ledc_reg.h rename to components/soc/esp32/include/soc/ledc_reg.h diff --git a/components/esp32/include/soc/ledc_struct.h b/components/soc/esp32/include/soc/ledc_struct.h similarity index 100% rename from components/esp32/include/soc/ledc_struct.h rename to components/soc/esp32/include/soc/ledc_struct.h diff --git a/components/esp32/include/soc/pcnt_reg.h b/components/soc/esp32/include/soc/pcnt_reg.h similarity index 100% rename from components/esp32/include/soc/pcnt_reg.h rename to components/soc/esp32/include/soc/pcnt_reg.h diff --git a/components/esp32/include/soc/pcnt_struct.h b/components/soc/esp32/include/soc/pcnt_struct.h similarity index 100% rename from components/esp32/include/soc/pcnt_struct.h rename to components/soc/esp32/include/soc/pcnt_struct.h diff --git a/components/esp32/include/soc/pid.h b/components/soc/esp32/include/soc/pid.h similarity index 100% rename from components/esp32/include/soc/pid.h rename to components/soc/esp32/include/soc/pid.h diff --git a/components/esp32/include/soc/rmt_reg.h b/components/soc/esp32/include/soc/rmt_reg.h similarity index 100% rename from components/esp32/include/soc/rmt_reg.h rename to components/soc/esp32/include/soc/rmt_reg.h diff --git a/components/esp32/include/soc/rmt_struct.h b/components/soc/esp32/include/soc/rmt_struct.h similarity index 100% rename from components/esp32/include/soc/rmt_struct.h rename to components/soc/esp32/include/soc/rmt_struct.h diff --git a/components/esp32/include/soc/rtc_cntl_reg.h b/components/soc/esp32/include/soc/rtc_cntl_reg.h similarity index 100% rename from components/esp32/include/soc/rtc_cntl_reg.h rename to components/soc/esp32/include/soc/rtc_cntl_reg.h diff --git a/components/esp32/include/soc/rtc_cntl_struct.h b/components/soc/esp32/include/soc/rtc_cntl_struct.h similarity index 100% rename from components/esp32/include/soc/rtc_cntl_struct.h rename to components/soc/esp32/include/soc/rtc_cntl_struct.h diff --git a/components/esp32/include/soc/rtc_io_reg.h b/components/soc/esp32/include/soc/rtc_io_reg.h similarity index 100% rename from components/esp32/include/soc/rtc_io_reg.h rename to components/soc/esp32/include/soc/rtc_io_reg.h diff --git a/components/esp32/include/soc/rtc_io_struct.h b/components/soc/esp32/include/soc/rtc_io_struct.h similarity index 100% rename from components/esp32/include/soc/rtc_io_struct.h rename to components/soc/esp32/include/soc/rtc_io_struct.h diff --git a/components/esp32/include/soc/sdmmc_reg.h b/components/soc/esp32/include/soc/sdmmc_reg.h similarity index 100% rename from components/esp32/include/soc/sdmmc_reg.h rename to components/soc/esp32/include/soc/sdmmc_reg.h diff --git a/components/esp32/include/soc/sdmmc_struct.h b/components/soc/esp32/include/soc/sdmmc_struct.h similarity index 100% rename from components/esp32/include/soc/sdmmc_struct.h rename to components/soc/esp32/include/soc/sdmmc_struct.h diff --git a/components/esp32/include/soc/sens_reg.h b/components/soc/esp32/include/soc/sens_reg.h similarity index 100% rename from components/esp32/include/soc/sens_reg.h rename to components/soc/esp32/include/soc/sens_reg.h diff --git a/components/esp32/include/soc/soc.h b/components/soc/esp32/include/soc/soc.h similarity index 100% rename from components/esp32/include/soc/soc.h rename to components/soc/esp32/include/soc/soc.h diff --git a/components/esp32/include/soc/soc_ulp.h b/components/soc/esp32/include/soc/soc_ulp.h similarity index 100% rename from components/esp32/include/soc/soc_ulp.h rename to components/soc/esp32/include/soc/soc_ulp.h diff --git a/components/esp32/include/soc/spi_reg.h b/components/soc/esp32/include/soc/spi_reg.h similarity index 100% rename from components/esp32/include/soc/spi_reg.h rename to components/soc/esp32/include/soc/spi_reg.h diff --git a/components/esp32/include/soc/spi_struct.h b/components/soc/esp32/include/soc/spi_struct.h similarity index 100% rename from components/esp32/include/soc/spi_struct.h rename to components/soc/esp32/include/soc/spi_struct.h diff --git a/components/esp32/include/soc/syscon_reg.h b/components/soc/esp32/include/soc/syscon_reg.h similarity index 100% rename from components/esp32/include/soc/syscon_reg.h rename to components/soc/esp32/include/soc/syscon_reg.h diff --git a/components/esp32/include/soc/syscon_struct.h b/components/soc/esp32/include/soc/syscon_struct.h similarity index 100% rename from components/esp32/include/soc/syscon_struct.h rename to components/soc/esp32/include/soc/syscon_struct.h diff --git a/components/esp32/include/soc/timer_group_reg.h b/components/soc/esp32/include/soc/timer_group_reg.h similarity index 100% rename from components/esp32/include/soc/timer_group_reg.h rename to components/soc/esp32/include/soc/timer_group_reg.h diff --git a/components/esp32/include/soc/timer_group_struct.h b/components/soc/esp32/include/soc/timer_group_struct.h similarity index 100% rename from components/esp32/include/soc/timer_group_struct.h rename to components/soc/esp32/include/soc/timer_group_struct.h diff --git a/components/esp32/include/soc/uart_reg.h b/components/soc/esp32/include/soc/uart_reg.h similarity index 100% rename from components/esp32/include/soc/uart_reg.h rename to components/soc/esp32/include/soc/uart_reg.h diff --git a/components/esp32/include/soc/uart_struct.h b/components/soc/esp32/include/soc/uart_struct.h similarity index 100% rename from components/esp32/include/soc/uart_struct.h rename to components/soc/esp32/include/soc/uart_struct.h diff --git a/components/esp32/include/soc/uhci_reg.h b/components/soc/esp32/include/soc/uhci_reg.h similarity index 100% rename from components/esp32/include/soc/uhci_reg.h rename to components/soc/esp32/include/soc/uhci_reg.h diff --git a/components/esp32/include/soc/uhci_struct.h b/components/soc/esp32/include/soc/uhci_struct.h similarity index 100% rename from components/esp32/include/soc/uhci_struct.h rename to components/soc/esp32/include/soc/uhci_struct.h diff --git a/components/esp32/include/soc/wdev_reg.h b/components/soc/esp32/include/soc/wdev_reg.h similarity index 100% rename from components/esp32/include/soc/wdev_reg.h rename to components/soc/esp32/include/soc/wdev_reg.h From 9ff446e6f9174d17899bc6f35092a58ad580d971 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Tue, 11 Apr 2017 15:44:22 +0800 Subject: [PATCH 3/5] soc: convert line endings to unix --- components/soc/esp32/include/soc/i2c_reg.h | 1902 +++---- components/soc/esp32/include/soc/ledc_reg.h | 4846 ++++++++--------- components/soc/esp32/include/soc/pcnt_reg.h | 3052 +++++------ components/soc/esp32/include/soc/rmt_reg.h | 4344 +++++++-------- components/soc/esp32/include/soc/rtc_io_reg.h | 3902 ++++++------- components/soc/esp32/include/soc/spi_reg.h | 3422 ++++++------ components/soc/esp32/include/soc/uart_reg.h | 2334 ++++---- 7 files changed, 11901 insertions(+), 11901 deletions(-) diff --git a/components/soc/esp32/include/soc/i2c_reg.h b/components/soc/esp32/include/soc/i2c_reg.h index 9693ca5b5..292695eb7 100644 --- a/components/soc/esp32/include/soc/i2c_reg.h +++ b/components/soc/esp32/include/soc/i2c_reg.h @@ -1,951 +1,951 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_I2C_REG_H_ -#define _SOC_I2C_REG_H_ - - -#include "soc.h" - -#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) - -#define I2C_SCL_LOW_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0000) -/* I2C_SCL_LOW_PERIOD : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This register is used to configure the low level width of SCL clock.*/ -#define I2C_SCL_LOW_PERIOD 0x00003FFF -#define I2C_SCL_LOW_PERIOD_M ((I2C_SCL_LOW_PERIOD_V)<<(I2C_SCL_LOW_PERIOD_S)) -#define I2C_SCL_LOW_PERIOD_V 0x3FFF -#define I2C_SCL_LOW_PERIOD_S 0 - -#define I2C_CTR_REG(i) (REG_I2C_BASE(i) + 0x0004) -/* I2C_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: This is the clock gating control bit for reading or writing registers.*/ -#define I2C_CLK_EN (BIT(8)) -#define I2C_CLK_EN_M (BIT(8)) -#define I2C_CLK_EN_V 0x1 -#define I2C_CLK_EN_S 8 -/* I2C_RX_LSB_FIRST : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: This bit is used to control the storage mode for received datas. - 1: receive data from most significant bit 0: receive data from least significant bit*/ -#define I2C_RX_LSB_FIRST (BIT(7)) -#define I2C_RX_LSB_FIRST_M (BIT(7)) -#define I2C_RX_LSB_FIRST_V 0x1 -#define I2C_RX_LSB_FIRST_S 7 -/* I2C_TX_LSB_FIRST : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: This bit is used to control the sending mode for data need to - be send. 1: receive data from most significant bit 0: receive data from least significant bit*/ -#define I2C_TX_LSB_FIRST (BIT(6)) -#define I2C_TX_LSB_FIRST_M (BIT(6)) -#define I2C_TX_LSB_FIRST_V 0x1 -#define I2C_TX_LSB_FIRST_S 6 -/* I2C_TRANS_START : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to start sending data in txfifo.*/ -#define I2C_TRANS_START (BIT(5)) -#define I2C_TRANS_START_M (BIT(5)) -#define I2C_TRANS_START_V 0x1 -#define I2C_TRANS_START_S 5 -/* I2C_MS_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to configure the module as i2c master clear this - bit to configure the module as i2c slave.*/ -#define I2C_MS_MODE (BIT(4)) -#define I2C_MS_MODE_M (BIT(4)) -#define I2C_MS_MODE_V 0x1 -#define I2C_MS_MODE_S 4 -/* I2C_SAMPLE_SCL_LEVEL : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to sample data in SCL low level. clear this bit - to sample data in SCL high level.*/ -#define I2C_SAMPLE_SCL_LEVEL (BIT(2)) -#define I2C_SAMPLE_SCL_LEVEL_M (BIT(2)) -#define I2C_SAMPLE_SCL_LEVEL_V 0x1 -#define I2C_SAMPLE_SCL_LEVEL_S 2 -/* I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: 1: normally ouput scl clock 0: exchange the function of scl_o - and scl_oe (scl_o is the original internal output scl signal scl_oe is the enable bit for the internal output scl signal)*/ -#define I2C_SCL_FORCE_OUT (BIT(1)) -#define I2C_SCL_FORCE_OUT_M (BIT(1)) -#define I2C_SCL_FORCE_OUT_V 0x1 -#define I2C_SCL_FORCE_OUT_S 1 -/* I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: 1: normally ouput sda data 0: exchange the function of sda_o - and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal)*/ -#define I2C_SDA_FORCE_OUT (BIT(0)) -#define I2C_SDA_FORCE_OUT_M (BIT(0)) -#define I2C_SDA_FORCE_OUT_V 0x1 -#define I2C_SDA_FORCE_OUT_S 0 - -#define I2C_SR_REG(i) (REG_I2C_BASE(i) + 0x0008) -/* I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */ -/*description: This register stores the value of state machine to produce SCL. - 3'h0: SCL_IDLE 3'h1:SCL_START 3'h2:SCL_LOW_EDGE 3'h3: SCL_LOW 3'h4:SCL_HIGH_EDGE 3'h5:SCL_HIGH 3'h6:SCL_STOP*/ -#define I2C_SCL_STATE_LAST 0x00000007 -#define I2C_SCL_STATE_LAST_M ((I2C_SCL_STATE_LAST_V)<<(I2C_SCL_STATE_LAST_S)) -#define I2C_SCL_STATE_LAST_V 0x7 -#define I2C_SCL_STATE_LAST_S 28 -/* I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */ -/*description: This register stores the value of state machine for i2c module. - 3'h0: SCL_MAIN_IDLE 3'h1: SCL_ADDRESS_SHIFT 3'h2: SCL_ACK_ADDRESS 3'h3: SCL_RX_DATA 3'h4 SCL_TX_DATA 3'h5:SCL_SEND_ACK 3'h6:SCL_WAIT_ACK*/ -#define I2C_SCL_MAIN_STATE_LAST 0x00000007 -#define I2C_SCL_MAIN_STATE_LAST_M ((I2C_SCL_MAIN_STATE_LAST_V)<<(I2C_SCL_MAIN_STATE_LAST_S)) -#define I2C_SCL_MAIN_STATE_LAST_V 0x7 -#define I2C_SCL_MAIN_STATE_LAST_S 24 -/* I2C_TXFIFO_CNT : RO ;bitpos:[23:18] ;default: 6'b0 ; */ -/*description: This register stores the amount of received data in ram.*/ -#define I2C_TXFIFO_CNT 0x0000003F -#define I2C_TXFIFO_CNT_M ((I2C_TXFIFO_CNT_V)<<(I2C_TXFIFO_CNT_S)) -#define I2C_TXFIFO_CNT_V 0x3F -#define I2C_TXFIFO_CNT_S 18 -/* I2C_RXFIFO_CNT : RO ;bitpos:[13:8] ;default: 6'b0 ; */ -/*description: This register represent the amount of data need to send.*/ -#define I2C_RXFIFO_CNT 0x0000003F -#define I2C_RXFIFO_CNT_M ((I2C_RXFIFO_CNT_V)<<(I2C_RXFIFO_CNT_S)) -#define I2C_RXFIFO_CNT_V 0x3F -#define I2C_RXFIFO_CNT_S 8 -/* I2C_BYTE_TRANS : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: This register changes to high level when one byte is transferred.*/ -#define I2C_BYTE_TRANS (BIT(6)) -#define I2C_BYTE_TRANS_M (BIT(6)) -#define I2C_BYTE_TRANS_V 0x1 -#define I2C_BYTE_TRANS_S 6 -/* I2C_SLAVE_ADDRESSED : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: when configured as i2c slave and the address send by master - is equal to slave's address then this bit will be high level.*/ -#define I2C_SLAVE_ADDRESSED (BIT(5)) -#define I2C_SLAVE_ADDRESSED_M (BIT(5)) -#define I2C_SLAVE_ADDRESSED_V 0x1 -#define I2C_SLAVE_ADDRESSED_S 5 -/* I2C_BUS_BUSY : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: 1:I2C bus is busy transferring data. 0:I2C bus is in idle state.*/ -#define I2C_BUS_BUSY (BIT(4)) -#define I2C_BUS_BUSY_M (BIT(4)) -#define I2C_BUS_BUSY_V 0x1 -#define I2C_BUS_BUSY_S 4 -/* I2C_ARB_LOST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: when I2C lost control of SDA line this register changes to high level.*/ -#define I2C_ARB_LOST (BIT(3)) -#define I2C_ARB_LOST_M (BIT(3)) -#define I2C_ARB_LOST_V 0x1 -#define I2C_ARB_LOST_S 3 -/* I2C_TIME_OUT : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: when I2C takes more than time_out_reg clocks to receive a data - then this register changes to high level.*/ -#define I2C_TIME_OUT (BIT(2)) -#define I2C_TIME_OUT_M (BIT(2)) -#define I2C_TIME_OUT_V 0x1 -#define I2C_TIME_OUT_S 2 -/* I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: when in slave mode 1: master read slave 0: master write slave.*/ -#define I2C_SLAVE_RW (BIT(1)) -#define I2C_SLAVE_RW_M (BIT(1)) -#define I2C_SLAVE_RW_V 0x1 -#define I2C_SLAVE_RW_S 1 -/* I2C_ACK_REC : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This register stores the value of ACK bit.*/ -#define I2C_ACK_REC (BIT(0)) -#define I2C_ACK_REC_M (BIT(0)) -#define I2C_ACK_REC_V 0x1 -#define I2C_ACK_REC_S 0 - -#define I2C_TO_REG(i) (REG_I2C_BASE(i) + 0x000c) -/* I2C_TIME_OUT_REG : R/W ;bitpos:[19:0] ;default: 20'b0 ; */ -/*description: This register is used to configure the max clock number of receiving a data.*/ -#define I2C_TIME_OUT_REG 0x000FFFFF -#define I2C_TIME_OUT_REG_M ((I2C_TIME_OUT_REG_V)<<(I2C_TIME_OUT_REG_S)) -#define I2C_TIME_OUT_REG_V 0xFFFFF -#define I2C_TIME_OUT_REG_S 0 - -#define I2C_SLAVE_ADDR_REG(i) (REG_I2C_BASE(i) + 0x0010) -/* I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: This register is used to enable slave 10bit address mode.*/ -#define I2C_ADDR_10BIT_EN (BIT(31)) -#define I2C_ADDR_10BIT_EN_M (BIT(31)) -#define I2C_ADDR_10BIT_EN_V 0x1 -#define I2C_ADDR_10BIT_EN_S 31 -/* I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */ -/*description: when configured as i2c slave this register is used to configure - slave's address.*/ -#define I2C_SLAVE_ADDR 0x00007FFF -#define I2C_SLAVE_ADDR_M ((I2C_SLAVE_ADDR_V)<<(I2C_SLAVE_ADDR_S)) -#define I2C_SLAVE_ADDR_V 0x7FFF -#define I2C_SLAVE_ADDR_S 0 - -#define I2C_RXFIFO_ST_REG(i) (REG_I2C_BASE(i) + 0x0014) -/* I2C_TXFIFO_END_ADDR : RO ;bitpos:[19:15] ;default: 5'b0 ; */ -/*description: This is the offset address of the last sending data as described - in nonfifo_tx_thres register.*/ -#define I2C_TXFIFO_END_ADDR 0x0000001F -#define I2C_TXFIFO_END_ADDR_M ((I2C_TXFIFO_END_ADDR_V)<<(I2C_TXFIFO_END_ADDR_S)) -#define I2C_TXFIFO_END_ADDR_V 0x1F -#define I2C_TXFIFO_END_ADDR_S 15 -/* I2C_TXFIFO_START_ADDR : RO ;bitpos:[14:10] ;default: 5'b0 ; */ -/*description: This is the offset address of the first sending data as described - in nonfifo_tx_thres register.*/ -#define I2C_TXFIFO_START_ADDR 0x0000001F -#define I2C_TXFIFO_START_ADDR_M ((I2C_TXFIFO_START_ADDR_V)<<(I2C_TXFIFO_START_ADDR_S)) -#define I2C_TXFIFO_START_ADDR_V 0x1F -#define I2C_TXFIFO_START_ADDR_S 10 -/* I2C_RXFIFO_END_ADDR : RO ;bitpos:[9:5] ;default: 5'b0 ; */ -/*description: This is the offset address of the first receiving data as described - in nonfifo_rx_thres_register.*/ -#define I2C_RXFIFO_END_ADDR 0x0000001F -#define I2C_RXFIFO_END_ADDR_M ((I2C_RXFIFO_END_ADDR_V)<<(I2C_RXFIFO_END_ADDR_S)) -#define I2C_RXFIFO_END_ADDR_V 0x1F -#define I2C_RXFIFO_END_ADDR_S 5 -/* I2C_RXFIFO_START_ADDR : RO ;bitpos:[4:0] ;default: 5'b0 ; */ -/*description: This is the offset address of the last receiving data as described - in nonfifo_rx_thres_register.*/ -#define I2C_RXFIFO_START_ADDR 0x0000001F -#define I2C_RXFIFO_START_ADDR_M ((I2C_RXFIFO_START_ADDR_V)<<(I2C_RXFIFO_START_ADDR_S)) -#define I2C_RXFIFO_START_ADDR_V 0x1F -#define I2C_RXFIFO_START_ADDR_S 0 - -#define I2C_FIFO_CONF_REG(i) (REG_I2C_BASE(i) + 0x0018) -/* I2C_NONFIFO_TX_THRES : R/W ;bitpos:[25:20] ;default: 6'h15 ; */ -/*description: when I2C sends more than nonfifo_tx_thres data it will produce - tx_send_empty_int_raw interrupt and update the current offset address of the sending data.*/ -#define I2C_NONFIFO_TX_THRES 0x0000003F -#define I2C_NONFIFO_TX_THRES_M ((I2C_NONFIFO_TX_THRES_V)<<(I2C_NONFIFO_TX_THRES_S)) -#define I2C_NONFIFO_TX_THRES_V 0x3F -#define I2C_NONFIFO_TX_THRES_S 20 -/* I2C_NONFIFO_RX_THRES : R/W ;bitpos:[19:14] ;default: 6'h15 ; */ -/*description: when I2C receives more than nonfifo_rx_thres data it will produce - rx_send_full_int_raw interrupt and update the current offset address of the receiving data.*/ -#define I2C_NONFIFO_RX_THRES 0x0000003F -#define I2C_NONFIFO_RX_THRES_M ((I2C_NONFIFO_RX_THRES_V)<<(I2C_NONFIFO_RX_THRES_S)) -#define I2C_NONFIFO_RX_THRES_V 0x3F -#define I2C_NONFIFO_RX_THRES_S 14 -/* I2C_TX_FIFO_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Set this bit to reset tx fifo when using apb fifo access.*/ -#define I2C_TX_FIFO_RST (BIT(13)) -#define I2C_TX_FIFO_RST_M (BIT(13)) -#define I2C_TX_FIFO_RST_V 0x1 -#define I2C_TX_FIFO_RST_S 13 -/* I2C_RX_FIFO_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to reset rx fifo when using apb fifo access.*/ -#define I2C_RX_FIFO_RST (BIT(12)) -#define I2C_RX_FIFO_RST_M (BIT(12)) -#define I2C_RX_FIFO_RST_V 0x1 -#define I2C_RX_FIFO_RST_S 12 -/* I2C_FIFO_ADDR_CFG_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: When this bit is set to 1 then the byte after address represent - the offset address of I2C Slave's ram.*/ -#define I2C_FIFO_ADDR_CFG_EN (BIT(11)) -#define I2C_FIFO_ADDR_CFG_EN_M (BIT(11)) -#define I2C_FIFO_ADDR_CFG_EN_V 0x1 -#define I2C_FIFO_ADDR_CFG_EN_S 11 -/* I2C_NONFIFO_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit to enble apb nonfifo access.*/ -#define I2C_NONFIFO_EN (BIT(10)) -#define I2C_NONFIFO_EN_M (BIT(10)) -#define I2C_NONFIFO_EN_V 0x1 -#define I2C_NONFIFO_EN_S 10 -/* I2C_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[9:5] ;default: 5'h4 ; */ -/*description: Config txfifo empty threhd value when using apb fifo access*/ -#define I2C_TXFIFO_EMPTY_THRHD 0x0000001F -#define I2C_TXFIFO_EMPTY_THRHD_M ((I2C_TXFIFO_EMPTY_THRHD_V)<<(I2C_TXFIFO_EMPTY_THRHD_S)) -#define I2C_TXFIFO_EMPTY_THRHD_V 0x1F -#define I2C_TXFIFO_EMPTY_THRHD_S 5 -/* I2C_RXFIFO_FULL_THRHD : R/W ;bitpos:[4:0] ;default: 5'hb ; */ -/*description: */ -#define I2C_RXFIFO_FULL_THRHD 0x0000001F -#define I2C_RXFIFO_FULL_THRHD_M ((I2C_RXFIFO_FULL_THRHD_V)<<(I2C_RXFIFO_FULL_THRHD_S)) -#define I2C_RXFIFO_FULL_THRHD_V 0x1F -#define I2C_RXFIFO_FULL_THRHD_S 0 - -#define I2C_DATA_APB_REG(i) (0x60013000 + (i) * 0x14000 + 0x001c) - -#define I2C_DATA_REG(i) (REG_I2C_BASE(i) + 0x001c) -/* I2C_FIFO_RDATA : RO ;bitpos:[7:0] ;default: 8'b0 ; */ -/*description: The register represent the byte data read from rxfifo when use apb fifo access*/ -#define I2C_FIFO_RDATA 0x000000FF -#define I2C_FIFO_RDATA_M ((I2C_FIFO_RDATA_V)<<(I2C_FIFO_RDATA_S)) -#define I2C_FIFO_RDATA_V 0xFF -#define I2C_FIFO_RDATA_S 0 - -#define I2C_INT_RAW_REG(i) (REG_I2C_BASE(i) + 0x0020) -/* I2C_TX_SEND_EMPTY_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for tx_send_empty_int interrupt.when - I2C sends more data than nonfifo_tx_thres it will produce tx_send_empty_int interrupt..*/ -#define I2C_TX_SEND_EMPTY_INT_RAW (BIT(12)) -#define I2C_TX_SEND_EMPTY_INT_RAW_M (BIT(12)) -#define I2C_TX_SEND_EMPTY_INT_RAW_V 0x1 -#define I2C_TX_SEND_EMPTY_INT_RAW_S 12 -/* I2C_RX_REC_FULL_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for rx_rec_full_int interrupt. when - I2C receives more data than nonfifo_rx_thres it will produce rx_rec_full_int interrupt.*/ -#define I2C_RX_REC_FULL_INT_RAW (BIT(11)) -#define I2C_RX_REC_FULL_INT_RAW_M (BIT(11)) -#define I2C_RX_REC_FULL_INT_RAW_V 0x1 -#define I2C_RX_REC_FULL_INT_RAW_S 11 -/* I2C_ACK_ERR_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for ack_err_int interrupt. when - I2C receives a wrong ACK bit it will produce ack_err_int interrupt..*/ -#define I2C_ACK_ERR_INT_RAW (BIT(10)) -#define I2C_ACK_ERR_INT_RAW_M (BIT(10)) -#define I2C_ACK_ERR_INT_RAW_V 0x1 -#define I2C_ACK_ERR_INT_RAW_S 10 -/* I2C_TRANS_START_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for trans_start_int interrupt. when - I2C sends the START bit it will produce trans_start_int interrupt.*/ -#define I2C_TRANS_START_INT_RAW (BIT(9)) -#define I2C_TRANS_START_INT_RAW_M (BIT(9)) -#define I2C_TRANS_START_INT_RAW_V 0x1 -#define I2C_TRANS_START_INT_RAW_S 9 -/* I2C_TIME_OUT_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for time_out_int interrupt. when - I2C takes a lot of time to receive a data it will produce time_out_int interrupt.*/ -#define I2C_TIME_OUT_INT_RAW (BIT(8)) -#define I2C_TIME_OUT_INT_RAW_M (BIT(8)) -#define I2C_TIME_OUT_INT_RAW_V 0x1 -#define I2C_TIME_OUT_INT_RAW_S 8 -/* I2C_TRANS_COMPLETE_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for trans_complete_int interrupt. - when I2C Master finished STOP command it will produce trans_complete_int interrupt.*/ -#define I2C_TRANS_COMPLETE_INT_RAW (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_RAW_M (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_RAW_V 0x1 -#define I2C_TRANS_COMPLETE_INT_RAW_S 7 -/* I2C_MASTER_TRAN_COMP_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for master_tra_comp_int interrupt. - when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt.*/ -#define I2C_MASTER_TRAN_COMP_INT_RAW (BIT(6)) -#define I2C_MASTER_TRAN_COMP_INT_RAW_M (BIT(6)) -#define I2C_MASTER_TRAN_COMP_INT_RAW_V 0x1 -#define I2C_MASTER_TRAN_COMP_INT_RAW_S 6 -/* I2C_ARBITRATION_LOST_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for arbitration_lost_int interrupt.when - I2C lost the usage right of I2C BUS it will produce arbitration_lost_int interrupt.*/ -#define I2C_ARBITRATION_LOST_INT_RAW (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_RAW_M (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_RAW_V 0x1 -#define I2C_ARBITRATION_LOST_INT_RAW_S 5 -/* I2C_SLAVE_TRAN_COMP_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for slave_tran_comp_int interrupt. - when I2C Slave detectsthe STOP bit it will produce slave_tran_comp_int interrupt.*/ -#define I2C_SLAVE_TRAN_COMP_INT_RAW (BIT(4)) -#define I2C_SLAVE_TRAN_COMP_INT_RAW_M (BIT(4)) -#define I2C_SLAVE_TRAN_COMP_INT_RAW_V 0x1 -#define I2C_SLAVE_TRAN_COMP_INT_RAW_S 4 -/* I2C_END_DETECT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for end_detect_int interrupt. when - I2C deals with the END command it will produce end_detect_int interrupt.*/ -#define I2C_END_DETECT_INT_RAW (BIT(3)) -#define I2C_END_DETECT_INT_RAW_M (BIT(3)) -#define I2C_END_DETECT_INT_RAW_V 0x1 -#define I2C_END_DETECT_INT_RAW_S 3 -/* I2C_RXFIFO_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for receiving data overflow when - use apb fifo access.*/ -#define I2C_RXFIFO_OVF_INT_RAW (BIT(2)) -#define I2C_RXFIFO_OVF_INT_RAW_M (BIT(2)) -#define I2C_RXFIFO_OVF_INT_RAW_V 0x1 -#define I2C_RXFIFO_OVF_INT_RAW_S 2 -/* I2C_TXFIFO_EMPTY_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for txfifo empty when use apb fifo access.*/ -#define I2C_TXFIFO_EMPTY_INT_RAW (BIT(1)) -#define I2C_TXFIFO_EMPTY_INT_RAW_M (BIT(1)) -#define I2C_TXFIFO_EMPTY_INT_RAW_V 0x1 -#define I2C_TXFIFO_EMPTY_INT_RAW_S 1 -/* I2C_RXFIFO_FULL_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for rxfifo full when use apb fifo access.*/ -#define I2C_RXFIFO_FULL_INT_RAW (BIT(0)) -#define I2C_RXFIFO_FULL_INT_RAW_M (BIT(0)) -#define I2C_RXFIFO_FULL_INT_RAW_V 0x1 -#define I2C_RXFIFO_FULL_INT_RAW_S 0 - -#define I2C_INT_CLR_REG(i) (REG_I2C_BASE(i) + 0x0024) -/* I2C_TX_SEND_EMPTY_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to clear the tx_send_empty_int interrupt.*/ -#define I2C_TX_SEND_EMPTY_INT_CLR (BIT(12)) -#define I2C_TX_SEND_EMPTY_INT_CLR_M (BIT(12)) -#define I2C_TX_SEND_EMPTY_INT_CLR_V 0x1 -#define I2C_TX_SEND_EMPTY_INT_CLR_S 12 -/* I2C_RX_REC_FULL_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rx_rec_full_int interrupt.*/ -#define I2C_RX_REC_FULL_INT_CLR (BIT(11)) -#define I2C_RX_REC_FULL_INT_CLR_M (BIT(11)) -#define I2C_RX_REC_FULL_INT_CLR_V 0x1 -#define I2C_RX_REC_FULL_INT_CLR_S 11 -/* I2C_ACK_ERR_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit to clear the ack_err_int interrupt.*/ -#define I2C_ACK_ERR_INT_CLR (BIT(10)) -#define I2C_ACK_ERR_INT_CLR_M (BIT(10)) -#define I2C_ACK_ERR_INT_CLR_V 0x1 -#define I2C_ACK_ERR_INT_CLR_S 10 -/* I2C_TRANS_START_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to clear the trans_start_int interrupt.*/ -#define I2C_TRANS_START_INT_CLR (BIT(9)) -#define I2C_TRANS_START_INT_CLR_M (BIT(9)) -#define I2C_TRANS_START_INT_CLR_V 0x1 -#define I2C_TRANS_START_INT_CLR_S 9 -/* I2C_TIME_OUT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to clear the time_out_int interrupt.*/ -#define I2C_TIME_OUT_INT_CLR (BIT(8)) -#define I2C_TIME_OUT_INT_CLR_M (BIT(8)) -#define I2C_TIME_OUT_INT_CLR_V 0x1 -#define I2C_TIME_OUT_INT_CLR_S 8 -/* I2C_TRANS_COMPLETE_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to clear the trans_complete_int interrupt.*/ -#define I2C_TRANS_COMPLETE_INT_CLR (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_CLR_M (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_CLR_V 0x1 -#define I2C_TRANS_COMPLETE_INT_CLR_S 7 -/* I2C_MASTER_TRAN_COMP_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to clear the master_tran_comp interrupt.*/ -#define I2C_MASTER_TRAN_COMP_INT_CLR (BIT(6)) -#define I2C_MASTER_TRAN_COMP_INT_CLR_M (BIT(6)) -#define I2C_MASTER_TRAN_COMP_INT_CLR_V 0x1 -#define I2C_MASTER_TRAN_COMP_INT_CLR_S 6 -/* I2C_ARBITRATION_LOST_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to clear the arbitration_lost_int interrupt.*/ -#define I2C_ARBITRATION_LOST_INT_CLR (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_CLR_M (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_CLR_V 0x1 -#define I2C_ARBITRATION_LOST_INT_CLR_S 5 -/* I2C_SLAVE_TRAN_COMP_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to clear the slave_tran_comp_int interrupt.*/ -#define I2C_SLAVE_TRAN_COMP_INT_CLR (BIT(4)) -#define I2C_SLAVE_TRAN_COMP_INT_CLR_M (BIT(4)) -#define I2C_SLAVE_TRAN_COMP_INT_CLR_V 0x1 -#define I2C_SLAVE_TRAN_COMP_INT_CLR_S 4 -/* I2C_END_DETECT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to clear the end_detect_int interrupt.*/ -#define I2C_END_DETECT_INT_CLR (BIT(3)) -#define I2C_END_DETECT_INT_CLR_M (BIT(3)) -#define I2C_END_DETECT_INT_CLR_V 0x1 -#define I2C_END_DETECT_INT_CLR_S 3 -/* I2C_RXFIFO_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rxfifo_ovf_int interrupt.*/ -#define I2C_RXFIFO_OVF_INT_CLR (BIT(2)) -#define I2C_RXFIFO_OVF_INT_CLR_M (BIT(2)) -#define I2C_RXFIFO_OVF_INT_CLR_V 0x1 -#define I2C_RXFIFO_OVF_INT_CLR_S 2 -/* I2C_TXFIFO_EMPTY_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to clear the txfifo_empty_int interrupt.*/ -#define I2C_TXFIFO_EMPTY_INT_CLR (BIT(1)) -#define I2C_TXFIFO_EMPTY_INT_CLR_M (BIT(1)) -#define I2C_TXFIFO_EMPTY_INT_CLR_V 0x1 -#define I2C_TXFIFO_EMPTY_INT_CLR_S 1 -/* I2C_RXFIFO_FULL_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rxfifo_full_int interrupt.*/ -#define I2C_RXFIFO_FULL_INT_CLR (BIT(0)) -#define I2C_RXFIFO_FULL_INT_CLR_M (BIT(0)) -#define I2C_RXFIFO_FULL_INT_CLR_V 0x1 -#define I2C_RXFIFO_FULL_INT_CLR_S 0 - -#define I2C_INT_ENA_REG(i) (REG_I2C_BASE(i) + 0x0028) -/* I2C_TX_SEND_EMPTY_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The enable bit for tx_send_empty_int interrupt.*/ -#define I2C_TX_SEND_EMPTY_INT_ENA (BIT(12)) -#define I2C_TX_SEND_EMPTY_INT_ENA_M (BIT(12)) -#define I2C_TX_SEND_EMPTY_INT_ENA_V 0x1 -#define I2C_TX_SEND_EMPTY_INT_ENA_S 12 -/* I2C_RX_REC_FULL_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The enable bit for rx_rec_full_int interrupt.*/ -#define I2C_RX_REC_FULL_INT_ENA (BIT(11)) -#define I2C_RX_REC_FULL_INT_ENA_M (BIT(11)) -#define I2C_RX_REC_FULL_INT_ENA_V 0x1 -#define I2C_RX_REC_FULL_INT_ENA_S 11 -/* I2C_ACK_ERR_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The enable bit for ack_err_int interrupt.*/ -#define I2C_ACK_ERR_INT_ENA (BIT(10)) -#define I2C_ACK_ERR_INT_ENA_M (BIT(10)) -#define I2C_ACK_ERR_INT_ENA_V 0x1 -#define I2C_ACK_ERR_INT_ENA_S 10 -/* I2C_TRANS_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The enable bit for trans_start_int interrupt.*/ -#define I2C_TRANS_START_INT_ENA (BIT(9)) -#define I2C_TRANS_START_INT_ENA_M (BIT(9)) -#define I2C_TRANS_START_INT_ENA_V 0x1 -#define I2C_TRANS_START_INT_ENA_S 9 -/* I2C_TIME_OUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The enable bit for time_out_int interrupt.*/ -#define I2C_TIME_OUT_INT_ENA (BIT(8)) -#define I2C_TIME_OUT_INT_ENA_M (BIT(8)) -#define I2C_TIME_OUT_INT_ENA_V 0x1 -#define I2C_TIME_OUT_INT_ENA_S 8 -/* I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The enable bit for trans_complete_int interrupt.*/ -#define I2C_TRANS_COMPLETE_INT_ENA (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_ENA_M (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_ENA_V 0x1 -#define I2C_TRANS_COMPLETE_INT_ENA_S 7 -/* I2C_MASTER_TRAN_COMP_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The enable bit for master_tran_comp_int interrupt.*/ -#define I2C_MASTER_TRAN_COMP_INT_ENA (BIT(6)) -#define I2C_MASTER_TRAN_COMP_INT_ENA_M (BIT(6)) -#define I2C_MASTER_TRAN_COMP_INT_ENA_V 0x1 -#define I2C_MASTER_TRAN_COMP_INT_ENA_S 6 -/* I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The enable bit for arbitration_lost_int interrupt.*/ -#define I2C_ARBITRATION_LOST_INT_ENA (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_ENA_M (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_ENA_V 0x1 -#define I2C_ARBITRATION_LOST_INT_ENA_S 5 -/* I2C_SLAVE_TRAN_COMP_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The enable bit for slave_tran_comp_int interrupt.*/ -#define I2C_SLAVE_TRAN_COMP_INT_ENA (BIT(4)) -#define I2C_SLAVE_TRAN_COMP_INT_ENA_M (BIT(4)) -#define I2C_SLAVE_TRAN_COMP_INT_ENA_V 0x1 -#define I2C_SLAVE_TRAN_COMP_INT_ENA_S 4 -/* I2C_END_DETECT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The enable bit for end_detect_int interrupt.*/ -#define I2C_END_DETECT_INT_ENA (BIT(3)) -#define I2C_END_DETECT_INT_ENA_M (BIT(3)) -#define I2C_END_DETECT_INT_ENA_V 0x1 -#define I2C_END_DETECT_INT_ENA_S 3 -/* I2C_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The enable bit for rxfifo_ovf_int interrupt.*/ -#define I2C_RXFIFO_OVF_INT_ENA (BIT(2)) -#define I2C_RXFIFO_OVF_INT_ENA_M (BIT(2)) -#define I2C_RXFIFO_OVF_INT_ENA_V 0x1 -#define I2C_RXFIFO_OVF_INT_ENA_S 2 -/* I2C_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The enable bit for txfifo_empty_int interrupt.*/ -#define I2C_TXFIFO_EMPTY_INT_ENA (BIT(1)) -#define I2C_TXFIFO_EMPTY_INT_ENA_M (BIT(1)) -#define I2C_TXFIFO_EMPTY_INT_ENA_V 0x1 -#define I2C_TXFIFO_EMPTY_INT_ENA_S 1 -/* I2C_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The enable bit for rxfifo_full_int interrupt.*/ -#define I2C_RXFIFO_FULL_INT_ENA (BIT(0)) -#define I2C_RXFIFO_FULL_INT_ENA_M (BIT(0)) -#define I2C_RXFIFO_FULL_INT_ENA_V 0x1 -#define I2C_RXFIFO_FULL_INT_ENA_S 0 - -#define I2C_INT_STATUS_REG(i) (REG_I2C_BASE(i) + 0x002c) -/* I2C_TX_SEND_EMPTY_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The masked interrupt status for tx_send_empty_int interrupt.*/ -#define I2C_TX_SEND_EMPTY_INT_ST (BIT(12)) -#define I2C_TX_SEND_EMPTY_INT_ST_M (BIT(12)) -#define I2C_TX_SEND_EMPTY_INT_ST_V 0x1 -#define I2C_TX_SEND_EMPTY_INT_ST_S 12 -/* I2C_RX_REC_FULL_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The masked interrupt status for rx_rec_full_int interrupt.*/ -#define I2C_RX_REC_FULL_INT_ST (BIT(11)) -#define I2C_RX_REC_FULL_INT_ST_M (BIT(11)) -#define I2C_RX_REC_FULL_INT_ST_V 0x1 -#define I2C_RX_REC_FULL_INT_ST_S 11 -/* I2C_ACK_ERR_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The masked interrupt status for ack_err_int interrupt.*/ -#define I2C_ACK_ERR_INT_ST (BIT(10)) -#define I2C_ACK_ERR_INT_ST_M (BIT(10)) -#define I2C_ACK_ERR_INT_ST_V 0x1 -#define I2C_ACK_ERR_INT_ST_S 10 -/* I2C_TRANS_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The masked interrupt status for trans_start_int interrupt.*/ -#define I2C_TRANS_START_INT_ST (BIT(9)) -#define I2C_TRANS_START_INT_ST_M (BIT(9)) -#define I2C_TRANS_START_INT_ST_V 0x1 -#define I2C_TRANS_START_INT_ST_S 9 -/* I2C_TIME_OUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The masked interrupt status for time_out_int interrupt.*/ -#define I2C_TIME_OUT_INT_ST (BIT(8)) -#define I2C_TIME_OUT_INT_ST_M (BIT(8)) -#define I2C_TIME_OUT_INT_ST_V 0x1 -#define I2C_TIME_OUT_INT_ST_S 8 -/* I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The masked interrupt status for trans_complete_int interrupt.*/ -#define I2C_TRANS_COMPLETE_INT_ST (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_ST_M (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_ST_V 0x1 -#define I2C_TRANS_COMPLETE_INT_ST_S 7 -/* I2C_MASTER_TRAN_COMP_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The masked interrupt status for master_tran_comp_int interrupt.*/ -#define I2C_MASTER_TRAN_COMP_INT_ST (BIT(6)) -#define I2C_MASTER_TRAN_COMP_INT_ST_M (BIT(6)) -#define I2C_MASTER_TRAN_COMP_INT_ST_V 0x1 -#define I2C_MASTER_TRAN_COMP_INT_ST_S 6 -/* I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The masked interrupt status for arbitration_lost_int interrupt.*/ -#define I2C_ARBITRATION_LOST_INT_ST (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_ST_M (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_ST_V 0x1 -#define I2C_ARBITRATION_LOST_INT_ST_S 5 -/* I2C_SLAVE_TRAN_COMP_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The masked interrupt status for slave_tran_comp_int interrupt.*/ -#define I2C_SLAVE_TRAN_COMP_INT_ST (BIT(4)) -#define I2C_SLAVE_TRAN_COMP_INT_ST_M (BIT(4)) -#define I2C_SLAVE_TRAN_COMP_INT_ST_V 0x1 -#define I2C_SLAVE_TRAN_COMP_INT_ST_S 4 -/* I2C_END_DETECT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The masked interrupt status for end_detect_int interrupt.*/ -#define I2C_END_DETECT_INT_ST (BIT(3)) -#define I2C_END_DETECT_INT_ST_M (BIT(3)) -#define I2C_END_DETECT_INT_ST_V 0x1 -#define I2C_END_DETECT_INT_ST_S 3 -/* I2C_RXFIFO_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The masked interrupt status for rxfifo_ovf_int interrupt.*/ -#define I2C_RXFIFO_OVF_INT_ST (BIT(2)) -#define I2C_RXFIFO_OVF_INT_ST_M (BIT(2)) -#define I2C_RXFIFO_OVF_INT_ST_V 0x1 -#define I2C_RXFIFO_OVF_INT_ST_S 2 -/* I2C_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The masked interrupt status for txfifo_empty_int interrupt.*/ -#define I2C_TXFIFO_EMPTY_INT_ST (BIT(1)) -#define I2C_TXFIFO_EMPTY_INT_ST_M (BIT(1)) -#define I2C_TXFIFO_EMPTY_INT_ST_V 0x1 -#define I2C_TXFIFO_EMPTY_INT_ST_S 1 -/* I2C_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The masked interrupt status for rxfifo_full_int interrupt.*/ -#define I2C_RXFIFO_FULL_INT_ST (BIT(0)) -#define I2C_RXFIFO_FULL_INT_ST_M (BIT(0)) -#define I2C_RXFIFO_FULL_INT_ST_V 0x1 -#define I2C_RXFIFO_FULL_INT_ST_S 0 - -#define I2C_SDA_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0030) -/* I2C_SDA_HOLD_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */ -/*description: This register is used to configure the clock num I2C used to - hold the data after the negedge of SCL.*/ -#define I2C_SDA_HOLD_TIME 0x000003FF -#define I2C_SDA_HOLD_TIME_M ((I2C_SDA_HOLD_TIME_V)<<(I2C_SDA_HOLD_TIME_S)) -#define I2C_SDA_HOLD_TIME_V 0x3FF -#define I2C_SDA_HOLD_TIME_S 0 - -#define I2C_SDA_SAMPLE_REG(i) (REG_I2C_BASE(i) + 0x0034) -/* I2C_SDA_SAMPLE_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */ -/*description: This register is used to configure the clock num I2C used to - sample data on SDA after the posedge of SCL*/ -#define I2C_SDA_SAMPLE_TIME 0x000003FF -#define I2C_SDA_SAMPLE_TIME_M ((I2C_SDA_SAMPLE_TIME_V)<<(I2C_SDA_SAMPLE_TIME_S)) -#define I2C_SDA_SAMPLE_TIME_V 0x3FF -#define I2C_SDA_SAMPLE_TIME_S 0 - -#define I2C_SCL_HIGH_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0038) -/* I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This register is used to configure the clock num during SCL is low level.*/ -#define I2C_SCL_HIGH_PERIOD 0x00003FFF -#define I2C_SCL_HIGH_PERIOD_M ((I2C_SCL_HIGH_PERIOD_V)<<(I2C_SCL_HIGH_PERIOD_S)) -#define I2C_SCL_HIGH_PERIOD_V 0x3FFF -#define I2C_SCL_HIGH_PERIOD_S 0 - -#define I2C_SCL_START_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0040) -/* I2C_SCL_START_HOLD_TIME : R/W ;bitpos:[9:0] ;default: 10'b1000 ; */ -/*description: This register is used to configure the clock num between the - negedge of SDA and negedge of SCL for start mark.*/ -#define I2C_SCL_START_HOLD_TIME 0x000003FF -#define I2C_SCL_START_HOLD_TIME_M ((I2C_SCL_START_HOLD_TIME_V)<<(I2C_SCL_START_HOLD_TIME_S)) -#define I2C_SCL_START_HOLD_TIME_V 0x3FF -#define I2C_SCL_START_HOLD_TIME_S 0 - -#define I2C_SCL_RSTART_SETUP_REG(i) (REG_I2C_BASE(i) + 0x0044) -/* I2C_SCL_RSTART_SETUP_TIME : R/W ;bitpos:[9:0] ;default: 10'b1000 ; */ -/*description: This register is used to configure the clock num between the - posedge of SCL and the negedge of SDA for restart mark.*/ -#define I2C_SCL_RSTART_SETUP_TIME 0x000003FF -#define I2C_SCL_RSTART_SETUP_TIME_M ((I2C_SCL_RSTART_SETUP_TIME_V)<<(I2C_SCL_RSTART_SETUP_TIME_S)) -#define I2C_SCL_RSTART_SETUP_TIME_V 0x3FF -#define I2C_SCL_RSTART_SETUP_TIME_S 0 - -#define I2C_SCL_STOP_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0048) -/* I2C_SCL_STOP_HOLD_TIME : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This register is used to configure the clock num after the STOP bit's posedge.*/ -#define I2C_SCL_STOP_HOLD_TIME 0x00003FFF -#define I2C_SCL_STOP_HOLD_TIME_M ((I2C_SCL_STOP_HOLD_TIME_V)<<(I2C_SCL_STOP_HOLD_TIME_S)) -#define I2C_SCL_STOP_HOLD_TIME_V 0x3FFF -#define I2C_SCL_STOP_HOLD_TIME_S 0 - -#define I2C_SCL_STOP_SETUP_REG(i) (REG_I2C_BASE(i) + 0x004C) -/* I2C_SCL_STOP_SETUP_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */ -/*description: This register is used to configure the clock num between the - posedge of SCL and the posedge of SDA.*/ -#define I2C_SCL_STOP_SETUP_TIME 0x000003FF -#define I2C_SCL_STOP_SETUP_TIME_M ((I2C_SCL_STOP_SETUP_TIME_V)<<(I2C_SCL_STOP_SETUP_TIME_S)) -#define I2C_SCL_STOP_SETUP_TIME_V 0x3FF -#define I2C_SCL_STOP_SETUP_TIME_S 0 - -#define I2C_SCL_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x0050) -/* I2C_SCL_FILTER_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: This is the filter enable bit for SCL.*/ -#define I2C_SCL_FILTER_EN (BIT(3)) -#define I2C_SCL_FILTER_EN_M (BIT(3)) -#define I2C_SCL_FILTER_EN_V 0x1 -#define I2C_SCL_FILTER_EN_S 3 -/* I2C_SCL_FILTER_THRES : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ -/*description: When input SCL's pulse width is smaller than this register value - I2C ignores this pulse.*/ -#define I2C_SCL_FILTER_THRES 0x00000007 -#define I2C_SCL_FILTER_THRES_M ((I2C_SCL_FILTER_THRES_V)<<(I2C_SCL_FILTER_THRES_S)) -#define I2C_SCL_FILTER_THRES_V 0x7 -#define I2C_SCL_FILTER_THRES_S 0 - -#define I2C_SDA_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x0054) -/* I2C_SDA_FILTER_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: This is the filter enable bit for SDA.*/ -#define I2C_SDA_FILTER_EN (BIT(3)) -#define I2C_SDA_FILTER_EN_M (BIT(3)) -#define I2C_SDA_FILTER_EN_V 0x1 -#define I2C_SDA_FILTER_EN_S 3 -/* I2C_SDA_FILTER_THRES : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ -/*description: When input SCL's pulse width is smaller than this register value - I2C ignores this pulse.*/ -#define I2C_SDA_FILTER_THRES 0x00000007 -#define I2C_SDA_FILTER_THRES_M ((I2C_SDA_FILTER_THRES_V)<<(I2C_SDA_FILTER_THRES_S)) -#define I2C_SDA_FILTER_THRES_V 0x7 -#define I2C_SDA_FILTER_THRES_S 0 - -#define I2C_COMD0_REG(i) (REG_I2C_BASE(i) + 0x0058) -/* I2C_COMMAND0_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command0 is done in I2C Master mode this bit changes to high level.*/ -#define I2C_COMMAND0_DONE (BIT(31)) -#define I2C_COMMAND0_DONE_M (BIT(31)) -#define I2C_COMMAND0_DONE_V 0x1 -#define I2C_COMMAND0_DONE_S 31 -/* I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command0. It consists of three part. op_code - is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ -#define I2C_COMMAND0 0x00003FFF -#define I2C_COMMAND0_M ((I2C_COMMAND0_V)<<(I2C_COMMAND0_S)) -#define I2C_COMMAND0_V 0x3FFF -#define I2C_COMMAND0_S 0 - -#define I2C_COMD1_REG(i) (REG_I2C_BASE(i) + 0x005C) -/* I2C_COMMAND1_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command1 is done in I2C Master mode this bit changes to high level.*/ -#define I2C_COMMAND1_DONE (BIT(31)) -#define I2C_COMMAND1_DONE_M (BIT(31)) -#define I2C_COMMAND1_DONE_V 0x1 -#define I2C_COMMAND1_DONE_S 31 -/* I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command1. It consists of three part. op_code - is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ -#define I2C_COMMAND1 0x00003FFF -#define I2C_COMMAND1_M ((I2C_COMMAND1_V)<<(I2C_COMMAND1_S)) -#define I2C_COMMAND1_V 0x3FFF -#define I2C_COMMAND1_S 0 - -#define I2C_COMD2_REG(i) (REG_I2C_BASE(i) + 0x0060) -/* I2C_COMMAND2_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command2 is done in I2C Master mode this bit changes to high level.*/ -#define I2C_COMMAND2_DONE (BIT(31)) -#define I2C_COMMAND2_DONE_M (BIT(31)) -#define I2C_COMMAND2_DONE_V 0x1 -#define I2C_COMMAND2_DONE_S 31 -/* I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command2. It consists of three part. op_code - is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ -#define I2C_COMMAND2 0x00003FFF -#define I2C_COMMAND2_M ((I2C_COMMAND2_V)<<(I2C_COMMAND2_S)) -#define I2C_COMMAND2_V 0x3FFF -#define I2C_COMMAND2_S 0 - -#define I2C_COMD3_REG(i) (REG_I2C_BASE(i) + 0x0064) -/* I2C_COMMAND3_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command3 is done in I2C Master mode this bit changes to high level.*/ -#define I2C_COMMAND3_DONE (BIT(31)) -#define I2C_COMMAND3_DONE_M (BIT(31)) -#define I2C_COMMAND3_DONE_V 0x1 -#define I2C_COMMAND3_DONE_S 31 -/* I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command3. It consists of three part. op_code - is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ -#define I2C_COMMAND3 0x00003FFF -#define I2C_COMMAND3_M ((I2C_COMMAND3_V)<<(I2C_COMMAND3_S)) -#define I2C_COMMAND3_V 0x3FFF -#define I2C_COMMAND3_S 0 - -#define I2C_COMD4_REG(i) (REG_I2C_BASE(i) + 0x0068) -/* I2C_COMMAND4_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command4 is done in I2C Master mode this bit changes to high level.*/ -#define I2C_COMMAND4_DONE (BIT(31)) -#define I2C_COMMAND4_DONE_M (BIT(31)) -#define I2C_COMMAND4_DONE_V 0x1 -#define I2C_COMMAND4_DONE_S 31 -/* I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command4. It consists of three part. op_code - is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ -#define I2C_COMMAND4 0x00003FFF -#define I2C_COMMAND4_M ((I2C_COMMAND4_V)<<(I2C_COMMAND4_S)) -#define I2C_COMMAND4_V 0x3FFF -#define I2C_COMMAND4_S 0 - -#define I2C_COMD5_REG(i) (REG_I2C_BASE(i) + 0x006C) -/* I2C_COMMAND5_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command5 is done in I2C Master mode this bit changes to high level.*/ -#define I2C_COMMAND5_DONE (BIT(31)) -#define I2C_COMMAND5_DONE_M (BIT(31)) -#define I2C_COMMAND5_DONE_V 0x1 -#define I2C_COMMAND5_DONE_S 31 -/* I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command5. It consists of three part. op_code - is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ -#define I2C_COMMAND5 0x00003FFF -#define I2C_COMMAND5_M ((I2C_COMMAND5_V)<<(I2C_COMMAND5_S)) -#define I2C_COMMAND5_V 0x3FFF -#define I2C_COMMAND5_S 0 - -#define I2C_COMD6_REG(i) (REG_I2C_BASE(i) + 0x0070) -/* I2C_COMMAND6_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command6 is done in I2C Master mode this bit changes to high level.*/ -#define I2C_COMMAND6_DONE (BIT(31)) -#define I2C_COMMAND6_DONE_M (BIT(31)) -#define I2C_COMMAND6_DONE_V 0x1 -#define I2C_COMMAND6_DONE_S 31 -/* I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command6. It consists of three part. op_code - is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ -#define I2C_COMMAND6 0x00003FFF -#define I2C_COMMAND6_M ((I2C_COMMAND6_V)<<(I2C_COMMAND6_S)) -#define I2C_COMMAND6_V 0x3FFF -#define I2C_COMMAND6_S 0 - -#define I2C_COMD7_REG(i) (REG_I2C_BASE(i) + 0x0074) -/* I2C_COMMAND7_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command7 is done in I2C Master mode this bit changes to high level.*/ -#define I2C_COMMAND7_DONE (BIT(31)) -#define I2C_COMMAND7_DONE_M (BIT(31)) -#define I2C_COMMAND7_DONE_V 0x1 -#define I2C_COMMAND7_DONE_S 31 -/* I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command7. It consists of three part. op_code - is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ -#define I2C_COMMAND7 0x00003FFF -#define I2C_COMMAND7_M ((I2C_COMMAND7_V)<<(I2C_COMMAND7_S)) -#define I2C_COMMAND7_V 0x3FFF -#define I2C_COMMAND7_S 0 - -#define I2C_COMD8_REG(i) (REG_I2C_BASE(i) + 0x0078) -/* I2C_COMMAND8_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command8 is done in I2C Master mode this bit changes to high level.*/ -#define I2C_COMMAND8_DONE (BIT(31)) -#define I2C_COMMAND8_DONE_M (BIT(31)) -#define I2C_COMMAND8_DONE_V 0x1 -#define I2C_COMMAND8_DONE_S 31 -/* I2C_COMMAND8 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command8. It consists of three part. op_code - is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ -#define I2C_COMMAND8 0x00003FFF -#define I2C_COMMAND8_M ((I2C_COMMAND8_V)<<(I2C_COMMAND8_S)) -#define I2C_COMMAND8_V 0x3FFF -#define I2C_COMMAND8_S 0 - -#define I2C_COMD9_REG(i) (REG_I2C_BASE(i) + 0x007C) -/* I2C_COMMAND9_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command9 is done in I2C Master mode this bit changes to high level.*/ -#define I2C_COMMAND9_DONE (BIT(31)) -#define I2C_COMMAND9_DONE_M (BIT(31)) -#define I2C_COMMAND9_DONE_V 0x1 -#define I2C_COMMAND9_DONE_S 31 -/* I2C_COMMAND9 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command9. It consists of three part. op_code - is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ -#define I2C_COMMAND9 0x00003FFF -#define I2C_COMMAND9_M ((I2C_COMMAND9_V)<<(I2C_COMMAND9_S)) -#define I2C_COMMAND9_V 0x3FFF -#define I2C_COMMAND9_S 0 - -#define I2C_COMD10_REG(i) (REG_I2C_BASE(i) + 0x0080) -/* I2C_COMMAND10_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command10 is done in I2C Master mode this bit changes to high level.*/ -#define I2C_COMMAND10_DONE (BIT(31)) -#define I2C_COMMAND10_DONE_M (BIT(31)) -#define I2C_COMMAND10_DONE_V 0x1 -#define I2C_COMMAND10_DONE_S 31 -/* I2C_COMMAND10 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command10. It consists of three part. - op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ -#define I2C_COMMAND10 0x00003FFF -#define I2C_COMMAND10_M ((I2C_COMMAND10_V)<<(I2C_COMMAND10_S)) -#define I2C_COMMAND10_V 0x3FFF -#define I2C_COMMAND10_S 0 - -#define I2C_COMD11_REG(i) (REG_I2C_BASE(i) + 0x0084) -/* I2C_COMMAND11_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command11 is done in I2C Master mode this bit changes to high level.*/ -#define I2C_COMMAND11_DONE (BIT(31)) -#define I2C_COMMAND11_DONE_M (BIT(31)) -#define I2C_COMMAND11_DONE_V 0x1 -#define I2C_COMMAND11_DONE_S 31 -/* I2C_COMMAND11 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command11. It consists of three part. - op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ -#define I2C_COMMAND11 0x00003FFF -#define I2C_COMMAND11_M ((I2C_COMMAND11_V)<<(I2C_COMMAND11_S)) -#define I2C_COMMAND11_V 0x3FFF -#define I2C_COMMAND11_S 0 - -#define I2C_COMD12_REG(i) (REG_I2C_BASE(i) + 0x0088) -/* I2C_COMMAND12_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command12 is done in I2C Master mode this bit changes to high level.*/ -#define I2C_COMMAND12_DONE (BIT(31)) -#define I2C_COMMAND12_DONE_M (BIT(31)) -#define I2C_COMMAND12_DONE_V 0x1 -#define I2C_COMMAND12_DONE_S 31 -/* I2C_COMMAND12 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command12. It consists of three part. - op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ -#define I2C_COMMAND12 0x00003FFF -#define I2C_COMMAND12_M ((I2C_COMMAND12_V)<<(I2C_COMMAND12_S)) -#define I2C_COMMAND12_V 0x3FFF -#define I2C_COMMAND12_S 0 - -#define I2C_COMD13_REG(i) (REG_I2C_BASE(i) + 0x008C) -/* I2C_COMMAND13_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command13 is done in I2C Master mode this bit changes to high level.*/ -#define I2C_COMMAND13_DONE (BIT(31)) -#define I2C_COMMAND13_DONE_M (BIT(31)) -#define I2C_COMMAND13_DONE_V 0x1 -#define I2C_COMMAND13_DONE_S 31 -/* I2C_COMMAND13 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command13. It consists of three part. - op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ -#define I2C_COMMAND13 0x00003FFF -#define I2C_COMMAND13_M ((I2C_COMMAND13_V)<<(I2C_COMMAND13_S)) -#define I2C_COMMAND13_V 0x3FFF -#define I2C_COMMAND13_S 0 - -#define I2C_COMD14_REG(i) (REG_I2C_BASE(i) + 0x0090) -/* I2C_COMMAND14_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command14 is done in I2C Master mode this bit changes to high level.*/ -#define I2C_COMMAND14_DONE (BIT(31)) -#define I2C_COMMAND14_DONE_M (BIT(31)) -#define I2C_COMMAND14_DONE_V 0x1 -#define I2C_COMMAND14_DONE_S 31 -/* I2C_COMMAND14 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command14. It consists of three part. - op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ -#define I2C_COMMAND14 0x00003FFF -#define I2C_COMMAND14_M ((I2C_COMMAND14_V)<<(I2C_COMMAND14_S)) -#define I2C_COMMAND14_V 0x3FFF -#define I2C_COMMAND14_S 0 - -#define I2C_COMD15_REG(i) (REG_I2C_BASE(i) + 0x0094) -/* I2C_COMMAND15_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command15 is done in I2C Master mode this bit changes to high level.*/ -#define I2C_COMMAND15_DONE (BIT(31)) -#define I2C_COMMAND15_DONE_M (BIT(31)) -#define I2C_COMMAND15_DONE_V 0x1 -#define I2C_COMMAND15_DONE_S 31 -/* I2C_COMMAND15 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command15. It consists of three part. - op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ -#define I2C_COMMAND15 0x00003FFF -#define I2C_COMMAND15_M ((I2C_COMMAND15_V)<<(I2C_COMMAND15_S)) -#define I2C_COMMAND15_V 0x3FFF -#define I2C_COMMAND15_S 0 - -#define I2C_DATE_REG(i) (REG_I2C_BASE(i) + 0x00F8) -/* I2C_DATE : R/W ;bitpos:[31:0] ;default: 32'h16042000 ; */ -/*description: */ -#define I2C_DATE 0xFFFFFFFF -#define I2C_DATE_M ((I2C_DATE_V)<<(I2C_DATE_S)) -#define I2C_DATE_V 0xFFFFFFFF -#define I2C_DATE_S 0 - -#define I2C_FIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x0100) - - - - -#endif /*_SOC_I2C_REG_H_ */ - - +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_I2C_REG_H_ +#define _SOC_I2C_REG_H_ + + +#include "soc.h" + +#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) + +#define I2C_SCL_LOW_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0000) +/* I2C_SCL_LOW_PERIOD : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This register is used to configure the low level width of SCL clock.*/ +#define I2C_SCL_LOW_PERIOD 0x00003FFF +#define I2C_SCL_LOW_PERIOD_M ((I2C_SCL_LOW_PERIOD_V)<<(I2C_SCL_LOW_PERIOD_S)) +#define I2C_SCL_LOW_PERIOD_V 0x3FFF +#define I2C_SCL_LOW_PERIOD_S 0 + +#define I2C_CTR_REG(i) (REG_I2C_BASE(i) + 0x0004) +/* I2C_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: This is the clock gating control bit for reading or writing registers.*/ +#define I2C_CLK_EN (BIT(8)) +#define I2C_CLK_EN_M (BIT(8)) +#define I2C_CLK_EN_V 0x1 +#define I2C_CLK_EN_S 8 +/* I2C_RX_LSB_FIRST : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: This bit is used to control the storage mode for received datas. + 1: receive data from most significant bit 0: receive data from least significant bit*/ +#define I2C_RX_LSB_FIRST (BIT(7)) +#define I2C_RX_LSB_FIRST_M (BIT(7)) +#define I2C_RX_LSB_FIRST_V 0x1 +#define I2C_RX_LSB_FIRST_S 7 +/* I2C_TX_LSB_FIRST : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This bit is used to control the sending mode for data need to + be send. 1: receive data from most significant bit 0: receive data from least significant bit*/ +#define I2C_TX_LSB_FIRST (BIT(6)) +#define I2C_TX_LSB_FIRST_M (BIT(6)) +#define I2C_TX_LSB_FIRST_V 0x1 +#define I2C_TX_LSB_FIRST_S 6 +/* I2C_TRANS_START : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to start sending data in txfifo.*/ +#define I2C_TRANS_START (BIT(5)) +#define I2C_TRANS_START_M (BIT(5)) +#define I2C_TRANS_START_V 0x1 +#define I2C_TRANS_START_S 5 +/* I2C_MS_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to configure the module as i2c master clear this + bit to configure the module as i2c slave.*/ +#define I2C_MS_MODE (BIT(4)) +#define I2C_MS_MODE_M (BIT(4)) +#define I2C_MS_MODE_V 0x1 +#define I2C_MS_MODE_S 4 +/* I2C_SAMPLE_SCL_LEVEL : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to sample data in SCL low level. clear this bit + to sample data in SCL high level.*/ +#define I2C_SAMPLE_SCL_LEVEL (BIT(2)) +#define I2C_SAMPLE_SCL_LEVEL_M (BIT(2)) +#define I2C_SAMPLE_SCL_LEVEL_V 0x1 +#define I2C_SAMPLE_SCL_LEVEL_S 2 +/* I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: 1: normally ouput scl clock 0: exchange the function of scl_o + and scl_oe (scl_o is the original internal output scl signal scl_oe is the enable bit for the internal output scl signal)*/ +#define I2C_SCL_FORCE_OUT (BIT(1)) +#define I2C_SCL_FORCE_OUT_M (BIT(1)) +#define I2C_SCL_FORCE_OUT_V 0x1 +#define I2C_SCL_FORCE_OUT_S 1 +/* I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: 1: normally ouput sda data 0: exchange the function of sda_o + and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal)*/ +#define I2C_SDA_FORCE_OUT (BIT(0)) +#define I2C_SDA_FORCE_OUT_M (BIT(0)) +#define I2C_SDA_FORCE_OUT_V 0x1 +#define I2C_SDA_FORCE_OUT_S 0 + +#define I2C_SR_REG(i) (REG_I2C_BASE(i) + 0x0008) +/* I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */ +/*description: This register stores the value of state machine to produce SCL. + 3'h0: SCL_IDLE 3'h1:SCL_START 3'h2:SCL_LOW_EDGE 3'h3: SCL_LOW 3'h4:SCL_HIGH_EDGE 3'h5:SCL_HIGH 3'h6:SCL_STOP*/ +#define I2C_SCL_STATE_LAST 0x00000007 +#define I2C_SCL_STATE_LAST_M ((I2C_SCL_STATE_LAST_V)<<(I2C_SCL_STATE_LAST_S)) +#define I2C_SCL_STATE_LAST_V 0x7 +#define I2C_SCL_STATE_LAST_S 28 +/* I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */ +/*description: This register stores the value of state machine for i2c module. + 3'h0: SCL_MAIN_IDLE 3'h1: SCL_ADDRESS_SHIFT 3'h2: SCL_ACK_ADDRESS 3'h3: SCL_RX_DATA 3'h4 SCL_TX_DATA 3'h5:SCL_SEND_ACK 3'h6:SCL_WAIT_ACK*/ +#define I2C_SCL_MAIN_STATE_LAST 0x00000007 +#define I2C_SCL_MAIN_STATE_LAST_M ((I2C_SCL_MAIN_STATE_LAST_V)<<(I2C_SCL_MAIN_STATE_LAST_S)) +#define I2C_SCL_MAIN_STATE_LAST_V 0x7 +#define I2C_SCL_MAIN_STATE_LAST_S 24 +/* I2C_TXFIFO_CNT : RO ;bitpos:[23:18] ;default: 6'b0 ; */ +/*description: This register stores the amount of received data in ram.*/ +#define I2C_TXFIFO_CNT 0x0000003F +#define I2C_TXFIFO_CNT_M ((I2C_TXFIFO_CNT_V)<<(I2C_TXFIFO_CNT_S)) +#define I2C_TXFIFO_CNT_V 0x3F +#define I2C_TXFIFO_CNT_S 18 +/* I2C_RXFIFO_CNT : RO ;bitpos:[13:8] ;default: 6'b0 ; */ +/*description: This register represent the amount of data need to send.*/ +#define I2C_RXFIFO_CNT 0x0000003F +#define I2C_RXFIFO_CNT_M ((I2C_RXFIFO_CNT_V)<<(I2C_RXFIFO_CNT_S)) +#define I2C_RXFIFO_CNT_V 0x3F +#define I2C_RXFIFO_CNT_S 8 +/* I2C_BYTE_TRANS : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This register changes to high level when one byte is transferred.*/ +#define I2C_BYTE_TRANS (BIT(6)) +#define I2C_BYTE_TRANS_M (BIT(6)) +#define I2C_BYTE_TRANS_V 0x1 +#define I2C_BYTE_TRANS_S 6 +/* I2C_SLAVE_ADDRESSED : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: when configured as i2c slave and the address send by master + is equal to slave's address then this bit will be high level.*/ +#define I2C_SLAVE_ADDRESSED (BIT(5)) +#define I2C_SLAVE_ADDRESSED_M (BIT(5)) +#define I2C_SLAVE_ADDRESSED_V 0x1 +#define I2C_SLAVE_ADDRESSED_S 5 +/* I2C_BUS_BUSY : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: 1:I2C bus is busy transferring data. 0:I2C bus is in idle state.*/ +#define I2C_BUS_BUSY (BIT(4)) +#define I2C_BUS_BUSY_M (BIT(4)) +#define I2C_BUS_BUSY_V 0x1 +#define I2C_BUS_BUSY_S 4 +/* I2C_ARB_LOST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: when I2C lost control of SDA line this register changes to high level.*/ +#define I2C_ARB_LOST (BIT(3)) +#define I2C_ARB_LOST_M (BIT(3)) +#define I2C_ARB_LOST_V 0x1 +#define I2C_ARB_LOST_S 3 +/* I2C_TIME_OUT : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: when I2C takes more than time_out_reg clocks to receive a data + then this register changes to high level.*/ +#define I2C_TIME_OUT (BIT(2)) +#define I2C_TIME_OUT_M (BIT(2)) +#define I2C_TIME_OUT_V 0x1 +#define I2C_TIME_OUT_S 2 +/* I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: when in slave mode 1: master read slave 0: master write slave.*/ +#define I2C_SLAVE_RW (BIT(1)) +#define I2C_SLAVE_RW_M (BIT(1)) +#define I2C_SLAVE_RW_V 0x1 +#define I2C_SLAVE_RW_S 1 +/* I2C_ACK_REC : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This register stores the value of ACK bit.*/ +#define I2C_ACK_REC (BIT(0)) +#define I2C_ACK_REC_M (BIT(0)) +#define I2C_ACK_REC_V 0x1 +#define I2C_ACK_REC_S 0 + +#define I2C_TO_REG(i) (REG_I2C_BASE(i) + 0x000c) +/* I2C_TIME_OUT_REG : R/W ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: This register is used to configure the max clock number of receiving a data.*/ +#define I2C_TIME_OUT_REG 0x000FFFFF +#define I2C_TIME_OUT_REG_M ((I2C_TIME_OUT_REG_V)<<(I2C_TIME_OUT_REG_S)) +#define I2C_TIME_OUT_REG_V 0xFFFFF +#define I2C_TIME_OUT_REG_S 0 + +#define I2C_SLAVE_ADDR_REG(i) (REG_I2C_BASE(i) + 0x0010) +/* I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: This register is used to enable slave 10bit address mode.*/ +#define I2C_ADDR_10BIT_EN (BIT(31)) +#define I2C_ADDR_10BIT_EN_M (BIT(31)) +#define I2C_ADDR_10BIT_EN_V 0x1 +#define I2C_ADDR_10BIT_EN_S 31 +/* I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */ +/*description: when configured as i2c slave this register is used to configure + slave's address.*/ +#define I2C_SLAVE_ADDR 0x00007FFF +#define I2C_SLAVE_ADDR_M ((I2C_SLAVE_ADDR_V)<<(I2C_SLAVE_ADDR_S)) +#define I2C_SLAVE_ADDR_V 0x7FFF +#define I2C_SLAVE_ADDR_S 0 + +#define I2C_RXFIFO_ST_REG(i) (REG_I2C_BASE(i) + 0x0014) +/* I2C_TXFIFO_END_ADDR : RO ;bitpos:[19:15] ;default: 5'b0 ; */ +/*description: This is the offset address of the last sending data as described + in nonfifo_tx_thres register.*/ +#define I2C_TXFIFO_END_ADDR 0x0000001F +#define I2C_TXFIFO_END_ADDR_M ((I2C_TXFIFO_END_ADDR_V)<<(I2C_TXFIFO_END_ADDR_S)) +#define I2C_TXFIFO_END_ADDR_V 0x1F +#define I2C_TXFIFO_END_ADDR_S 15 +/* I2C_TXFIFO_START_ADDR : RO ;bitpos:[14:10] ;default: 5'b0 ; */ +/*description: This is the offset address of the first sending data as described + in nonfifo_tx_thres register.*/ +#define I2C_TXFIFO_START_ADDR 0x0000001F +#define I2C_TXFIFO_START_ADDR_M ((I2C_TXFIFO_START_ADDR_V)<<(I2C_TXFIFO_START_ADDR_S)) +#define I2C_TXFIFO_START_ADDR_V 0x1F +#define I2C_TXFIFO_START_ADDR_S 10 +/* I2C_RXFIFO_END_ADDR : RO ;bitpos:[9:5] ;default: 5'b0 ; */ +/*description: This is the offset address of the first receiving data as described + in nonfifo_rx_thres_register.*/ +#define I2C_RXFIFO_END_ADDR 0x0000001F +#define I2C_RXFIFO_END_ADDR_M ((I2C_RXFIFO_END_ADDR_V)<<(I2C_RXFIFO_END_ADDR_S)) +#define I2C_RXFIFO_END_ADDR_V 0x1F +#define I2C_RXFIFO_END_ADDR_S 5 +/* I2C_RXFIFO_START_ADDR : RO ;bitpos:[4:0] ;default: 5'b0 ; */ +/*description: This is the offset address of the last receiving data as described + in nonfifo_rx_thres_register.*/ +#define I2C_RXFIFO_START_ADDR 0x0000001F +#define I2C_RXFIFO_START_ADDR_M ((I2C_RXFIFO_START_ADDR_V)<<(I2C_RXFIFO_START_ADDR_S)) +#define I2C_RXFIFO_START_ADDR_V 0x1F +#define I2C_RXFIFO_START_ADDR_S 0 + +#define I2C_FIFO_CONF_REG(i) (REG_I2C_BASE(i) + 0x0018) +/* I2C_NONFIFO_TX_THRES : R/W ;bitpos:[25:20] ;default: 6'h15 ; */ +/*description: when I2C sends more than nonfifo_tx_thres data it will produce + tx_send_empty_int_raw interrupt and update the current offset address of the sending data.*/ +#define I2C_NONFIFO_TX_THRES 0x0000003F +#define I2C_NONFIFO_TX_THRES_M ((I2C_NONFIFO_TX_THRES_V)<<(I2C_NONFIFO_TX_THRES_S)) +#define I2C_NONFIFO_TX_THRES_V 0x3F +#define I2C_NONFIFO_TX_THRES_S 20 +/* I2C_NONFIFO_RX_THRES : R/W ;bitpos:[19:14] ;default: 6'h15 ; */ +/*description: when I2C receives more than nonfifo_rx_thres data it will produce + rx_send_full_int_raw interrupt and update the current offset address of the receiving data.*/ +#define I2C_NONFIFO_RX_THRES 0x0000003F +#define I2C_NONFIFO_RX_THRES_M ((I2C_NONFIFO_RX_THRES_V)<<(I2C_NONFIFO_RX_THRES_S)) +#define I2C_NONFIFO_RX_THRES_V 0x3F +#define I2C_NONFIFO_RX_THRES_S 14 +/* I2C_TX_FIFO_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Set this bit to reset tx fifo when using apb fifo access.*/ +#define I2C_TX_FIFO_RST (BIT(13)) +#define I2C_TX_FIFO_RST_M (BIT(13)) +#define I2C_TX_FIFO_RST_V 0x1 +#define I2C_TX_FIFO_RST_S 13 +/* I2C_RX_FIFO_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to reset rx fifo when using apb fifo access.*/ +#define I2C_RX_FIFO_RST (BIT(12)) +#define I2C_RX_FIFO_RST_M (BIT(12)) +#define I2C_RX_FIFO_RST_V 0x1 +#define I2C_RX_FIFO_RST_S 12 +/* I2C_FIFO_ADDR_CFG_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: When this bit is set to 1 then the byte after address represent + the offset address of I2C Slave's ram.*/ +#define I2C_FIFO_ADDR_CFG_EN (BIT(11)) +#define I2C_FIFO_ADDR_CFG_EN_M (BIT(11)) +#define I2C_FIFO_ADDR_CFG_EN_V 0x1 +#define I2C_FIFO_ADDR_CFG_EN_S 11 +/* I2C_NONFIFO_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to enble apb nonfifo access.*/ +#define I2C_NONFIFO_EN (BIT(10)) +#define I2C_NONFIFO_EN_M (BIT(10)) +#define I2C_NONFIFO_EN_V 0x1 +#define I2C_NONFIFO_EN_S 10 +/* I2C_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[9:5] ;default: 5'h4 ; */ +/*description: Config txfifo empty threhd value when using apb fifo access*/ +#define I2C_TXFIFO_EMPTY_THRHD 0x0000001F +#define I2C_TXFIFO_EMPTY_THRHD_M ((I2C_TXFIFO_EMPTY_THRHD_V)<<(I2C_TXFIFO_EMPTY_THRHD_S)) +#define I2C_TXFIFO_EMPTY_THRHD_V 0x1F +#define I2C_TXFIFO_EMPTY_THRHD_S 5 +/* I2C_RXFIFO_FULL_THRHD : R/W ;bitpos:[4:0] ;default: 5'hb ; */ +/*description: */ +#define I2C_RXFIFO_FULL_THRHD 0x0000001F +#define I2C_RXFIFO_FULL_THRHD_M ((I2C_RXFIFO_FULL_THRHD_V)<<(I2C_RXFIFO_FULL_THRHD_S)) +#define I2C_RXFIFO_FULL_THRHD_V 0x1F +#define I2C_RXFIFO_FULL_THRHD_S 0 + +#define I2C_DATA_APB_REG(i) (0x60013000 + (i) * 0x14000 + 0x001c) + +#define I2C_DATA_REG(i) (REG_I2C_BASE(i) + 0x001c) +/* I2C_FIFO_RDATA : RO ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: The register represent the byte data read from rxfifo when use apb fifo access*/ +#define I2C_FIFO_RDATA 0x000000FF +#define I2C_FIFO_RDATA_M ((I2C_FIFO_RDATA_V)<<(I2C_FIFO_RDATA_S)) +#define I2C_FIFO_RDATA_V 0xFF +#define I2C_FIFO_RDATA_S 0 + +#define I2C_INT_RAW_REG(i) (REG_I2C_BASE(i) + 0x0020) +/* I2C_TX_SEND_EMPTY_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for tx_send_empty_int interrupt.when + I2C sends more data than nonfifo_tx_thres it will produce tx_send_empty_int interrupt..*/ +#define I2C_TX_SEND_EMPTY_INT_RAW (BIT(12)) +#define I2C_TX_SEND_EMPTY_INT_RAW_M (BIT(12)) +#define I2C_TX_SEND_EMPTY_INT_RAW_V 0x1 +#define I2C_TX_SEND_EMPTY_INT_RAW_S 12 +/* I2C_RX_REC_FULL_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for rx_rec_full_int interrupt. when + I2C receives more data than nonfifo_rx_thres it will produce rx_rec_full_int interrupt.*/ +#define I2C_RX_REC_FULL_INT_RAW (BIT(11)) +#define I2C_RX_REC_FULL_INT_RAW_M (BIT(11)) +#define I2C_RX_REC_FULL_INT_RAW_V 0x1 +#define I2C_RX_REC_FULL_INT_RAW_S 11 +/* I2C_ACK_ERR_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for ack_err_int interrupt. when + I2C receives a wrong ACK bit it will produce ack_err_int interrupt..*/ +#define I2C_ACK_ERR_INT_RAW (BIT(10)) +#define I2C_ACK_ERR_INT_RAW_M (BIT(10)) +#define I2C_ACK_ERR_INT_RAW_V 0x1 +#define I2C_ACK_ERR_INT_RAW_S 10 +/* I2C_TRANS_START_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for trans_start_int interrupt. when + I2C sends the START bit it will produce trans_start_int interrupt.*/ +#define I2C_TRANS_START_INT_RAW (BIT(9)) +#define I2C_TRANS_START_INT_RAW_M (BIT(9)) +#define I2C_TRANS_START_INT_RAW_V 0x1 +#define I2C_TRANS_START_INT_RAW_S 9 +/* I2C_TIME_OUT_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for time_out_int interrupt. when + I2C takes a lot of time to receive a data it will produce time_out_int interrupt.*/ +#define I2C_TIME_OUT_INT_RAW (BIT(8)) +#define I2C_TIME_OUT_INT_RAW_M (BIT(8)) +#define I2C_TIME_OUT_INT_RAW_V 0x1 +#define I2C_TIME_OUT_INT_RAW_S 8 +/* I2C_TRANS_COMPLETE_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for trans_complete_int interrupt. + when I2C Master finished STOP command it will produce trans_complete_int interrupt.*/ +#define I2C_TRANS_COMPLETE_INT_RAW (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_RAW_M (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_RAW_V 0x1 +#define I2C_TRANS_COMPLETE_INT_RAW_S 7 +/* I2C_MASTER_TRAN_COMP_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for master_tra_comp_int interrupt. + when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt.*/ +#define I2C_MASTER_TRAN_COMP_INT_RAW (BIT(6)) +#define I2C_MASTER_TRAN_COMP_INT_RAW_M (BIT(6)) +#define I2C_MASTER_TRAN_COMP_INT_RAW_V 0x1 +#define I2C_MASTER_TRAN_COMP_INT_RAW_S 6 +/* I2C_ARBITRATION_LOST_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for arbitration_lost_int interrupt.when + I2C lost the usage right of I2C BUS it will produce arbitration_lost_int interrupt.*/ +#define I2C_ARBITRATION_LOST_INT_RAW (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_RAW_M (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_RAW_V 0x1 +#define I2C_ARBITRATION_LOST_INT_RAW_S 5 +/* I2C_SLAVE_TRAN_COMP_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for slave_tran_comp_int interrupt. + when I2C Slave detectsthe STOP bit it will produce slave_tran_comp_int interrupt.*/ +#define I2C_SLAVE_TRAN_COMP_INT_RAW (BIT(4)) +#define I2C_SLAVE_TRAN_COMP_INT_RAW_M (BIT(4)) +#define I2C_SLAVE_TRAN_COMP_INT_RAW_V 0x1 +#define I2C_SLAVE_TRAN_COMP_INT_RAW_S 4 +/* I2C_END_DETECT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for end_detect_int interrupt. when + I2C deals with the END command it will produce end_detect_int interrupt.*/ +#define I2C_END_DETECT_INT_RAW (BIT(3)) +#define I2C_END_DETECT_INT_RAW_M (BIT(3)) +#define I2C_END_DETECT_INT_RAW_V 0x1 +#define I2C_END_DETECT_INT_RAW_S 3 +/* I2C_RXFIFO_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for receiving data overflow when + use apb fifo access.*/ +#define I2C_RXFIFO_OVF_INT_RAW (BIT(2)) +#define I2C_RXFIFO_OVF_INT_RAW_M (BIT(2)) +#define I2C_RXFIFO_OVF_INT_RAW_V 0x1 +#define I2C_RXFIFO_OVF_INT_RAW_S 2 +/* I2C_TXFIFO_EMPTY_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for txfifo empty when use apb fifo access.*/ +#define I2C_TXFIFO_EMPTY_INT_RAW (BIT(1)) +#define I2C_TXFIFO_EMPTY_INT_RAW_M (BIT(1)) +#define I2C_TXFIFO_EMPTY_INT_RAW_V 0x1 +#define I2C_TXFIFO_EMPTY_INT_RAW_S 1 +/* I2C_RXFIFO_FULL_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for rxfifo full when use apb fifo access.*/ +#define I2C_RXFIFO_FULL_INT_RAW (BIT(0)) +#define I2C_RXFIFO_FULL_INT_RAW_M (BIT(0)) +#define I2C_RXFIFO_FULL_INT_RAW_V 0x1 +#define I2C_RXFIFO_FULL_INT_RAW_S 0 + +#define I2C_INT_CLR_REG(i) (REG_I2C_BASE(i) + 0x0024) +/* I2C_TX_SEND_EMPTY_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to clear the tx_send_empty_int interrupt.*/ +#define I2C_TX_SEND_EMPTY_INT_CLR (BIT(12)) +#define I2C_TX_SEND_EMPTY_INT_CLR_M (BIT(12)) +#define I2C_TX_SEND_EMPTY_INT_CLR_V 0x1 +#define I2C_TX_SEND_EMPTY_INT_CLR_S 12 +/* I2C_RX_REC_FULL_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rx_rec_full_int interrupt.*/ +#define I2C_RX_REC_FULL_INT_CLR (BIT(11)) +#define I2C_RX_REC_FULL_INT_CLR_M (BIT(11)) +#define I2C_RX_REC_FULL_INT_CLR_V 0x1 +#define I2C_RX_REC_FULL_INT_CLR_S 11 +/* I2C_ACK_ERR_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to clear the ack_err_int interrupt.*/ +#define I2C_ACK_ERR_INT_CLR (BIT(10)) +#define I2C_ACK_ERR_INT_CLR_M (BIT(10)) +#define I2C_ACK_ERR_INT_CLR_V 0x1 +#define I2C_ACK_ERR_INT_CLR_S 10 +/* I2C_TRANS_START_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to clear the trans_start_int interrupt.*/ +#define I2C_TRANS_START_INT_CLR (BIT(9)) +#define I2C_TRANS_START_INT_CLR_M (BIT(9)) +#define I2C_TRANS_START_INT_CLR_V 0x1 +#define I2C_TRANS_START_INT_CLR_S 9 +/* I2C_TIME_OUT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to clear the time_out_int interrupt.*/ +#define I2C_TIME_OUT_INT_CLR (BIT(8)) +#define I2C_TIME_OUT_INT_CLR_M (BIT(8)) +#define I2C_TIME_OUT_INT_CLR_V 0x1 +#define I2C_TIME_OUT_INT_CLR_S 8 +/* I2C_TRANS_COMPLETE_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to clear the trans_complete_int interrupt.*/ +#define I2C_TRANS_COMPLETE_INT_CLR (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_CLR_M (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_CLR_V 0x1 +#define I2C_TRANS_COMPLETE_INT_CLR_S 7 +/* I2C_MASTER_TRAN_COMP_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to clear the master_tran_comp interrupt.*/ +#define I2C_MASTER_TRAN_COMP_INT_CLR (BIT(6)) +#define I2C_MASTER_TRAN_COMP_INT_CLR_M (BIT(6)) +#define I2C_MASTER_TRAN_COMP_INT_CLR_V 0x1 +#define I2C_MASTER_TRAN_COMP_INT_CLR_S 6 +/* I2C_ARBITRATION_LOST_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to clear the arbitration_lost_int interrupt.*/ +#define I2C_ARBITRATION_LOST_INT_CLR (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_CLR_M (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_CLR_V 0x1 +#define I2C_ARBITRATION_LOST_INT_CLR_S 5 +/* I2C_SLAVE_TRAN_COMP_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to clear the slave_tran_comp_int interrupt.*/ +#define I2C_SLAVE_TRAN_COMP_INT_CLR (BIT(4)) +#define I2C_SLAVE_TRAN_COMP_INT_CLR_M (BIT(4)) +#define I2C_SLAVE_TRAN_COMP_INT_CLR_V 0x1 +#define I2C_SLAVE_TRAN_COMP_INT_CLR_S 4 +/* I2C_END_DETECT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear the end_detect_int interrupt.*/ +#define I2C_END_DETECT_INT_CLR (BIT(3)) +#define I2C_END_DETECT_INT_CLR_M (BIT(3)) +#define I2C_END_DETECT_INT_CLR_V 0x1 +#define I2C_END_DETECT_INT_CLR_S 3 +/* I2C_RXFIFO_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rxfifo_ovf_int interrupt.*/ +#define I2C_RXFIFO_OVF_INT_CLR (BIT(2)) +#define I2C_RXFIFO_OVF_INT_CLR_M (BIT(2)) +#define I2C_RXFIFO_OVF_INT_CLR_V 0x1 +#define I2C_RXFIFO_OVF_INT_CLR_S 2 +/* I2C_TXFIFO_EMPTY_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear the txfifo_empty_int interrupt.*/ +#define I2C_TXFIFO_EMPTY_INT_CLR (BIT(1)) +#define I2C_TXFIFO_EMPTY_INT_CLR_M (BIT(1)) +#define I2C_TXFIFO_EMPTY_INT_CLR_V 0x1 +#define I2C_TXFIFO_EMPTY_INT_CLR_S 1 +/* I2C_RXFIFO_FULL_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rxfifo_full_int interrupt.*/ +#define I2C_RXFIFO_FULL_INT_CLR (BIT(0)) +#define I2C_RXFIFO_FULL_INT_CLR_M (BIT(0)) +#define I2C_RXFIFO_FULL_INT_CLR_V 0x1 +#define I2C_RXFIFO_FULL_INT_CLR_S 0 + +#define I2C_INT_ENA_REG(i) (REG_I2C_BASE(i) + 0x0028) +/* I2C_TX_SEND_EMPTY_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The enable bit for tx_send_empty_int interrupt.*/ +#define I2C_TX_SEND_EMPTY_INT_ENA (BIT(12)) +#define I2C_TX_SEND_EMPTY_INT_ENA_M (BIT(12)) +#define I2C_TX_SEND_EMPTY_INT_ENA_V 0x1 +#define I2C_TX_SEND_EMPTY_INT_ENA_S 12 +/* I2C_RX_REC_FULL_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The enable bit for rx_rec_full_int interrupt.*/ +#define I2C_RX_REC_FULL_INT_ENA (BIT(11)) +#define I2C_RX_REC_FULL_INT_ENA_M (BIT(11)) +#define I2C_RX_REC_FULL_INT_ENA_V 0x1 +#define I2C_RX_REC_FULL_INT_ENA_S 11 +/* I2C_ACK_ERR_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The enable bit for ack_err_int interrupt.*/ +#define I2C_ACK_ERR_INT_ENA (BIT(10)) +#define I2C_ACK_ERR_INT_ENA_M (BIT(10)) +#define I2C_ACK_ERR_INT_ENA_V 0x1 +#define I2C_ACK_ERR_INT_ENA_S 10 +/* I2C_TRANS_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The enable bit for trans_start_int interrupt.*/ +#define I2C_TRANS_START_INT_ENA (BIT(9)) +#define I2C_TRANS_START_INT_ENA_M (BIT(9)) +#define I2C_TRANS_START_INT_ENA_V 0x1 +#define I2C_TRANS_START_INT_ENA_S 9 +/* I2C_TIME_OUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The enable bit for time_out_int interrupt.*/ +#define I2C_TIME_OUT_INT_ENA (BIT(8)) +#define I2C_TIME_OUT_INT_ENA_M (BIT(8)) +#define I2C_TIME_OUT_INT_ENA_V 0x1 +#define I2C_TIME_OUT_INT_ENA_S 8 +/* I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The enable bit for trans_complete_int interrupt.*/ +#define I2C_TRANS_COMPLETE_INT_ENA (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ENA_M (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ENA_V 0x1 +#define I2C_TRANS_COMPLETE_INT_ENA_S 7 +/* I2C_MASTER_TRAN_COMP_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The enable bit for master_tran_comp_int interrupt.*/ +#define I2C_MASTER_TRAN_COMP_INT_ENA (BIT(6)) +#define I2C_MASTER_TRAN_COMP_INT_ENA_M (BIT(6)) +#define I2C_MASTER_TRAN_COMP_INT_ENA_V 0x1 +#define I2C_MASTER_TRAN_COMP_INT_ENA_S 6 +/* I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The enable bit for arbitration_lost_int interrupt.*/ +#define I2C_ARBITRATION_LOST_INT_ENA (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ENA_M (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ENA_V 0x1 +#define I2C_ARBITRATION_LOST_INT_ENA_S 5 +/* I2C_SLAVE_TRAN_COMP_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The enable bit for slave_tran_comp_int interrupt.*/ +#define I2C_SLAVE_TRAN_COMP_INT_ENA (BIT(4)) +#define I2C_SLAVE_TRAN_COMP_INT_ENA_M (BIT(4)) +#define I2C_SLAVE_TRAN_COMP_INT_ENA_V 0x1 +#define I2C_SLAVE_TRAN_COMP_INT_ENA_S 4 +/* I2C_END_DETECT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The enable bit for end_detect_int interrupt.*/ +#define I2C_END_DETECT_INT_ENA (BIT(3)) +#define I2C_END_DETECT_INT_ENA_M (BIT(3)) +#define I2C_END_DETECT_INT_ENA_V 0x1 +#define I2C_END_DETECT_INT_ENA_S 3 +/* I2C_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The enable bit for rxfifo_ovf_int interrupt.*/ +#define I2C_RXFIFO_OVF_INT_ENA (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ENA_M (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ENA_V 0x1 +#define I2C_RXFIFO_OVF_INT_ENA_S 2 +/* I2C_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The enable bit for txfifo_empty_int interrupt.*/ +#define I2C_TXFIFO_EMPTY_INT_ENA (BIT(1)) +#define I2C_TXFIFO_EMPTY_INT_ENA_M (BIT(1)) +#define I2C_TXFIFO_EMPTY_INT_ENA_V 0x1 +#define I2C_TXFIFO_EMPTY_INT_ENA_S 1 +/* I2C_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The enable bit for rxfifo_full_int interrupt.*/ +#define I2C_RXFIFO_FULL_INT_ENA (BIT(0)) +#define I2C_RXFIFO_FULL_INT_ENA_M (BIT(0)) +#define I2C_RXFIFO_FULL_INT_ENA_V 0x1 +#define I2C_RXFIFO_FULL_INT_ENA_S 0 + +#define I2C_INT_STATUS_REG(i) (REG_I2C_BASE(i) + 0x002c) +/* I2C_TX_SEND_EMPTY_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The masked interrupt status for tx_send_empty_int interrupt.*/ +#define I2C_TX_SEND_EMPTY_INT_ST (BIT(12)) +#define I2C_TX_SEND_EMPTY_INT_ST_M (BIT(12)) +#define I2C_TX_SEND_EMPTY_INT_ST_V 0x1 +#define I2C_TX_SEND_EMPTY_INT_ST_S 12 +/* I2C_RX_REC_FULL_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The masked interrupt status for rx_rec_full_int interrupt.*/ +#define I2C_RX_REC_FULL_INT_ST (BIT(11)) +#define I2C_RX_REC_FULL_INT_ST_M (BIT(11)) +#define I2C_RX_REC_FULL_INT_ST_V 0x1 +#define I2C_RX_REC_FULL_INT_ST_S 11 +/* I2C_ACK_ERR_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The masked interrupt status for ack_err_int interrupt.*/ +#define I2C_ACK_ERR_INT_ST (BIT(10)) +#define I2C_ACK_ERR_INT_ST_M (BIT(10)) +#define I2C_ACK_ERR_INT_ST_V 0x1 +#define I2C_ACK_ERR_INT_ST_S 10 +/* I2C_TRANS_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The masked interrupt status for trans_start_int interrupt.*/ +#define I2C_TRANS_START_INT_ST (BIT(9)) +#define I2C_TRANS_START_INT_ST_M (BIT(9)) +#define I2C_TRANS_START_INT_ST_V 0x1 +#define I2C_TRANS_START_INT_ST_S 9 +/* I2C_TIME_OUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The masked interrupt status for time_out_int interrupt.*/ +#define I2C_TIME_OUT_INT_ST (BIT(8)) +#define I2C_TIME_OUT_INT_ST_M (BIT(8)) +#define I2C_TIME_OUT_INT_ST_V 0x1 +#define I2C_TIME_OUT_INT_ST_S 8 +/* I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The masked interrupt status for trans_complete_int interrupt.*/ +#define I2C_TRANS_COMPLETE_INT_ST (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ST_M (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ST_V 0x1 +#define I2C_TRANS_COMPLETE_INT_ST_S 7 +/* I2C_MASTER_TRAN_COMP_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The masked interrupt status for master_tran_comp_int interrupt.*/ +#define I2C_MASTER_TRAN_COMP_INT_ST (BIT(6)) +#define I2C_MASTER_TRAN_COMP_INT_ST_M (BIT(6)) +#define I2C_MASTER_TRAN_COMP_INT_ST_V 0x1 +#define I2C_MASTER_TRAN_COMP_INT_ST_S 6 +/* I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The masked interrupt status for arbitration_lost_int interrupt.*/ +#define I2C_ARBITRATION_LOST_INT_ST (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ST_M (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ST_V 0x1 +#define I2C_ARBITRATION_LOST_INT_ST_S 5 +/* I2C_SLAVE_TRAN_COMP_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The masked interrupt status for slave_tran_comp_int interrupt.*/ +#define I2C_SLAVE_TRAN_COMP_INT_ST (BIT(4)) +#define I2C_SLAVE_TRAN_COMP_INT_ST_M (BIT(4)) +#define I2C_SLAVE_TRAN_COMP_INT_ST_V 0x1 +#define I2C_SLAVE_TRAN_COMP_INT_ST_S 4 +/* I2C_END_DETECT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The masked interrupt status for end_detect_int interrupt.*/ +#define I2C_END_DETECT_INT_ST (BIT(3)) +#define I2C_END_DETECT_INT_ST_M (BIT(3)) +#define I2C_END_DETECT_INT_ST_V 0x1 +#define I2C_END_DETECT_INT_ST_S 3 +/* I2C_RXFIFO_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The masked interrupt status for rxfifo_ovf_int interrupt.*/ +#define I2C_RXFIFO_OVF_INT_ST (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ST_M (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ST_V 0x1 +#define I2C_RXFIFO_OVF_INT_ST_S 2 +/* I2C_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The masked interrupt status for txfifo_empty_int interrupt.*/ +#define I2C_TXFIFO_EMPTY_INT_ST (BIT(1)) +#define I2C_TXFIFO_EMPTY_INT_ST_M (BIT(1)) +#define I2C_TXFIFO_EMPTY_INT_ST_V 0x1 +#define I2C_TXFIFO_EMPTY_INT_ST_S 1 +/* I2C_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The masked interrupt status for rxfifo_full_int interrupt.*/ +#define I2C_RXFIFO_FULL_INT_ST (BIT(0)) +#define I2C_RXFIFO_FULL_INT_ST_M (BIT(0)) +#define I2C_RXFIFO_FULL_INT_ST_V 0x1 +#define I2C_RXFIFO_FULL_INT_ST_S 0 + +#define I2C_SDA_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0030) +/* I2C_SDA_HOLD_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */ +/*description: This register is used to configure the clock num I2C used to + hold the data after the negedge of SCL.*/ +#define I2C_SDA_HOLD_TIME 0x000003FF +#define I2C_SDA_HOLD_TIME_M ((I2C_SDA_HOLD_TIME_V)<<(I2C_SDA_HOLD_TIME_S)) +#define I2C_SDA_HOLD_TIME_V 0x3FF +#define I2C_SDA_HOLD_TIME_S 0 + +#define I2C_SDA_SAMPLE_REG(i) (REG_I2C_BASE(i) + 0x0034) +/* I2C_SDA_SAMPLE_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */ +/*description: This register is used to configure the clock num I2C used to + sample data on SDA after the posedge of SCL*/ +#define I2C_SDA_SAMPLE_TIME 0x000003FF +#define I2C_SDA_SAMPLE_TIME_M ((I2C_SDA_SAMPLE_TIME_V)<<(I2C_SDA_SAMPLE_TIME_S)) +#define I2C_SDA_SAMPLE_TIME_V 0x3FF +#define I2C_SDA_SAMPLE_TIME_S 0 + +#define I2C_SCL_HIGH_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0038) +/* I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This register is used to configure the clock num during SCL is low level.*/ +#define I2C_SCL_HIGH_PERIOD 0x00003FFF +#define I2C_SCL_HIGH_PERIOD_M ((I2C_SCL_HIGH_PERIOD_V)<<(I2C_SCL_HIGH_PERIOD_S)) +#define I2C_SCL_HIGH_PERIOD_V 0x3FFF +#define I2C_SCL_HIGH_PERIOD_S 0 + +#define I2C_SCL_START_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0040) +/* I2C_SCL_START_HOLD_TIME : R/W ;bitpos:[9:0] ;default: 10'b1000 ; */ +/*description: This register is used to configure the clock num between the + negedge of SDA and negedge of SCL for start mark.*/ +#define I2C_SCL_START_HOLD_TIME 0x000003FF +#define I2C_SCL_START_HOLD_TIME_M ((I2C_SCL_START_HOLD_TIME_V)<<(I2C_SCL_START_HOLD_TIME_S)) +#define I2C_SCL_START_HOLD_TIME_V 0x3FF +#define I2C_SCL_START_HOLD_TIME_S 0 + +#define I2C_SCL_RSTART_SETUP_REG(i) (REG_I2C_BASE(i) + 0x0044) +/* I2C_SCL_RSTART_SETUP_TIME : R/W ;bitpos:[9:0] ;default: 10'b1000 ; */ +/*description: This register is used to configure the clock num between the + posedge of SCL and the negedge of SDA for restart mark.*/ +#define I2C_SCL_RSTART_SETUP_TIME 0x000003FF +#define I2C_SCL_RSTART_SETUP_TIME_M ((I2C_SCL_RSTART_SETUP_TIME_V)<<(I2C_SCL_RSTART_SETUP_TIME_S)) +#define I2C_SCL_RSTART_SETUP_TIME_V 0x3FF +#define I2C_SCL_RSTART_SETUP_TIME_S 0 + +#define I2C_SCL_STOP_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0048) +/* I2C_SCL_STOP_HOLD_TIME : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This register is used to configure the clock num after the STOP bit's posedge.*/ +#define I2C_SCL_STOP_HOLD_TIME 0x00003FFF +#define I2C_SCL_STOP_HOLD_TIME_M ((I2C_SCL_STOP_HOLD_TIME_V)<<(I2C_SCL_STOP_HOLD_TIME_S)) +#define I2C_SCL_STOP_HOLD_TIME_V 0x3FFF +#define I2C_SCL_STOP_HOLD_TIME_S 0 + +#define I2C_SCL_STOP_SETUP_REG(i) (REG_I2C_BASE(i) + 0x004C) +/* I2C_SCL_STOP_SETUP_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */ +/*description: This register is used to configure the clock num between the + posedge of SCL and the posedge of SDA.*/ +#define I2C_SCL_STOP_SETUP_TIME 0x000003FF +#define I2C_SCL_STOP_SETUP_TIME_M ((I2C_SCL_STOP_SETUP_TIME_V)<<(I2C_SCL_STOP_SETUP_TIME_S)) +#define I2C_SCL_STOP_SETUP_TIME_V 0x3FF +#define I2C_SCL_STOP_SETUP_TIME_S 0 + +#define I2C_SCL_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x0050) +/* I2C_SCL_FILTER_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: This is the filter enable bit for SCL.*/ +#define I2C_SCL_FILTER_EN (BIT(3)) +#define I2C_SCL_FILTER_EN_M (BIT(3)) +#define I2C_SCL_FILTER_EN_V 0x1 +#define I2C_SCL_FILTER_EN_S 3 +/* I2C_SCL_FILTER_THRES : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: When input SCL's pulse width is smaller than this register value + I2C ignores this pulse.*/ +#define I2C_SCL_FILTER_THRES 0x00000007 +#define I2C_SCL_FILTER_THRES_M ((I2C_SCL_FILTER_THRES_V)<<(I2C_SCL_FILTER_THRES_S)) +#define I2C_SCL_FILTER_THRES_V 0x7 +#define I2C_SCL_FILTER_THRES_S 0 + +#define I2C_SDA_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x0054) +/* I2C_SDA_FILTER_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: This is the filter enable bit for SDA.*/ +#define I2C_SDA_FILTER_EN (BIT(3)) +#define I2C_SDA_FILTER_EN_M (BIT(3)) +#define I2C_SDA_FILTER_EN_V 0x1 +#define I2C_SDA_FILTER_EN_S 3 +/* I2C_SDA_FILTER_THRES : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: When input SCL's pulse width is smaller than this register value + I2C ignores this pulse.*/ +#define I2C_SDA_FILTER_THRES 0x00000007 +#define I2C_SDA_FILTER_THRES_M ((I2C_SDA_FILTER_THRES_V)<<(I2C_SDA_FILTER_THRES_S)) +#define I2C_SDA_FILTER_THRES_V 0x7 +#define I2C_SDA_FILTER_THRES_S 0 + +#define I2C_COMD0_REG(i) (REG_I2C_BASE(i) + 0x0058) +/* I2C_COMMAND0_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command0 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND0_DONE (BIT(31)) +#define I2C_COMMAND0_DONE_M (BIT(31)) +#define I2C_COMMAND0_DONE_V 0x1 +#define I2C_COMMAND0_DONE_S 31 +/* I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command0. It consists of three part. op_code + is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND0 0x00003FFF +#define I2C_COMMAND0_M ((I2C_COMMAND0_V)<<(I2C_COMMAND0_S)) +#define I2C_COMMAND0_V 0x3FFF +#define I2C_COMMAND0_S 0 + +#define I2C_COMD1_REG(i) (REG_I2C_BASE(i) + 0x005C) +/* I2C_COMMAND1_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command1 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND1_DONE (BIT(31)) +#define I2C_COMMAND1_DONE_M (BIT(31)) +#define I2C_COMMAND1_DONE_V 0x1 +#define I2C_COMMAND1_DONE_S 31 +/* I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command1. It consists of three part. op_code + is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND1 0x00003FFF +#define I2C_COMMAND1_M ((I2C_COMMAND1_V)<<(I2C_COMMAND1_S)) +#define I2C_COMMAND1_V 0x3FFF +#define I2C_COMMAND1_S 0 + +#define I2C_COMD2_REG(i) (REG_I2C_BASE(i) + 0x0060) +/* I2C_COMMAND2_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command2 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND2_DONE (BIT(31)) +#define I2C_COMMAND2_DONE_M (BIT(31)) +#define I2C_COMMAND2_DONE_V 0x1 +#define I2C_COMMAND2_DONE_S 31 +/* I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command2. It consists of three part. op_code + is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND2 0x00003FFF +#define I2C_COMMAND2_M ((I2C_COMMAND2_V)<<(I2C_COMMAND2_S)) +#define I2C_COMMAND2_V 0x3FFF +#define I2C_COMMAND2_S 0 + +#define I2C_COMD3_REG(i) (REG_I2C_BASE(i) + 0x0064) +/* I2C_COMMAND3_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command3 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND3_DONE (BIT(31)) +#define I2C_COMMAND3_DONE_M (BIT(31)) +#define I2C_COMMAND3_DONE_V 0x1 +#define I2C_COMMAND3_DONE_S 31 +/* I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command3. It consists of three part. op_code + is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND3 0x00003FFF +#define I2C_COMMAND3_M ((I2C_COMMAND3_V)<<(I2C_COMMAND3_S)) +#define I2C_COMMAND3_V 0x3FFF +#define I2C_COMMAND3_S 0 + +#define I2C_COMD4_REG(i) (REG_I2C_BASE(i) + 0x0068) +/* I2C_COMMAND4_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command4 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND4_DONE (BIT(31)) +#define I2C_COMMAND4_DONE_M (BIT(31)) +#define I2C_COMMAND4_DONE_V 0x1 +#define I2C_COMMAND4_DONE_S 31 +/* I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command4. It consists of three part. op_code + is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND4 0x00003FFF +#define I2C_COMMAND4_M ((I2C_COMMAND4_V)<<(I2C_COMMAND4_S)) +#define I2C_COMMAND4_V 0x3FFF +#define I2C_COMMAND4_S 0 + +#define I2C_COMD5_REG(i) (REG_I2C_BASE(i) + 0x006C) +/* I2C_COMMAND5_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command5 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND5_DONE (BIT(31)) +#define I2C_COMMAND5_DONE_M (BIT(31)) +#define I2C_COMMAND5_DONE_V 0x1 +#define I2C_COMMAND5_DONE_S 31 +/* I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command5. It consists of three part. op_code + is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND5 0x00003FFF +#define I2C_COMMAND5_M ((I2C_COMMAND5_V)<<(I2C_COMMAND5_S)) +#define I2C_COMMAND5_V 0x3FFF +#define I2C_COMMAND5_S 0 + +#define I2C_COMD6_REG(i) (REG_I2C_BASE(i) + 0x0070) +/* I2C_COMMAND6_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command6 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND6_DONE (BIT(31)) +#define I2C_COMMAND6_DONE_M (BIT(31)) +#define I2C_COMMAND6_DONE_V 0x1 +#define I2C_COMMAND6_DONE_S 31 +/* I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command6. It consists of three part. op_code + is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND6 0x00003FFF +#define I2C_COMMAND6_M ((I2C_COMMAND6_V)<<(I2C_COMMAND6_S)) +#define I2C_COMMAND6_V 0x3FFF +#define I2C_COMMAND6_S 0 + +#define I2C_COMD7_REG(i) (REG_I2C_BASE(i) + 0x0074) +/* I2C_COMMAND7_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command7 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND7_DONE (BIT(31)) +#define I2C_COMMAND7_DONE_M (BIT(31)) +#define I2C_COMMAND7_DONE_V 0x1 +#define I2C_COMMAND7_DONE_S 31 +/* I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command7. It consists of three part. op_code + is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND7 0x00003FFF +#define I2C_COMMAND7_M ((I2C_COMMAND7_V)<<(I2C_COMMAND7_S)) +#define I2C_COMMAND7_V 0x3FFF +#define I2C_COMMAND7_S 0 + +#define I2C_COMD8_REG(i) (REG_I2C_BASE(i) + 0x0078) +/* I2C_COMMAND8_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command8 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND8_DONE (BIT(31)) +#define I2C_COMMAND8_DONE_M (BIT(31)) +#define I2C_COMMAND8_DONE_V 0x1 +#define I2C_COMMAND8_DONE_S 31 +/* I2C_COMMAND8 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command8. It consists of three part. op_code + is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND8 0x00003FFF +#define I2C_COMMAND8_M ((I2C_COMMAND8_V)<<(I2C_COMMAND8_S)) +#define I2C_COMMAND8_V 0x3FFF +#define I2C_COMMAND8_S 0 + +#define I2C_COMD9_REG(i) (REG_I2C_BASE(i) + 0x007C) +/* I2C_COMMAND9_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command9 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND9_DONE (BIT(31)) +#define I2C_COMMAND9_DONE_M (BIT(31)) +#define I2C_COMMAND9_DONE_V 0x1 +#define I2C_COMMAND9_DONE_S 31 +/* I2C_COMMAND9 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command9. It consists of three part. op_code + is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND9 0x00003FFF +#define I2C_COMMAND9_M ((I2C_COMMAND9_V)<<(I2C_COMMAND9_S)) +#define I2C_COMMAND9_V 0x3FFF +#define I2C_COMMAND9_S 0 + +#define I2C_COMD10_REG(i) (REG_I2C_BASE(i) + 0x0080) +/* I2C_COMMAND10_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command10 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND10_DONE (BIT(31)) +#define I2C_COMMAND10_DONE_M (BIT(31)) +#define I2C_COMMAND10_DONE_V 0x1 +#define I2C_COMMAND10_DONE_S 31 +/* I2C_COMMAND10 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command10. It consists of three part. + op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND10 0x00003FFF +#define I2C_COMMAND10_M ((I2C_COMMAND10_V)<<(I2C_COMMAND10_S)) +#define I2C_COMMAND10_V 0x3FFF +#define I2C_COMMAND10_S 0 + +#define I2C_COMD11_REG(i) (REG_I2C_BASE(i) + 0x0084) +/* I2C_COMMAND11_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command11 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND11_DONE (BIT(31)) +#define I2C_COMMAND11_DONE_M (BIT(31)) +#define I2C_COMMAND11_DONE_V 0x1 +#define I2C_COMMAND11_DONE_S 31 +/* I2C_COMMAND11 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command11. It consists of three part. + op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND11 0x00003FFF +#define I2C_COMMAND11_M ((I2C_COMMAND11_V)<<(I2C_COMMAND11_S)) +#define I2C_COMMAND11_V 0x3FFF +#define I2C_COMMAND11_S 0 + +#define I2C_COMD12_REG(i) (REG_I2C_BASE(i) + 0x0088) +/* I2C_COMMAND12_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command12 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND12_DONE (BIT(31)) +#define I2C_COMMAND12_DONE_M (BIT(31)) +#define I2C_COMMAND12_DONE_V 0x1 +#define I2C_COMMAND12_DONE_S 31 +/* I2C_COMMAND12 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command12. It consists of three part. + op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND12 0x00003FFF +#define I2C_COMMAND12_M ((I2C_COMMAND12_V)<<(I2C_COMMAND12_S)) +#define I2C_COMMAND12_V 0x3FFF +#define I2C_COMMAND12_S 0 + +#define I2C_COMD13_REG(i) (REG_I2C_BASE(i) + 0x008C) +/* I2C_COMMAND13_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command13 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND13_DONE (BIT(31)) +#define I2C_COMMAND13_DONE_M (BIT(31)) +#define I2C_COMMAND13_DONE_V 0x1 +#define I2C_COMMAND13_DONE_S 31 +/* I2C_COMMAND13 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command13. It consists of three part. + op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND13 0x00003FFF +#define I2C_COMMAND13_M ((I2C_COMMAND13_V)<<(I2C_COMMAND13_S)) +#define I2C_COMMAND13_V 0x3FFF +#define I2C_COMMAND13_S 0 + +#define I2C_COMD14_REG(i) (REG_I2C_BASE(i) + 0x0090) +/* I2C_COMMAND14_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command14 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND14_DONE (BIT(31)) +#define I2C_COMMAND14_DONE_M (BIT(31)) +#define I2C_COMMAND14_DONE_V 0x1 +#define I2C_COMMAND14_DONE_S 31 +/* I2C_COMMAND14 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command14. It consists of three part. + op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND14 0x00003FFF +#define I2C_COMMAND14_M ((I2C_COMMAND14_V)<<(I2C_COMMAND14_S)) +#define I2C_COMMAND14_V 0x3FFF +#define I2C_COMMAND14_S 0 + +#define I2C_COMD15_REG(i) (REG_I2C_BASE(i) + 0x0094) +/* I2C_COMMAND15_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When command15 is done in I2C Master mode this bit changes to high level.*/ +#define I2C_COMMAND15_DONE (BIT(31)) +#define I2C_COMMAND15_DONE_M (BIT(31)) +#define I2C_COMMAND15_DONE_V 0x1 +#define I2C_COMMAND15_DONE_S 31 +/* I2C_COMMAND15 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: This is the content of command15. It consists of three part. + op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +#define I2C_COMMAND15 0x00003FFF +#define I2C_COMMAND15_M ((I2C_COMMAND15_V)<<(I2C_COMMAND15_S)) +#define I2C_COMMAND15_V 0x3FFF +#define I2C_COMMAND15_S 0 + +#define I2C_DATE_REG(i) (REG_I2C_BASE(i) + 0x00F8) +/* I2C_DATE : R/W ;bitpos:[31:0] ;default: 32'h16042000 ; */ +/*description: */ +#define I2C_DATE 0xFFFFFFFF +#define I2C_DATE_M ((I2C_DATE_V)<<(I2C_DATE_S)) +#define I2C_DATE_V 0xFFFFFFFF +#define I2C_DATE_S 0 + +#define I2C_FIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x0100) + + + + +#endif /*_SOC_I2C_REG_H_ */ + + diff --git a/components/soc/esp32/include/soc/ledc_reg.h b/components/soc/esp32/include/soc/ledc_reg.h index 1137e3da7..6d6abf8b8 100644 --- a/components/soc/esp32/include/soc/ledc_reg.h +++ b/components/soc/esp32/include/soc/ledc_reg.h @@ -1,2423 +1,2423 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_LEDC_REG_H_ -#define _SOC_LEDC_REG_H_ - - -#include "soc.h" -#define LEDC_HSCH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0000) -/* LEDC_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ -/*description: This bit is clock gating control signal. when software config - LED_PWM internal registers it controls the register clock.*/ -#define LEDC_CLK_EN (BIT(31)) -#define LEDC_CLK_EN_M (BIT(31)) -#define LEDC_CLK_EN_V 0x1 -#define LEDC_CLK_EN_S 31 -/* LEDC_IDLE_LV_HSCH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when high speed channel0 is off.*/ -#define LEDC_IDLE_LV_HSCH0 (BIT(3)) -#define LEDC_IDLE_LV_HSCH0_M (BIT(3)) -#define LEDC_IDLE_LV_HSCH0_V 0x1 -#define LEDC_IDLE_LV_HSCH0_S 3 -/* LEDC_SIG_OUT_EN_HSCH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for high speed channel0*/ -#define LEDC_SIG_OUT_EN_HSCH0 (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH0_M (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH0_V 0x1 -#define LEDC_SIG_OUT_EN_HSCH0_S 2 -/* LEDC_TIMER_SEL_HSCH0 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four high speed timers the two bits are used to select - one of them for high speed channel0. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ -#define LEDC_TIMER_SEL_HSCH0 0x00000003 -#define LEDC_TIMER_SEL_HSCH0_M ((LEDC_TIMER_SEL_HSCH0_V)<<(LEDC_TIMER_SEL_HSCH0_S)) -#define LEDC_TIMER_SEL_HSCH0_V 0x3 -#define LEDC_TIMER_SEL_HSCH0_S 0 - -#define LEDC_HSCH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x0004) -/* LEDC_HPOINT_HSCH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when htimerx(x=[0 3]) selected - by high speed channel0 has reached reg_hpoint_hsch0[19:0]*/ -#define LEDC_HPOINT_HSCH0 0x000FFFFF -#define LEDC_HPOINT_HSCH0_M ((LEDC_HPOINT_HSCH0_V)<<(LEDC_HPOINT_HSCH0_S)) -#define LEDC_HPOINT_HSCH0_V 0xFFFFF -#define LEDC_HPOINT_HSCH0_S 0 - -#define LEDC_HSCH0_DUTY_REG (DR_REG_LEDC_BASE + 0x0008) -/* LEDC_DUTY_HSCH0 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When hstimerx(x=[0 - 3]) choosed by high speed channel0 has reached reg_lpoint_hsch0 the output signal changes to low. reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4]) (1) reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_HSCH0 0x01FFFFFF -#define LEDC_DUTY_HSCH0_M ((LEDC_DUTY_HSCH0_V)<<(LEDC_DUTY_HSCH0_S)) -#define LEDC_DUTY_HSCH0_V 0x1FFFFFF -#define LEDC_DUTY_HSCH0_S 0 - -#define LEDC_HSCH0_CONF1_REG (DR_REG_LEDC_BASE + 0x000C) -/* LEDC_DUTY_START_HSCH0 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch0 reg_duty_cycle_hsch0 and reg_duty_scale_hsch0 - has been configured. these register won't take effect until set reg_duty_start_hsch0. this bit is automatically cleared by hardware.*/ -#define LEDC_DUTY_START_HSCH0 (BIT(31)) -#define LEDC_DUTY_START_HSCH0_M (BIT(31)) -#define LEDC_DUTY_START_HSCH0_V 0x1 -#define LEDC_DUTY_START_HSCH0_S 31 -/* LEDC_DUTY_INC_HSCH0 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for high speed channel0.*/ -#define LEDC_DUTY_INC_HSCH0 (BIT(30)) -#define LEDC_DUTY_INC_HSCH0_M (BIT(30)) -#define LEDC_DUTY_INC_HSCH0_V 0x1 -#define LEDC_DUTY_INC_HSCH0_S 30 -/* LEDC_DUTY_NUM_HSCH0 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for high speed channel0.*/ -#define LEDC_DUTY_NUM_HSCH0 0x000003FF -#define LEDC_DUTY_NUM_HSCH0_M ((LEDC_DUTY_NUM_HSCH0_V)<<(LEDC_DUTY_NUM_HSCH0_S)) -#define LEDC_DUTY_NUM_HSCH0_V 0x3FF -#define LEDC_DUTY_NUM_HSCH0_S 20 -/* LEDC_DUTY_CYCLE_HSCH0 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_hsch0 cycles for high speed channel0.*/ -#define LEDC_DUTY_CYCLE_HSCH0 0x000003FF -#define LEDC_DUTY_CYCLE_HSCH0_M ((LEDC_DUTY_CYCLE_HSCH0_V)<<(LEDC_DUTY_CYCLE_HSCH0_S)) -#define LEDC_DUTY_CYCLE_HSCH0_V 0x3FF -#define LEDC_DUTY_CYCLE_HSCH0_S 10 -/* LEDC_DUTY_SCALE_HSCH0 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - high speed channel0.*/ -#define LEDC_DUTY_SCALE_HSCH0 0x000003FF -#define LEDC_DUTY_SCALE_HSCH0_M ((LEDC_DUTY_SCALE_HSCH0_V)<<(LEDC_DUTY_SCALE_HSCH0_S)) -#define LEDC_DUTY_SCALE_HSCH0_V 0x3FF -#define LEDC_DUTY_SCALE_HSCH0_S 0 - -#define LEDC_HSCH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0010) -/* LEDC_DUTY_HSCH0 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for high speed channel0.*/ -#define LEDC_DUTY_HSCH0 0x01FFFFFF -#define LEDC_DUTY_HSCH0_M ((LEDC_DUTY_HSCH0_V)<<(LEDC_DUTY_HSCH0_S)) -#define LEDC_DUTY_HSCH0_V 0x1FFFFFF -#define LEDC_DUTY_HSCH0_S 0 - -#define LEDC_HSCH1_CONF0_REG (DR_REG_LEDC_BASE + 0x0014) -/* LEDC_IDLE_LV_HSCH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when high speed channel1 is off.*/ -#define LEDC_IDLE_LV_HSCH1 (BIT(3)) -#define LEDC_IDLE_LV_HSCH1_M (BIT(3)) -#define LEDC_IDLE_LV_HSCH1_V 0x1 -#define LEDC_IDLE_LV_HSCH1_S 3 -/* LEDC_SIG_OUT_EN_HSCH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for high speed channel1*/ -#define LEDC_SIG_OUT_EN_HSCH1 (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH1_M (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH1_V 0x1 -#define LEDC_SIG_OUT_EN_HSCH1_S 2 -/* LEDC_TIMER_SEL_HSCH1 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four high speed timers the two bits are used to select - one of them for high speed channel1. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ -#define LEDC_TIMER_SEL_HSCH1 0x00000003 -#define LEDC_TIMER_SEL_HSCH1_M ((LEDC_TIMER_SEL_HSCH1_V)<<(LEDC_TIMER_SEL_HSCH1_S)) -#define LEDC_TIMER_SEL_HSCH1_V 0x3 -#define LEDC_TIMER_SEL_HSCH1_S 0 - -#define LEDC_HSCH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x0018) -/* LEDC_HPOINT_HSCH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when htimerx(x=[0 3]) selected - by high speed channel1 has reached reg_hpoint_hsch1[19:0]*/ -#define LEDC_HPOINT_HSCH1 0x000FFFFF -#define LEDC_HPOINT_HSCH1_M ((LEDC_HPOINT_HSCH1_V)<<(LEDC_HPOINT_HSCH1_S)) -#define LEDC_HPOINT_HSCH1_V 0xFFFFF -#define LEDC_HPOINT_HSCH1_S 0 - -#define LEDC_HSCH1_DUTY_REG (DR_REG_LEDC_BASE + 0x001C) -/* LEDC_DUTY_HSCH1 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When hstimerx(x=[0 - 3]) choosed by high speed channel1 has reached reg_lpoint_hsch1 the output signal changes to low. reg_lpoint_hsch1=(reg_hpoint_hsch1[19:0]+reg_duty_hsch1[24:4]) (1) reg_lpoint_hsch1=(reg_hpoint_hsch1[19:0]+reg_duty_hsch1[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_HSCH1 0x01FFFFFF -#define LEDC_DUTY_HSCH1_M ((LEDC_DUTY_HSCH1_V)<<(LEDC_DUTY_HSCH1_S)) -#define LEDC_DUTY_HSCH1_V 0x1FFFFFF -#define LEDC_DUTY_HSCH1_S 0 - -#define LEDC_HSCH1_CONF1_REG (DR_REG_LEDC_BASE + 0x0020) -/* LEDC_DUTY_START_HSCH1 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 - has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ -#define LEDC_DUTY_START_HSCH1 (BIT(31)) -#define LEDC_DUTY_START_HSCH1_M (BIT(31)) -#define LEDC_DUTY_START_HSCH1_V 0x1 -#define LEDC_DUTY_START_HSCH1_S 31 -/* LEDC_DUTY_INC_HSCH1 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for high speed channel1.*/ -#define LEDC_DUTY_INC_HSCH1 (BIT(30)) -#define LEDC_DUTY_INC_HSCH1_M (BIT(30)) -#define LEDC_DUTY_INC_HSCH1_V 0x1 -#define LEDC_DUTY_INC_HSCH1_S 30 -/* LEDC_DUTY_NUM_HSCH1 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for high speed channel1.*/ -#define LEDC_DUTY_NUM_HSCH1 0x000003FF -#define LEDC_DUTY_NUM_HSCH1_M ((LEDC_DUTY_NUM_HSCH1_V)<<(LEDC_DUTY_NUM_HSCH1_S)) -#define LEDC_DUTY_NUM_HSCH1_V 0x3FF -#define LEDC_DUTY_NUM_HSCH1_S 20 -/* LEDC_DUTY_CYCLE_HSCH1 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_hsch1 cycles for high speed channel1.*/ -#define LEDC_DUTY_CYCLE_HSCH1 0x000003FF -#define LEDC_DUTY_CYCLE_HSCH1_M ((LEDC_DUTY_CYCLE_HSCH1_V)<<(LEDC_DUTY_CYCLE_HSCH1_S)) -#define LEDC_DUTY_CYCLE_HSCH1_V 0x3FF -#define LEDC_DUTY_CYCLE_HSCH1_S 10 -/* LEDC_DUTY_SCALE_HSCH1 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - high speed channel1.*/ -#define LEDC_DUTY_SCALE_HSCH1 0x000003FF -#define LEDC_DUTY_SCALE_HSCH1_M ((LEDC_DUTY_SCALE_HSCH1_V)<<(LEDC_DUTY_SCALE_HSCH1_S)) -#define LEDC_DUTY_SCALE_HSCH1_V 0x3FF -#define LEDC_DUTY_SCALE_HSCH1_S 0 - -#define LEDC_HSCH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0024) -/* LEDC_DUTY_HSCH1 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for high speed channel1.*/ -#define LEDC_DUTY_HSCH1 0x01FFFFFF -#define LEDC_DUTY_HSCH1_M ((LEDC_DUTY_HSCH1_V)<<(LEDC_DUTY_HSCH1_S)) -#define LEDC_DUTY_HSCH1_V 0x1FFFFFF -#define LEDC_DUTY_HSCH1_S 0 - -#define LEDC_HSCH2_CONF0_REG (DR_REG_LEDC_BASE + 0x0028) -/* LEDC_IDLE_LV_HSCH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when high speed channel2 is off.*/ -#define LEDC_IDLE_LV_HSCH2 (BIT(3)) -#define LEDC_IDLE_LV_HSCH2_M (BIT(3)) -#define LEDC_IDLE_LV_HSCH2_V 0x1 -#define LEDC_IDLE_LV_HSCH2_S 3 -/* LEDC_SIG_OUT_EN_HSCH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for high speed channel2*/ -#define LEDC_SIG_OUT_EN_HSCH2 (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH2_M (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH2_V 0x1 -#define LEDC_SIG_OUT_EN_HSCH2_S 2 -/* LEDC_TIMER_SEL_HSCH2 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four high speed timers the two bits are used to select - one of them for high speed channel2. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ -#define LEDC_TIMER_SEL_HSCH2 0x00000003 -#define LEDC_TIMER_SEL_HSCH2_M ((LEDC_TIMER_SEL_HSCH2_V)<<(LEDC_TIMER_SEL_HSCH2_S)) -#define LEDC_TIMER_SEL_HSCH2_V 0x3 -#define LEDC_TIMER_SEL_HSCH2_S 0 - -#define LEDC_HSCH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x002C) -/* LEDC_HPOINT_HSCH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when htimerx(x=[0 3]) selected - by high speed channel2 has reached reg_hpoint_hsch2[19:0]*/ -#define LEDC_HPOINT_HSCH2 0x000FFFFF -#define LEDC_HPOINT_HSCH2_M ((LEDC_HPOINT_HSCH2_V)<<(LEDC_HPOINT_HSCH2_S)) -#define LEDC_HPOINT_HSCH2_V 0xFFFFF -#define LEDC_HPOINT_HSCH2_S 0 - -#define LEDC_HSCH2_DUTY_REG (DR_REG_LEDC_BASE + 0x0030) -/* LEDC_DUTY_HSCH2 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When hstimerx(x=[0 - 3]) choosed by high speed channel2 has reached reg_lpoint_hsch2 the output signal changes to low. reg_lpoint_hsch2=(reg_hpoint_hsch2[19:0]+reg_duty_hsch2[24:4]) (1) reg_lpoint_hsch2=(reg_hpoint_hsch2[19:0]+reg_duty_hsch2[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_HSCH2 0x01FFFFFF -#define LEDC_DUTY_HSCH2_M ((LEDC_DUTY_HSCH2_V)<<(LEDC_DUTY_HSCH2_S)) -#define LEDC_DUTY_HSCH2_V 0x1FFFFFF -#define LEDC_DUTY_HSCH2_S 0 - -#define LEDC_HSCH2_CONF1_REG (DR_REG_LEDC_BASE + 0x0034) -/* LEDC_DUTY_START_HSCH2 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch2 reg_duty_cycle_hsch2 and reg_duty_scale_hsch2 - has been configured. these register won't take effect until set reg_duty_start_hsch2. this bit is automatically cleared by hardware.*/ -#define LEDC_DUTY_START_HSCH2 (BIT(31)) -#define LEDC_DUTY_START_HSCH2_M (BIT(31)) -#define LEDC_DUTY_START_HSCH2_V 0x1 -#define LEDC_DUTY_START_HSCH2_S 31 -/* LEDC_DUTY_INC_HSCH2 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for high speed channel2.*/ -#define LEDC_DUTY_INC_HSCH2 (BIT(30)) -#define LEDC_DUTY_INC_HSCH2_M (BIT(30)) -#define LEDC_DUTY_INC_HSCH2_V 0x1 -#define LEDC_DUTY_INC_HSCH2_S 30 -/* LEDC_DUTY_NUM_HSCH2 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for high speed channel2.*/ -#define LEDC_DUTY_NUM_HSCH2 0x000003FF -#define LEDC_DUTY_NUM_HSCH2_M ((LEDC_DUTY_NUM_HSCH2_V)<<(LEDC_DUTY_NUM_HSCH2_S)) -#define LEDC_DUTY_NUM_HSCH2_V 0x3FF -#define LEDC_DUTY_NUM_HSCH2_S 20 -/* LEDC_DUTY_CYCLE_HSCH2 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_hsch2 cycles for high speed channel2.*/ -#define LEDC_DUTY_CYCLE_HSCH2 0x000003FF -#define LEDC_DUTY_CYCLE_HSCH2_M ((LEDC_DUTY_CYCLE_HSCH2_V)<<(LEDC_DUTY_CYCLE_HSCH2_S)) -#define LEDC_DUTY_CYCLE_HSCH2_V 0x3FF -#define LEDC_DUTY_CYCLE_HSCH2_S 10 -/* LEDC_DUTY_SCALE_HSCH2 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - high speed channel2.*/ -#define LEDC_DUTY_SCALE_HSCH2 0x000003FF -#define LEDC_DUTY_SCALE_HSCH2_M ((LEDC_DUTY_SCALE_HSCH2_V)<<(LEDC_DUTY_SCALE_HSCH2_S)) -#define LEDC_DUTY_SCALE_HSCH2_V 0x3FF -#define LEDC_DUTY_SCALE_HSCH2_S 0 - -#define LEDC_HSCH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0038) -/* LEDC_DUTY_HSCH2 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for high speed channel2.*/ -#define LEDC_DUTY_HSCH2 0x01FFFFFF -#define LEDC_DUTY_HSCH2_M ((LEDC_DUTY_HSCH2_V)<<(LEDC_DUTY_HSCH2_S)) -#define LEDC_DUTY_HSCH2_V 0x1FFFFFF -#define LEDC_DUTY_HSCH2_S 0 - -#define LEDC_HSCH3_CONF0_REG (DR_REG_LEDC_BASE + 0x003C) -/* LEDC_IDLE_LV_HSCH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when high speed channel3 is off.*/ -#define LEDC_IDLE_LV_HSCH3 (BIT(3)) -#define LEDC_IDLE_LV_HSCH3_M (BIT(3)) -#define LEDC_IDLE_LV_HSCH3_V 0x1 -#define LEDC_IDLE_LV_HSCH3_S 3 -/* LEDC_SIG_OUT_EN_HSCH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for high speed channel3*/ -#define LEDC_SIG_OUT_EN_HSCH3 (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH3_M (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH3_V 0x1 -#define LEDC_SIG_OUT_EN_HSCH3_S 2 -/* LEDC_TIMER_SEL_HSCH3 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four high speed timers the two bits are used to select - one of them for high speed channel3. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ -#define LEDC_TIMER_SEL_HSCH3 0x00000003 -#define LEDC_TIMER_SEL_HSCH3_M ((LEDC_TIMER_SEL_HSCH3_V)<<(LEDC_TIMER_SEL_HSCH3_S)) -#define LEDC_TIMER_SEL_HSCH3_V 0x3 -#define LEDC_TIMER_SEL_HSCH3_S 0 - -#define LEDC_HSCH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x0040) -/* LEDC_HPOINT_HSCH3 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when htimerx(x=[0 3]) selected - by high speed channel3 has reached reg_hpoint_hsch3[19:0]*/ -#define LEDC_HPOINT_HSCH3 0x000FFFFF -#define LEDC_HPOINT_HSCH3_M ((LEDC_HPOINT_HSCH3_V)<<(LEDC_HPOINT_HSCH3_S)) -#define LEDC_HPOINT_HSCH3_V 0xFFFFF -#define LEDC_HPOINT_HSCH3_S 0 - -#define LEDC_HSCH3_DUTY_REG (DR_REG_LEDC_BASE + 0x0044) -/* LEDC_DUTY_HSCH3 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When hstimerx(x=[0 - 3]) choosed by high speed channel3 has reached reg_lpoint_hsch3 the output signal changes to low. reg_lpoint_hsch3=(reg_hpoint_hsch3[19:0]+reg_duty_hsch3[24:4]) (1) reg_lpoint_hsch3=(reg_hpoint_hsch3[19:0]+reg_duty_hsch3[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_HSCH3 0x01FFFFFF -#define LEDC_DUTY_HSCH3_M ((LEDC_DUTY_HSCH3_V)<<(LEDC_DUTY_HSCH3_S)) -#define LEDC_DUTY_HSCH3_V 0x1FFFFFF -#define LEDC_DUTY_HSCH3_S 0 - -#define LEDC_HSCH3_CONF1_REG (DR_REG_LEDC_BASE + 0x0048) -/* LEDC_DUTY_START_HSCH3 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch3 reg_duty_cycle_hsch3 and reg_duty_scale_hsch3 - has been configured. these register won't take effect until set reg_duty_start_hsch3. this bit is automatically cleared by hardware.*/ -#define LEDC_DUTY_START_HSCH3 (BIT(31)) -#define LEDC_DUTY_START_HSCH3_M (BIT(31)) -#define LEDC_DUTY_START_HSCH3_V 0x1 -#define LEDC_DUTY_START_HSCH3_S 31 -/* LEDC_DUTY_INC_HSCH3 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for high speed channel3.*/ -#define LEDC_DUTY_INC_HSCH3 (BIT(30)) -#define LEDC_DUTY_INC_HSCH3_M (BIT(30)) -#define LEDC_DUTY_INC_HSCH3_V 0x1 -#define LEDC_DUTY_INC_HSCH3_S 30 -/* LEDC_DUTY_NUM_HSCH3 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for high speed channel3.*/ -#define LEDC_DUTY_NUM_HSCH3 0x000003FF -#define LEDC_DUTY_NUM_HSCH3_M ((LEDC_DUTY_NUM_HSCH3_V)<<(LEDC_DUTY_NUM_HSCH3_S)) -#define LEDC_DUTY_NUM_HSCH3_V 0x3FF -#define LEDC_DUTY_NUM_HSCH3_S 20 -/* LEDC_DUTY_CYCLE_HSCH3 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_hsch3 cycles for high speed channel3.*/ -#define LEDC_DUTY_CYCLE_HSCH3 0x000003FF -#define LEDC_DUTY_CYCLE_HSCH3_M ((LEDC_DUTY_CYCLE_HSCH3_V)<<(LEDC_DUTY_CYCLE_HSCH3_S)) -#define LEDC_DUTY_CYCLE_HSCH3_V 0x3FF -#define LEDC_DUTY_CYCLE_HSCH3_S 10 -/* LEDC_DUTY_SCALE_HSCH3 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - high speed channel3.*/ -#define LEDC_DUTY_SCALE_HSCH3 0x000003FF -#define LEDC_DUTY_SCALE_HSCH3_M ((LEDC_DUTY_SCALE_HSCH3_V)<<(LEDC_DUTY_SCALE_HSCH3_S)) -#define LEDC_DUTY_SCALE_HSCH3_V 0x3FF -#define LEDC_DUTY_SCALE_HSCH3_S 0 - -#define LEDC_HSCH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x004C) -/* LEDC_DUTY_HSCH3 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for high speed channel3.*/ -#define LEDC_DUTY_HSCH3 0x01FFFFFF -#define LEDC_DUTY_HSCH3_M ((LEDC_DUTY_HSCH3_V)<<(LEDC_DUTY_HSCH3_S)) -#define LEDC_DUTY_HSCH3_V 0x1FFFFFF -#define LEDC_DUTY_HSCH3_S 0 - -#define LEDC_HSCH4_CONF0_REG (DR_REG_LEDC_BASE + 0x0050) -/* LEDC_IDLE_LV_HSCH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when high speed channel4 is off.*/ -#define LEDC_IDLE_LV_HSCH4 (BIT(3)) -#define LEDC_IDLE_LV_HSCH4_M (BIT(3)) -#define LEDC_IDLE_LV_HSCH4_V 0x1 -#define LEDC_IDLE_LV_HSCH4_S 3 -/* LEDC_SIG_OUT_EN_HSCH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for high speed channel4*/ -#define LEDC_SIG_OUT_EN_HSCH4 (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH4_M (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH4_V 0x1 -#define LEDC_SIG_OUT_EN_HSCH4_S 2 -/* LEDC_TIMER_SEL_HSCH4 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four high speed timers the two bits are used to select - one of them for high speed channel4. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ -#define LEDC_TIMER_SEL_HSCH4 0x00000003 -#define LEDC_TIMER_SEL_HSCH4_M ((LEDC_TIMER_SEL_HSCH4_V)<<(LEDC_TIMER_SEL_HSCH4_S)) -#define LEDC_TIMER_SEL_HSCH4_V 0x3 -#define LEDC_TIMER_SEL_HSCH4_S 0 - -#define LEDC_HSCH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x0054) -/* LEDC_HPOINT_HSCH4 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when htimerx(x=[0 3]) selected - by high speed channel4 has reached reg_hpoint_hsch4[19:0]*/ -#define LEDC_HPOINT_HSCH4 0x000FFFFF -#define LEDC_HPOINT_HSCH4_M ((LEDC_HPOINT_HSCH4_V)<<(LEDC_HPOINT_HSCH4_S)) -#define LEDC_HPOINT_HSCH4_V 0xFFFFF -#define LEDC_HPOINT_HSCH4_S 0 - -#define LEDC_HSCH4_DUTY_REG (DR_REG_LEDC_BASE + 0x0058) -/* LEDC_DUTY_HSCH4 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When hstimerx(x=[0 - 3]) choosed by high speed channel4 has reached reg_lpoint_hsch4 the output signal changes to low. reg_lpoint_hsch4=(reg_hpoint_hsch4[19:0]+reg_duty_hsch4[24:4]) (1) reg_lpoint_hsch4=(reg_hpoint_hsch4[19:0]+reg_duty_hsch4[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_HSCH4 0x01FFFFFF -#define LEDC_DUTY_HSCH4_M ((LEDC_DUTY_HSCH4_V)<<(LEDC_DUTY_HSCH4_S)) -#define LEDC_DUTY_HSCH4_V 0x1FFFFFF -#define LEDC_DUTY_HSCH4_S 0 - -#define LEDC_HSCH4_CONF1_REG (DR_REG_LEDC_BASE + 0x005C) -/* LEDC_DUTY_START_HSCH4 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 - has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ -#define LEDC_DUTY_START_HSCH4 (BIT(31)) -#define LEDC_DUTY_START_HSCH4_M (BIT(31)) -#define LEDC_DUTY_START_HSCH4_V 0x1 -#define LEDC_DUTY_START_HSCH4_S 31 -/* LEDC_DUTY_INC_HSCH4 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for high speed channel4.*/ -#define LEDC_DUTY_INC_HSCH4 (BIT(30)) -#define LEDC_DUTY_INC_HSCH4_M (BIT(30)) -#define LEDC_DUTY_INC_HSCH4_V 0x1 -#define LEDC_DUTY_INC_HSCH4_S 30 -/* LEDC_DUTY_NUM_HSCH4 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for high speed channel1.*/ -#define LEDC_DUTY_NUM_HSCH4 0x000003FF -#define LEDC_DUTY_NUM_HSCH4_M ((LEDC_DUTY_NUM_HSCH4_V)<<(LEDC_DUTY_NUM_HSCH4_S)) -#define LEDC_DUTY_NUM_HSCH4_V 0x3FF -#define LEDC_DUTY_NUM_HSCH4_S 20 -/* LEDC_DUTY_CYCLE_HSCH4 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_hsch4 cycles for high speed channel4.*/ -#define LEDC_DUTY_CYCLE_HSCH4 0x000003FF -#define LEDC_DUTY_CYCLE_HSCH4_M ((LEDC_DUTY_CYCLE_HSCH4_V)<<(LEDC_DUTY_CYCLE_HSCH4_S)) -#define LEDC_DUTY_CYCLE_HSCH4_V 0x3FF -#define LEDC_DUTY_CYCLE_HSCH4_S 10 -/* LEDC_DUTY_SCALE_HSCH4 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - high speed channel4.*/ -#define LEDC_DUTY_SCALE_HSCH4 0x000003FF -#define LEDC_DUTY_SCALE_HSCH4_M ((LEDC_DUTY_SCALE_HSCH4_V)<<(LEDC_DUTY_SCALE_HSCH4_S)) -#define LEDC_DUTY_SCALE_HSCH4_V 0x3FF -#define LEDC_DUTY_SCALE_HSCH4_S 0 - -#define LEDC_HSCH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0060) -/* LEDC_DUTY_HSCH4 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for high speed channel4.*/ -#define LEDC_DUTY_HSCH4 0x01FFFFFF -#define LEDC_DUTY_HSCH4_M ((LEDC_DUTY_HSCH4_V)<<(LEDC_DUTY_HSCH4_S)) -#define LEDC_DUTY_HSCH4_V 0x1FFFFFF -#define LEDC_DUTY_HSCH4_S 0 - -#define LEDC_HSCH5_CONF0_REG (DR_REG_LEDC_BASE + 0x0064) -/* LEDC_IDLE_LV_HSCH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when high speed channel5 is off.*/ -#define LEDC_IDLE_LV_HSCH5 (BIT(3)) -#define LEDC_IDLE_LV_HSCH5_M (BIT(3)) -#define LEDC_IDLE_LV_HSCH5_V 0x1 -#define LEDC_IDLE_LV_HSCH5_S 3 -/* LEDC_SIG_OUT_EN_HSCH5 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for high speed channel5.*/ -#define LEDC_SIG_OUT_EN_HSCH5 (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH5_M (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH5_V 0x1 -#define LEDC_SIG_OUT_EN_HSCH5_S 2 -/* LEDC_TIMER_SEL_HSCH5 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four high speed timers the two bits are used to select - one of them for high speed channel5. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ -#define LEDC_TIMER_SEL_HSCH5 0x00000003 -#define LEDC_TIMER_SEL_HSCH5_M ((LEDC_TIMER_SEL_HSCH5_V)<<(LEDC_TIMER_SEL_HSCH5_S)) -#define LEDC_TIMER_SEL_HSCH5_V 0x3 -#define LEDC_TIMER_SEL_HSCH5_S 0 - -#define LEDC_HSCH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x0068) -/* LEDC_HPOINT_HSCH5 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when htimerx(x=[0 3]) selected - by high speed channel5 has reached reg_hpoint_hsch5[19:0]*/ -#define LEDC_HPOINT_HSCH5 0x000FFFFF -#define LEDC_HPOINT_HSCH5_M ((LEDC_HPOINT_HSCH5_V)<<(LEDC_HPOINT_HSCH5_S)) -#define LEDC_HPOINT_HSCH5_V 0xFFFFF -#define LEDC_HPOINT_HSCH5_S 0 - -#define LEDC_HSCH5_DUTY_REG (DR_REG_LEDC_BASE + 0x006C) -/* LEDC_DUTY_HSCH5 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When hstimerx(x=[0 - 3]) choosed by high speed channel5 has reached reg_lpoint_hsch5 the output signal changes to low. reg_lpoint_hsch5=(reg_hpoint_hsch5[19:0]+reg_duty_hsch5[24:4]) (1) reg_lpoint_hsch5=(reg_hpoint_hsch5[19:0]+reg_duty_hsch5[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_HSCH5 0x01FFFFFF -#define LEDC_DUTY_HSCH5_M ((LEDC_DUTY_HSCH5_V)<<(LEDC_DUTY_HSCH5_S)) -#define LEDC_DUTY_HSCH5_V 0x1FFFFFF -#define LEDC_DUTY_HSCH5_S 0 - -#define LEDC_HSCH5_CONF1_REG (DR_REG_LEDC_BASE + 0x0070) -/* LEDC_DUTY_START_HSCH5 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch5 reg_duty_cycle_hsch5 and reg_duty_scale_hsch5 - has been configured. these register won't take effect until set reg_duty_start_hsch5. this bit is automatically cleared by hardware.*/ -#define LEDC_DUTY_START_HSCH5 (BIT(31)) -#define LEDC_DUTY_START_HSCH5_M (BIT(31)) -#define LEDC_DUTY_START_HSCH5_V 0x1 -#define LEDC_DUTY_START_HSCH5_S 31 -/* LEDC_DUTY_INC_HSCH5 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for high speed channel5.*/ -#define LEDC_DUTY_INC_HSCH5 (BIT(30)) -#define LEDC_DUTY_INC_HSCH5_M (BIT(30)) -#define LEDC_DUTY_INC_HSCH5_V 0x1 -#define LEDC_DUTY_INC_HSCH5_S 30 -/* LEDC_DUTY_NUM_HSCH5 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for high speed channel5.*/ -#define LEDC_DUTY_NUM_HSCH5 0x000003FF -#define LEDC_DUTY_NUM_HSCH5_M ((LEDC_DUTY_NUM_HSCH5_V)<<(LEDC_DUTY_NUM_HSCH5_S)) -#define LEDC_DUTY_NUM_HSCH5_V 0x3FF -#define LEDC_DUTY_NUM_HSCH5_S 20 -/* LEDC_DUTY_CYCLE_HSCH5 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_hsch5 cycles for high speed channel5.*/ -#define LEDC_DUTY_CYCLE_HSCH5 0x000003FF -#define LEDC_DUTY_CYCLE_HSCH5_M ((LEDC_DUTY_CYCLE_HSCH5_V)<<(LEDC_DUTY_CYCLE_HSCH5_S)) -#define LEDC_DUTY_CYCLE_HSCH5_V 0x3FF -#define LEDC_DUTY_CYCLE_HSCH5_S 10 -/* LEDC_DUTY_SCALE_HSCH5 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - high speed channel5.*/ -#define LEDC_DUTY_SCALE_HSCH5 0x000003FF -#define LEDC_DUTY_SCALE_HSCH5_M ((LEDC_DUTY_SCALE_HSCH5_V)<<(LEDC_DUTY_SCALE_HSCH5_S)) -#define LEDC_DUTY_SCALE_HSCH5_V 0x3FF -#define LEDC_DUTY_SCALE_HSCH5_S 0 - -#define LEDC_HSCH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0074) -/* LEDC_DUTY_HSCH5 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for high speed channel5.*/ -#define LEDC_DUTY_HSCH5 0x01FFFFFF -#define LEDC_DUTY_HSCH5_M ((LEDC_DUTY_HSCH5_V)<<(LEDC_DUTY_HSCH5_S)) -#define LEDC_DUTY_HSCH5_V 0x1FFFFFF -#define LEDC_DUTY_HSCH5_S 0 - -#define LEDC_HSCH6_CONF0_REG (DR_REG_LEDC_BASE + 0x0078) -/* LEDC_IDLE_LV_HSCH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when high speed channel6 is off.*/ -#define LEDC_IDLE_LV_HSCH6 (BIT(3)) -#define LEDC_IDLE_LV_HSCH6_M (BIT(3)) -#define LEDC_IDLE_LV_HSCH6_V 0x1 -#define LEDC_IDLE_LV_HSCH6_S 3 -/* LEDC_SIG_OUT_EN_HSCH6 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for high speed channel6*/ -#define LEDC_SIG_OUT_EN_HSCH6 (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH6_M (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH6_V 0x1 -#define LEDC_SIG_OUT_EN_HSCH6_S 2 -/* LEDC_TIMER_SEL_HSCH6 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four high speed timers the two bits are used to select - one of them for high speed channel6. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ -#define LEDC_TIMER_SEL_HSCH6 0x00000003 -#define LEDC_TIMER_SEL_HSCH6_M ((LEDC_TIMER_SEL_HSCH6_V)<<(LEDC_TIMER_SEL_HSCH6_S)) -#define LEDC_TIMER_SEL_HSCH6_V 0x3 -#define LEDC_TIMER_SEL_HSCH6_S 0 - -#define LEDC_HSCH6_HPOINT_REG (DR_REG_LEDC_BASE + 0x007C) -/* LEDC_HPOINT_HSCH6 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when htimerx(x=[0 3]) selected - by high speed channel6 has reached reg_hpoint_hsch6[19:0]*/ -#define LEDC_HPOINT_HSCH6 0x000FFFFF -#define LEDC_HPOINT_HSCH6_M ((LEDC_HPOINT_HSCH6_V)<<(LEDC_HPOINT_HSCH6_S)) -#define LEDC_HPOINT_HSCH6_V 0xFFFFF -#define LEDC_HPOINT_HSCH6_S 0 - -#define LEDC_HSCH6_DUTY_REG (DR_REG_LEDC_BASE + 0x0080) -/* LEDC_DUTY_HSCH6 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When hstimerx(x=[0 - 3]) choosed by high speed channel6 has reached reg_lpoint_hsch6 the output signal changes to low. reg_lpoint_hsch6=(reg_hpoint_hsch6[19:0]+reg_duty_hsch6[24:4]) (1) reg_lpoint_hsch6=(reg_hpoint_hsch6[19:0]+reg_duty_hsch6[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_HSCH6 0x01FFFFFF -#define LEDC_DUTY_HSCH6_M ((LEDC_DUTY_HSCH6_V)<<(LEDC_DUTY_HSCH6_S)) -#define LEDC_DUTY_HSCH6_V 0x1FFFFFF -#define LEDC_DUTY_HSCH6_S 0 - -#define LEDC_HSCH6_CONF1_REG (DR_REG_LEDC_BASE + 0x0084) -/* LEDC_DUTY_START_HSCH6 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 - has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ -#define LEDC_DUTY_START_HSCH6 (BIT(31)) -#define LEDC_DUTY_START_HSCH6_M (BIT(31)) -#define LEDC_DUTY_START_HSCH6_V 0x1 -#define LEDC_DUTY_START_HSCH6_S 31 -/* LEDC_DUTY_INC_HSCH6 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for high speed channel6.*/ -#define LEDC_DUTY_INC_HSCH6 (BIT(30)) -#define LEDC_DUTY_INC_HSCH6_M (BIT(30)) -#define LEDC_DUTY_INC_HSCH6_V 0x1 -#define LEDC_DUTY_INC_HSCH6_S 30 -/* LEDC_DUTY_NUM_HSCH6 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for high speed channel6.*/ -#define LEDC_DUTY_NUM_HSCH6 0x000003FF -#define LEDC_DUTY_NUM_HSCH6_M ((LEDC_DUTY_NUM_HSCH6_V)<<(LEDC_DUTY_NUM_HSCH6_S)) -#define LEDC_DUTY_NUM_HSCH6_V 0x3FF -#define LEDC_DUTY_NUM_HSCH6_S 20 -/* LEDC_DUTY_CYCLE_HSCH6 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_hsch6 cycles for high speed channel6.*/ -#define LEDC_DUTY_CYCLE_HSCH6 0x000003FF -#define LEDC_DUTY_CYCLE_HSCH6_M ((LEDC_DUTY_CYCLE_HSCH6_V)<<(LEDC_DUTY_CYCLE_HSCH6_S)) -#define LEDC_DUTY_CYCLE_HSCH6_V 0x3FF -#define LEDC_DUTY_CYCLE_HSCH6_S 10 -/* LEDC_DUTY_SCALE_HSCH6 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - high speed channel6.*/ -#define LEDC_DUTY_SCALE_HSCH6 0x000003FF -#define LEDC_DUTY_SCALE_HSCH6_M ((LEDC_DUTY_SCALE_HSCH6_V)<<(LEDC_DUTY_SCALE_HSCH6_S)) -#define LEDC_DUTY_SCALE_HSCH6_V 0x3FF -#define LEDC_DUTY_SCALE_HSCH6_S 0 - -#define LEDC_HSCH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0088) -/* LEDC_DUTY_HSCH6 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for high speed channel6.*/ -#define LEDC_DUTY_HSCH6 0x01FFFFFF -#define LEDC_DUTY_HSCH6_M ((LEDC_DUTY_HSCH6_V)<<(LEDC_DUTY_HSCH6_S)) -#define LEDC_DUTY_HSCH6_V 0x1FFFFFF -#define LEDC_DUTY_HSCH6_S 0 - -#define LEDC_HSCH7_CONF0_REG (DR_REG_LEDC_BASE + 0x008C) -/* LEDC_IDLE_LV_HSCH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when high speed channel7 is off.*/ -#define LEDC_IDLE_LV_HSCH7 (BIT(3)) -#define LEDC_IDLE_LV_HSCH7_M (BIT(3)) -#define LEDC_IDLE_LV_HSCH7_V 0x1 -#define LEDC_IDLE_LV_HSCH7_S 3 -/* LEDC_SIG_OUT_EN_HSCH7 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for high speed channel7.*/ -#define LEDC_SIG_OUT_EN_HSCH7 (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH7_M (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH7_V 0x1 -#define LEDC_SIG_OUT_EN_HSCH7_S 2 -/* LEDC_TIMER_SEL_HSCH7 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four high speed timers the two bits are used to select - one of them for high speed channel7. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ -#define LEDC_TIMER_SEL_HSCH7 0x00000003 -#define LEDC_TIMER_SEL_HSCH7_M ((LEDC_TIMER_SEL_HSCH7_V)<<(LEDC_TIMER_SEL_HSCH7_S)) -#define LEDC_TIMER_SEL_HSCH7_V 0x3 -#define LEDC_TIMER_SEL_HSCH7_S 0 - -#define LEDC_HSCH7_HPOINT_REG (DR_REG_LEDC_BASE + 0x0090) -/* LEDC_HPOINT_HSCH7 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when htimerx(x=[0 3]) selected - by high speed channel7 has reached reg_hpoint_hsch7[19:0]*/ -#define LEDC_HPOINT_HSCH7 0x000FFFFF -#define LEDC_HPOINT_HSCH7_M ((LEDC_HPOINT_HSCH7_V)<<(LEDC_HPOINT_HSCH7_S)) -#define LEDC_HPOINT_HSCH7_V 0xFFFFF -#define LEDC_HPOINT_HSCH7_S 0 - -#define LEDC_HSCH7_DUTY_REG (DR_REG_LEDC_BASE + 0x0094) -/* LEDC_DUTY_HSCH7 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When hstimerx(x=[0 - 3]) choosed by high speed channel7 has reached reg_lpoint_hsch7 the output signal changes to low. reg_lpoint_hsch7=(reg_hpoint_hsch7[19:0]+reg_duty_hsch7[24:4]) (1) reg_lpoint_hsch7=(reg_hpoint_hsch7[19:0]+reg_duty_hsch7[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_HSCH7 0x01FFFFFF -#define LEDC_DUTY_HSCH7_M ((LEDC_DUTY_HSCH7_V)<<(LEDC_DUTY_HSCH7_S)) -#define LEDC_DUTY_HSCH7_V 0x1FFFFFF -#define LEDC_DUTY_HSCH7_S 0 - -#define LEDC_HSCH7_CONF1_REG (DR_REG_LEDC_BASE + 0x0098) -/* LEDC_DUTY_START_HSCH7 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 - has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ -#define LEDC_DUTY_START_HSCH7 (BIT(31)) -#define LEDC_DUTY_START_HSCH7_M (BIT(31)) -#define LEDC_DUTY_START_HSCH7_V 0x1 -#define LEDC_DUTY_START_HSCH7_S 31 -/* LEDC_DUTY_INC_HSCH7 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for high speed channel6.*/ -#define LEDC_DUTY_INC_HSCH7 (BIT(30)) -#define LEDC_DUTY_INC_HSCH7_M (BIT(30)) -#define LEDC_DUTY_INC_HSCH7_V 0x1 -#define LEDC_DUTY_INC_HSCH7_S 30 -/* LEDC_DUTY_NUM_HSCH7 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for high speed channel6.*/ -#define LEDC_DUTY_NUM_HSCH7 0x000003FF -#define LEDC_DUTY_NUM_HSCH7_M ((LEDC_DUTY_NUM_HSCH7_V)<<(LEDC_DUTY_NUM_HSCH7_S)) -#define LEDC_DUTY_NUM_HSCH7_V 0x3FF -#define LEDC_DUTY_NUM_HSCH7_S 20 -/* LEDC_DUTY_CYCLE_HSCH7 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_hsch7 cycles for high speed channel7.*/ -#define LEDC_DUTY_CYCLE_HSCH7 0x000003FF -#define LEDC_DUTY_CYCLE_HSCH7_M ((LEDC_DUTY_CYCLE_HSCH7_V)<<(LEDC_DUTY_CYCLE_HSCH7_S)) -#define LEDC_DUTY_CYCLE_HSCH7_V 0x3FF -#define LEDC_DUTY_CYCLE_HSCH7_S 10 -/* LEDC_DUTY_SCALE_HSCH7 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - high speed channel7.*/ -#define LEDC_DUTY_SCALE_HSCH7 0x000003FF -#define LEDC_DUTY_SCALE_HSCH7_M ((LEDC_DUTY_SCALE_HSCH7_V)<<(LEDC_DUTY_SCALE_HSCH7_S)) -#define LEDC_DUTY_SCALE_HSCH7_V 0x3FF -#define LEDC_DUTY_SCALE_HSCH7_S 0 - -#define LEDC_HSCH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x009C) -/* LEDC_DUTY_HSCH7 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for high speed channel7.*/ -#define LEDC_DUTY_HSCH7 0x01FFFFFF -#define LEDC_DUTY_HSCH7_M ((LEDC_DUTY_HSCH7_V)<<(LEDC_DUTY_HSCH7_S)) -#define LEDC_DUTY_HSCH7_V 0x1FFFFFF -#define LEDC_DUTY_HSCH7_S 0 - -#define LEDC_LSCH0_CONF0_REG (DR_REG_LEDC_BASE + 0x00A0) -/* LEDC_PARA_UP_LSCH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This bit is used to update register LEDC_LSCH0_HPOINT and LEDC_LSCH0_DUTY - for low speed channel0.*/ -#define LEDC_PARA_UP_LSCH0 (BIT(4)) -#define LEDC_PARA_UP_LSCH0_M (BIT(4)) -#define LEDC_PARA_UP_LSCH0_V 0x1 -#define LEDC_PARA_UP_LSCH0_S 4 -/* LEDC_IDLE_LV_LSCH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when low speed channel0 is off.*/ -#define LEDC_IDLE_LV_LSCH0 (BIT(3)) -#define LEDC_IDLE_LV_LSCH0_M (BIT(3)) -#define LEDC_IDLE_LV_LSCH0_V 0x1 -#define LEDC_IDLE_LV_LSCH0_S 3 -/* LEDC_SIG_OUT_EN_LSCH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for low speed channel0.*/ -#define LEDC_SIG_OUT_EN_LSCH0 (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH0_M (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH0_V 0x1 -#define LEDC_SIG_OUT_EN_LSCH0_S 2 -/* LEDC_TIMER_SEL_LSCH0 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four low speed timers the two bits are used to select - one of them for low speed channel0. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ -#define LEDC_TIMER_SEL_LSCH0 0x00000003 -#define LEDC_TIMER_SEL_LSCH0_M ((LEDC_TIMER_SEL_LSCH0_V)<<(LEDC_TIMER_SEL_LSCH0_S)) -#define LEDC_TIMER_SEL_LSCH0_V 0x3 -#define LEDC_TIMER_SEL_LSCH0_S 0 - -#define LEDC_LSCH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x00A4) -/* LEDC_HPOINT_LSCH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when lstimerx(x=[0 3]) selected - by low speed channel0 has reached reg_hpoint_lsch0[19:0]*/ -#define LEDC_HPOINT_LSCH0 0x000FFFFF -#define LEDC_HPOINT_LSCH0_M ((LEDC_HPOINT_LSCH0_V)<<(LEDC_HPOINT_LSCH0_S)) -#define LEDC_HPOINT_LSCH0_V 0xFFFFF -#define LEDC_HPOINT_LSCH0_S 0 - -#define LEDC_LSCH0_DUTY_REG (DR_REG_LEDC_BASE + 0x00A8) -/* LEDC_DUTY_LSCH0 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When lstimerx(x=[0 - 3]) choosed by low speed channel0 has reached reg_lpoint_lsch0 the output signal changes to low. reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4]) (1) reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_LSCH0 0x01FFFFFF -#define LEDC_DUTY_LSCH0_M ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S)) -#define LEDC_DUTY_LSCH0_V 0x1FFFFFF -#define LEDC_DUTY_LSCH0_S 0 - -#define LEDC_LSCH0_CONF1_REG (DR_REG_LEDC_BASE + 0x00AC) -/* LEDC_DUTY_START_LSCH0 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 - has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ -#define LEDC_DUTY_START_LSCH0 (BIT(31)) -#define LEDC_DUTY_START_LSCH0_M (BIT(31)) -#define LEDC_DUTY_START_LSCH0_V 0x1 -#define LEDC_DUTY_START_LSCH0_S 31 -/* LEDC_DUTY_INC_LSCH0 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for low speed channel6.*/ -#define LEDC_DUTY_INC_LSCH0 (BIT(30)) -#define LEDC_DUTY_INC_LSCH0_M (BIT(30)) -#define LEDC_DUTY_INC_LSCH0_V 0x1 -#define LEDC_DUTY_INC_LSCH0_S 30 -/* LEDC_DUTY_NUM_LSCH0 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for low speed channel6.*/ -#define LEDC_DUTY_NUM_LSCH0 0x000003FF -#define LEDC_DUTY_NUM_LSCH0_M ((LEDC_DUTY_NUM_LSCH0_V)<<(LEDC_DUTY_NUM_LSCH0_S)) -#define LEDC_DUTY_NUM_LSCH0_V 0x3FF -#define LEDC_DUTY_NUM_LSCH0_S 20 -/* LEDC_DUTY_CYCLE_LSCH0 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_lsch0 cycles for low speed channel0.*/ -#define LEDC_DUTY_CYCLE_LSCH0 0x000003FF -#define LEDC_DUTY_CYCLE_LSCH0_M ((LEDC_DUTY_CYCLE_LSCH0_V)<<(LEDC_DUTY_CYCLE_LSCH0_S)) -#define LEDC_DUTY_CYCLE_LSCH0_V 0x3FF -#define LEDC_DUTY_CYCLE_LSCH0_S 10 -/* LEDC_DUTY_SCALE_LSCH0 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - low speed channel0.*/ -#define LEDC_DUTY_SCALE_LSCH0 0x000003FF -#define LEDC_DUTY_SCALE_LSCH0_M ((LEDC_DUTY_SCALE_LSCH0_V)<<(LEDC_DUTY_SCALE_LSCH0_S)) -#define LEDC_DUTY_SCALE_LSCH0_V 0x3FF -#define LEDC_DUTY_SCALE_LSCH0_S 0 - -#define LEDC_LSCH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00B0) -/* LEDC_DUTY_LSCH0 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for low speed channel0.*/ -#define LEDC_DUTY_LSCH0 0x01FFFFFF -#define LEDC_DUTY_LSCH0_M ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S)) -#define LEDC_DUTY_LSCH0_V 0x1FFFFFF -#define LEDC_DUTY_LSCH0_S 0 - -#define LEDC_LSCH1_CONF0_REG (DR_REG_LEDC_BASE + 0x00B4) -/* LEDC_PARA_UP_LSCH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This bit is used to update register LEDC_LSCH1_HPOINT and LEDC_LSCH1_DUTY - for low speed channel1.*/ -#define LEDC_PARA_UP_LSCH1 (BIT(4)) -#define LEDC_PARA_UP_LSCH1_M (BIT(4)) -#define LEDC_PARA_UP_LSCH1_V 0x1 -#define LEDC_PARA_UP_LSCH1_S 4 -/* LEDC_IDLE_LV_LSCH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when low speed channel1 is off.*/ -#define LEDC_IDLE_LV_LSCH1 (BIT(3)) -#define LEDC_IDLE_LV_LSCH1_M (BIT(3)) -#define LEDC_IDLE_LV_LSCH1_V 0x1 -#define LEDC_IDLE_LV_LSCH1_S 3 -/* LEDC_SIG_OUT_EN_LSCH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for low speed channel1.*/ -#define LEDC_SIG_OUT_EN_LSCH1 (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH1_M (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH1_V 0x1 -#define LEDC_SIG_OUT_EN_LSCH1_S 2 -/* LEDC_TIMER_SEL_LSCH1 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four low speed timers the two bits are used to select - one of them for low speed channel1. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ -#define LEDC_TIMER_SEL_LSCH1 0x00000003 -#define LEDC_TIMER_SEL_LSCH1_M ((LEDC_TIMER_SEL_LSCH1_V)<<(LEDC_TIMER_SEL_LSCH1_S)) -#define LEDC_TIMER_SEL_LSCH1_V 0x3 -#define LEDC_TIMER_SEL_LSCH1_S 0 - -#define LEDC_LSCH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x00B8) -/* LEDC_HPOINT_LSCH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when lstimerx(x=[0 3]) selected - by low speed channel1 has reached reg_hpoint_lsch1[19:0]*/ -#define LEDC_HPOINT_LSCH1 0x000FFFFF -#define LEDC_HPOINT_LSCH1_M ((LEDC_HPOINT_LSCH1_V)<<(LEDC_HPOINT_LSCH1_S)) -#define LEDC_HPOINT_LSCH1_V 0xFFFFF -#define LEDC_HPOINT_LSCH1_S 0 - -#define LEDC_LSCH1_DUTY_REG (DR_REG_LEDC_BASE + 0x00BC) -/* LEDC_DUTY_LSCH1 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When lstimerx(x=[0 - 3]) choosed by low speed channel1 has reached reg_lpoint_lsch1 the output signal changes to low. reg_lpoint_lsch1=(reg_hpoint_lsch1[19:0]+reg_duty_lsch1[24:4]) (1) reg_lpoint_lsch1=(reg_hpoint_lsch1[19:0]+reg_duty_lsch1[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_LSCH1 0x01FFFFFF -#define LEDC_DUTY_LSCH1_M ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S)) -#define LEDC_DUTY_LSCH1_V 0x1FFFFFF -#define LEDC_DUTY_LSCH1_S 0 - -#define LEDC_LSCH1_CONF1_REG (DR_REG_LEDC_BASE + 0x00C0) -/* LEDC_DUTY_START_LSCH1 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 - has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ -#define LEDC_DUTY_START_LSCH1 (BIT(31)) -#define LEDC_DUTY_START_LSCH1_M (BIT(31)) -#define LEDC_DUTY_START_LSCH1_V 0x1 -#define LEDC_DUTY_START_LSCH1_S 31 -/* LEDC_DUTY_INC_LSCH1 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for low speed channel1.*/ -#define LEDC_DUTY_INC_LSCH1 (BIT(30)) -#define LEDC_DUTY_INC_LSCH1_M (BIT(30)) -#define LEDC_DUTY_INC_LSCH1_V 0x1 -#define LEDC_DUTY_INC_LSCH1_S 30 -/* LEDC_DUTY_NUM_LSCH1 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for low speed channel1.*/ -#define LEDC_DUTY_NUM_LSCH1 0x000003FF -#define LEDC_DUTY_NUM_LSCH1_M ((LEDC_DUTY_NUM_LSCH1_V)<<(LEDC_DUTY_NUM_LSCH1_S)) -#define LEDC_DUTY_NUM_LSCH1_V 0x3FF -#define LEDC_DUTY_NUM_LSCH1_S 20 -/* LEDC_DUTY_CYCLE_LSCH1 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_lsch1 cycles for low speed channel1.*/ -#define LEDC_DUTY_CYCLE_LSCH1 0x000003FF -#define LEDC_DUTY_CYCLE_LSCH1_M ((LEDC_DUTY_CYCLE_LSCH1_V)<<(LEDC_DUTY_CYCLE_LSCH1_S)) -#define LEDC_DUTY_CYCLE_LSCH1_V 0x3FF -#define LEDC_DUTY_CYCLE_LSCH1_S 10 -/* LEDC_DUTY_SCALE_LSCH1 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - low speed channel1.*/ -#define LEDC_DUTY_SCALE_LSCH1 0x000003FF -#define LEDC_DUTY_SCALE_LSCH1_M ((LEDC_DUTY_SCALE_LSCH1_V)<<(LEDC_DUTY_SCALE_LSCH1_S)) -#define LEDC_DUTY_SCALE_LSCH1_V 0x3FF -#define LEDC_DUTY_SCALE_LSCH1_S 0 - -#define LEDC_LSCH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00C4) -/* LEDC_DUTY_LSCH1 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for low speed channel1.*/ -#define LEDC_DUTY_LSCH1 0x01FFFFFF -#define LEDC_DUTY_LSCH1_M ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S)) -#define LEDC_DUTY_LSCH1_V 0x1FFFFFF -#define LEDC_DUTY_LSCH1_S 0 - -#define LEDC_LSCH2_CONF0_REG (DR_REG_LEDC_BASE + 0x00C8) -/* LEDC_PARA_UP_LSCH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This bit is used to update register LEDC_LSCH2_HPOINT and LEDC_LSCH2_DUTY - for low speed channel2.*/ -#define LEDC_PARA_UP_LSCH2 (BIT(4)) -#define LEDC_PARA_UP_LSCH2_M (BIT(4)) -#define LEDC_PARA_UP_LSCH2_V 0x1 -#define LEDC_PARA_UP_LSCH2_S 4 -/* LEDC_IDLE_LV_LSCH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when low speed channel2 is off.*/ -#define LEDC_IDLE_LV_LSCH2 (BIT(3)) -#define LEDC_IDLE_LV_LSCH2_M (BIT(3)) -#define LEDC_IDLE_LV_LSCH2_V 0x1 -#define LEDC_IDLE_LV_LSCH2_S 3 -/* LEDC_SIG_OUT_EN_LSCH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for low speed channel2.*/ -#define LEDC_SIG_OUT_EN_LSCH2 (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH2_M (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH2_V 0x1 -#define LEDC_SIG_OUT_EN_LSCH2_S 2 -/* LEDC_TIMER_SEL_LSCH2 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four low speed timers the two bits are used to select - one of them for low speed channel2. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ -#define LEDC_TIMER_SEL_LSCH2 0x00000003 -#define LEDC_TIMER_SEL_LSCH2_M ((LEDC_TIMER_SEL_LSCH2_V)<<(LEDC_TIMER_SEL_LSCH2_S)) -#define LEDC_TIMER_SEL_LSCH2_V 0x3 -#define LEDC_TIMER_SEL_LSCH2_S 0 - -#define LEDC_LSCH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x00CC) -/* LEDC_HPOINT_LSCH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when lstimerx(x=[0 3]) selected - by low speed channel2 has reached reg_hpoint_lsch2[19:0]*/ -#define LEDC_HPOINT_LSCH2 0x000FFFFF -#define LEDC_HPOINT_LSCH2_M ((LEDC_HPOINT_LSCH2_V)<<(LEDC_HPOINT_LSCH2_S)) -#define LEDC_HPOINT_LSCH2_V 0xFFFFF -#define LEDC_HPOINT_LSCH2_S 0 - -#define LEDC_LSCH2_DUTY_REG (DR_REG_LEDC_BASE + 0x00D0) -/* LEDC_DUTY_LSCH2 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When lstimerx(x=[0 - 3]) choosed by low speed channel2 has reached reg_lpoint_lsch2 the output signal changes to low. reg_lpoint_lsch2=(reg_hpoint_lsch2[19:0]+reg_duty_lsch2[24:4]) (1) reg_lpoint_lsch2=(reg_hpoint_lsch2[19:0]+reg_duty_lsch2[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_LSCH2 0x01FFFFFF -#define LEDC_DUTY_LSCH2_M ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S)) -#define LEDC_DUTY_LSCH2_V 0x1FFFFFF -#define LEDC_DUTY_LSCH2_S 0 - -#define LEDC_LSCH2_CONF1_REG (DR_REG_LEDC_BASE + 0x00D4) -/* LEDC_DUTY_START_LSCH2 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch2 reg_duty_cycle_hsch2 and reg_duty_scale_hsch2 - has been configured. these register won't take effect until set reg_duty_start_hsch2. this bit is automatically cleared by hardware.*/ -#define LEDC_DUTY_START_LSCH2 (BIT(31)) -#define LEDC_DUTY_START_LSCH2_M (BIT(31)) -#define LEDC_DUTY_START_LSCH2_V 0x1 -#define LEDC_DUTY_START_LSCH2_S 31 -/* LEDC_DUTY_INC_LSCH2 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for low speed channel2.*/ -#define LEDC_DUTY_INC_LSCH2 (BIT(30)) -#define LEDC_DUTY_INC_LSCH2_M (BIT(30)) -#define LEDC_DUTY_INC_LSCH2_V 0x1 -#define LEDC_DUTY_INC_LSCH2_S 30 -/* LEDC_DUTY_NUM_LSCH2 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for low speed channel2.*/ -#define LEDC_DUTY_NUM_LSCH2 0x000003FF -#define LEDC_DUTY_NUM_LSCH2_M ((LEDC_DUTY_NUM_LSCH2_V)<<(LEDC_DUTY_NUM_LSCH2_S)) -#define LEDC_DUTY_NUM_LSCH2_V 0x3FF -#define LEDC_DUTY_NUM_LSCH2_S 20 -/* LEDC_DUTY_CYCLE_LSCH2 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_lsch2 cycles for low speed channel2.*/ -#define LEDC_DUTY_CYCLE_LSCH2 0x000003FF -#define LEDC_DUTY_CYCLE_LSCH2_M ((LEDC_DUTY_CYCLE_LSCH2_V)<<(LEDC_DUTY_CYCLE_LSCH2_S)) -#define LEDC_DUTY_CYCLE_LSCH2_V 0x3FF -#define LEDC_DUTY_CYCLE_LSCH2_S 10 -/* LEDC_DUTY_SCALE_LSCH2 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - low speed channel2.*/ -#define LEDC_DUTY_SCALE_LSCH2 0x000003FF -#define LEDC_DUTY_SCALE_LSCH2_M ((LEDC_DUTY_SCALE_LSCH2_V)<<(LEDC_DUTY_SCALE_LSCH2_S)) -#define LEDC_DUTY_SCALE_LSCH2_V 0x3FF -#define LEDC_DUTY_SCALE_LSCH2_S 0 - -#define LEDC_LSCH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00D8) -/* LEDC_DUTY_LSCH2 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for low speed channel2.*/ -#define LEDC_DUTY_LSCH2 0x01FFFFFF -#define LEDC_DUTY_LSCH2_M ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S)) -#define LEDC_DUTY_LSCH2_V 0x1FFFFFF -#define LEDC_DUTY_LSCH2_S 0 - -#define LEDC_LSCH3_CONF0_REG (DR_REG_LEDC_BASE + 0x00DC) -/* LEDC_PARA_UP_LSCH3 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This bit is used to update register LEDC_LSCH3_HPOINT and LEDC_LSCH3_DUTY - for low speed channel3.*/ -#define LEDC_PARA_UP_LSCH3 (BIT(4)) -#define LEDC_PARA_UP_LSCH3_M (BIT(4)) -#define LEDC_PARA_UP_LSCH3_V 0x1 -#define LEDC_PARA_UP_LSCH3_S 4 -/* LEDC_IDLE_LV_LSCH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when low speed channel3 is off.*/ -#define LEDC_IDLE_LV_LSCH3 (BIT(3)) -#define LEDC_IDLE_LV_LSCH3_M (BIT(3)) -#define LEDC_IDLE_LV_LSCH3_V 0x1 -#define LEDC_IDLE_LV_LSCH3_S 3 -/* LEDC_SIG_OUT_EN_LSCH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for low speed channel3.*/ -#define LEDC_SIG_OUT_EN_LSCH3 (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH3_M (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH3_V 0x1 -#define LEDC_SIG_OUT_EN_LSCH3_S 2 -/* LEDC_TIMER_SEL_LSCH3 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four low speed timers the two bits are used to select - one of them for low speed channel3. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ -#define LEDC_TIMER_SEL_LSCH3 0x00000003 -#define LEDC_TIMER_SEL_LSCH3_M ((LEDC_TIMER_SEL_LSCH3_V)<<(LEDC_TIMER_SEL_LSCH3_S)) -#define LEDC_TIMER_SEL_LSCH3_V 0x3 -#define LEDC_TIMER_SEL_LSCH3_S 0 - -#define LEDC_LSCH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x00E0) -/* LEDC_HPOINT_LSCH3 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when lstimerx(x=[0 3]) selected - by low speed channel3 has reached reg_hpoint_lsch3[19:0]*/ -#define LEDC_HPOINT_LSCH3 0x000FFFFF -#define LEDC_HPOINT_LSCH3_M ((LEDC_HPOINT_LSCH3_V)<<(LEDC_HPOINT_LSCH3_S)) -#define LEDC_HPOINT_LSCH3_V 0xFFFFF -#define LEDC_HPOINT_LSCH3_S 0 - -#define LEDC_LSCH3_DUTY_REG (DR_REG_LEDC_BASE + 0x00E4) -/* LEDC_DUTY_LSCH3 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When lstimerx(x=[0 - 3]) choosed by low speed channel3 has reached reg_lpoint_lsch3 the output signal changes to low. reg_lpoint_lsch3=(reg_hpoint_lsch3[19:0]+reg_duty_lsch3[24:4]) (1) reg_lpoint_lsch3=(reg_hpoint_lsch3[19:0]+reg_duty_lsch3[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_LSCH3 0x01FFFFFF -#define LEDC_DUTY_LSCH3_M ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S)) -#define LEDC_DUTY_LSCH3_V 0x1FFFFFF -#define LEDC_DUTY_LSCH3_S 0 - -#define LEDC_LSCH3_CONF1_REG (DR_REG_LEDC_BASE + 0x00E8) -/* LEDC_DUTY_START_LSCH3 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch3 reg_duty_cycle_hsch3 and reg_duty_scale_hsch3 - has been configured. these register won't take effect until set reg_duty_start_hsch3. this bit is automatically cleared by hardware.*/ -#define LEDC_DUTY_START_LSCH3 (BIT(31)) -#define LEDC_DUTY_START_LSCH3_M (BIT(31)) -#define LEDC_DUTY_START_LSCH3_V 0x1 -#define LEDC_DUTY_START_LSCH3_S 31 -/* LEDC_DUTY_INC_LSCH3 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for low speed channel3.*/ -#define LEDC_DUTY_INC_LSCH3 (BIT(30)) -#define LEDC_DUTY_INC_LSCH3_M (BIT(30)) -#define LEDC_DUTY_INC_LSCH3_V 0x1 -#define LEDC_DUTY_INC_LSCH3_S 30 -/* LEDC_DUTY_NUM_LSCH3 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for low speed channel3.*/ -#define LEDC_DUTY_NUM_LSCH3 0x000003FF -#define LEDC_DUTY_NUM_LSCH3_M ((LEDC_DUTY_NUM_LSCH3_V)<<(LEDC_DUTY_NUM_LSCH3_S)) -#define LEDC_DUTY_NUM_LSCH3_V 0x3FF -#define LEDC_DUTY_NUM_LSCH3_S 20 -/* LEDC_DUTY_CYCLE_LSCH3 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_lsch3 cycles for low speed channel3.*/ -#define LEDC_DUTY_CYCLE_LSCH3 0x000003FF -#define LEDC_DUTY_CYCLE_LSCH3_M ((LEDC_DUTY_CYCLE_LSCH3_V)<<(LEDC_DUTY_CYCLE_LSCH3_S)) -#define LEDC_DUTY_CYCLE_LSCH3_V 0x3FF -#define LEDC_DUTY_CYCLE_LSCH3_S 10 -/* LEDC_DUTY_SCALE_LSCH3 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - low speed channel3.*/ -#define LEDC_DUTY_SCALE_LSCH3 0x000003FF -#define LEDC_DUTY_SCALE_LSCH3_M ((LEDC_DUTY_SCALE_LSCH3_V)<<(LEDC_DUTY_SCALE_LSCH3_S)) -#define LEDC_DUTY_SCALE_LSCH3_V 0x3FF -#define LEDC_DUTY_SCALE_LSCH3_S 0 - -#define LEDC_LSCH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00EC) -/* LEDC_DUTY_LSCH3 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for low speed channel3.*/ -#define LEDC_DUTY_LSCH3 0x01FFFFFF -#define LEDC_DUTY_LSCH3_M ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S)) -#define LEDC_DUTY_LSCH3_V 0x1FFFFFF -#define LEDC_DUTY_LSCH3_S 0 - -#define LEDC_LSCH4_CONF0_REG (DR_REG_LEDC_BASE + 0x00F0) -/* LEDC_PARA_UP_LSCH4 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This bit is used to update register LEDC_LSCH4_HPOINT and LEDC_LSCH4_DUTY - for low speed channel4.*/ -#define LEDC_PARA_UP_LSCH4 (BIT(4)) -#define LEDC_PARA_UP_LSCH4_M (BIT(4)) -#define LEDC_PARA_UP_LSCH4_V 0x1 -#define LEDC_PARA_UP_LSCH4_S 4 -/* LEDC_IDLE_LV_LSCH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when low speed channel4 is off.*/ -#define LEDC_IDLE_LV_LSCH4 (BIT(3)) -#define LEDC_IDLE_LV_LSCH4_M (BIT(3)) -#define LEDC_IDLE_LV_LSCH4_V 0x1 -#define LEDC_IDLE_LV_LSCH4_S 3 -/* LEDC_SIG_OUT_EN_LSCH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for low speed channel4.*/ -#define LEDC_SIG_OUT_EN_LSCH4 (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH4_M (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH4_V 0x1 -#define LEDC_SIG_OUT_EN_LSCH4_S 2 -/* LEDC_TIMER_SEL_LSCH4 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four low speed timers the two bits are used to select - one of them for low speed channel4. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ -#define LEDC_TIMER_SEL_LSCH4 0x00000003 -#define LEDC_TIMER_SEL_LSCH4_M ((LEDC_TIMER_SEL_LSCH4_V)<<(LEDC_TIMER_SEL_LSCH4_S)) -#define LEDC_TIMER_SEL_LSCH4_V 0x3 -#define LEDC_TIMER_SEL_LSCH4_S 0 - -#define LEDC_LSCH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x00F4) -/* LEDC_HPOINT_LSCH4 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when lstimerx(x=[0 3]) selected - by low speed channel4 has reached reg_hpoint_lsch4[19:0]*/ -#define LEDC_HPOINT_LSCH4 0x000FFFFF -#define LEDC_HPOINT_LSCH4_M ((LEDC_HPOINT_LSCH4_V)<<(LEDC_HPOINT_LSCH4_S)) -#define LEDC_HPOINT_LSCH4_V 0xFFFFF -#define LEDC_HPOINT_LSCH4_S 0 - -#define LEDC_LSCH4_DUTY_REG (DR_REG_LEDC_BASE + 0x00F8) -/* LEDC_DUTY_LSCH4 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When lstimerx(x=[0 - 3]) choosed by low speed channel4 has reached reg_lpoint_lsch4 the output signal changes to low. reg_lpoint_lsch4=(reg_hpoint_lsch4[19:0]+reg_duty_lsch4[24:4]) (1) reg_lpoint_lsch4=(reg_hpoint_lsch4[19:0]+reg_duty_lsch4[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_LSCH4 0x01FFFFFF -#define LEDC_DUTY_LSCH4_M ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S)) -#define LEDC_DUTY_LSCH4_V 0x1FFFFFF -#define LEDC_DUTY_LSCH4_S 0 - -#define LEDC_LSCH4_CONF1_REG (DR_REG_LEDC_BASE + 0x00FC) -/* LEDC_DUTY_START_LSCH4 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch4 reg_duty_cycle_hsch4 and reg_duty_scale_hsch4 - has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware.*/ -#define LEDC_DUTY_START_LSCH4 (BIT(31)) -#define LEDC_DUTY_START_LSCH4_M (BIT(31)) -#define LEDC_DUTY_START_LSCH4_V 0x1 -#define LEDC_DUTY_START_LSCH4_S 31 -/* LEDC_DUTY_INC_LSCH4 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for low speed channel4.*/ -#define LEDC_DUTY_INC_LSCH4 (BIT(30)) -#define LEDC_DUTY_INC_LSCH4_M (BIT(30)) -#define LEDC_DUTY_INC_LSCH4_V 0x1 -#define LEDC_DUTY_INC_LSCH4_S 30 -/* LEDC_DUTY_NUM_LSCH4 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for low speed channel4.*/ -#define LEDC_DUTY_NUM_LSCH4 0x000003FF -#define LEDC_DUTY_NUM_LSCH4_M ((LEDC_DUTY_NUM_LSCH4_V)<<(LEDC_DUTY_NUM_LSCH4_S)) -#define LEDC_DUTY_NUM_LSCH4_V 0x3FF -#define LEDC_DUTY_NUM_LSCH4_S 20 -/* LEDC_DUTY_CYCLE_LSCH4 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_lsch4 cycles for low speed channel4.*/ -#define LEDC_DUTY_CYCLE_LSCH4 0x000003FF -#define LEDC_DUTY_CYCLE_LSCH4_M ((LEDC_DUTY_CYCLE_LSCH4_V)<<(LEDC_DUTY_CYCLE_LSCH4_S)) -#define LEDC_DUTY_CYCLE_LSCH4_V 0x3FF -#define LEDC_DUTY_CYCLE_LSCH4_S 10 -/* LEDC_DUTY_SCALE_LSCH4 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - low speed channel4.*/ -#define LEDC_DUTY_SCALE_LSCH4 0x000003FF -#define LEDC_DUTY_SCALE_LSCH4_M ((LEDC_DUTY_SCALE_LSCH4_V)<<(LEDC_DUTY_SCALE_LSCH4_S)) -#define LEDC_DUTY_SCALE_LSCH4_V 0x3FF -#define LEDC_DUTY_SCALE_LSCH4_S 0 - -#define LEDC_LSCH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0100) -/* LEDC_DUTY_LSCH4 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for low speed channel4.*/ -#define LEDC_DUTY_LSCH4 0x01FFFFFF -#define LEDC_DUTY_LSCH4_M ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S)) -#define LEDC_DUTY_LSCH4_V 0x1FFFFFF -#define LEDC_DUTY_LSCH4_S 0 - -#define LEDC_LSCH5_CONF0_REG (DR_REG_LEDC_BASE + 0x0104) -/* LEDC_PARA_UP_LSCH5 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This bit is used to update register LEDC_LSCH5_HPOINT and LEDC_LSCH5_DUTY - for low speed channel5.*/ -#define LEDC_PARA_UP_LSCH5 (BIT(4)) -#define LEDC_PARA_UP_LSCH5_M (BIT(4)) -#define LEDC_PARA_UP_LSCH5_V 0x1 -#define LEDC_PARA_UP_LSCH5_S 4 -/* LEDC_IDLE_LV_LSCH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when low speed channel5 is off.*/ -#define LEDC_IDLE_LV_LSCH5 (BIT(3)) -#define LEDC_IDLE_LV_LSCH5_M (BIT(3)) -#define LEDC_IDLE_LV_LSCH5_V 0x1 -#define LEDC_IDLE_LV_LSCH5_S 3 -/* LEDC_SIG_OUT_EN_LSCH5 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for low speed channel5.*/ -#define LEDC_SIG_OUT_EN_LSCH5 (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH5_M (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH5_V 0x1 -#define LEDC_SIG_OUT_EN_LSCH5_S 2 -/* LEDC_TIMER_SEL_LSCH5 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four low speed timers the two bits are used to select - one of them for low speed channel5. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ -#define LEDC_TIMER_SEL_LSCH5 0x00000003 -#define LEDC_TIMER_SEL_LSCH5_M ((LEDC_TIMER_SEL_LSCH5_V)<<(LEDC_TIMER_SEL_LSCH5_S)) -#define LEDC_TIMER_SEL_LSCH5_V 0x3 -#define LEDC_TIMER_SEL_LSCH5_S 0 - -#define LEDC_LSCH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x0108) -/* LEDC_HPOINT_LSCH5 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when lstimerx(x=[0 3]) selected - by low speed channel5 has reached reg_hpoint_lsch5[19:0]*/ -#define LEDC_HPOINT_LSCH5 0x000FFFFF -#define LEDC_HPOINT_LSCH5_M ((LEDC_HPOINT_LSCH5_V)<<(LEDC_HPOINT_LSCH5_S)) -#define LEDC_HPOINT_LSCH5_V 0xFFFFF -#define LEDC_HPOINT_LSCH5_S 0 - -#define LEDC_LSCH5_DUTY_REG (DR_REG_LEDC_BASE + 0x010C) -/* LEDC_DUTY_LSCH5 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When lstimerx(x=[0 - 3]) choosed by low speed channel5 has reached reg_lpoint_lsch5 the output signal changes to low. reg_lpoint_lsch5=(reg_hpoint_lsch5[19:0]+reg_duty_lsch5[24:4]) (1) reg_lpoint_lsch5=(reg_hpoint_lsch5[19:0]+reg_duty_lsch5[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_LSCH5 0x01FFFFFF -#define LEDC_DUTY_LSCH5_M ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S)) -#define LEDC_DUTY_LSCH5_V 0x1FFFFFF -#define LEDC_DUTY_LSCH5_S 0 - -#define LEDC_LSCH5_CONF1_REG (DR_REG_LEDC_BASE + 0x0110) -/* LEDC_DUTY_START_LSCH5 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch4 reg_duty_cycle_hsch4 and reg_duty_scale_hsch4 - has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware.*/ -#define LEDC_DUTY_START_LSCH5 (BIT(31)) -#define LEDC_DUTY_START_LSCH5_M (BIT(31)) -#define LEDC_DUTY_START_LSCH5_V 0x1 -#define LEDC_DUTY_START_LSCH5_S 31 -/* LEDC_DUTY_INC_LSCH5 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for low speed channel5.*/ -#define LEDC_DUTY_INC_LSCH5 (BIT(30)) -#define LEDC_DUTY_INC_LSCH5_M (BIT(30)) -#define LEDC_DUTY_INC_LSCH5_V 0x1 -#define LEDC_DUTY_INC_LSCH5_S 30 -/* LEDC_DUTY_NUM_LSCH5 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for low speed channel5.*/ -#define LEDC_DUTY_NUM_LSCH5 0x000003FF -#define LEDC_DUTY_NUM_LSCH5_M ((LEDC_DUTY_NUM_LSCH5_V)<<(LEDC_DUTY_NUM_LSCH5_S)) -#define LEDC_DUTY_NUM_LSCH5_V 0x3FF -#define LEDC_DUTY_NUM_LSCH5_S 20 -/* LEDC_DUTY_CYCLE_LSCH5 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_lsch5 cycles for low speed channel4.*/ -#define LEDC_DUTY_CYCLE_LSCH5 0x000003FF -#define LEDC_DUTY_CYCLE_LSCH5_M ((LEDC_DUTY_CYCLE_LSCH5_V)<<(LEDC_DUTY_CYCLE_LSCH5_S)) -#define LEDC_DUTY_CYCLE_LSCH5_V 0x3FF -#define LEDC_DUTY_CYCLE_LSCH5_S 10 -/* LEDC_DUTY_SCALE_LSCH5 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - low speed channel5.*/ -#define LEDC_DUTY_SCALE_LSCH5 0x000003FF -#define LEDC_DUTY_SCALE_LSCH5_M ((LEDC_DUTY_SCALE_LSCH5_V)<<(LEDC_DUTY_SCALE_LSCH5_S)) -#define LEDC_DUTY_SCALE_LSCH5_V 0x3FF -#define LEDC_DUTY_SCALE_LSCH5_S 0 - -#define LEDC_LSCH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0114) -/* LEDC_DUTY_LSCH5 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for low speed channel5.*/ -#define LEDC_DUTY_LSCH5 0x01FFFFFF -#define LEDC_DUTY_LSCH5_M ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S)) -#define LEDC_DUTY_LSCH5_V 0x1FFFFFF -#define LEDC_DUTY_LSCH5_S 0 - -#define LEDC_LSCH6_CONF0_REG (DR_REG_LEDC_BASE + 0x0118) -/* LEDC_PARA_UP_LSCH6 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This bit is used to update register LEDC_LSCH6_HPOINT and LEDC_LSCH6_DUTY - for low speed channel6.*/ -#define LEDC_PARA_UP_LSCH6 (BIT(4)) -#define LEDC_PARA_UP_LSCH6_M (BIT(4)) -#define LEDC_PARA_UP_LSCH6_V 0x1 -#define LEDC_PARA_UP_LSCH6_S 4 -/* LEDC_IDLE_LV_LSCH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when low speed channel6 is off.*/ -#define LEDC_IDLE_LV_LSCH6 (BIT(3)) -#define LEDC_IDLE_LV_LSCH6_M (BIT(3)) -#define LEDC_IDLE_LV_LSCH6_V 0x1 -#define LEDC_IDLE_LV_LSCH6_S 3 -/* LEDC_SIG_OUT_EN_LSCH6 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for low speed channel6.*/ -#define LEDC_SIG_OUT_EN_LSCH6 (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH6_M (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH6_V 0x1 -#define LEDC_SIG_OUT_EN_LSCH6_S 2 -/* LEDC_TIMER_SEL_LSCH6 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four low speed timers the two bits are used to select - one of them for low speed channel6. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ -#define LEDC_TIMER_SEL_LSCH6 0x00000003 -#define LEDC_TIMER_SEL_LSCH6_M ((LEDC_TIMER_SEL_LSCH6_V)<<(LEDC_TIMER_SEL_LSCH6_S)) -#define LEDC_TIMER_SEL_LSCH6_V 0x3 -#define LEDC_TIMER_SEL_LSCH6_S 0 - -#define LEDC_LSCH6_HPOINT_REG (DR_REG_LEDC_BASE + 0x011C) -/* LEDC_HPOINT_LSCH6 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when lstimerx(x=[0 3]) selected - by low speed channel6 has reached reg_hpoint_lsch6[19:0]*/ -#define LEDC_HPOINT_LSCH6 0x000FFFFF -#define LEDC_HPOINT_LSCH6_M ((LEDC_HPOINT_LSCH6_V)<<(LEDC_HPOINT_LSCH6_S)) -#define LEDC_HPOINT_LSCH6_V 0xFFFFF -#define LEDC_HPOINT_LSCH6_S 0 - -#define LEDC_LSCH6_DUTY_REG (DR_REG_LEDC_BASE + 0x0120) -/* LEDC_DUTY_LSCH6 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When lstimerx(x=[0 - 3]) choosed by low speed channel6 has reached reg_lpoint_lsch6 the output signal changes to low. reg_lpoint_lsch6=(reg_hpoint_lsch6[19:0]+reg_duty_lsch6[24:4]) (1) reg_lpoint_lsch6=(reg_hpoint_lsch6[19:0]+reg_duty_lsch6[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_LSCH6 0x01FFFFFF -#define LEDC_DUTY_LSCH6_M ((LEDC_DUTY_LSCH6_V)<<(LEDC_DUTY_LSCH6_S)) -#define LEDC_DUTY_LSCH6_V 0x1FFFFFF -#define LEDC_DUTY_LSCH6_S 0 - -#define LEDC_LSCH6_CONF1_REG (DR_REG_LEDC_BASE + 0x0124) -/* LEDC_DUTY_START_LSCH6 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch6 reg_duty_cycle_hsch6 and reg_duty_scale_hsch6 - has been configured. these register won't take effect until set reg_duty_start_hsch6. this bit is automatically cleared by hardware.*/ -#define LEDC_DUTY_START_LSCH6 (BIT(31)) -#define LEDC_DUTY_START_LSCH6_M (BIT(31)) -#define LEDC_DUTY_START_LSCH6_V 0x1 -#define LEDC_DUTY_START_LSCH6_S 31 -/* LEDC_DUTY_INC_LSCH6 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for low speed channel6.*/ -#define LEDC_DUTY_INC_LSCH6 (BIT(30)) -#define LEDC_DUTY_INC_LSCH6_M (BIT(30)) -#define LEDC_DUTY_INC_LSCH6_V 0x1 -#define LEDC_DUTY_INC_LSCH6_S 30 -/* LEDC_DUTY_NUM_LSCH6 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for low speed channel6.*/ -#define LEDC_DUTY_NUM_LSCH6 0x000003FF -#define LEDC_DUTY_NUM_LSCH6_M ((LEDC_DUTY_NUM_LSCH6_V)<<(LEDC_DUTY_NUM_LSCH6_S)) -#define LEDC_DUTY_NUM_LSCH6_V 0x3FF -#define LEDC_DUTY_NUM_LSCH6_S 20 -/* LEDC_DUTY_CYCLE_LSCH6 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_lsch6 cycles for low speed channel6.*/ -#define LEDC_DUTY_CYCLE_LSCH6 0x000003FF -#define LEDC_DUTY_CYCLE_LSCH6_M ((LEDC_DUTY_CYCLE_LSCH6_V)<<(LEDC_DUTY_CYCLE_LSCH6_S)) -#define LEDC_DUTY_CYCLE_LSCH6_V 0x3FF -#define LEDC_DUTY_CYCLE_LSCH6_S 10 -/* LEDC_DUTY_SCALE_LSCH6 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - low speed channel6.*/ -#define LEDC_DUTY_SCALE_LSCH6 0x000003FF -#define LEDC_DUTY_SCALE_LSCH6_M ((LEDC_DUTY_SCALE_LSCH6_V)<<(LEDC_DUTY_SCALE_LSCH6_S)) -#define LEDC_DUTY_SCALE_LSCH6_V 0x3FF -#define LEDC_DUTY_SCALE_LSCH6_S 0 - -#define LEDC_LSCH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0128) -/* LEDC_DUTY_LSCH6 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for low speed channel6.*/ -#define LEDC_DUTY_LSCH6 0x01FFFFFF -#define LEDC_DUTY_LSCH6_M ((LEDC_DUTY_LSCH6_V)<<(LEDC_DUTY_LSCH6_S)) -#define LEDC_DUTY_LSCH6_V 0x1FFFFFF -#define LEDC_DUTY_LSCH6_S 0 - -#define LEDC_LSCH7_CONF0_REG (DR_REG_LEDC_BASE + 0x012C) -/* LEDC_PARA_UP_LSCH7 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This bit is used to update register LEDC_LSCH7_HPOINT and LEDC_LSCH7_DUTY - for low speed channel7.*/ -#define LEDC_PARA_UP_LSCH7 (BIT(4)) -#define LEDC_PARA_UP_LSCH7_M (BIT(4)) -#define LEDC_PARA_UP_LSCH7_V 0x1 -#define LEDC_PARA_UP_LSCH7_S 4 -/* LEDC_IDLE_LV_LSCH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when low speed channel7 is off.*/ -#define LEDC_IDLE_LV_LSCH7 (BIT(3)) -#define LEDC_IDLE_LV_LSCH7_M (BIT(3)) -#define LEDC_IDLE_LV_LSCH7_V 0x1 -#define LEDC_IDLE_LV_LSCH7_S 3 -/* LEDC_SIG_OUT_EN_LSCH7 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for low speed channel7.*/ -#define LEDC_SIG_OUT_EN_LSCH7 (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH7_M (BIT(2)) -#define LEDC_SIG_OUT_EN_LSCH7_V 0x1 -#define LEDC_SIG_OUT_EN_LSCH7_S 2 -/* LEDC_TIMER_SEL_LSCH7 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four low speed timers the two bits are used to select - one of them for low speed channel7. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ -#define LEDC_TIMER_SEL_LSCH7 0x00000003 -#define LEDC_TIMER_SEL_LSCH7_M ((LEDC_TIMER_SEL_LSCH7_V)<<(LEDC_TIMER_SEL_LSCH7_S)) -#define LEDC_TIMER_SEL_LSCH7_V 0x3 -#define LEDC_TIMER_SEL_LSCH7_S 0 - -#define LEDC_LSCH7_HPOINT_REG (DR_REG_LEDC_BASE + 0x0130) -/* LEDC_HPOINT_LSCH7 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when lstimerx(x=[0 3]) selected - by low speed channel7 has reached reg_hpoint_lsch7[19:0]*/ -#define LEDC_HPOINT_LSCH7 0x000FFFFF -#define LEDC_HPOINT_LSCH7_M ((LEDC_HPOINT_LSCH7_V)<<(LEDC_HPOINT_LSCH7_S)) -#define LEDC_HPOINT_LSCH7_V 0xFFFFF -#define LEDC_HPOINT_LSCH7_S 0 - -#define LEDC_LSCH7_DUTY_REG (DR_REG_LEDC_BASE + 0x0134) -/* LEDC_DUTY_LSCH7 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When lstimerx(x=[0 - 3]) choosed by low speed channel7 has reached reg_lpoint_lsch7 the output signal changes to low. reg_lpoint_lsch7=(reg_hpoint_lsch7[19:0]+reg_duty_lsch7[24:4]) (1) reg_lpoint_lsch7=(reg_hpoint_lsch7[19:0]+reg_duty_lsch7[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_LSCH7 0x01FFFFFF -#define LEDC_DUTY_LSCH7_M ((LEDC_DUTY_LSCH7_V)<<(LEDC_DUTY_LSCH7_S)) -#define LEDC_DUTY_LSCH7_V 0x1FFFFFF -#define LEDC_DUTY_LSCH7_S 0 - -#define LEDC_LSCH7_CONF1_REG (DR_REG_LEDC_BASE + 0x0138) -/* LEDC_DUTY_START_LSCH7 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch4 reg_duty_cycle_hsch4 and reg_duty_scale_hsch4 - has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware.*/ -#define LEDC_DUTY_START_LSCH7 (BIT(31)) -#define LEDC_DUTY_START_LSCH7_M (BIT(31)) -#define LEDC_DUTY_START_LSCH7_V 0x1 -#define LEDC_DUTY_START_LSCH7_S 31 -/* LEDC_DUTY_INC_LSCH7 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for low speed channel4.*/ -#define LEDC_DUTY_INC_LSCH7 (BIT(30)) -#define LEDC_DUTY_INC_LSCH7_M (BIT(30)) -#define LEDC_DUTY_INC_LSCH7_V 0x1 -#define LEDC_DUTY_INC_LSCH7_S 30 -/* LEDC_DUTY_NUM_LSCH7 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for low speed channel4.*/ -#define LEDC_DUTY_NUM_LSCH7 0x000003FF -#define LEDC_DUTY_NUM_LSCH7_M ((LEDC_DUTY_NUM_LSCH7_V)<<(LEDC_DUTY_NUM_LSCH7_S)) -#define LEDC_DUTY_NUM_LSCH7_V 0x3FF -#define LEDC_DUTY_NUM_LSCH7_S 20 -/* LEDC_DUTY_CYCLE_LSCH7 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_lsch7 cycles for low speed channel7.*/ -#define LEDC_DUTY_CYCLE_LSCH7 0x000003FF -#define LEDC_DUTY_CYCLE_LSCH7_M ((LEDC_DUTY_CYCLE_LSCH7_V)<<(LEDC_DUTY_CYCLE_LSCH7_S)) -#define LEDC_DUTY_CYCLE_LSCH7_V 0x3FF -#define LEDC_DUTY_CYCLE_LSCH7_S 10 -/* LEDC_DUTY_SCALE_LSCH7 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - low speed channel7.*/ -#define LEDC_DUTY_SCALE_LSCH7 0x000003FF -#define LEDC_DUTY_SCALE_LSCH7_M ((LEDC_DUTY_SCALE_LSCH7_V)<<(LEDC_DUTY_SCALE_LSCH7_S)) -#define LEDC_DUTY_SCALE_LSCH7_V 0x3FF -#define LEDC_DUTY_SCALE_LSCH7_S 0 - -#define LEDC_LSCH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x013C) -/* LEDC_DUTY_LSCH7 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for low speed channel7.*/ -#define LEDC_DUTY_LSCH7 0x01FFFFFF -#define LEDC_DUTY_LSCH7_M ((LEDC_DUTY_LSCH7_V)<<(LEDC_DUTY_LSCH7_S)) -#define LEDC_DUTY_LSCH7_V 0x1FFFFFF -#define LEDC_DUTY_LSCH7_S 0 - -#define LEDC_HSTIMER0_CONF_REG (DR_REG_LEDC_BASE + 0x0140) -/* LEDC_TICK_SEL_HSTIMER0 : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: This bit is used to choose apb_clk or ref_tick for high speed - timer0. 1'b1:apb_clk 0:ref_tick*/ -#define LEDC_TICK_SEL_HSTIMER0 (BIT(25)) -#define LEDC_TICK_SEL_HSTIMER0_M (BIT(25)) -#define LEDC_TICK_SEL_HSTIMER0_V 0x1 -#define LEDC_TICK_SEL_HSTIMER0_S 25 -/* LEDC_HSTIMER0_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ -/*description: This bit is used to reset high speed timer0 the counter will be 0 after reset.*/ -#define LEDC_HSTIMER0_RST (BIT(24)) -#define LEDC_HSTIMER0_RST_M (BIT(24)) -#define LEDC_HSTIMER0_RST_V 0x1 -#define LEDC_HSTIMER0_RST_S 24 -/* LEDC_HSTIMER0_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: This bit is used to pause the counter in high speed timer0*/ -#define LEDC_HSTIMER0_PAUSE (BIT(23)) -#define LEDC_HSTIMER0_PAUSE_M (BIT(23)) -#define LEDC_HSTIMER0_PAUSE_V 0x1 -#define LEDC_HSTIMER0_PAUSE_S 23 -/* LEDC_DIV_NUM_HSTIMER0 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ -/*description: This register is used to configure parameter for divider in high - speed timer0 the least significant eight bits represent the decimal part.*/ -#define LEDC_DIV_NUM_HSTIMER0 0x0003FFFF -#define LEDC_DIV_NUM_HSTIMER0_M ((LEDC_DIV_NUM_HSTIMER0_V)<<(LEDC_DIV_NUM_HSTIMER0_S)) -#define LEDC_DIV_NUM_HSTIMER0_V 0x3FFFF -#define LEDC_DIV_NUM_HSTIMER0_S 5 -/* LEDC_HSTIMER0_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: This register controls the range of the counter in high speed - timer0. the counter range is [0 2**reg_hstimer0_lim] the max bit width for counter is 20.*/ -#define LEDC_HSTIMER0_LIM 0x0000001F -#define LEDC_HSTIMER0_LIM_M ((LEDC_HSTIMER0_LIM_V)<<(LEDC_HSTIMER0_LIM_S)) -#define LEDC_HSTIMER0_LIM_V 0x1F -#define LEDC_HSTIMER0_LIM_S 0 - -#define LEDC_HSTIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0x0144) -/* LEDC_HSTIMER0_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ -/*description: software can read this register to get the current counter value - in high speed timer0*/ -#define LEDC_HSTIMER0_CNT 0x000FFFFF -#define LEDC_HSTIMER0_CNT_M ((LEDC_HSTIMER0_CNT_V)<<(LEDC_HSTIMER0_CNT_S)) -#define LEDC_HSTIMER0_CNT_V 0xFFFFF -#define LEDC_HSTIMER0_CNT_S 0 - -#define LEDC_HSTIMER1_CONF_REG (DR_REG_LEDC_BASE + 0x0148) -/* LEDC_TICK_SEL_HSTIMER1 : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: This bit is used to choose apb_clk or ref_tick for high speed - timer1. 1'b1:apb_clk 0:ref_tick*/ -#define LEDC_TICK_SEL_HSTIMER1 (BIT(25)) -#define LEDC_TICK_SEL_HSTIMER1_M (BIT(25)) -#define LEDC_TICK_SEL_HSTIMER1_V 0x1 -#define LEDC_TICK_SEL_HSTIMER1_S 25 -/* LEDC_HSTIMER1_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ -/*description: This bit is used to reset high speed timer1 the counter will be 0 after reset.*/ -#define LEDC_HSTIMER1_RST (BIT(24)) -#define LEDC_HSTIMER1_RST_M (BIT(24)) -#define LEDC_HSTIMER1_RST_V 0x1 -#define LEDC_HSTIMER1_RST_S 24 -/* LEDC_HSTIMER1_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: This bit is used to pause the counter in high speed timer1*/ -#define LEDC_HSTIMER1_PAUSE (BIT(23)) -#define LEDC_HSTIMER1_PAUSE_M (BIT(23)) -#define LEDC_HSTIMER1_PAUSE_V 0x1 -#define LEDC_HSTIMER1_PAUSE_S 23 -/* LEDC_DIV_NUM_HSTIMER1 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ -/*description: This register is used to configure parameter for divider in high - speed timer1 the least significant eight bits represent the decimal part.*/ -#define LEDC_DIV_NUM_HSTIMER1 0x0003FFFF -#define LEDC_DIV_NUM_HSTIMER1_M ((LEDC_DIV_NUM_HSTIMER1_V)<<(LEDC_DIV_NUM_HSTIMER1_S)) -#define LEDC_DIV_NUM_HSTIMER1_V 0x3FFFF -#define LEDC_DIV_NUM_HSTIMER1_S 5 -/* LEDC_HSTIMER1_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: This register controls the range of the counter in high speed - timer1. the counter range is [0 2**reg_hstimer1_lim] the max bit width for counter is 20.*/ -#define LEDC_HSTIMER1_LIM 0x0000001F -#define LEDC_HSTIMER1_LIM_M ((LEDC_HSTIMER1_LIM_V)<<(LEDC_HSTIMER1_LIM_S)) -#define LEDC_HSTIMER1_LIM_V 0x1F -#define LEDC_HSTIMER1_LIM_S 0 - -#define LEDC_HSTIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0x014C) -/* LEDC_HSTIMER1_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ -/*description: software can read this register to get the current counter value - in high speed timer1.*/ -#define LEDC_HSTIMER1_CNT 0x000FFFFF -#define LEDC_HSTIMER1_CNT_M ((LEDC_HSTIMER1_CNT_V)<<(LEDC_HSTIMER1_CNT_S)) -#define LEDC_HSTIMER1_CNT_V 0xFFFFF -#define LEDC_HSTIMER1_CNT_S 0 - -#define LEDC_HSTIMER2_CONF_REG (DR_REG_LEDC_BASE + 0x0150) -/* LEDC_TICK_SEL_HSTIMER2 : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: This bit is used to choose apb_clk or ref_tick for high speed - timer2. 1'b1:apb_clk 0:ref_tick*/ -#define LEDC_TICK_SEL_HSTIMER2 (BIT(25)) -#define LEDC_TICK_SEL_HSTIMER2_M (BIT(25)) -#define LEDC_TICK_SEL_HSTIMER2_V 0x1 -#define LEDC_TICK_SEL_HSTIMER2_S 25 -/* LEDC_HSTIMER2_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ -/*description: This bit is used to reset high speed timer2 the counter will be 0 after reset.*/ -#define LEDC_HSTIMER2_RST (BIT(24)) -#define LEDC_HSTIMER2_RST_M (BIT(24)) -#define LEDC_HSTIMER2_RST_V 0x1 -#define LEDC_HSTIMER2_RST_S 24 -/* LEDC_HSTIMER2_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: This bit is used to pause the counter in high speed timer2*/ -#define LEDC_HSTIMER2_PAUSE (BIT(23)) -#define LEDC_HSTIMER2_PAUSE_M (BIT(23)) -#define LEDC_HSTIMER2_PAUSE_V 0x1 -#define LEDC_HSTIMER2_PAUSE_S 23 -/* LEDC_DIV_NUM_HSTIMER2 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ -/*description: This register is used to configure parameter for divider in high - speed timer2 the least significant eight bits represent the decimal part.*/ -#define LEDC_DIV_NUM_HSTIMER2 0x0003FFFF -#define LEDC_DIV_NUM_HSTIMER2_M ((LEDC_DIV_NUM_HSTIMER2_V)<<(LEDC_DIV_NUM_HSTIMER2_S)) -#define LEDC_DIV_NUM_HSTIMER2_V 0x3FFFF -#define LEDC_DIV_NUM_HSTIMER2_S 5 -/* LEDC_HSTIMER2_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: This register controls the range of the counter in high speed - timer2. the counter range is [0 2**reg_hstimer2_lim] the max bit width for counter is 20.*/ -#define LEDC_HSTIMER2_LIM 0x0000001F -#define LEDC_HSTIMER2_LIM_M ((LEDC_HSTIMER2_LIM_V)<<(LEDC_HSTIMER2_LIM_S)) -#define LEDC_HSTIMER2_LIM_V 0x1F -#define LEDC_HSTIMER2_LIM_S 0 - -#define LEDC_HSTIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0x0154) -/* LEDC_HSTIMER2_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ -/*description: software can read this register to get the current counter value - in high speed timer2*/ -#define LEDC_HSTIMER2_CNT 0x000FFFFF -#define LEDC_HSTIMER2_CNT_M ((LEDC_HSTIMER2_CNT_V)<<(LEDC_HSTIMER2_CNT_S)) -#define LEDC_HSTIMER2_CNT_V 0xFFFFF -#define LEDC_HSTIMER2_CNT_S 0 - -#define LEDC_HSTIMER3_CONF_REG (DR_REG_LEDC_BASE + 0x0158) -/* LEDC_TICK_SEL_HSTIMER3 : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: This bit is used to choose apb_clk or ref_tick for high speed - timer3. 1'b1:apb_clk 0:ref_tick*/ -#define LEDC_TICK_SEL_HSTIMER3 (BIT(25)) -#define LEDC_TICK_SEL_HSTIMER3_M (BIT(25)) -#define LEDC_TICK_SEL_HSTIMER3_V 0x1 -#define LEDC_TICK_SEL_HSTIMER3_S 25 -/* LEDC_HSTIMER3_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ -/*description: This bit is used to reset high speed timer3 the counter will be 0 after reset.*/ -#define LEDC_HSTIMER3_RST (BIT(24)) -#define LEDC_HSTIMER3_RST_M (BIT(24)) -#define LEDC_HSTIMER3_RST_V 0x1 -#define LEDC_HSTIMER3_RST_S 24 -/* LEDC_HSTIMER3_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: This bit is used to pause the counter in high speed timer3*/ -#define LEDC_HSTIMER3_PAUSE (BIT(23)) -#define LEDC_HSTIMER3_PAUSE_M (BIT(23)) -#define LEDC_HSTIMER3_PAUSE_V 0x1 -#define LEDC_HSTIMER3_PAUSE_S 23 -/* LEDC_DIV_NUM_HSTIMER3 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ -/*description: This register is used to configure parameter for divider in high - speed timer3 the least significant eight bits represent the decimal part.*/ -#define LEDC_DIV_NUM_HSTIMER3 0x0003FFFF -#define LEDC_DIV_NUM_HSTIMER3_M ((LEDC_DIV_NUM_HSTIMER3_V)<<(LEDC_DIV_NUM_HSTIMER3_S)) -#define LEDC_DIV_NUM_HSTIMER3_V 0x3FFFF -#define LEDC_DIV_NUM_HSTIMER3_S 5 -/* LEDC_HSTIMER3_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: This register controls the range of the counter in high speed - timer3. the counter range is [0 2**reg_hstimer3_lim] the max bit width for counter is 20.*/ -#define LEDC_HSTIMER3_LIM 0x0000001F -#define LEDC_HSTIMER3_LIM_M ((LEDC_HSTIMER3_LIM_V)<<(LEDC_HSTIMER3_LIM_S)) -#define LEDC_HSTIMER3_LIM_V 0x1F -#define LEDC_HSTIMER3_LIM_S 0 - -#define LEDC_HSTIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0x015C) -/* LEDC_HSTIMER3_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ -/*description: software can read this register to get the current counter value - in high speed timer3*/ -#define LEDC_HSTIMER3_CNT 0x000FFFFF -#define LEDC_HSTIMER3_CNT_M ((LEDC_HSTIMER3_CNT_V)<<(LEDC_HSTIMER3_CNT_S)) -#define LEDC_HSTIMER3_CNT_V 0xFFFFF -#define LEDC_HSTIMER3_CNT_S 0 - -#define LEDC_LSTIMER0_CONF_REG (DR_REG_LEDC_BASE + 0x0160) -/* LEDC_LSTIMER0_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */ -/*description: Set this bit to update reg_div_num_lstime0 and reg_lstimer0_lim.*/ -#define LEDC_LSTIMER0_PARA_UP (BIT(26)) -#define LEDC_LSTIMER0_PARA_UP_M (BIT(26)) -#define LEDC_LSTIMER0_PARA_UP_V 0x1 -#define LEDC_LSTIMER0_PARA_UP_S 26 -/* LEDC_TICK_SEL_LSTIMER0 : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: This bit is used to choose slow_clk or ref_tick for low speed - timer0. 1'b1:slow_clk 0:ref_tick*/ -#define LEDC_TICK_SEL_LSTIMER0 (BIT(25)) -#define LEDC_TICK_SEL_LSTIMER0_M (BIT(25)) -#define LEDC_TICK_SEL_LSTIMER0_V 0x1 -#define LEDC_TICK_SEL_LSTIMER0_S 25 -/* LEDC_LSTIMER0_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ -/*description: This bit is used to reset low speed timer0 the counter will be 0 after reset.*/ -#define LEDC_LSTIMER0_RST (BIT(24)) -#define LEDC_LSTIMER0_RST_M (BIT(24)) -#define LEDC_LSTIMER0_RST_V 0x1 -#define LEDC_LSTIMER0_RST_S 24 -/* LEDC_LSTIMER0_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: This bit is used to pause the counter in low speed timer0.*/ -#define LEDC_LSTIMER0_PAUSE (BIT(23)) -#define LEDC_LSTIMER0_PAUSE_M (BIT(23)) -#define LEDC_LSTIMER0_PAUSE_V 0x1 -#define LEDC_LSTIMER0_PAUSE_S 23 -/* LEDC_DIV_NUM_LSTIMER0 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ -/*description: This register is used to configure parameter for divider in low - speed timer0 the least significant eight bits represent the decimal part.*/ -#define LEDC_DIV_NUM_LSTIMER0 0x0003FFFF -#define LEDC_DIV_NUM_LSTIMER0_M ((LEDC_DIV_NUM_LSTIMER0_V)<<(LEDC_DIV_NUM_LSTIMER0_S)) -#define LEDC_DIV_NUM_LSTIMER0_V 0x3FFFF -#define LEDC_DIV_NUM_LSTIMER0_S 5 -/* LEDC_LSTIMER0_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: This register controls the range of the counter in low speed - timer0. the counter range is [0 2**reg_lstimer0_lim] the max bit width for counter is 20.*/ -#define LEDC_LSTIMER0_LIM 0x0000001F -#define LEDC_LSTIMER0_LIM_M ((LEDC_LSTIMER0_LIM_V)<<(LEDC_LSTIMER0_LIM_S)) -#define LEDC_LSTIMER0_LIM_V 0x1F -#define LEDC_LSTIMER0_LIM_S 0 - -#define LEDC_LSTIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0x0164) -/* LEDC_LSTIMER0_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ -/*description: software can read this register to get the current counter value - in low speed timer0.*/ -#define LEDC_LSTIMER0_CNT 0x000FFFFF -#define LEDC_LSTIMER0_CNT_M ((LEDC_LSTIMER0_CNT_V)<<(LEDC_LSTIMER0_CNT_S)) -#define LEDC_LSTIMER0_CNT_V 0xFFFFF -#define LEDC_LSTIMER0_CNT_S 0 - -#define LEDC_LSTIMER1_CONF_REG (DR_REG_LEDC_BASE + 0x0168) -/* LEDC_LSTIMER1_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */ -/*description: Set this bit to update reg_div_num_lstime1 and reg_lstimer1_lim.*/ -#define LEDC_LSTIMER1_PARA_UP (BIT(26)) -#define LEDC_LSTIMER1_PARA_UP_M (BIT(26)) -#define LEDC_LSTIMER1_PARA_UP_V 0x1 -#define LEDC_LSTIMER1_PARA_UP_S 26 -/* LEDC_TICK_SEL_LSTIMER1 : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: This bit is used to choose slow_clk or ref_tick for low speed - timer1. 1'b1:slow_clk 0:ref_tick*/ -#define LEDC_TICK_SEL_LSTIMER1 (BIT(25)) -#define LEDC_TICK_SEL_LSTIMER1_M (BIT(25)) -#define LEDC_TICK_SEL_LSTIMER1_V 0x1 -#define LEDC_TICK_SEL_LSTIMER1_S 25 -/* LEDC_LSTIMER1_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ -/*description: This bit is used to reset low speed timer1 the counter will be 0 after reset.*/ -#define LEDC_LSTIMER1_RST (BIT(24)) -#define LEDC_LSTIMER1_RST_M (BIT(24)) -#define LEDC_LSTIMER1_RST_V 0x1 -#define LEDC_LSTIMER1_RST_S 24 -/* LEDC_LSTIMER1_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: This bit is used to pause the counter in low speed timer1.*/ -#define LEDC_LSTIMER1_PAUSE (BIT(23)) -#define LEDC_LSTIMER1_PAUSE_M (BIT(23)) -#define LEDC_LSTIMER1_PAUSE_V 0x1 -#define LEDC_LSTIMER1_PAUSE_S 23 -/* LEDC_DIV_NUM_LSTIMER1 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ -/*description: This register is used to configure parameter for divider in low - speed timer1 the least significant eight bits represent the decimal part.*/ -#define LEDC_DIV_NUM_LSTIMER1 0x0003FFFF -#define LEDC_DIV_NUM_LSTIMER1_M ((LEDC_DIV_NUM_LSTIMER1_V)<<(LEDC_DIV_NUM_LSTIMER1_S)) -#define LEDC_DIV_NUM_LSTIMER1_V 0x3FFFF -#define LEDC_DIV_NUM_LSTIMER1_S 5 -/* LEDC_LSTIMER1_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: This register controls the range of the counter in low speed - timer1. the counter range is [0 2**reg_lstimer1_lim] the max bit width for counter is 20.*/ -#define LEDC_LSTIMER1_LIM 0x0000001F -#define LEDC_LSTIMER1_LIM_M ((LEDC_LSTIMER1_LIM_V)<<(LEDC_LSTIMER1_LIM_S)) -#define LEDC_LSTIMER1_LIM_V 0x1F -#define LEDC_LSTIMER1_LIM_S 0 - -#define LEDC_LSTIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0x016C) -/* LEDC_LSTIMER1_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ -/*description: software can read this register to get the current counter value - in low speed timer1.*/ -#define LEDC_LSTIMER1_CNT 0x000FFFFF -#define LEDC_LSTIMER1_CNT_M ((LEDC_LSTIMER1_CNT_V)<<(LEDC_LSTIMER1_CNT_S)) -#define LEDC_LSTIMER1_CNT_V 0xFFFFF -#define LEDC_LSTIMER1_CNT_S 0 - -#define LEDC_LSTIMER2_CONF_REG (DR_REG_LEDC_BASE + 0x0170) -/* LEDC_LSTIMER2_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */ -/*description: Set this bit to update reg_div_num_lstime2 and reg_lstimer2_lim.*/ -#define LEDC_LSTIMER2_PARA_UP (BIT(26)) -#define LEDC_LSTIMER2_PARA_UP_M (BIT(26)) -#define LEDC_LSTIMER2_PARA_UP_V 0x1 -#define LEDC_LSTIMER2_PARA_UP_S 26 -/* LEDC_TICK_SEL_LSTIMER2 : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: This bit is used to choose slow_clk or ref_tick for low speed - timer2. 1'b1:slow_clk 0:ref_tick*/ -#define LEDC_TICK_SEL_LSTIMER2 (BIT(25)) -#define LEDC_TICK_SEL_LSTIMER2_M (BIT(25)) -#define LEDC_TICK_SEL_LSTIMER2_V 0x1 -#define LEDC_TICK_SEL_LSTIMER2_S 25 -/* LEDC_LSTIMER2_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ -/*description: This bit is used to reset low speed timer2 the counter will be 0 after reset.*/ -#define LEDC_LSTIMER2_RST (BIT(24)) -#define LEDC_LSTIMER2_RST_M (BIT(24)) -#define LEDC_LSTIMER2_RST_V 0x1 -#define LEDC_LSTIMER2_RST_S 24 -/* LEDC_LSTIMER2_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: This bit is used to pause the counter in low speed timer2.*/ -#define LEDC_LSTIMER2_PAUSE (BIT(23)) -#define LEDC_LSTIMER2_PAUSE_M (BIT(23)) -#define LEDC_LSTIMER2_PAUSE_V 0x1 -#define LEDC_LSTIMER2_PAUSE_S 23 -/* LEDC_DIV_NUM_LSTIMER2 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ -/*description: This register is used to configure parameter for divider in low - speed timer2 the least significant eight bits represent the decimal part.*/ -#define LEDC_DIV_NUM_LSTIMER2 0x0003FFFF -#define LEDC_DIV_NUM_LSTIMER2_M ((LEDC_DIV_NUM_LSTIMER2_V)<<(LEDC_DIV_NUM_LSTIMER2_S)) -#define LEDC_DIV_NUM_LSTIMER2_V 0x3FFFF -#define LEDC_DIV_NUM_LSTIMER2_S 5 -/* LEDC_LSTIMER2_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: This register controls the range of the counter in low speed - timer2. the counter range is [0 2**reg_lstimer2_lim] the max bit width for counter is 20.*/ -#define LEDC_LSTIMER2_LIM 0x0000001F -#define LEDC_LSTIMER2_LIM_M ((LEDC_LSTIMER2_LIM_V)<<(LEDC_LSTIMER2_LIM_S)) -#define LEDC_LSTIMER2_LIM_V 0x1F -#define LEDC_LSTIMER2_LIM_S 0 - -#define LEDC_LSTIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0x0174) -/* LEDC_LSTIMER2_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ -/*description: software can read this register to get the current counter value - in low speed timer2.*/ -#define LEDC_LSTIMER2_CNT 0x000FFFFF -#define LEDC_LSTIMER2_CNT_M ((LEDC_LSTIMER2_CNT_V)<<(LEDC_LSTIMER2_CNT_S)) -#define LEDC_LSTIMER2_CNT_V 0xFFFFF -#define LEDC_LSTIMER2_CNT_S 0 - -#define LEDC_LSTIMER3_CONF_REG (DR_REG_LEDC_BASE + 0x0178) -/* LEDC_LSTIMER3_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */ -/*description: Set this bit to update reg_div_num_lstime3 and reg_lstimer3_lim.*/ -#define LEDC_LSTIMER3_PARA_UP (BIT(26)) -#define LEDC_LSTIMER3_PARA_UP_M (BIT(26)) -#define LEDC_LSTIMER3_PARA_UP_V 0x1 -#define LEDC_LSTIMER3_PARA_UP_S 26 -/* LEDC_TICK_SEL_LSTIMER3 : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: This bit is used to choose slow_clk or ref_tick for low speed - timer3. 1'b1:slow_clk 0:ref_tick*/ -#define LEDC_TICK_SEL_LSTIMER3 (BIT(25)) -#define LEDC_TICK_SEL_LSTIMER3_M (BIT(25)) -#define LEDC_TICK_SEL_LSTIMER3_V 0x1 -#define LEDC_TICK_SEL_LSTIMER3_S 25 -/* LEDC_LSTIMER3_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ -/*description: This bit is used to reset low speed timer3 the counter will be 0 after reset.*/ -#define LEDC_LSTIMER3_RST (BIT(24)) -#define LEDC_LSTIMER3_RST_M (BIT(24)) -#define LEDC_LSTIMER3_RST_V 0x1 -#define LEDC_LSTIMER3_RST_S 24 -/* LEDC_LSTIMER3_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: This bit is used to pause the counter in low speed timer3.*/ -#define LEDC_LSTIMER3_PAUSE (BIT(23)) -#define LEDC_LSTIMER3_PAUSE_M (BIT(23)) -#define LEDC_LSTIMER3_PAUSE_V 0x1 -#define LEDC_LSTIMER3_PAUSE_S 23 -/* LEDC_DIV_NUM_LSTIMER3 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ -/*description: This register is used to configure parameter for divider in low - speed timer3 the least significant eight bits represent the decimal part.*/ -#define LEDC_DIV_NUM_LSTIMER3 0x0003FFFF -#define LEDC_DIV_NUM_LSTIMER3_M ((LEDC_DIV_NUM_LSTIMER3_V)<<(LEDC_DIV_NUM_LSTIMER3_S)) -#define LEDC_DIV_NUM_LSTIMER3_V 0x3FFFF -#define LEDC_DIV_NUM_LSTIMER3_S 5 -/* LEDC_LSTIMER3_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: This register controls the range of the counter in low speed - timer3. the counter range is [0 2**reg_lstimer3_lim] the max bit width for counter is 20.*/ -#define LEDC_LSTIMER3_LIM 0x0000001F -#define LEDC_LSTIMER3_LIM_M ((LEDC_LSTIMER3_LIM_V)<<(LEDC_LSTIMER3_LIM_S)) -#define LEDC_LSTIMER3_LIM_V 0x1F -#define LEDC_LSTIMER3_LIM_S 0 - -#define LEDC_LSTIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0x017C) -/* LEDC_LSTIMER3_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ -/*description: software can read this register to get the current counter value - in low speed timer3.*/ -#define LEDC_LSTIMER3_CNT 0x000FFFFF -#define LEDC_LSTIMER3_CNT_M ((LEDC_LSTIMER3_CNT_V)<<(LEDC_LSTIMER3_CNT_S)) -#define LEDC_LSTIMER3_CNT_V 0xFFFFF -#define LEDC_LSTIMER3_CNT_S 0 - -#define LEDC_INT_RAW_REG (DR_REG_LEDC_BASE + 0x0180) -/* LEDC_DUTY_CHNG_END_LSCH7_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for low speed channel 7 duty change done.*/ -#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW (BIT(23)) -#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_M (BIT(23)) -#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_S 23 -/* LEDC_DUTY_CHNG_END_LSCH6_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for low speed channel 6 duty change done.*/ -#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW (BIT(22)) -#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_M (BIT(22)) -#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_S 22 -/* LEDC_DUTY_CHNG_END_LSCH5_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for low speed channel 5 duty change done.*/ -#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW (BIT(21)) -#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_M (BIT(21)) -#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_S 21 -/* LEDC_DUTY_CHNG_END_LSCH4_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for low speed channel 4 duty change done.*/ -#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW (BIT(20)) -#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_M (BIT(20)) -#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_S 20 -/* LEDC_DUTY_CHNG_END_LSCH3_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for low speed channel 3 duty change done.*/ -#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW (BIT(19)) -#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_M (BIT(19)) -#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_S 19 -/* LEDC_DUTY_CHNG_END_LSCH2_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for low speed channel 2 duty change done.*/ -#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW (BIT(18)) -#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_M (BIT(18)) -#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_S 18 -/* LEDC_DUTY_CHNG_END_LSCH1_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for low speed channel 1 duty change done.*/ -#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW (BIT(17)) -#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_M (BIT(17)) -#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_S 17 -/* LEDC_DUTY_CHNG_END_LSCH0_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for low speed channel 0 duty change done.*/ -#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW (BIT(16)) -#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_M (BIT(16)) -#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_S 16 -/* LEDC_DUTY_CHNG_END_HSCH7_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for high speed channel 7 duty change done.*/ -#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW (BIT(15)) -#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_M (BIT(15)) -#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_S 15 -/* LEDC_DUTY_CHNG_END_HSCH6_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for high speed channel 6 duty change done.*/ -#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW (BIT(14)) -#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_M (BIT(14)) -#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_S 14 -/* LEDC_DUTY_CHNG_END_HSCH5_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for high speed channel 5 duty change done.*/ -#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW (BIT(13)) -#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_M (BIT(13)) -#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_S 13 -/* LEDC_DUTY_CHNG_END_HSCH4_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for high speed channel 4 duty change done.*/ -#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW (BIT(12)) -#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_M (BIT(12)) -#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_S 12 -/* LEDC_DUTY_CHNG_END_HSCH3_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for high speed channel 3 duty change done.*/ -#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW (BIT(11)) -#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_M (BIT(11)) -#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_S 11 -/* LEDC_DUTY_CHNG_END_HSCH2_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for high speed channel 2 duty change done.*/ -#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW (BIT(10)) -#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_M (BIT(10)) -#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_S 10 -/* LEDC_DUTY_CHNG_END_HSCH1_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for high speed channel 1 duty change done.*/ -#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW (BIT(9)) -#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_M (BIT(9)) -#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_S 9 -/* LEDC_DUTY_CHNG_END_HSCH0_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for high speed channel 0 duty change done.*/ -#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW (BIT(8)) -#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_M (BIT(8)) -#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_S 8 -/* LEDC_LSTIMER3_OVF_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for low speed channel3 counter overflow.*/ -#define LEDC_LSTIMER3_OVF_INT_RAW (BIT(7)) -#define LEDC_LSTIMER3_OVF_INT_RAW_M (BIT(7)) -#define LEDC_LSTIMER3_OVF_INT_RAW_V 0x1 -#define LEDC_LSTIMER3_OVF_INT_RAW_S 7 -/* LEDC_LSTIMER2_OVF_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for low speed channel2 counter overflow.*/ -#define LEDC_LSTIMER2_OVF_INT_RAW (BIT(6)) -#define LEDC_LSTIMER2_OVF_INT_RAW_M (BIT(6)) -#define LEDC_LSTIMER2_OVF_INT_RAW_V 0x1 -#define LEDC_LSTIMER2_OVF_INT_RAW_S 6 -/* LEDC_LSTIMER1_OVF_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for low speed channel1 counter overflow.*/ -#define LEDC_LSTIMER1_OVF_INT_RAW (BIT(5)) -#define LEDC_LSTIMER1_OVF_INT_RAW_M (BIT(5)) -#define LEDC_LSTIMER1_OVF_INT_RAW_V 0x1 -#define LEDC_LSTIMER1_OVF_INT_RAW_S 5 -/* LEDC_LSTIMER0_OVF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for low speed channel0 counter overflow.*/ -#define LEDC_LSTIMER0_OVF_INT_RAW (BIT(4)) -#define LEDC_LSTIMER0_OVF_INT_RAW_M (BIT(4)) -#define LEDC_LSTIMER0_OVF_INT_RAW_V 0x1 -#define LEDC_LSTIMER0_OVF_INT_RAW_S 4 -/* LEDC_HSTIMER3_OVF_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for high speed channel3 counter overflow.*/ -#define LEDC_HSTIMER3_OVF_INT_RAW (BIT(3)) -#define LEDC_HSTIMER3_OVF_INT_RAW_M (BIT(3)) -#define LEDC_HSTIMER3_OVF_INT_RAW_V 0x1 -#define LEDC_HSTIMER3_OVF_INT_RAW_S 3 -/* LEDC_HSTIMER2_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for high speed channel2 counter overflow.*/ -#define LEDC_HSTIMER2_OVF_INT_RAW (BIT(2)) -#define LEDC_HSTIMER2_OVF_INT_RAW_M (BIT(2)) -#define LEDC_HSTIMER2_OVF_INT_RAW_V 0x1 -#define LEDC_HSTIMER2_OVF_INT_RAW_S 2 -/* LEDC_HSTIMER1_OVF_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for high speed channel1 counter overflow.*/ -#define LEDC_HSTIMER1_OVF_INT_RAW (BIT(1)) -#define LEDC_HSTIMER1_OVF_INT_RAW_M (BIT(1)) -#define LEDC_HSTIMER1_OVF_INT_RAW_V 0x1 -#define LEDC_HSTIMER1_OVF_INT_RAW_S 1 -/* LEDC_HSTIMER0_OVF_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for high speed channel0 counter overflow.*/ -#define LEDC_HSTIMER0_OVF_INT_RAW (BIT(0)) -#define LEDC_HSTIMER0_OVF_INT_RAW_M (BIT(0)) -#define LEDC_HSTIMER0_OVF_INT_RAW_V 0x1 -#define LEDC_HSTIMER0_OVF_INT_RAW_S 0 - -#define LEDC_INT_ST_REG (DR_REG_LEDC_BASE + 0x0184) -/* LEDC_DUTY_CHNG_END_LSCH7_INT_ST : RO ;bitpos:[23] ;default: 1'h0 ; */ -/*description: The interrupt status bit for low speed channel 7 duty change done event*/ -#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST (BIT(23)) -#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_M (BIT(23)) -#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_S 23 -/* LEDC_DUTY_CHNG_END_LSCH6_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: The interrupt status bit for low speed channel 6 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST (BIT(22)) -#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_M (BIT(22)) -#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_S 22 -/* LEDC_DUTY_CHNG_END_LSCH5_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: The interrupt status bit for low speed channel 5 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST (BIT(21)) -#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_M (BIT(21)) -#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_S 21 -/* LEDC_DUTY_CHNG_END_LSCH4_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: The interrupt status bit for low speed channel 4 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST (BIT(20)) -#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_M (BIT(20)) -#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_S 20 -/* LEDC_DUTY_CHNG_END_LSCH3_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: The interrupt status bit for low speed channel 3 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST (BIT(19)) -#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_M (BIT(19)) -#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_S 19 -/* LEDC_DUTY_CHNG_END_LSCH2_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: The interrupt status bit for low speed channel 2 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST (BIT(18)) -#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_M (BIT(18)) -#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_S 18 -/* LEDC_DUTY_CHNG_END_LSCH1_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: The interrupt status bit for low speed channel 1 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST (BIT(17)) -#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_M (BIT(17)) -#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_S 17 -/* LEDC_DUTY_CHNG_END_LSCH0_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: The interrupt status bit for low speed channel 0 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST (BIT(16)) -#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_M (BIT(16)) -#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_S 16 -/* LEDC_DUTY_CHNG_END_HSCH7_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: The interrupt status bit for high speed channel 7 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST (BIT(15)) -#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_M (BIT(15)) -#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_S 15 -/* LEDC_DUTY_CHNG_END_HSCH6_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: The interrupt status bit for high speed channel 6 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST (BIT(14)) -#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_M (BIT(14)) -#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_S 14 -/* LEDC_DUTY_CHNG_END_HSCH5_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The interrupt status bit for high speed channel 5 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST (BIT(13)) -#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_M (BIT(13)) -#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_S 13 -/* LEDC_DUTY_CHNG_END_HSCH4_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The interrupt status bit for high speed channel 4 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST (BIT(12)) -#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_M (BIT(12)) -#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_S 12 -/* LEDC_DUTY_CHNG_END_HSCH3_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The interrupt status bit for high speed channel 3 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST (BIT(11)) -#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_M (BIT(11)) -#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_S 11 -/* LEDC_DUTY_CHNG_END_HSCH2_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The interrupt status bit for high speed channel 2 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST (BIT(10)) -#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_M (BIT(10)) -#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_S 10 -/* LEDC_DUTY_CHNG_END_HSCH1_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The interrupt status bit for high speed channel 1 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST (BIT(9)) -#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_M (BIT(9)) -#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_S 9 -/* LEDC_DUTY_CHNG_END_HSCH0_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The interrupt status bit for high speed channel 0 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST (BIT(8)) -#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_M (BIT(8)) -#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_S 8 -/* LEDC_LSTIMER3_OVF_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The interrupt status bit for low speed channel3 counter overflow event.*/ -#define LEDC_LSTIMER3_OVF_INT_ST (BIT(7)) -#define LEDC_LSTIMER3_OVF_INT_ST_M (BIT(7)) -#define LEDC_LSTIMER3_OVF_INT_ST_V 0x1 -#define LEDC_LSTIMER3_OVF_INT_ST_S 7 -/* LEDC_LSTIMER2_OVF_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The interrupt status bit for low speed channel2 counter overflow event.*/ -#define LEDC_LSTIMER2_OVF_INT_ST (BIT(6)) -#define LEDC_LSTIMER2_OVF_INT_ST_M (BIT(6)) -#define LEDC_LSTIMER2_OVF_INT_ST_V 0x1 -#define LEDC_LSTIMER2_OVF_INT_ST_S 6 -/* LEDC_LSTIMER1_OVF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The interrupt status bit for low speed channel1 counter overflow event.*/ -#define LEDC_LSTIMER1_OVF_INT_ST (BIT(5)) -#define LEDC_LSTIMER1_OVF_INT_ST_M (BIT(5)) -#define LEDC_LSTIMER1_OVF_INT_ST_V 0x1 -#define LEDC_LSTIMER1_OVF_INT_ST_S 5 -/* LEDC_LSTIMER0_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The interrupt status bit for low speed channel0 counter overflow event.*/ -#define LEDC_LSTIMER0_OVF_INT_ST (BIT(4)) -#define LEDC_LSTIMER0_OVF_INT_ST_M (BIT(4)) -#define LEDC_LSTIMER0_OVF_INT_ST_V 0x1 -#define LEDC_LSTIMER0_OVF_INT_ST_S 4 -/* LEDC_HSTIMER3_OVF_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The interrupt status bit for high speed channel3 counter overflow event.*/ -#define LEDC_HSTIMER3_OVF_INT_ST (BIT(3)) -#define LEDC_HSTIMER3_OVF_INT_ST_M (BIT(3)) -#define LEDC_HSTIMER3_OVF_INT_ST_V 0x1 -#define LEDC_HSTIMER3_OVF_INT_ST_S 3 -/* LEDC_HSTIMER2_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The interrupt status bit for high speed channel2 counter overflow event.*/ -#define LEDC_HSTIMER2_OVF_INT_ST (BIT(2)) -#define LEDC_HSTIMER2_OVF_INT_ST_M (BIT(2)) -#define LEDC_HSTIMER2_OVF_INT_ST_V 0x1 -#define LEDC_HSTIMER2_OVF_INT_ST_S 2 -/* LEDC_HSTIMER1_OVF_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The interrupt status bit for high speed channel1 counter overflow event.*/ -#define LEDC_HSTIMER1_OVF_INT_ST (BIT(1)) -#define LEDC_HSTIMER1_OVF_INT_ST_M (BIT(1)) -#define LEDC_HSTIMER1_OVF_INT_ST_V 0x1 -#define LEDC_HSTIMER1_OVF_INT_ST_S 1 -/* LEDC_HSTIMER0_OVF_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The interrupt status bit for high speed channel0 counter overflow event.*/ -#define LEDC_HSTIMER0_OVF_INT_ST (BIT(0)) -#define LEDC_HSTIMER0_OVF_INT_ST_M (BIT(0)) -#define LEDC_HSTIMER0_OVF_INT_ST_V 0x1 -#define LEDC_HSTIMER0_OVF_INT_ST_S 0 - -#define LEDC_INT_ENA_REG (DR_REG_LEDC_BASE + 0x0188) -/* LEDC_DUTY_CHNG_END_LSCH7_INT_ENA : R/W ;bitpos:[23] ;default: 1'h0 ; */ -/*description: The interrupt enable bit for low speed channel 7 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA (BIT(23)) -#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_M (BIT(23)) -#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_S 23 -/* LEDC_DUTY_CHNG_END_LSCH6_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for low speed channel 6 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA (BIT(22)) -#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_M (BIT(22)) -#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_S 22 -/* LEDC_DUTY_CHNG_END_LSCH5_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for low speed channel 5 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA (BIT(21)) -#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_M (BIT(21)) -#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_S 21 -/* LEDC_DUTY_CHNG_END_LSCH4_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for low speed channel 4 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA (BIT(20)) -#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_M (BIT(20)) -#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_S 20 -/* LEDC_DUTY_CHNG_END_LSCH3_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for low speed channel 3 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA (BIT(19)) -#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_M (BIT(19)) -#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_S 19 -/* LEDC_DUTY_CHNG_END_LSCH2_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for low speed channel 2 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA (BIT(18)) -#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_M (BIT(18)) -#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_S 18 -/* LEDC_DUTY_CHNG_END_LSCH1_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for low speed channel 1 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA (BIT(17)) -#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_M (BIT(17)) -#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_S 17 -/* LEDC_DUTY_CHNG_END_LSCH0_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for low speed channel 0 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA (BIT(16)) -#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_M (BIT(16)) -#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S 16 -/* LEDC_DUTY_CHNG_END_HSCH7_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for high speed channel 7 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA (BIT(15)) -#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_M (BIT(15)) -#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_S 15 -/* LEDC_DUTY_CHNG_END_HSCH6_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for high speed channel 6 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA (BIT(14)) -#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_M (BIT(14)) -#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_S 14 -/* LEDC_DUTY_CHNG_END_HSCH5_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for high speed channel 5 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA (BIT(13)) -#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_M (BIT(13)) -#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_S 13 -/* LEDC_DUTY_CHNG_END_HSCH4_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for high speed channel 4 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA (BIT(12)) -#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_M (BIT(12)) -#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_S 12 -/* LEDC_DUTY_CHNG_END_HSCH3_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for high speed channel 3 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA (BIT(11)) -#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_M (BIT(11)) -#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_S 11 -/* LEDC_DUTY_CHNG_END_HSCH2_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for high speed channel 2 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA (BIT(10)) -#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_M (BIT(10)) -#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_S 10 -/* LEDC_DUTY_CHNG_END_HSCH1_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for high speed channel 1 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA (BIT(9)) -#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_M (BIT(9)) -#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_S 9 -/* LEDC_DUTY_CHNG_END_HSCH0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for high speed channel 0 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA (BIT(8)) -#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_M (BIT(8)) -#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_S 8 -/* LEDC_LSTIMER3_OVF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for low speed channel3 counter overflow interrupt.*/ -#define LEDC_LSTIMER3_OVF_INT_ENA (BIT(7)) -#define LEDC_LSTIMER3_OVF_INT_ENA_M (BIT(7)) -#define LEDC_LSTIMER3_OVF_INT_ENA_V 0x1 -#define LEDC_LSTIMER3_OVF_INT_ENA_S 7 -/* LEDC_LSTIMER2_OVF_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for low speed channel2 counter overflow interrupt.*/ -#define LEDC_LSTIMER2_OVF_INT_ENA (BIT(6)) -#define LEDC_LSTIMER2_OVF_INT_ENA_M (BIT(6)) -#define LEDC_LSTIMER2_OVF_INT_ENA_V 0x1 -#define LEDC_LSTIMER2_OVF_INT_ENA_S 6 -/* LEDC_LSTIMER1_OVF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for low speed channel1 counter overflow interrupt.*/ -#define LEDC_LSTIMER1_OVF_INT_ENA (BIT(5)) -#define LEDC_LSTIMER1_OVF_INT_ENA_M (BIT(5)) -#define LEDC_LSTIMER1_OVF_INT_ENA_V 0x1 -#define LEDC_LSTIMER1_OVF_INT_ENA_S 5 -/* LEDC_LSTIMER0_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for low speed channel0 counter overflow interrupt.*/ -#define LEDC_LSTIMER0_OVF_INT_ENA (BIT(4)) -#define LEDC_LSTIMER0_OVF_INT_ENA_M (BIT(4)) -#define LEDC_LSTIMER0_OVF_INT_ENA_V 0x1 -#define LEDC_LSTIMER0_OVF_INT_ENA_S 4 -/* LEDC_HSTIMER3_OVF_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for high speed channel3 counter overflow interrupt.*/ -#define LEDC_HSTIMER3_OVF_INT_ENA (BIT(3)) -#define LEDC_HSTIMER3_OVF_INT_ENA_M (BIT(3)) -#define LEDC_HSTIMER3_OVF_INT_ENA_V 0x1 -#define LEDC_HSTIMER3_OVF_INT_ENA_S 3 -/* LEDC_HSTIMER2_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for high speed channel2 counter overflow interrupt.*/ -#define LEDC_HSTIMER2_OVF_INT_ENA (BIT(2)) -#define LEDC_HSTIMER2_OVF_INT_ENA_M (BIT(2)) -#define LEDC_HSTIMER2_OVF_INT_ENA_V 0x1 -#define LEDC_HSTIMER2_OVF_INT_ENA_S 2 -/* LEDC_HSTIMER1_OVF_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for high speed channel1 counter overflow interrupt.*/ -#define LEDC_HSTIMER1_OVF_INT_ENA (BIT(1)) -#define LEDC_HSTIMER1_OVF_INT_ENA_M (BIT(1)) -#define LEDC_HSTIMER1_OVF_INT_ENA_V 0x1 -#define LEDC_HSTIMER1_OVF_INT_ENA_S 1 -/* LEDC_HSTIMER0_OVF_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for high speed channel0 counter overflow interrupt.*/ -#define LEDC_HSTIMER0_OVF_INT_ENA (BIT(0)) -#define LEDC_HSTIMER0_OVF_INT_ENA_M (BIT(0)) -#define LEDC_HSTIMER0_OVF_INT_ENA_V 0x1 -#define LEDC_HSTIMER0_OVF_INT_ENA_S 0 - -#define LEDC_INT_CLR_REG (DR_REG_LEDC_BASE + 0x018C) -/* LEDC_DUTY_CHNG_END_LSCH7_INT_CLR : WO ;bitpos:[23] ;default: 1'h0 ; */ -/*description: Set this bit to clear low speed channel 7 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR (BIT(23)) -#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_M (BIT(23)) -#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_S 23 -/* LEDC_DUTY_CHNG_END_LSCH6_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: Set this bit to clear low speed channel 6 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR (BIT(22)) -#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_M (BIT(22)) -#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_S 22 -/* LEDC_DUTY_CHNG_END_LSCH5_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Set this bit to clear low speed channel 5 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR (BIT(21)) -#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_M (BIT(21)) -#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_S 21 -/* LEDC_DUTY_CHNG_END_LSCH4_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: Set this bit to clear low speed channel 4 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR (BIT(20)) -#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_M (BIT(20)) -#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_S 20 -/* LEDC_DUTY_CHNG_END_LSCH3_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: Set this bit to clear low speed channel 3 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR (BIT(19)) -#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_M (BIT(19)) -#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_S 19 -/* LEDC_DUTY_CHNG_END_LSCH2_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: Set this bit to clear low speed channel 2 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR (BIT(18)) -#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_M (BIT(18)) -#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_S 18 -/* LEDC_DUTY_CHNG_END_LSCH1_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: Set this bit to clear low speed channel 1 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR (BIT(17)) -#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_M (BIT(17)) -#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_S 17 -/* LEDC_DUTY_CHNG_END_LSCH0_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: Set this bit to clear low speed channel 0 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR (BIT(16)) -#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_M (BIT(16)) -#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_S 16 -/* LEDC_DUTY_CHNG_END_HSCH7_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: Set this bit to clear high speed channel 7 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR (BIT(15)) -#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_M (BIT(15)) -#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_S 15 -/* LEDC_DUTY_CHNG_END_HSCH6_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Set this bit to clear high speed channel 6 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR (BIT(14)) -#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_M (BIT(14)) -#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_S 14 -/* LEDC_DUTY_CHNG_END_HSCH5_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Set this bit to clear high speed channel 5 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR (BIT(13)) -#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_M (BIT(13)) -#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_S 13 -/* LEDC_DUTY_CHNG_END_HSCH4_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to clear high speed channel 4 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR (BIT(12)) -#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_M (BIT(12)) -#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_S 12 -/* LEDC_DUTY_CHNG_END_HSCH3_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Set this bit to clear high speed channel 3 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR (BIT(11)) -#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_M (BIT(11)) -#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_S 11 -/* LEDC_DUTY_CHNG_END_HSCH2_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit to clear high speed channel 2 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR (BIT(10)) -#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_M (BIT(10)) -#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_S 10 -/* LEDC_DUTY_CHNG_END_HSCH1_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to clear high speed channel 1 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR (BIT(9)) -#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_M (BIT(9)) -#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_S 9 -/* LEDC_DUTY_CHNG_END_HSCH0_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to clear high speed channel 0 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR (BIT(8)) -#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_M (BIT(8)) -#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_S 8 -/* LEDC_LSTIMER3_OVF_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to clear low speed channel3 counter overflow interrupt.*/ -#define LEDC_LSTIMER3_OVF_INT_CLR (BIT(7)) -#define LEDC_LSTIMER3_OVF_INT_CLR_M (BIT(7)) -#define LEDC_LSTIMER3_OVF_INT_CLR_V 0x1 -#define LEDC_LSTIMER3_OVF_INT_CLR_S 7 -/* LEDC_LSTIMER2_OVF_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to clear low speed channel2 counter overflow interrupt.*/ -#define LEDC_LSTIMER2_OVF_INT_CLR (BIT(6)) -#define LEDC_LSTIMER2_OVF_INT_CLR_M (BIT(6)) -#define LEDC_LSTIMER2_OVF_INT_CLR_V 0x1 -#define LEDC_LSTIMER2_OVF_INT_CLR_S 6 -/* LEDC_LSTIMER1_OVF_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to clear low speed channel1 counter overflow interrupt.*/ -#define LEDC_LSTIMER1_OVF_INT_CLR (BIT(5)) -#define LEDC_LSTIMER1_OVF_INT_CLR_M (BIT(5)) -#define LEDC_LSTIMER1_OVF_INT_CLR_V 0x1 -#define LEDC_LSTIMER1_OVF_INT_CLR_S 5 -/* LEDC_LSTIMER0_OVF_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to clear low speed channel0 counter overflow interrupt.*/ -#define LEDC_LSTIMER0_OVF_INT_CLR (BIT(4)) -#define LEDC_LSTIMER0_OVF_INT_CLR_M (BIT(4)) -#define LEDC_LSTIMER0_OVF_INT_CLR_V 0x1 -#define LEDC_LSTIMER0_OVF_INT_CLR_S 4 -/* LEDC_HSTIMER3_OVF_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to clear high speed channel3 counter overflow interrupt.*/ -#define LEDC_HSTIMER3_OVF_INT_CLR (BIT(3)) -#define LEDC_HSTIMER3_OVF_INT_CLR_M (BIT(3)) -#define LEDC_HSTIMER3_OVF_INT_CLR_V 0x1 -#define LEDC_HSTIMER3_OVF_INT_CLR_S 3 -/* LEDC_HSTIMER2_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to clear high speed channel2 counter overflow interrupt.*/ -#define LEDC_HSTIMER2_OVF_INT_CLR (BIT(2)) -#define LEDC_HSTIMER2_OVF_INT_CLR_M (BIT(2)) -#define LEDC_HSTIMER2_OVF_INT_CLR_V 0x1 -#define LEDC_HSTIMER2_OVF_INT_CLR_S 2 -/* LEDC_HSTIMER1_OVF_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to clear high speed channel1 counter overflow interrupt.*/ -#define LEDC_HSTIMER1_OVF_INT_CLR (BIT(1)) -#define LEDC_HSTIMER1_OVF_INT_CLR_M (BIT(1)) -#define LEDC_HSTIMER1_OVF_INT_CLR_V 0x1 -#define LEDC_HSTIMER1_OVF_INT_CLR_S 1 -/* LEDC_HSTIMER0_OVF_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to clear high speed channel0 counter overflow interrupt.*/ -#define LEDC_HSTIMER0_OVF_INT_CLR (BIT(0)) -#define LEDC_HSTIMER0_OVF_INT_CLR_M (BIT(0)) -#define LEDC_HSTIMER0_OVF_INT_CLR_V 0x1 -#define LEDC_HSTIMER0_OVF_INT_CLR_S 0 - -#define LEDC_CONF_REG (DR_REG_LEDC_BASE + 0x0190) -/* LEDC_APB_CLK_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit is used to set the frequency of slow_clk. 1'b1:80mhz 1'b0:8mhz*/ -#define LEDC_APB_CLK_SEL (BIT(0)) -#define LEDC_APB_CLK_SEL_M (BIT(0)) -#define LEDC_APB_CLK_SEL_V 0x1 -#define LEDC_APB_CLK_SEL_S 0 - -#define LEDC_DATE_REG (DR_REG_LEDC_BASE + 0x01FC) -/* LEDC_DATE : R/W ;bitpos:[31:0] ;default: 32'h16031700 ; */ -/*description: This register represents the version .*/ -#define LEDC_DATE 0xFFFFFFFF -#define LEDC_DATE_M ((LEDC_DATE_V)<<(LEDC_DATE_S)) -#define LEDC_DATE_V 0xFFFFFFFF -#define LEDC_DATE_S 0 - - - - -#endif /*_SOC_LEDC_REG_H_ */ - - +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_LEDC_REG_H_ +#define _SOC_LEDC_REG_H_ + + +#include "soc.h" +#define LEDC_HSCH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0000) +/* LEDC_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: This bit is clock gating control signal. when software config + LED_PWM internal registers it controls the register clock.*/ +#define LEDC_CLK_EN (BIT(31)) +#define LEDC_CLK_EN_M (BIT(31)) +#define LEDC_CLK_EN_V 0x1 +#define LEDC_CLK_EN_S 31 +/* LEDC_IDLE_LV_HSCH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when high speed channel0 is off.*/ +#define LEDC_IDLE_LV_HSCH0 (BIT(3)) +#define LEDC_IDLE_LV_HSCH0_M (BIT(3)) +#define LEDC_IDLE_LV_HSCH0_V 0x1 +#define LEDC_IDLE_LV_HSCH0_S 3 +/* LEDC_SIG_OUT_EN_HSCH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for high speed channel0*/ +#define LEDC_SIG_OUT_EN_HSCH0 (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH0_M (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH0_V 0x1 +#define LEDC_SIG_OUT_EN_HSCH0_S 2 +/* LEDC_TIMER_SEL_HSCH0 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four high speed timers the two bits are used to select + one of them for high speed channel0. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ +#define LEDC_TIMER_SEL_HSCH0 0x00000003 +#define LEDC_TIMER_SEL_HSCH0_M ((LEDC_TIMER_SEL_HSCH0_V)<<(LEDC_TIMER_SEL_HSCH0_S)) +#define LEDC_TIMER_SEL_HSCH0_V 0x3 +#define LEDC_TIMER_SEL_HSCH0_S 0 + +#define LEDC_HSCH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x0004) +/* LEDC_HPOINT_HSCH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when htimerx(x=[0 3]) selected + by high speed channel0 has reached reg_hpoint_hsch0[19:0]*/ +#define LEDC_HPOINT_HSCH0 0x000FFFFF +#define LEDC_HPOINT_HSCH0_M ((LEDC_HPOINT_HSCH0_V)<<(LEDC_HPOINT_HSCH0_S)) +#define LEDC_HPOINT_HSCH0_V 0xFFFFF +#define LEDC_HPOINT_HSCH0_S 0 + +#define LEDC_HSCH0_DUTY_REG (DR_REG_LEDC_BASE + 0x0008) +/* LEDC_DUTY_HSCH0 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When hstimerx(x=[0 + 3]) choosed by high speed channel0 has reached reg_lpoint_hsch0 the output signal changes to low. reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4]) (1) reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_HSCH0 0x01FFFFFF +#define LEDC_DUTY_HSCH0_M ((LEDC_DUTY_HSCH0_V)<<(LEDC_DUTY_HSCH0_S)) +#define LEDC_DUTY_HSCH0_V 0x1FFFFFF +#define LEDC_DUTY_HSCH0_S 0 + +#define LEDC_HSCH0_CONF1_REG (DR_REG_LEDC_BASE + 0x000C) +/* LEDC_DUTY_START_HSCH0 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch0 reg_duty_cycle_hsch0 and reg_duty_scale_hsch0 + has been configured. these register won't take effect until set reg_duty_start_hsch0. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_HSCH0 (BIT(31)) +#define LEDC_DUTY_START_HSCH0_M (BIT(31)) +#define LEDC_DUTY_START_HSCH0_V 0x1 +#define LEDC_DUTY_START_HSCH0_S 31 +/* LEDC_DUTY_INC_HSCH0 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for high speed channel0.*/ +#define LEDC_DUTY_INC_HSCH0 (BIT(30)) +#define LEDC_DUTY_INC_HSCH0_M (BIT(30)) +#define LEDC_DUTY_INC_HSCH0_V 0x1 +#define LEDC_DUTY_INC_HSCH0_S 30 +/* LEDC_DUTY_NUM_HSCH0 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for high speed channel0.*/ +#define LEDC_DUTY_NUM_HSCH0 0x000003FF +#define LEDC_DUTY_NUM_HSCH0_M ((LEDC_DUTY_NUM_HSCH0_V)<<(LEDC_DUTY_NUM_HSCH0_S)) +#define LEDC_DUTY_NUM_HSCH0_V 0x3FF +#define LEDC_DUTY_NUM_HSCH0_S 20 +/* LEDC_DUTY_CYCLE_HSCH0 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_hsch0 cycles for high speed channel0.*/ +#define LEDC_DUTY_CYCLE_HSCH0 0x000003FF +#define LEDC_DUTY_CYCLE_HSCH0_M ((LEDC_DUTY_CYCLE_HSCH0_V)<<(LEDC_DUTY_CYCLE_HSCH0_S)) +#define LEDC_DUTY_CYCLE_HSCH0_V 0x3FF +#define LEDC_DUTY_CYCLE_HSCH0_S 10 +/* LEDC_DUTY_SCALE_HSCH0 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + high speed channel0.*/ +#define LEDC_DUTY_SCALE_HSCH0 0x000003FF +#define LEDC_DUTY_SCALE_HSCH0_M ((LEDC_DUTY_SCALE_HSCH0_V)<<(LEDC_DUTY_SCALE_HSCH0_S)) +#define LEDC_DUTY_SCALE_HSCH0_V 0x3FF +#define LEDC_DUTY_SCALE_HSCH0_S 0 + +#define LEDC_HSCH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0010) +/* LEDC_DUTY_HSCH0 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for high speed channel0.*/ +#define LEDC_DUTY_HSCH0 0x01FFFFFF +#define LEDC_DUTY_HSCH0_M ((LEDC_DUTY_HSCH0_V)<<(LEDC_DUTY_HSCH0_S)) +#define LEDC_DUTY_HSCH0_V 0x1FFFFFF +#define LEDC_DUTY_HSCH0_S 0 + +#define LEDC_HSCH1_CONF0_REG (DR_REG_LEDC_BASE + 0x0014) +/* LEDC_IDLE_LV_HSCH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when high speed channel1 is off.*/ +#define LEDC_IDLE_LV_HSCH1 (BIT(3)) +#define LEDC_IDLE_LV_HSCH1_M (BIT(3)) +#define LEDC_IDLE_LV_HSCH1_V 0x1 +#define LEDC_IDLE_LV_HSCH1_S 3 +/* LEDC_SIG_OUT_EN_HSCH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for high speed channel1*/ +#define LEDC_SIG_OUT_EN_HSCH1 (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH1_M (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH1_V 0x1 +#define LEDC_SIG_OUT_EN_HSCH1_S 2 +/* LEDC_TIMER_SEL_HSCH1 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four high speed timers the two bits are used to select + one of them for high speed channel1. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ +#define LEDC_TIMER_SEL_HSCH1 0x00000003 +#define LEDC_TIMER_SEL_HSCH1_M ((LEDC_TIMER_SEL_HSCH1_V)<<(LEDC_TIMER_SEL_HSCH1_S)) +#define LEDC_TIMER_SEL_HSCH1_V 0x3 +#define LEDC_TIMER_SEL_HSCH1_S 0 + +#define LEDC_HSCH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x0018) +/* LEDC_HPOINT_HSCH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when htimerx(x=[0 3]) selected + by high speed channel1 has reached reg_hpoint_hsch1[19:0]*/ +#define LEDC_HPOINT_HSCH1 0x000FFFFF +#define LEDC_HPOINT_HSCH1_M ((LEDC_HPOINT_HSCH1_V)<<(LEDC_HPOINT_HSCH1_S)) +#define LEDC_HPOINT_HSCH1_V 0xFFFFF +#define LEDC_HPOINT_HSCH1_S 0 + +#define LEDC_HSCH1_DUTY_REG (DR_REG_LEDC_BASE + 0x001C) +/* LEDC_DUTY_HSCH1 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When hstimerx(x=[0 + 3]) choosed by high speed channel1 has reached reg_lpoint_hsch1 the output signal changes to low. reg_lpoint_hsch1=(reg_hpoint_hsch1[19:0]+reg_duty_hsch1[24:4]) (1) reg_lpoint_hsch1=(reg_hpoint_hsch1[19:0]+reg_duty_hsch1[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_HSCH1 0x01FFFFFF +#define LEDC_DUTY_HSCH1_M ((LEDC_DUTY_HSCH1_V)<<(LEDC_DUTY_HSCH1_S)) +#define LEDC_DUTY_HSCH1_V 0x1FFFFFF +#define LEDC_DUTY_HSCH1_S 0 + +#define LEDC_HSCH1_CONF1_REG (DR_REG_LEDC_BASE + 0x0020) +/* LEDC_DUTY_START_HSCH1 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 + has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_HSCH1 (BIT(31)) +#define LEDC_DUTY_START_HSCH1_M (BIT(31)) +#define LEDC_DUTY_START_HSCH1_V 0x1 +#define LEDC_DUTY_START_HSCH1_S 31 +/* LEDC_DUTY_INC_HSCH1 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for high speed channel1.*/ +#define LEDC_DUTY_INC_HSCH1 (BIT(30)) +#define LEDC_DUTY_INC_HSCH1_M (BIT(30)) +#define LEDC_DUTY_INC_HSCH1_V 0x1 +#define LEDC_DUTY_INC_HSCH1_S 30 +/* LEDC_DUTY_NUM_HSCH1 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for high speed channel1.*/ +#define LEDC_DUTY_NUM_HSCH1 0x000003FF +#define LEDC_DUTY_NUM_HSCH1_M ((LEDC_DUTY_NUM_HSCH1_V)<<(LEDC_DUTY_NUM_HSCH1_S)) +#define LEDC_DUTY_NUM_HSCH1_V 0x3FF +#define LEDC_DUTY_NUM_HSCH1_S 20 +/* LEDC_DUTY_CYCLE_HSCH1 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_hsch1 cycles for high speed channel1.*/ +#define LEDC_DUTY_CYCLE_HSCH1 0x000003FF +#define LEDC_DUTY_CYCLE_HSCH1_M ((LEDC_DUTY_CYCLE_HSCH1_V)<<(LEDC_DUTY_CYCLE_HSCH1_S)) +#define LEDC_DUTY_CYCLE_HSCH1_V 0x3FF +#define LEDC_DUTY_CYCLE_HSCH1_S 10 +/* LEDC_DUTY_SCALE_HSCH1 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + high speed channel1.*/ +#define LEDC_DUTY_SCALE_HSCH1 0x000003FF +#define LEDC_DUTY_SCALE_HSCH1_M ((LEDC_DUTY_SCALE_HSCH1_V)<<(LEDC_DUTY_SCALE_HSCH1_S)) +#define LEDC_DUTY_SCALE_HSCH1_V 0x3FF +#define LEDC_DUTY_SCALE_HSCH1_S 0 + +#define LEDC_HSCH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0024) +/* LEDC_DUTY_HSCH1 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for high speed channel1.*/ +#define LEDC_DUTY_HSCH1 0x01FFFFFF +#define LEDC_DUTY_HSCH1_M ((LEDC_DUTY_HSCH1_V)<<(LEDC_DUTY_HSCH1_S)) +#define LEDC_DUTY_HSCH1_V 0x1FFFFFF +#define LEDC_DUTY_HSCH1_S 0 + +#define LEDC_HSCH2_CONF0_REG (DR_REG_LEDC_BASE + 0x0028) +/* LEDC_IDLE_LV_HSCH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when high speed channel2 is off.*/ +#define LEDC_IDLE_LV_HSCH2 (BIT(3)) +#define LEDC_IDLE_LV_HSCH2_M (BIT(3)) +#define LEDC_IDLE_LV_HSCH2_V 0x1 +#define LEDC_IDLE_LV_HSCH2_S 3 +/* LEDC_SIG_OUT_EN_HSCH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for high speed channel2*/ +#define LEDC_SIG_OUT_EN_HSCH2 (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH2_M (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH2_V 0x1 +#define LEDC_SIG_OUT_EN_HSCH2_S 2 +/* LEDC_TIMER_SEL_HSCH2 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four high speed timers the two bits are used to select + one of them for high speed channel2. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ +#define LEDC_TIMER_SEL_HSCH2 0x00000003 +#define LEDC_TIMER_SEL_HSCH2_M ((LEDC_TIMER_SEL_HSCH2_V)<<(LEDC_TIMER_SEL_HSCH2_S)) +#define LEDC_TIMER_SEL_HSCH2_V 0x3 +#define LEDC_TIMER_SEL_HSCH2_S 0 + +#define LEDC_HSCH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x002C) +/* LEDC_HPOINT_HSCH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when htimerx(x=[0 3]) selected + by high speed channel2 has reached reg_hpoint_hsch2[19:0]*/ +#define LEDC_HPOINT_HSCH2 0x000FFFFF +#define LEDC_HPOINT_HSCH2_M ((LEDC_HPOINT_HSCH2_V)<<(LEDC_HPOINT_HSCH2_S)) +#define LEDC_HPOINT_HSCH2_V 0xFFFFF +#define LEDC_HPOINT_HSCH2_S 0 + +#define LEDC_HSCH2_DUTY_REG (DR_REG_LEDC_BASE + 0x0030) +/* LEDC_DUTY_HSCH2 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When hstimerx(x=[0 + 3]) choosed by high speed channel2 has reached reg_lpoint_hsch2 the output signal changes to low. reg_lpoint_hsch2=(reg_hpoint_hsch2[19:0]+reg_duty_hsch2[24:4]) (1) reg_lpoint_hsch2=(reg_hpoint_hsch2[19:0]+reg_duty_hsch2[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_HSCH2 0x01FFFFFF +#define LEDC_DUTY_HSCH2_M ((LEDC_DUTY_HSCH2_V)<<(LEDC_DUTY_HSCH2_S)) +#define LEDC_DUTY_HSCH2_V 0x1FFFFFF +#define LEDC_DUTY_HSCH2_S 0 + +#define LEDC_HSCH2_CONF1_REG (DR_REG_LEDC_BASE + 0x0034) +/* LEDC_DUTY_START_HSCH2 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch2 reg_duty_cycle_hsch2 and reg_duty_scale_hsch2 + has been configured. these register won't take effect until set reg_duty_start_hsch2. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_HSCH2 (BIT(31)) +#define LEDC_DUTY_START_HSCH2_M (BIT(31)) +#define LEDC_DUTY_START_HSCH2_V 0x1 +#define LEDC_DUTY_START_HSCH2_S 31 +/* LEDC_DUTY_INC_HSCH2 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for high speed channel2.*/ +#define LEDC_DUTY_INC_HSCH2 (BIT(30)) +#define LEDC_DUTY_INC_HSCH2_M (BIT(30)) +#define LEDC_DUTY_INC_HSCH2_V 0x1 +#define LEDC_DUTY_INC_HSCH2_S 30 +/* LEDC_DUTY_NUM_HSCH2 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for high speed channel2.*/ +#define LEDC_DUTY_NUM_HSCH2 0x000003FF +#define LEDC_DUTY_NUM_HSCH2_M ((LEDC_DUTY_NUM_HSCH2_V)<<(LEDC_DUTY_NUM_HSCH2_S)) +#define LEDC_DUTY_NUM_HSCH2_V 0x3FF +#define LEDC_DUTY_NUM_HSCH2_S 20 +/* LEDC_DUTY_CYCLE_HSCH2 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_hsch2 cycles for high speed channel2.*/ +#define LEDC_DUTY_CYCLE_HSCH2 0x000003FF +#define LEDC_DUTY_CYCLE_HSCH2_M ((LEDC_DUTY_CYCLE_HSCH2_V)<<(LEDC_DUTY_CYCLE_HSCH2_S)) +#define LEDC_DUTY_CYCLE_HSCH2_V 0x3FF +#define LEDC_DUTY_CYCLE_HSCH2_S 10 +/* LEDC_DUTY_SCALE_HSCH2 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + high speed channel2.*/ +#define LEDC_DUTY_SCALE_HSCH2 0x000003FF +#define LEDC_DUTY_SCALE_HSCH2_M ((LEDC_DUTY_SCALE_HSCH2_V)<<(LEDC_DUTY_SCALE_HSCH2_S)) +#define LEDC_DUTY_SCALE_HSCH2_V 0x3FF +#define LEDC_DUTY_SCALE_HSCH2_S 0 + +#define LEDC_HSCH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0038) +/* LEDC_DUTY_HSCH2 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for high speed channel2.*/ +#define LEDC_DUTY_HSCH2 0x01FFFFFF +#define LEDC_DUTY_HSCH2_M ((LEDC_DUTY_HSCH2_V)<<(LEDC_DUTY_HSCH2_S)) +#define LEDC_DUTY_HSCH2_V 0x1FFFFFF +#define LEDC_DUTY_HSCH2_S 0 + +#define LEDC_HSCH3_CONF0_REG (DR_REG_LEDC_BASE + 0x003C) +/* LEDC_IDLE_LV_HSCH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when high speed channel3 is off.*/ +#define LEDC_IDLE_LV_HSCH3 (BIT(3)) +#define LEDC_IDLE_LV_HSCH3_M (BIT(3)) +#define LEDC_IDLE_LV_HSCH3_V 0x1 +#define LEDC_IDLE_LV_HSCH3_S 3 +/* LEDC_SIG_OUT_EN_HSCH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for high speed channel3*/ +#define LEDC_SIG_OUT_EN_HSCH3 (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH3_M (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH3_V 0x1 +#define LEDC_SIG_OUT_EN_HSCH3_S 2 +/* LEDC_TIMER_SEL_HSCH3 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four high speed timers the two bits are used to select + one of them for high speed channel3. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ +#define LEDC_TIMER_SEL_HSCH3 0x00000003 +#define LEDC_TIMER_SEL_HSCH3_M ((LEDC_TIMER_SEL_HSCH3_V)<<(LEDC_TIMER_SEL_HSCH3_S)) +#define LEDC_TIMER_SEL_HSCH3_V 0x3 +#define LEDC_TIMER_SEL_HSCH3_S 0 + +#define LEDC_HSCH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x0040) +/* LEDC_HPOINT_HSCH3 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when htimerx(x=[0 3]) selected + by high speed channel3 has reached reg_hpoint_hsch3[19:0]*/ +#define LEDC_HPOINT_HSCH3 0x000FFFFF +#define LEDC_HPOINT_HSCH3_M ((LEDC_HPOINT_HSCH3_V)<<(LEDC_HPOINT_HSCH3_S)) +#define LEDC_HPOINT_HSCH3_V 0xFFFFF +#define LEDC_HPOINT_HSCH3_S 0 + +#define LEDC_HSCH3_DUTY_REG (DR_REG_LEDC_BASE + 0x0044) +/* LEDC_DUTY_HSCH3 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When hstimerx(x=[0 + 3]) choosed by high speed channel3 has reached reg_lpoint_hsch3 the output signal changes to low. reg_lpoint_hsch3=(reg_hpoint_hsch3[19:0]+reg_duty_hsch3[24:4]) (1) reg_lpoint_hsch3=(reg_hpoint_hsch3[19:0]+reg_duty_hsch3[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_HSCH3 0x01FFFFFF +#define LEDC_DUTY_HSCH3_M ((LEDC_DUTY_HSCH3_V)<<(LEDC_DUTY_HSCH3_S)) +#define LEDC_DUTY_HSCH3_V 0x1FFFFFF +#define LEDC_DUTY_HSCH3_S 0 + +#define LEDC_HSCH3_CONF1_REG (DR_REG_LEDC_BASE + 0x0048) +/* LEDC_DUTY_START_HSCH3 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch3 reg_duty_cycle_hsch3 and reg_duty_scale_hsch3 + has been configured. these register won't take effect until set reg_duty_start_hsch3. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_HSCH3 (BIT(31)) +#define LEDC_DUTY_START_HSCH3_M (BIT(31)) +#define LEDC_DUTY_START_HSCH3_V 0x1 +#define LEDC_DUTY_START_HSCH3_S 31 +/* LEDC_DUTY_INC_HSCH3 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for high speed channel3.*/ +#define LEDC_DUTY_INC_HSCH3 (BIT(30)) +#define LEDC_DUTY_INC_HSCH3_M (BIT(30)) +#define LEDC_DUTY_INC_HSCH3_V 0x1 +#define LEDC_DUTY_INC_HSCH3_S 30 +/* LEDC_DUTY_NUM_HSCH3 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for high speed channel3.*/ +#define LEDC_DUTY_NUM_HSCH3 0x000003FF +#define LEDC_DUTY_NUM_HSCH3_M ((LEDC_DUTY_NUM_HSCH3_V)<<(LEDC_DUTY_NUM_HSCH3_S)) +#define LEDC_DUTY_NUM_HSCH3_V 0x3FF +#define LEDC_DUTY_NUM_HSCH3_S 20 +/* LEDC_DUTY_CYCLE_HSCH3 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_hsch3 cycles for high speed channel3.*/ +#define LEDC_DUTY_CYCLE_HSCH3 0x000003FF +#define LEDC_DUTY_CYCLE_HSCH3_M ((LEDC_DUTY_CYCLE_HSCH3_V)<<(LEDC_DUTY_CYCLE_HSCH3_S)) +#define LEDC_DUTY_CYCLE_HSCH3_V 0x3FF +#define LEDC_DUTY_CYCLE_HSCH3_S 10 +/* LEDC_DUTY_SCALE_HSCH3 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + high speed channel3.*/ +#define LEDC_DUTY_SCALE_HSCH3 0x000003FF +#define LEDC_DUTY_SCALE_HSCH3_M ((LEDC_DUTY_SCALE_HSCH3_V)<<(LEDC_DUTY_SCALE_HSCH3_S)) +#define LEDC_DUTY_SCALE_HSCH3_V 0x3FF +#define LEDC_DUTY_SCALE_HSCH3_S 0 + +#define LEDC_HSCH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x004C) +/* LEDC_DUTY_HSCH3 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for high speed channel3.*/ +#define LEDC_DUTY_HSCH3 0x01FFFFFF +#define LEDC_DUTY_HSCH3_M ((LEDC_DUTY_HSCH3_V)<<(LEDC_DUTY_HSCH3_S)) +#define LEDC_DUTY_HSCH3_V 0x1FFFFFF +#define LEDC_DUTY_HSCH3_S 0 + +#define LEDC_HSCH4_CONF0_REG (DR_REG_LEDC_BASE + 0x0050) +/* LEDC_IDLE_LV_HSCH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when high speed channel4 is off.*/ +#define LEDC_IDLE_LV_HSCH4 (BIT(3)) +#define LEDC_IDLE_LV_HSCH4_M (BIT(3)) +#define LEDC_IDLE_LV_HSCH4_V 0x1 +#define LEDC_IDLE_LV_HSCH4_S 3 +/* LEDC_SIG_OUT_EN_HSCH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for high speed channel4*/ +#define LEDC_SIG_OUT_EN_HSCH4 (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH4_M (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH4_V 0x1 +#define LEDC_SIG_OUT_EN_HSCH4_S 2 +/* LEDC_TIMER_SEL_HSCH4 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four high speed timers the two bits are used to select + one of them for high speed channel4. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ +#define LEDC_TIMER_SEL_HSCH4 0x00000003 +#define LEDC_TIMER_SEL_HSCH4_M ((LEDC_TIMER_SEL_HSCH4_V)<<(LEDC_TIMER_SEL_HSCH4_S)) +#define LEDC_TIMER_SEL_HSCH4_V 0x3 +#define LEDC_TIMER_SEL_HSCH4_S 0 + +#define LEDC_HSCH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x0054) +/* LEDC_HPOINT_HSCH4 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when htimerx(x=[0 3]) selected + by high speed channel4 has reached reg_hpoint_hsch4[19:0]*/ +#define LEDC_HPOINT_HSCH4 0x000FFFFF +#define LEDC_HPOINT_HSCH4_M ((LEDC_HPOINT_HSCH4_V)<<(LEDC_HPOINT_HSCH4_S)) +#define LEDC_HPOINT_HSCH4_V 0xFFFFF +#define LEDC_HPOINT_HSCH4_S 0 + +#define LEDC_HSCH4_DUTY_REG (DR_REG_LEDC_BASE + 0x0058) +/* LEDC_DUTY_HSCH4 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When hstimerx(x=[0 + 3]) choosed by high speed channel4 has reached reg_lpoint_hsch4 the output signal changes to low. reg_lpoint_hsch4=(reg_hpoint_hsch4[19:0]+reg_duty_hsch4[24:4]) (1) reg_lpoint_hsch4=(reg_hpoint_hsch4[19:0]+reg_duty_hsch4[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_HSCH4 0x01FFFFFF +#define LEDC_DUTY_HSCH4_M ((LEDC_DUTY_HSCH4_V)<<(LEDC_DUTY_HSCH4_S)) +#define LEDC_DUTY_HSCH4_V 0x1FFFFFF +#define LEDC_DUTY_HSCH4_S 0 + +#define LEDC_HSCH4_CONF1_REG (DR_REG_LEDC_BASE + 0x005C) +/* LEDC_DUTY_START_HSCH4 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 + has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_HSCH4 (BIT(31)) +#define LEDC_DUTY_START_HSCH4_M (BIT(31)) +#define LEDC_DUTY_START_HSCH4_V 0x1 +#define LEDC_DUTY_START_HSCH4_S 31 +/* LEDC_DUTY_INC_HSCH4 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for high speed channel4.*/ +#define LEDC_DUTY_INC_HSCH4 (BIT(30)) +#define LEDC_DUTY_INC_HSCH4_M (BIT(30)) +#define LEDC_DUTY_INC_HSCH4_V 0x1 +#define LEDC_DUTY_INC_HSCH4_S 30 +/* LEDC_DUTY_NUM_HSCH4 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for high speed channel1.*/ +#define LEDC_DUTY_NUM_HSCH4 0x000003FF +#define LEDC_DUTY_NUM_HSCH4_M ((LEDC_DUTY_NUM_HSCH4_V)<<(LEDC_DUTY_NUM_HSCH4_S)) +#define LEDC_DUTY_NUM_HSCH4_V 0x3FF +#define LEDC_DUTY_NUM_HSCH4_S 20 +/* LEDC_DUTY_CYCLE_HSCH4 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_hsch4 cycles for high speed channel4.*/ +#define LEDC_DUTY_CYCLE_HSCH4 0x000003FF +#define LEDC_DUTY_CYCLE_HSCH4_M ((LEDC_DUTY_CYCLE_HSCH4_V)<<(LEDC_DUTY_CYCLE_HSCH4_S)) +#define LEDC_DUTY_CYCLE_HSCH4_V 0x3FF +#define LEDC_DUTY_CYCLE_HSCH4_S 10 +/* LEDC_DUTY_SCALE_HSCH4 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + high speed channel4.*/ +#define LEDC_DUTY_SCALE_HSCH4 0x000003FF +#define LEDC_DUTY_SCALE_HSCH4_M ((LEDC_DUTY_SCALE_HSCH4_V)<<(LEDC_DUTY_SCALE_HSCH4_S)) +#define LEDC_DUTY_SCALE_HSCH4_V 0x3FF +#define LEDC_DUTY_SCALE_HSCH4_S 0 + +#define LEDC_HSCH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0060) +/* LEDC_DUTY_HSCH4 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for high speed channel4.*/ +#define LEDC_DUTY_HSCH4 0x01FFFFFF +#define LEDC_DUTY_HSCH4_M ((LEDC_DUTY_HSCH4_V)<<(LEDC_DUTY_HSCH4_S)) +#define LEDC_DUTY_HSCH4_V 0x1FFFFFF +#define LEDC_DUTY_HSCH4_S 0 + +#define LEDC_HSCH5_CONF0_REG (DR_REG_LEDC_BASE + 0x0064) +/* LEDC_IDLE_LV_HSCH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when high speed channel5 is off.*/ +#define LEDC_IDLE_LV_HSCH5 (BIT(3)) +#define LEDC_IDLE_LV_HSCH5_M (BIT(3)) +#define LEDC_IDLE_LV_HSCH5_V 0x1 +#define LEDC_IDLE_LV_HSCH5_S 3 +/* LEDC_SIG_OUT_EN_HSCH5 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for high speed channel5.*/ +#define LEDC_SIG_OUT_EN_HSCH5 (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH5_M (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH5_V 0x1 +#define LEDC_SIG_OUT_EN_HSCH5_S 2 +/* LEDC_TIMER_SEL_HSCH5 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four high speed timers the two bits are used to select + one of them for high speed channel5. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ +#define LEDC_TIMER_SEL_HSCH5 0x00000003 +#define LEDC_TIMER_SEL_HSCH5_M ((LEDC_TIMER_SEL_HSCH5_V)<<(LEDC_TIMER_SEL_HSCH5_S)) +#define LEDC_TIMER_SEL_HSCH5_V 0x3 +#define LEDC_TIMER_SEL_HSCH5_S 0 + +#define LEDC_HSCH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x0068) +/* LEDC_HPOINT_HSCH5 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when htimerx(x=[0 3]) selected + by high speed channel5 has reached reg_hpoint_hsch5[19:0]*/ +#define LEDC_HPOINT_HSCH5 0x000FFFFF +#define LEDC_HPOINT_HSCH5_M ((LEDC_HPOINT_HSCH5_V)<<(LEDC_HPOINT_HSCH5_S)) +#define LEDC_HPOINT_HSCH5_V 0xFFFFF +#define LEDC_HPOINT_HSCH5_S 0 + +#define LEDC_HSCH5_DUTY_REG (DR_REG_LEDC_BASE + 0x006C) +/* LEDC_DUTY_HSCH5 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When hstimerx(x=[0 + 3]) choosed by high speed channel5 has reached reg_lpoint_hsch5 the output signal changes to low. reg_lpoint_hsch5=(reg_hpoint_hsch5[19:0]+reg_duty_hsch5[24:4]) (1) reg_lpoint_hsch5=(reg_hpoint_hsch5[19:0]+reg_duty_hsch5[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_HSCH5 0x01FFFFFF +#define LEDC_DUTY_HSCH5_M ((LEDC_DUTY_HSCH5_V)<<(LEDC_DUTY_HSCH5_S)) +#define LEDC_DUTY_HSCH5_V 0x1FFFFFF +#define LEDC_DUTY_HSCH5_S 0 + +#define LEDC_HSCH5_CONF1_REG (DR_REG_LEDC_BASE + 0x0070) +/* LEDC_DUTY_START_HSCH5 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch5 reg_duty_cycle_hsch5 and reg_duty_scale_hsch5 + has been configured. these register won't take effect until set reg_duty_start_hsch5. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_HSCH5 (BIT(31)) +#define LEDC_DUTY_START_HSCH5_M (BIT(31)) +#define LEDC_DUTY_START_HSCH5_V 0x1 +#define LEDC_DUTY_START_HSCH5_S 31 +/* LEDC_DUTY_INC_HSCH5 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for high speed channel5.*/ +#define LEDC_DUTY_INC_HSCH5 (BIT(30)) +#define LEDC_DUTY_INC_HSCH5_M (BIT(30)) +#define LEDC_DUTY_INC_HSCH5_V 0x1 +#define LEDC_DUTY_INC_HSCH5_S 30 +/* LEDC_DUTY_NUM_HSCH5 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for high speed channel5.*/ +#define LEDC_DUTY_NUM_HSCH5 0x000003FF +#define LEDC_DUTY_NUM_HSCH5_M ((LEDC_DUTY_NUM_HSCH5_V)<<(LEDC_DUTY_NUM_HSCH5_S)) +#define LEDC_DUTY_NUM_HSCH5_V 0x3FF +#define LEDC_DUTY_NUM_HSCH5_S 20 +/* LEDC_DUTY_CYCLE_HSCH5 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_hsch5 cycles for high speed channel5.*/ +#define LEDC_DUTY_CYCLE_HSCH5 0x000003FF +#define LEDC_DUTY_CYCLE_HSCH5_M ((LEDC_DUTY_CYCLE_HSCH5_V)<<(LEDC_DUTY_CYCLE_HSCH5_S)) +#define LEDC_DUTY_CYCLE_HSCH5_V 0x3FF +#define LEDC_DUTY_CYCLE_HSCH5_S 10 +/* LEDC_DUTY_SCALE_HSCH5 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + high speed channel5.*/ +#define LEDC_DUTY_SCALE_HSCH5 0x000003FF +#define LEDC_DUTY_SCALE_HSCH5_M ((LEDC_DUTY_SCALE_HSCH5_V)<<(LEDC_DUTY_SCALE_HSCH5_S)) +#define LEDC_DUTY_SCALE_HSCH5_V 0x3FF +#define LEDC_DUTY_SCALE_HSCH5_S 0 + +#define LEDC_HSCH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0074) +/* LEDC_DUTY_HSCH5 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for high speed channel5.*/ +#define LEDC_DUTY_HSCH5 0x01FFFFFF +#define LEDC_DUTY_HSCH5_M ((LEDC_DUTY_HSCH5_V)<<(LEDC_DUTY_HSCH5_S)) +#define LEDC_DUTY_HSCH5_V 0x1FFFFFF +#define LEDC_DUTY_HSCH5_S 0 + +#define LEDC_HSCH6_CONF0_REG (DR_REG_LEDC_BASE + 0x0078) +/* LEDC_IDLE_LV_HSCH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when high speed channel6 is off.*/ +#define LEDC_IDLE_LV_HSCH6 (BIT(3)) +#define LEDC_IDLE_LV_HSCH6_M (BIT(3)) +#define LEDC_IDLE_LV_HSCH6_V 0x1 +#define LEDC_IDLE_LV_HSCH6_S 3 +/* LEDC_SIG_OUT_EN_HSCH6 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for high speed channel6*/ +#define LEDC_SIG_OUT_EN_HSCH6 (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH6_M (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH6_V 0x1 +#define LEDC_SIG_OUT_EN_HSCH6_S 2 +/* LEDC_TIMER_SEL_HSCH6 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four high speed timers the two bits are used to select + one of them for high speed channel6. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ +#define LEDC_TIMER_SEL_HSCH6 0x00000003 +#define LEDC_TIMER_SEL_HSCH6_M ((LEDC_TIMER_SEL_HSCH6_V)<<(LEDC_TIMER_SEL_HSCH6_S)) +#define LEDC_TIMER_SEL_HSCH6_V 0x3 +#define LEDC_TIMER_SEL_HSCH6_S 0 + +#define LEDC_HSCH6_HPOINT_REG (DR_REG_LEDC_BASE + 0x007C) +/* LEDC_HPOINT_HSCH6 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when htimerx(x=[0 3]) selected + by high speed channel6 has reached reg_hpoint_hsch6[19:0]*/ +#define LEDC_HPOINT_HSCH6 0x000FFFFF +#define LEDC_HPOINT_HSCH6_M ((LEDC_HPOINT_HSCH6_V)<<(LEDC_HPOINT_HSCH6_S)) +#define LEDC_HPOINT_HSCH6_V 0xFFFFF +#define LEDC_HPOINT_HSCH6_S 0 + +#define LEDC_HSCH6_DUTY_REG (DR_REG_LEDC_BASE + 0x0080) +/* LEDC_DUTY_HSCH6 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When hstimerx(x=[0 + 3]) choosed by high speed channel6 has reached reg_lpoint_hsch6 the output signal changes to low. reg_lpoint_hsch6=(reg_hpoint_hsch6[19:0]+reg_duty_hsch6[24:4]) (1) reg_lpoint_hsch6=(reg_hpoint_hsch6[19:0]+reg_duty_hsch6[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_HSCH6 0x01FFFFFF +#define LEDC_DUTY_HSCH6_M ((LEDC_DUTY_HSCH6_V)<<(LEDC_DUTY_HSCH6_S)) +#define LEDC_DUTY_HSCH6_V 0x1FFFFFF +#define LEDC_DUTY_HSCH6_S 0 + +#define LEDC_HSCH6_CONF1_REG (DR_REG_LEDC_BASE + 0x0084) +/* LEDC_DUTY_START_HSCH6 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 + has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_HSCH6 (BIT(31)) +#define LEDC_DUTY_START_HSCH6_M (BIT(31)) +#define LEDC_DUTY_START_HSCH6_V 0x1 +#define LEDC_DUTY_START_HSCH6_S 31 +/* LEDC_DUTY_INC_HSCH6 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for high speed channel6.*/ +#define LEDC_DUTY_INC_HSCH6 (BIT(30)) +#define LEDC_DUTY_INC_HSCH6_M (BIT(30)) +#define LEDC_DUTY_INC_HSCH6_V 0x1 +#define LEDC_DUTY_INC_HSCH6_S 30 +/* LEDC_DUTY_NUM_HSCH6 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for high speed channel6.*/ +#define LEDC_DUTY_NUM_HSCH6 0x000003FF +#define LEDC_DUTY_NUM_HSCH6_M ((LEDC_DUTY_NUM_HSCH6_V)<<(LEDC_DUTY_NUM_HSCH6_S)) +#define LEDC_DUTY_NUM_HSCH6_V 0x3FF +#define LEDC_DUTY_NUM_HSCH6_S 20 +/* LEDC_DUTY_CYCLE_HSCH6 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_hsch6 cycles for high speed channel6.*/ +#define LEDC_DUTY_CYCLE_HSCH6 0x000003FF +#define LEDC_DUTY_CYCLE_HSCH6_M ((LEDC_DUTY_CYCLE_HSCH6_V)<<(LEDC_DUTY_CYCLE_HSCH6_S)) +#define LEDC_DUTY_CYCLE_HSCH6_V 0x3FF +#define LEDC_DUTY_CYCLE_HSCH6_S 10 +/* LEDC_DUTY_SCALE_HSCH6 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + high speed channel6.*/ +#define LEDC_DUTY_SCALE_HSCH6 0x000003FF +#define LEDC_DUTY_SCALE_HSCH6_M ((LEDC_DUTY_SCALE_HSCH6_V)<<(LEDC_DUTY_SCALE_HSCH6_S)) +#define LEDC_DUTY_SCALE_HSCH6_V 0x3FF +#define LEDC_DUTY_SCALE_HSCH6_S 0 + +#define LEDC_HSCH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0088) +/* LEDC_DUTY_HSCH6 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for high speed channel6.*/ +#define LEDC_DUTY_HSCH6 0x01FFFFFF +#define LEDC_DUTY_HSCH6_M ((LEDC_DUTY_HSCH6_V)<<(LEDC_DUTY_HSCH6_S)) +#define LEDC_DUTY_HSCH6_V 0x1FFFFFF +#define LEDC_DUTY_HSCH6_S 0 + +#define LEDC_HSCH7_CONF0_REG (DR_REG_LEDC_BASE + 0x008C) +/* LEDC_IDLE_LV_HSCH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when high speed channel7 is off.*/ +#define LEDC_IDLE_LV_HSCH7 (BIT(3)) +#define LEDC_IDLE_LV_HSCH7_M (BIT(3)) +#define LEDC_IDLE_LV_HSCH7_V 0x1 +#define LEDC_IDLE_LV_HSCH7_S 3 +/* LEDC_SIG_OUT_EN_HSCH7 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for high speed channel7.*/ +#define LEDC_SIG_OUT_EN_HSCH7 (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH7_M (BIT(2)) +#define LEDC_SIG_OUT_EN_HSCH7_V 0x1 +#define LEDC_SIG_OUT_EN_HSCH7_S 2 +/* LEDC_TIMER_SEL_HSCH7 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four high speed timers the two bits are used to select + one of them for high speed channel7. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ +#define LEDC_TIMER_SEL_HSCH7 0x00000003 +#define LEDC_TIMER_SEL_HSCH7_M ((LEDC_TIMER_SEL_HSCH7_V)<<(LEDC_TIMER_SEL_HSCH7_S)) +#define LEDC_TIMER_SEL_HSCH7_V 0x3 +#define LEDC_TIMER_SEL_HSCH7_S 0 + +#define LEDC_HSCH7_HPOINT_REG (DR_REG_LEDC_BASE + 0x0090) +/* LEDC_HPOINT_HSCH7 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when htimerx(x=[0 3]) selected + by high speed channel7 has reached reg_hpoint_hsch7[19:0]*/ +#define LEDC_HPOINT_HSCH7 0x000FFFFF +#define LEDC_HPOINT_HSCH7_M ((LEDC_HPOINT_HSCH7_V)<<(LEDC_HPOINT_HSCH7_S)) +#define LEDC_HPOINT_HSCH7_V 0xFFFFF +#define LEDC_HPOINT_HSCH7_S 0 + +#define LEDC_HSCH7_DUTY_REG (DR_REG_LEDC_BASE + 0x0094) +/* LEDC_DUTY_HSCH7 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When hstimerx(x=[0 + 3]) choosed by high speed channel7 has reached reg_lpoint_hsch7 the output signal changes to low. reg_lpoint_hsch7=(reg_hpoint_hsch7[19:0]+reg_duty_hsch7[24:4]) (1) reg_lpoint_hsch7=(reg_hpoint_hsch7[19:0]+reg_duty_hsch7[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_HSCH7 0x01FFFFFF +#define LEDC_DUTY_HSCH7_M ((LEDC_DUTY_HSCH7_V)<<(LEDC_DUTY_HSCH7_S)) +#define LEDC_DUTY_HSCH7_V 0x1FFFFFF +#define LEDC_DUTY_HSCH7_S 0 + +#define LEDC_HSCH7_CONF1_REG (DR_REG_LEDC_BASE + 0x0098) +/* LEDC_DUTY_START_HSCH7 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 + has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_HSCH7 (BIT(31)) +#define LEDC_DUTY_START_HSCH7_M (BIT(31)) +#define LEDC_DUTY_START_HSCH7_V 0x1 +#define LEDC_DUTY_START_HSCH7_S 31 +/* LEDC_DUTY_INC_HSCH7 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for high speed channel6.*/ +#define LEDC_DUTY_INC_HSCH7 (BIT(30)) +#define LEDC_DUTY_INC_HSCH7_M (BIT(30)) +#define LEDC_DUTY_INC_HSCH7_V 0x1 +#define LEDC_DUTY_INC_HSCH7_S 30 +/* LEDC_DUTY_NUM_HSCH7 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for high speed channel6.*/ +#define LEDC_DUTY_NUM_HSCH7 0x000003FF +#define LEDC_DUTY_NUM_HSCH7_M ((LEDC_DUTY_NUM_HSCH7_V)<<(LEDC_DUTY_NUM_HSCH7_S)) +#define LEDC_DUTY_NUM_HSCH7_V 0x3FF +#define LEDC_DUTY_NUM_HSCH7_S 20 +/* LEDC_DUTY_CYCLE_HSCH7 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_hsch7 cycles for high speed channel7.*/ +#define LEDC_DUTY_CYCLE_HSCH7 0x000003FF +#define LEDC_DUTY_CYCLE_HSCH7_M ((LEDC_DUTY_CYCLE_HSCH7_V)<<(LEDC_DUTY_CYCLE_HSCH7_S)) +#define LEDC_DUTY_CYCLE_HSCH7_V 0x3FF +#define LEDC_DUTY_CYCLE_HSCH7_S 10 +/* LEDC_DUTY_SCALE_HSCH7 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + high speed channel7.*/ +#define LEDC_DUTY_SCALE_HSCH7 0x000003FF +#define LEDC_DUTY_SCALE_HSCH7_M ((LEDC_DUTY_SCALE_HSCH7_V)<<(LEDC_DUTY_SCALE_HSCH7_S)) +#define LEDC_DUTY_SCALE_HSCH7_V 0x3FF +#define LEDC_DUTY_SCALE_HSCH7_S 0 + +#define LEDC_HSCH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x009C) +/* LEDC_DUTY_HSCH7 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for high speed channel7.*/ +#define LEDC_DUTY_HSCH7 0x01FFFFFF +#define LEDC_DUTY_HSCH7_M ((LEDC_DUTY_HSCH7_V)<<(LEDC_DUTY_HSCH7_S)) +#define LEDC_DUTY_HSCH7_V 0x1FFFFFF +#define LEDC_DUTY_HSCH7_S 0 + +#define LEDC_LSCH0_CONF0_REG (DR_REG_LEDC_BASE + 0x00A0) +/* LEDC_PARA_UP_LSCH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This bit is used to update register LEDC_LSCH0_HPOINT and LEDC_LSCH0_DUTY + for low speed channel0.*/ +#define LEDC_PARA_UP_LSCH0 (BIT(4)) +#define LEDC_PARA_UP_LSCH0_M (BIT(4)) +#define LEDC_PARA_UP_LSCH0_V 0x1 +#define LEDC_PARA_UP_LSCH0_S 4 +/* LEDC_IDLE_LV_LSCH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when low speed channel0 is off.*/ +#define LEDC_IDLE_LV_LSCH0 (BIT(3)) +#define LEDC_IDLE_LV_LSCH0_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH0_V 0x1 +#define LEDC_IDLE_LV_LSCH0_S 3 +/* LEDC_SIG_OUT_EN_LSCH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for low speed channel0.*/ +#define LEDC_SIG_OUT_EN_LSCH0 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH0_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH0_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH0_S 2 +/* LEDC_TIMER_SEL_LSCH0 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four low speed timers the two bits are used to select + one of them for low speed channel0. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ +#define LEDC_TIMER_SEL_LSCH0 0x00000003 +#define LEDC_TIMER_SEL_LSCH0_M ((LEDC_TIMER_SEL_LSCH0_V)<<(LEDC_TIMER_SEL_LSCH0_S)) +#define LEDC_TIMER_SEL_LSCH0_V 0x3 +#define LEDC_TIMER_SEL_LSCH0_S 0 + +#define LEDC_LSCH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x00A4) +/* LEDC_HPOINT_LSCH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when lstimerx(x=[0 3]) selected + by low speed channel0 has reached reg_hpoint_lsch0[19:0]*/ +#define LEDC_HPOINT_LSCH0 0x000FFFFF +#define LEDC_HPOINT_LSCH0_M ((LEDC_HPOINT_LSCH0_V)<<(LEDC_HPOINT_LSCH0_S)) +#define LEDC_HPOINT_LSCH0_V 0xFFFFF +#define LEDC_HPOINT_LSCH0_S 0 + +#define LEDC_LSCH0_DUTY_REG (DR_REG_LEDC_BASE + 0x00A8) +/* LEDC_DUTY_LSCH0 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When lstimerx(x=[0 + 3]) choosed by low speed channel0 has reached reg_lpoint_lsch0 the output signal changes to low. reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4]) (1) reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_LSCH0 0x01FFFFFF +#define LEDC_DUTY_LSCH0_M ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S)) +#define LEDC_DUTY_LSCH0_V 0x1FFFFFF +#define LEDC_DUTY_LSCH0_S 0 + +#define LEDC_LSCH0_CONF1_REG (DR_REG_LEDC_BASE + 0x00AC) +/* LEDC_DUTY_START_LSCH0 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 + has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_LSCH0 (BIT(31)) +#define LEDC_DUTY_START_LSCH0_M (BIT(31)) +#define LEDC_DUTY_START_LSCH0_V 0x1 +#define LEDC_DUTY_START_LSCH0_S 31 +/* LEDC_DUTY_INC_LSCH0 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for low speed channel6.*/ +#define LEDC_DUTY_INC_LSCH0 (BIT(30)) +#define LEDC_DUTY_INC_LSCH0_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH0_V 0x1 +#define LEDC_DUTY_INC_LSCH0_S 30 +/* LEDC_DUTY_NUM_LSCH0 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for low speed channel6.*/ +#define LEDC_DUTY_NUM_LSCH0 0x000003FF +#define LEDC_DUTY_NUM_LSCH0_M ((LEDC_DUTY_NUM_LSCH0_V)<<(LEDC_DUTY_NUM_LSCH0_S)) +#define LEDC_DUTY_NUM_LSCH0_V 0x3FF +#define LEDC_DUTY_NUM_LSCH0_S 20 +/* LEDC_DUTY_CYCLE_LSCH0 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_lsch0 cycles for low speed channel0.*/ +#define LEDC_DUTY_CYCLE_LSCH0 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH0_M ((LEDC_DUTY_CYCLE_LSCH0_V)<<(LEDC_DUTY_CYCLE_LSCH0_S)) +#define LEDC_DUTY_CYCLE_LSCH0_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH0_S 10 +/* LEDC_DUTY_SCALE_LSCH0 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + low speed channel0.*/ +#define LEDC_DUTY_SCALE_LSCH0 0x000003FF +#define LEDC_DUTY_SCALE_LSCH0_M ((LEDC_DUTY_SCALE_LSCH0_V)<<(LEDC_DUTY_SCALE_LSCH0_S)) +#define LEDC_DUTY_SCALE_LSCH0_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH0_S 0 + +#define LEDC_LSCH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00B0) +/* LEDC_DUTY_LSCH0 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for low speed channel0.*/ +#define LEDC_DUTY_LSCH0 0x01FFFFFF +#define LEDC_DUTY_LSCH0_M ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S)) +#define LEDC_DUTY_LSCH0_V 0x1FFFFFF +#define LEDC_DUTY_LSCH0_S 0 + +#define LEDC_LSCH1_CONF0_REG (DR_REG_LEDC_BASE + 0x00B4) +/* LEDC_PARA_UP_LSCH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This bit is used to update register LEDC_LSCH1_HPOINT and LEDC_LSCH1_DUTY + for low speed channel1.*/ +#define LEDC_PARA_UP_LSCH1 (BIT(4)) +#define LEDC_PARA_UP_LSCH1_M (BIT(4)) +#define LEDC_PARA_UP_LSCH1_V 0x1 +#define LEDC_PARA_UP_LSCH1_S 4 +/* LEDC_IDLE_LV_LSCH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when low speed channel1 is off.*/ +#define LEDC_IDLE_LV_LSCH1 (BIT(3)) +#define LEDC_IDLE_LV_LSCH1_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH1_V 0x1 +#define LEDC_IDLE_LV_LSCH1_S 3 +/* LEDC_SIG_OUT_EN_LSCH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for low speed channel1.*/ +#define LEDC_SIG_OUT_EN_LSCH1 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH1_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH1_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH1_S 2 +/* LEDC_TIMER_SEL_LSCH1 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four low speed timers the two bits are used to select + one of them for low speed channel1. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ +#define LEDC_TIMER_SEL_LSCH1 0x00000003 +#define LEDC_TIMER_SEL_LSCH1_M ((LEDC_TIMER_SEL_LSCH1_V)<<(LEDC_TIMER_SEL_LSCH1_S)) +#define LEDC_TIMER_SEL_LSCH1_V 0x3 +#define LEDC_TIMER_SEL_LSCH1_S 0 + +#define LEDC_LSCH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x00B8) +/* LEDC_HPOINT_LSCH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when lstimerx(x=[0 3]) selected + by low speed channel1 has reached reg_hpoint_lsch1[19:0]*/ +#define LEDC_HPOINT_LSCH1 0x000FFFFF +#define LEDC_HPOINT_LSCH1_M ((LEDC_HPOINT_LSCH1_V)<<(LEDC_HPOINT_LSCH1_S)) +#define LEDC_HPOINT_LSCH1_V 0xFFFFF +#define LEDC_HPOINT_LSCH1_S 0 + +#define LEDC_LSCH1_DUTY_REG (DR_REG_LEDC_BASE + 0x00BC) +/* LEDC_DUTY_LSCH1 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When lstimerx(x=[0 + 3]) choosed by low speed channel1 has reached reg_lpoint_lsch1 the output signal changes to low. reg_lpoint_lsch1=(reg_hpoint_lsch1[19:0]+reg_duty_lsch1[24:4]) (1) reg_lpoint_lsch1=(reg_hpoint_lsch1[19:0]+reg_duty_lsch1[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_LSCH1 0x01FFFFFF +#define LEDC_DUTY_LSCH1_M ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S)) +#define LEDC_DUTY_LSCH1_V 0x1FFFFFF +#define LEDC_DUTY_LSCH1_S 0 + +#define LEDC_LSCH1_CONF1_REG (DR_REG_LEDC_BASE + 0x00C0) +/* LEDC_DUTY_START_LSCH1 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 + has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_LSCH1 (BIT(31)) +#define LEDC_DUTY_START_LSCH1_M (BIT(31)) +#define LEDC_DUTY_START_LSCH1_V 0x1 +#define LEDC_DUTY_START_LSCH1_S 31 +/* LEDC_DUTY_INC_LSCH1 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for low speed channel1.*/ +#define LEDC_DUTY_INC_LSCH1 (BIT(30)) +#define LEDC_DUTY_INC_LSCH1_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH1_V 0x1 +#define LEDC_DUTY_INC_LSCH1_S 30 +/* LEDC_DUTY_NUM_LSCH1 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for low speed channel1.*/ +#define LEDC_DUTY_NUM_LSCH1 0x000003FF +#define LEDC_DUTY_NUM_LSCH1_M ((LEDC_DUTY_NUM_LSCH1_V)<<(LEDC_DUTY_NUM_LSCH1_S)) +#define LEDC_DUTY_NUM_LSCH1_V 0x3FF +#define LEDC_DUTY_NUM_LSCH1_S 20 +/* LEDC_DUTY_CYCLE_LSCH1 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_lsch1 cycles for low speed channel1.*/ +#define LEDC_DUTY_CYCLE_LSCH1 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH1_M ((LEDC_DUTY_CYCLE_LSCH1_V)<<(LEDC_DUTY_CYCLE_LSCH1_S)) +#define LEDC_DUTY_CYCLE_LSCH1_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH1_S 10 +/* LEDC_DUTY_SCALE_LSCH1 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + low speed channel1.*/ +#define LEDC_DUTY_SCALE_LSCH1 0x000003FF +#define LEDC_DUTY_SCALE_LSCH1_M ((LEDC_DUTY_SCALE_LSCH1_V)<<(LEDC_DUTY_SCALE_LSCH1_S)) +#define LEDC_DUTY_SCALE_LSCH1_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH1_S 0 + +#define LEDC_LSCH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00C4) +/* LEDC_DUTY_LSCH1 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for low speed channel1.*/ +#define LEDC_DUTY_LSCH1 0x01FFFFFF +#define LEDC_DUTY_LSCH1_M ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S)) +#define LEDC_DUTY_LSCH1_V 0x1FFFFFF +#define LEDC_DUTY_LSCH1_S 0 + +#define LEDC_LSCH2_CONF0_REG (DR_REG_LEDC_BASE + 0x00C8) +/* LEDC_PARA_UP_LSCH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This bit is used to update register LEDC_LSCH2_HPOINT and LEDC_LSCH2_DUTY + for low speed channel2.*/ +#define LEDC_PARA_UP_LSCH2 (BIT(4)) +#define LEDC_PARA_UP_LSCH2_M (BIT(4)) +#define LEDC_PARA_UP_LSCH2_V 0x1 +#define LEDC_PARA_UP_LSCH2_S 4 +/* LEDC_IDLE_LV_LSCH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when low speed channel2 is off.*/ +#define LEDC_IDLE_LV_LSCH2 (BIT(3)) +#define LEDC_IDLE_LV_LSCH2_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH2_V 0x1 +#define LEDC_IDLE_LV_LSCH2_S 3 +/* LEDC_SIG_OUT_EN_LSCH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for low speed channel2.*/ +#define LEDC_SIG_OUT_EN_LSCH2 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH2_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH2_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH2_S 2 +/* LEDC_TIMER_SEL_LSCH2 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four low speed timers the two bits are used to select + one of them for low speed channel2. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ +#define LEDC_TIMER_SEL_LSCH2 0x00000003 +#define LEDC_TIMER_SEL_LSCH2_M ((LEDC_TIMER_SEL_LSCH2_V)<<(LEDC_TIMER_SEL_LSCH2_S)) +#define LEDC_TIMER_SEL_LSCH2_V 0x3 +#define LEDC_TIMER_SEL_LSCH2_S 0 + +#define LEDC_LSCH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x00CC) +/* LEDC_HPOINT_LSCH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when lstimerx(x=[0 3]) selected + by low speed channel2 has reached reg_hpoint_lsch2[19:0]*/ +#define LEDC_HPOINT_LSCH2 0x000FFFFF +#define LEDC_HPOINT_LSCH2_M ((LEDC_HPOINT_LSCH2_V)<<(LEDC_HPOINT_LSCH2_S)) +#define LEDC_HPOINT_LSCH2_V 0xFFFFF +#define LEDC_HPOINT_LSCH2_S 0 + +#define LEDC_LSCH2_DUTY_REG (DR_REG_LEDC_BASE + 0x00D0) +/* LEDC_DUTY_LSCH2 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When lstimerx(x=[0 + 3]) choosed by low speed channel2 has reached reg_lpoint_lsch2 the output signal changes to low. reg_lpoint_lsch2=(reg_hpoint_lsch2[19:0]+reg_duty_lsch2[24:4]) (1) reg_lpoint_lsch2=(reg_hpoint_lsch2[19:0]+reg_duty_lsch2[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_LSCH2 0x01FFFFFF +#define LEDC_DUTY_LSCH2_M ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S)) +#define LEDC_DUTY_LSCH2_V 0x1FFFFFF +#define LEDC_DUTY_LSCH2_S 0 + +#define LEDC_LSCH2_CONF1_REG (DR_REG_LEDC_BASE + 0x00D4) +/* LEDC_DUTY_START_LSCH2 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch2 reg_duty_cycle_hsch2 and reg_duty_scale_hsch2 + has been configured. these register won't take effect until set reg_duty_start_hsch2. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_LSCH2 (BIT(31)) +#define LEDC_DUTY_START_LSCH2_M (BIT(31)) +#define LEDC_DUTY_START_LSCH2_V 0x1 +#define LEDC_DUTY_START_LSCH2_S 31 +/* LEDC_DUTY_INC_LSCH2 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for low speed channel2.*/ +#define LEDC_DUTY_INC_LSCH2 (BIT(30)) +#define LEDC_DUTY_INC_LSCH2_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH2_V 0x1 +#define LEDC_DUTY_INC_LSCH2_S 30 +/* LEDC_DUTY_NUM_LSCH2 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for low speed channel2.*/ +#define LEDC_DUTY_NUM_LSCH2 0x000003FF +#define LEDC_DUTY_NUM_LSCH2_M ((LEDC_DUTY_NUM_LSCH2_V)<<(LEDC_DUTY_NUM_LSCH2_S)) +#define LEDC_DUTY_NUM_LSCH2_V 0x3FF +#define LEDC_DUTY_NUM_LSCH2_S 20 +/* LEDC_DUTY_CYCLE_LSCH2 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_lsch2 cycles for low speed channel2.*/ +#define LEDC_DUTY_CYCLE_LSCH2 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH2_M ((LEDC_DUTY_CYCLE_LSCH2_V)<<(LEDC_DUTY_CYCLE_LSCH2_S)) +#define LEDC_DUTY_CYCLE_LSCH2_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH2_S 10 +/* LEDC_DUTY_SCALE_LSCH2 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + low speed channel2.*/ +#define LEDC_DUTY_SCALE_LSCH2 0x000003FF +#define LEDC_DUTY_SCALE_LSCH2_M ((LEDC_DUTY_SCALE_LSCH2_V)<<(LEDC_DUTY_SCALE_LSCH2_S)) +#define LEDC_DUTY_SCALE_LSCH2_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH2_S 0 + +#define LEDC_LSCH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00D8) +/* LEDC_DUTY_LSCH2 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for low speed channel2.*/ +#define LEDC_DUTY_LSCH2 0x01FFFFFF +#define LEDC_DUTY_LSCH2_M ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S)) +#define LEDC_DUTY_LSCH2_V 0x1FFFFFF +#define LEDC_DUTY_LSCH2_S 0 + +#define LEDC_LSCH3_CONF0_REG (DR_REG_LEDC_BASE + 0x00DC) +/* LEDC_PARA_UP_LSCH3 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This bit is used to update register LEDC_LSCH3_HPOINT and LEDC_LSCH3_DUTY + for low speed channel3.*/ +#define LEDC_PARA_UP_LSCH3 (BIT(4)) +#define LEDC_PARA_UP_LSCH3_M (BIT(4)) +#define LEDC_PARA_UP_LSCH3_V 0x1 +#define LEDC_PARA_UP_LSCH3_S 4 +/* LEDC_IDLE_LV_LSCH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when low speed channel3 is off.*/ +#define LEDC_IDLE_LV_LSCH3 (BIT(3)) +#define LEDC_IDLE_LV_LSCH3_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH3_V 0x1 +#define LEDC_IDLE_LV_LSCH3_S 3 +/* LEDC_SIG_OUT_EN_LSCH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for low speed channel3.*/ +#define LEDC_SIG_OUT_EN_LSCH3 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH3_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH3_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH3_S 2 +/* LEDC_TIMER_SEL_LSCH3 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four low speed timers the two bits are used to select + one of them for low speed channel3. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ +#define LEDC_TIMER_SEL_LSCH3 0x00000003 +#define LEDC_TIMER_SEL_LSCH3_M ((LEDC_TIMER_SEL_LSCH3_V)<<(LEDC_TIMER_SEL_LSCH3_S)) +#define LEDC_TIMER_SEL_LSCH3_V 0x3 +#define LEDC_TIMER_SEL_LSCH3_S 0 + +#define LEDC_LSCH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x00E0) +/* LEDC_HPOINT_LSCH3 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when lstimerx(x=[0 3]) selected + by low speed channel3 has reached reg_hpoint_lsch3[19:0]*/ +#define LEDC_HPOINT_LSCH3 0x000FFFFF +#define LEDC_HPOINT_LSCH3_M ((LEDC_HPOINT_LSCH3_V)<<(LEDC_HPOINT_LSCH3_S)) +#define LEDC_HPOINT_LSCH3_V 0xFFFFF +#define LEDC_HPOINT_LSCH3_S 0 + +#define LEDC_LSCH3_DUTY_REG (DR_REG_LEDC_BASE + 0x00E4) +/* LEDC_DUTY_LSCH3 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When lstimerx(x=[0 + 3]) choosed by low speed channel3 has reached reg_lpoint_lsch3 the output signal changes to low. reg_lpoint_lsch3=(reg_hpoint_lsch3[19:0]+reg_duty_lsch3[24:4]) (1) reg_lpoint_lsch3=(reg_hpoint_lsch3[19:0]+reg_duty_lsch3[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_LSCH3 0x01FFFFFF +#define LEDC_DUTY_LSCH3_M ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S)) +#define LEDC_DUTY_LSCH3_V 0x1FFFFFF +#define LEDC_DUTY_LSCH3_S 0 + +#define LEDC_LSCH3_CONF1_REG (DR_REG_LEDC_BASE + 0x00E8) +/* LEDC_DUTY_START_LSCH3 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch3 reg_duty_cycle_hsch3 and reg_duty_scale_hsch3 + has been configured. these register won't take effect until set reg_duty_start_hsch3. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_LSCH3 (BIT(31)) +#define LEDC_DUTY_START_LSCH3_M (BIT(31)) +#define LEDC_DUTY_START_LSCH3_V 0x1 +#define LEDC_DUTY_START_LSCH3_S 31 +/* LEDC_DUTY_INC_LSCH3 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for low speed channel3.*/ +#define LEDC_DUTY_INC_LSCH3 (BIT(30)) +#define LEDC_DUTY_INC_LSCH3_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH3_V 0x1 +#define LEDC_DUTY_INC_LSCH3_S 30 +/* LEDC_DUTY_NUM_LSCH3 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for low speed channel3.*/ +#define LEDC_DUTY_NUM_LSCH3 0x000003FF +#define LEDC_DUTY_NUM_LSCH3_M ((LEDC_DUTY_NUM_LSCH3_V)<<(LEDC_DUTY_NUM_LSCH3_S)) +#define LEDC_DUTY_NUM_LSCH3_V 0x3FF +#define LEDC_DUTY_NUM_LSCH3_S 20 +/* LEDC_DUTY_CYCLE_LSCH3 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_lsch3 cycles for low speed channel3.*/ +#define LEDC_DUTY_CYCLE_LSCH3 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH3_M ((LEDC_DUTY_CYCLE_LSCH3_V)<<(LEDC_DUTY_CYCLE_LSCH3_S)) +#define LEDC_DUTY_CYCLE_LSCH3_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH3_S 10 +/* LEDC_DUTY_SCALE_LSCH3 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + low speed channel3.*/ +#define LEDC_DUTY_SCALE_LSCH3 0x000003FF +#define LEDC_DUTY_SCALE_LSCH3_M ((LEDC_DUTY_SCALE_LSCH3_V)<<(LEDC_DUTY_SCALE_LSCH3_S)) +#define LEDC_DUTY_SCALE_LSCH3_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH3_S 0 + +#define LEDC_LSCH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00EC) +/* LEDC_DUTY_LSCH3 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for low speed channel3.*/ +#define LEDC_DUTY_LSCH3 0x01FFFFFF +#define LEDC_DUTY_LSCH3_M ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S)) +#define LEDC_DUTY_LSCH3_V 0x1FFFFFF +#define LEDC_DUTY_LSCH3_S 0 + +#define LEDC_LSCH4_CONF0_REG (DR_REG_LEDC_BASE + 0x00F0) +/* LEDC_PARA_UP_LSCH4 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This bit is used to update register LEDC_LSCH4_HPOINT and LEDC_LSCH4_DUTY + for low speed channel4.*/ +#define LEDC_PARA_UP_LSCH4 (BIT(4)) +#define LEDC_PARA_UP_LSCH4_M (BIT(4)) +#define LEDC_PARA_UP_LSCH4_V 0x1 +#define LEDC_PARA_UP_LSCH4_S 4 +/* LEDC_IDLE_LV_LSCH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when low speed channel4 is off.*/ +#define LEDC_IDLE_LV_LSCH4 (BIT(3)) +#define LEDC_IDLE_LV_LSCH4_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH4_V 0x1 +#define LEDC_IDLE_LV_LSCH4_S 3 +/* LEDC_SIG_OUT_EN_LSCH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for low speed channel4.*/ +#define LEDC_SIG_OUT_EN_LSCH4 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH4_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH4_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH4_S 2 +/* LEDC_TIMER_SEL_LSCH4 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four low speed timers the two bits are used to select + one of them for low speed channel4. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ +#define LEDC_TIMER_SEL_LSCH4 0x00000003 +#define LEDC_TIMER_SEL_LSCH4_M ((LEDC_TIMER_SEL_LSCH4_V)<<(LEDC_TIMER_SEL_LSCH4_S)) +#define LEDC_TIMER_SEL_LSCH4_V 0x3 +#define LEDC_TIMER_SEL_LSCH4_S 0 + +#define LEDC_LSCH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x00F4) +/* LEDC_HPOINT_LSCH4 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when lstimerx(x=[0 3]) selected + by low speed channel4 has reached reg_hpoint_lsch4[19:0]*/ +#define LEDC_HPOINT_LSCH4 0x000FFFFF +#define LEDC_HPOINT_LSCH4_M ((LEDC_HPOINT_LSCH4_V)<<(LEDC_HPOINT_LSCH4_S)) +#define LEDC_HPOINT_LSCH4_V 0xFFFFF +#define LEDC_HPOINT_LSCH4_S 0 + +#define LEDC_LSCH4_DUTY_REG (DR_REG_LEDC_BASE + 0x00F8) +/* LEDC_DUTY_LSCH4 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When lstimerx(x=[0 + 3]) choosed by low speed channel4 has reached reg_lpoint_lsch4 the output signal changes to low. reg_lpoint_lsch4=(reg_hpoint_lsch4[19:0]+reg_duty_lsch4[24:4]) (1) reg_lpoint_lsch4=(reg_hpoint_lsch4[19:0]+reg_duty_lsch4[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_LSCH4 0x01FFFFFF +#define LEDC_DUTY_LSCH4_M ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S)) +#define LEDC_DUTY_LSCH4_V 0x1FFFFFF +#define LEDC_DUTY_LSCH4_S 0 + +#define LEDC_LSCH4_CONF1_REG (DR_REG_LEDC_BASE + 0x00FC) +/* LEDC_DUTY_START_LSCH4 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch4 reg_duty_cycle_hsch4 and reg_duty_scale_hsch4 + has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_LSCH4 (BIT(31)) +#define LEDC_DUTY_START_LSCH4_M (BIT(31)) +#define LEDC_DUTY_START_LSCH4_V 0x1 +#define LEDC_DUTY_START_LSCH4_S 31 +/* LEDC_DUTY_INC_LSCH4 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for low speed channel4.*/ +#define LEDC_DUTY_INC_LSCH4 (BIT(30)) +#define LEDC_DUTY_INC_LSCH4_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH4_V 0x1 +#define LEDC_DUTY_INC_LSCH4_S 30 +/* LEDC_DUTY_NUM_LSCH4 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for low speed channel4.*/ +#define LEDC_DUTY_NUM_LSCH4 0x000003FF +#define LEDC_DUTY_NUM_LSCH4_M ((LEDC_DUTY_NUM_LSCH4_V)<<(LEDC_DUTY_NUM_LSCH4_S)) +#define LEDC_DUTY_NUM_LSCH4_V 0x3FF +#define LEDC_DUTY_NUM_LSCH4_S 20 +/* LEDC_DUTY_CYCLE_LSCH4 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_lsch4 cycles for low speed channel4.*/ +#define LEDC_DUTY_CYCLE_LSCH4 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH4_M ((LEDC_DUTY_CYCLE_LSCH4_V)<<(LEDC_DUTY_CYCLE_LSCH4_S)) +#define LEDC_DUTY_CYCLE_LSCH4_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH4_S 10 +/* LEDC_DUTY_SCALE_LSCH4 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + low speed channel4.*/ +#define LEDC_DUTY_SCALE_LSCH4 0x000003FF +#define LEDC_DUTY_SCALE_LSCH4_M ((LEDC_DUTY_SCALE_LSCH4_V)<<(LEDC_DUTY_SCALE_LSCH4_S)) +#define LEDC_DUTY_SCALE_LSCH4_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH4_S 0 + +#define LEDC_LSCH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0100) +/* LEDC_DUTY_LSCH4 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for low speed channel4.*/ +#define LEDC_DUTY_LSCH4 0x01FFFFFF +#define LEDC_DUTY_LSCH4_M ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S)) +#define LEDC_DUTY_LSCH4_V 0x1FFFFFF +#define LEDC_DUTY_LSCH4_S 0 + +#define LEDC_LSCH5_CONF0_REG (DR_REG_LEDC_BASE + 0x0104) +/* LEDC_PARA_UP_LSCH5 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This bit is used to update register LEDC_LSCH5_HPOINT and LEDC_LSCH5_DUTY + for low speed channel5.*/ +#define LEDC_PARA_UP_LSCH5 (BIT(4)) +#define LEDC_PARA_UP_LSCH5_M (BIT(4)) +#define LEDC_PARA_UP_LSCH5_V 0x1 +#define LEDC_PARA_UP_LSCH5_S 4 +/* LEDC_IDLE_LV_LSCH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when low speed channel5 is off.*/ +#define LEDC_IDLE_LV_LSCH5 (BIT(3)) +#define LEDC_IDLE_LV_LSCH5_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH5_V 0x1 +#define LEDC_IDLE_LV_LSCH5_S 3 +/* LEDC_SIG_OUT_EN_LSCH5 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for low speed channel5.*/ +#define LEDC_SIG_OUT_EN_LSCH5 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH5_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH5_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH5_S 2 +/* LEDC_TIMER_SEL_LSCH5 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four low speed timers the two bits are used to select + one of them for low speed channel5. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ +#define LEDC_TIMER_SEL_LSCH5 0x00000003 +#define LEDC_TIMER_SEL_LSCH5_M ((LEDC_TIMER_SEL_LSCH5_V)<<(LEDC_TIMER_SEL_LSCH5_S)) +#define LEDC_TIMER_SEL_LSCH5_V 0x3 +#define LEDC_TIMER_SEL_LSCH5_S 0 + +#define LEDC_LSCH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x0108) +/* LEDC_HPOINT_LSCH5 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when lstimerx(x=[0 3]) selected + by low speed channel5 has reached reg_hpoint_lsch5[19:0]*/ +#define LEDC_HPOINT_LSCH5 0x000FFFFF +#define LEDC_HPOINT_LSCH5_M ((LEDC_HPOINT_LSCH5_V)<<(LEDC_HPOINT_LSCH5_S)) +#define LEDC_HPOINT_LSCH5_V 0xFFFFF +#define LEDC_HPOINT_LSCH5_S 0 + +#define LEDC_LSCH5_DUTY_REG (DR_REG_LEDC_BASE + 0x010C) +/* LEDC_DUTY_LSCH5 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When lstimerx(x=[0 + 3]) choosed by low speed channel5 has reached reg_lpoint_lsch5 the output signal changes to low. reg_lpoint_lsch5=(reg_hpoint_lsch5[19:0]+reg_duty_lsch5[24:4]) (1) reg_lpoint_lsch5=(reg_hpoint_lsch5[19:0]+reg_duty_lsch5[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_LSCH5 0x01FFFFFF +#define LEDC_DUTY_LSCH5_M ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S)) +#define LEDC_DUTY_LSCH5_V 0x1FFFFFF +#define LEDC_DUTY_LSCH5_S 0 + +#define LEDC_LSCH5_CONF1_REG (DR_REG_LEDC_BASE + 0x0110) +/* LEDC_DUTY_START_LSCH5 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch4 reg_duty_cycle_hsch4 and reg_duty_scale_hsch4 + has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_LSCH5 (BIT(31)) +#define LEDC_DUTY_START_LSCH5_M (BIT(31)) +#define LEDC_DUTY_START_LSCH5_V 0x1 +#define LEDC_DUTY_START_LSCH5_S 31 +/* LEDC_DUTY_INC_LSCH5 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for low speed channel5.*/ +#define LEDC_DUTY_INC_LSCH5 (BIT(30)) +#define LEDC_DUTY_INC_LSCH5_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH5_V 0x1 +#define LEDC_DUTY_INC_LSCH5_S 30 +/* LEDC_DUTY_NUM_LSCH5 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for low speed channel5.*/ +#define LEDC_DUTY_NUM_LSCH5 0x000003FF +#define LEDC_DUTY_NUM_LSCH5_M ((LEDC_DUTY_NUM_LSCH5_V)<<(LEDC_DUTY_NUM_LSCH5_S)) +#define LEDC_DUTY_NUM_LSCH5_V 0x3FF +#define LEDC_DUTY_NUM_LSCH5_S 20 +/* LEDC_DUTY_CYCLE_LSCH5 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_lsch5 cycles for low speed channel4.*/ +#define LEDC_DUTY_CYCLE_LSCH5 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH5_M ((LEDC_DUTY_CYCLE_LSCH5_V)<<(LEDC_DUTY_CYCLE_LSCH5_S)) +#define LEDC_DUTY_CYCLE_LSCH5_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH5_S 10 +/* LEDC_DUTY_SCALE_LSCH5 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + low speed channel5.*/ +#define LEDC_DUTY_SCALE_LSCH5 0x000003FF +#define LEDC_DUTY_SCALE_LSCH5_M ((LEDC_DUTY_SCALE_LSCH5_V)<<(LEDC_DUTY_SCALE_LSCH5_S)) +#define LEDC_DUTY_SCALE_LSCH5_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH5_S 0 + +#define LEDC_LSCH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0114) +/* LEDC_DUTY_LSCH5 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for low speed channel5.*/ +#define LEDC_DUTY_LSCH5 0x01FFFFFF +#define LEDC_DUTY_LSCH5_M ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S)) +#define LEDC_DUTY_LSCH5_V 0x1FFFFFF +#define LEDC_DUTY_LSCH5_S 0 + +#define LEDC_LSCH6_CONF0_REG (DR_REG_LEDC_BASE + 0x0118) +/* LEDC_PARA_UP_LSCH6 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This bit is used to update register LEDC_LSCH6_HPOINT and LEDC_LSCH6_DUTY + for low speed channel6.*/ +#define LEDC_PARA_UP_LSCH6 (BIT(4)) +#define LEDC_PARA_UP_LSCH6_M (BIT(4)) +#define LEDC_PARA_UP_LSCH6_V 0x1 +#define LEDC_PARA_UP_LSCH6_S 4 +/* LEDC_IDLE_LV_LSCH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when low speed channel6 is off.*/ +#define LEDC_IDLE_LV_LSCH6 (BIT(3)) +#define LEDC_IDLE_LV_LSCH6_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH6_V 0x1 +#define LEDC_IDLE_LV_LSCH6_S 3 +/* LEDC_SIG_OUT_EN_LSCH6 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for low speed channel6.*/ +#define LEDC_SIG_OUT_EN_LSCH6 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH6_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH6_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH6_S 2 +/* LEDC_TIMER_SEL_LSCH6 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four low speed timers the two bits are used to select + one of them for low speed channel6. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ +#define LEDC_TIMER_SEL_LSCH6 0x00000003 +#define LEDC_TIMER_SEL_LSCH6_M ((LEDC_TIMER_SEL_LSCH6_V)<<(LEDC_TIMER_SEL_LSCH6_S)) +#define LEDC_TIMER_SEL_LSCH6_V 0x3 +#define LEDC_TIMER_SEL_LSCH6_S 0 + +#define LEDC_LSCH6_HPOINT_REG (DR_REG_LEDC_BASE + 0x011C) +/* LEDC_HPOINT_LSCH6 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when lstimerx(x=[0 3]) selected + by low speed channel6 has reached reg_hpoint_lsch6[19:0]*/ +#define LEDC_HPOINT_LSCH6 0x000FFFFF +#define LEDC_HPOINT_LSCH6_M ((LEDC_HPOINT_LSCH6_V)<<(LEDC_HPOINT_LSCH6_S)) +#define LEDC_HPOINT_LSCH6_V 0xFFFFF +#define LEDC_HPOINT_LSCH6_S 0 + +#define LEDC_LSCH6_DUTY_REG (DR_REG_LEDC_BASE + 0x0120) +/* LEDC_DUTY_LSCH6 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When lstimerx(x=[0 + 3]) choosed by low speed channel6 has reached reg_lpoint_lsch6 the output signal changes to low. reg_lpoint_lsch6=(reg_hpoint_lsch6[19:0]+reg_duty_lsch6[24:4]) (1) reg_lpoint_lsch6=(reg_hpoint_lsch6[19:0]+reg_duty_lsch6[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_LSCH6 0x01FFFFFF +#define LEDC_DUTY_LSCH6_M ((LEDC_DUTY_LSCH6_V)<<(LEDC_DUTY_LSCH6_S)) +#define LEDC_DUTY_LSCH6_V 0x1FFFFFF +#define LEDC_DUTY_LSCH6_S 0 + +#define LEDC_LSCH6_CONF1_REG (DR_REG_LEDC_BASE + 0x0124) +/* LEDC_DUTY_START_LSCH6 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch6 reg_duty_cycle_hsch6 and reg_duty_scale_hsch6 + has been configured. these register won't take effect until set reg_duty_start_hsch6. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_LSCH6 (BIT(31)) +#define LEDC_DUTY_START_LSCH6_M (BIT(31)) +#define LEDC_DUTY_START_LSCH6_V 0x1 +#define LEDC_DUTY_START_LSCH6_S 31 +/* LEDC_DUTY_INC_LSCH6 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for low speed channel6.*/ +#define LEDC_DUTY_INC_LSCH6 (BIT(30)) +#define LEDC_DUTY_INC_LSCH6_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH6_V 0x1 +#define LEDC_DUTY_INC_LSCH6_S 30 +/* LEDC_DUTY_NUM_LSCH6 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for low speed channel6.*/ +#define LEDC_DUTY_NUM_LSCH6 0x000003FF +#define LEDC_DUTY_NUM_LSCH6_M ((LEDC_DUTY_NUM_LSCH6_V)<<(LEDC_DUTY_NUM_LSCH6_S)) +#define LEDC_DUTY_NUM_LSCH6_V 0x3FF +#define LEDC_DUTY_NUM_LSCH6_S 20 +/* LEDC_DUTY_CYCLE_LSCH6 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_lsch6 cycles for low speed channel6.*/ +#define LEDC_DUTY_CYCLE_LSCH6 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH6_M ((LEDC_DUTY_CYCLE_LSCH6_V)<<(LEDC_DUTY_CYCLE_LSCH6_S)) +#define LEDC_DUTY_CYCLE_LSCH6_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH6_S 10 +/* LEDC_DUTY_SCALE_LSCH6 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + low speed channel6.*/ +#define LEDC_DUTY_SCALE_LSCH6 0x000003FF +#define LEDC_DUTY_SCALE_LSCH6_M ((LEDC_DUTY_SCALE_LSCH6_V)<<(LEDC_DUTY_SCALE_LSCH6_S)) +#define LEDC_DUTY_SCALE_LSCH6_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH6_S 0 + +#define LEDC_LSCH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0128) +/* LEDC_DUTY_LSCH6 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for low speed channel6.*/ +#define LEDC_DUTY_LSCH6 0x01FFFFFF +#define LEDC_DUTY_LSCH6_M ((LEDC_DUTY_LSCH6_V)<<(LEDC_DUTY_LSCH6_S)) +#define LEDC_DUTY_LSCH6_V 0x1FFFFFF +#define LEDC_DUTY_LSCH6_S 0 + +#define LEDC_LSCH7_CONF0_REG (DR_REG_LEDC_BASE + 0x012C) +/* LEDC_PARA_UP_LSCH7 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This bit is used to update register LEDC_LSCH7_HPOINT and LEDC_LSCH7_DUTY + for low speed channel7.*/ +#define LEDC_PARA_UP_LSCH7 (BIT(4)) +#define LEDC_PARA_UP_LSCH7_M (BIT(4)) +#define LEDC_PARA_UP_LSCH7_V 0x1 +#define LEDC_PARA_UP_LSCH7_S 4 +/* LEDC_IDLE_LV_LSCH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This bit is used to control the output value when low speed channel7 is off.*/ +#define LEDC_IDLE_LV_LSCH7 (BIT(3)) +#define LEDC_IDLE_LV_LSCH7_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH7_V 0x1 +#define LEDC_IDLE_LV_LSCH7_S 3 +/* LEDC_SIG_OUT_EN_LSCH7 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for low speed channel7.*/ +#define LEDC_SIG_OUT_EN_LSCH7 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH7_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH7_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH7_S 2 +/* LEDC_TIMER_SEL_LSCH7 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: There are four low speed timers the two bits are used to select + one of them for low speed channel7. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ +#define LEDC_TIMER_SEL_LSCH7 0x00000003 +#define LEDC_TIMER_SEL_LSCH7_M ((LEDC_TIMER_SEL_LSCH7_V)<<(LEDC_TIMER_SEL_LSCH7_S)) +#define LEDC_TIMER_SEL_LSCH7_V 0x3 +#define LEDC_TIMER_SEL_LSCH7_S 0 + +#define LEDC_LSCH7_HPOINT_REG (DR_REG_LEDC_BASE + 0x0130) +/* LEDC_HPOINT_LSCH7 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The output value changes to high when lstimerx(x=[0 3]) selected + by low speed channel7 has reached reg_hpoint_lsch7[19:0]*/ +#define LEDC_HPOINT_LSCH7 0x000FFFFF +#define LEDC_HPOINT_LSCH7_M ((LEDC_HPOINT_LSCH7_V)<<(LEDC_HPOINT_LSCH7_S)) +#define LEDC_HPOINT_LSCH7_V 0xFFFFF +#define LEDC_HPOINT_LSCH7_S 0 + +#define LEDC_LSCH7_DUTY_REG (DR_REG_LEDC_BASE + 0x0134) +/* LEDC_DUTY_LSCH7 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: The register is used to control output duty. When lstimerx(x=[0 + 3]) choosed by low speed channel7 has reached reg_lpoint_lsch7 the output signal changes to low. reg_lpoint_lsch7=(reg_hpoint_lsch7[19:0]+reg_duty_lsch7[24:4]) (1) reg_lpoint_lsch7=(reg_hpoint_lsch7[19:0]+reg_duty_lsch7[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ +#define LEDC_DUTY_LSCH7 0x01FFFFFF +#define LEDC_DUTY_LSCH7_M ((LEDC_DUTY_LSCH7_V)<<(LEDC_DUTY_LSCH7_S)) +#define LEDC_DUTY_LSCH7_V 0x1FFFFFF +#define LEDC_DUTY_LSCH7_S 0 + +#define LEDC_LSCH7_CONF1_REG (DR_REG_LEDC_BASE + 0x0138) +/* LEDC_DUTY_START_LSCH7 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: When reg_duty_num_hsch4 reg_duty_cycle_hsch4 and reg_duty_scale_hsch4 + has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware.*/ +#define LEDC_DUTY_START_LSCH7 (BIT(31)) +#define LEDC_DUTY_START_LSCH7_M (BIT(31)) +#define LEDC_DUTY_START_LSCH7_V 0x1 +#define LEDC_DUTY_START_LSCH7_S 31 +/* LEDC_DUTY_INC_LSCH7 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: This register is used to increase the duty of output signal or + decrease the duty of output signal for low speed channel4.*/ +#define LEDC_DUTY_INC_LSCH7 (BIT(30)) +#define LEDC_DUTY_INC_LSCH7_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH7_V 0x1 +#define LEDC_DUTY_INC_LSCH7_S 30 +/* LEDC_DUTY_NUM_LSCH7 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: This register is used to control the num of increased or decreased + times for low speed channel4.*/ +#define LEDC_DUTY_NUM_LSCH7 0x000003FF +#define LEDC_DUTY_NUM_LSCH7_M ((LEDC_DUTY_NUM_LSCH7_V)<<(LEDC_DUTY_NUM_LSCH7_S)) +#define LEDC_DUTY_NUM_LSCH7_V 0x3FF +#define LEDC_DUTY_NUM_LSCH7_S 20 +/* LEDC_DUTY_CYCLE_LSCH7 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: This register is used to increase or decrease the duty every + reg_duty_cycle_lsch7 cycles for low speed channel7.*/ +#define LEDC_DUTY_CYCLE_LSCH7 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH7_M ((LEDC_DUTY_CYCLE_LSCH7_V)<<(LEDC_DUTY_CYCLE_LSCH7_S)) +#define LEDC_DUTY_CYCLE_LSCH7_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH7_S 10 +/* LEDC_DUTY_SCALE_LSCH7 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register controls the increase or decrease step scale for + low speed channel7.*/ +#define LEDC_DUTY_SCALE_LSCH7 0x000003FF +#define LEDC_DUTY_SCALE_LSCH7_M ((LEDC_DUTY_SCALE_LSCH7_V)<<(LEDC_DUTY_SCALE_LSCH7_S)) +#define LEDC_DUTY_SCALE_LSCH7_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH7_S 0 + +#define LEDC_LSCH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x013C) +/* LEDC_DUTY_LSCH7 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ +/*description: This register represents the current duty of the output signal + for low speed channel7.*/ +#define LEDC_DUTY_LSCH7 0x01FFFFFF +#define LEDC_DUTY_LSCH7_M ((LEDC_DUTY_LSCH7_V)<<(LEDC_DUTY_LSCH7_S)) +#define LEDC_DUTY_LSCH7_V 0x1FFFFFF +#define LEDC_DUTY_LSCH7_S 0 + +#define LEDC_HSTIMER0_CONF_REG (DR_REG_LEDC_BASE + 0x0140) +/* LEDC_TICK_SEL_HSTIMER0 : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: This bit is used to choose apb_clk or ref_tick for high speed + timer0. 1'b1:apb_clk 0:ref_tick*/ +#define LEDC_TICK_SEL_HSTIMER0 (BIT(25)) +#define LEDC_TICK_SEL_HSTIMER0_M (BIT(25)) +#define LEDC_TICK_SEL_HSTIMER0_V 0x1 +#define LEDC_TICK_SEL_HSTIMER0_S 25 +/* LEDC_HSTIMER0_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: This bit is used to reset high speed timer0 the counter will be 0 after reset.*/ +#define LEDC_HSTIMER0_RST (BIT(24)) +#define LEDC_HSTIMER0_RST_M (BIT(24)) +#define LEDC_HSTIMER0_RST_V 0x1 +#define LEDC_HSTIMER0_RST_S 24 +/* LEDC_HSTIMER0_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: This bit is used to pause the counter in high speed timer0*/ +#define LEDC_HSTIMER0_PAUSE (BIT(23)) +#define LEDC_HSTIMER0_PAUSE_M (BIT(23)) +#define LEDC_HSTIMER0_PAUSE_V 0x1 +#define LEDC_HSTIMER0_PAUSE_S 23 +/* LEDC_DIV_NUM_HSTIMER0 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ +/*description: This register is used to configure parameter for divider in high + speed timer0 the least significant eight bits represent the decimal part.*/ +#define LEDC_DIV_NUM_HSTIMER0 0x0003FFFF +#define LEDC_DIV_NUM_HSTIMER0_M ((LEDC_DIV_NUM_HSTIMER0_V)<<(LEDC_DIV_NUM_HSTIMER0_S)) +#define LEDC_DIV_NUM_HSTIMER0_V 0x3FFFF +#define LEDC_DIV_NUM_HSTIMER0_S 5 +/* LEDC_HSTIMER0_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: This register controls the range of the counter in high speed + timer0. the counter range is [0 2**reg_hstimer0_lim] the max bit width for counter is 20.*/ +#define LEDC_HSTIMER0_LIM 0x0000001F +#define LEDC_HSTIMER0_LIM_M ((LEDC_HSTIMER0_LIM_V)<<(LEDC_HSTIMER0_LIM_S)) +#define LEDC_HSTIMER0_LIM_V 0x1F +#define LEDC_HSTIMER0_LIM_S 0 + +#define LEDC_HSTIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0x0144) +/* LEDC_HSTIMER0_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: software can read this register to get the current counter value + in high speed timer0*/ +#define LEDC_HSTIMER0_CNT 0x000FFFFF +#define LEDC_HSTIMER0_CNT_M ((LEDC_HSTIMER0_CNT_V)<<(LEDC_HSTIMER0_CNT_S)) +#define LEDC_HSTIMER0_CNT_V 0xFFFFF +#define LEDC_HSTIMER0_CNT_S 0 + +#define LEDC_HSTIMER1_CONF_REG (DR_REG_LEDC_BASE + 0x0148) +/* LEDC_TICK_SEL_HSTIMER1 : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: This bit is used to choose apb_clk or ref_tick for high speed + timer1. 1'b1:apb_clk 0:ref_tick*/ +#define LEDC_TICK_SEL_HSTIMER1 (BIT(25)) +#define LEDC_TICK_SEL_HSTIMER1_M (BIT(25)) +#define LEDC_TICK_SEL_HSTIMER1_V 0x1 +#define LEDC_TICK_SEL_HSTIMER1_S 25 +/* LEDC_HSTIMER1_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: This bit is used to reset high speed timer1 the counter will be 0 after reset.*/ +#define LEDC_HSTIMER1_RST (BIT(24)) +#define LEDC_HSTIMER1_RST_M (BIT(24)) +#define LEDC_HSTIMER1_RST_V 0x1 +#define LEDC_HSTIMER1_RST_S 24 +/* LEDC_HSTIMER1_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: This bit is used to pause the counter in high speed timer1*/ +#define LEDC_HSTIMER1_PAUSE (BIT(23)) +#define LEDC_HSTIMER1_PAUSE_M (BIT(23)) +#define LEDC_HSTIMER1_PAUSE_V 0x1 +#define LEDC_HSTIMER1_PAUSE_S 23 +/* LEDC_DIV_NUM_HSTIMER1 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ +/*description: This register is used to configure parameter for divider in high + speed timer1 the least significant eight bits represent the decimal part.*/ +#define LEDC_DIV_NUM_HSTIMER1 0x0003FFFF +#define LEDC_DIV_NUM_HSTIMER1_M ((LEDC_DIV_NUM_HSTIMER1_V)<<(LEDC_DIV_NUM_HSTIMER1_S)) +#define LEDC_DIV_NUM_HSTIMER1_V 0x3FFFF +#define LEDC_DIV_NUM_HSTIMER1_S 5 +/* LEDC_HSTIMER1_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: This register controls the range of the counter in high speed + timer1. the counter range is [0 2**reg_hstimer1_lim] the max bit width for counter is 20.*/ +#define LEDC_HSTIMER1_LIM 0x0000001F +#define LEDC_HSTIMER1_LIM_M ((LEDC_HSTIMER1_LIM_V)<<(LEDC_HSTIMER1_LIM_S)) +#define LEDC_HSTIMER1_LIM_V 0x1F +#define LEDC_HSTIMER1_LIM_S 0 + +#define LEDC_HSTIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0x014C) +/* LEDC_HSTIMER1_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: software can read this register to get the current counter value + in high speed timer1.*/ +#define LEDC_HSTIMER1_CNT 0x000FFFFF +#define LEDC_HSTIMER1_CNT_M ((LEDC_HSTIMER1_CNT_V)<<(LEDC_HSTIMER1_CNT_S)) +#define LEDC_HSTIMER1_CNT_V 0xFFFFF +#define LEDC_HSTIMER1_CNT_S 0 + +#define LEDC_HSTIMER2_CONF_REG (DR_REG_LEDC_BASE + 0x0150) +/* LEDC_TICK_SEL_HSTIMER2 : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: This bit is used to choose apb_clk or ref_tick for high speed + timer2. 1'b1:apb_clk 0:ref_tick*/ +#define LEDC_TICK_SEL_HSTIMER2 (BIT(25)) +#define LEDC_TICK_SEL_HSTIMER2_M (BIT(25)) +#define LEDC_TICK_SEL_HSTIMER2_V 0x1 +#define LEDC_TICK_SEL_HSTIMER2_S 25 +/* LEDC_HSTIMER2_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: This bit is used to reset high speed timer2 the counter will be 0 after reset.*/ +#define LEDC_HSTIMER2_RST (BIT(24)) +#define LEDC_HSTIMER2_RST_M (BIT(24)) +#define LEDC_HSTIMER2_RST_V 0x1 +#define LEDC_HSTIMER2_RST_S 24 +/* LEDC_HSTIMER2_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: This bit is used to pause the counter in high speed timer2*/ +#define LEDC_HSTIMER2_PAUSE (BIT(23)) +#define LEDC_HSTIMER2_PAUSE_M (BIT(23)) +#define LEDC_HSTIMER2_PAUSE_V 0x1 +#define LEDC_HSTIMER2_PAUSE_S 23 +/* LEDC_DIV_NUM_HSTIMER2 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ +/*description: This register is used to configure parameter for divider in high + speed timer2 the least significant eight bits represent the decimal part.*/ +#define LEDC_DIV_NUM_HSTIMER2 0x0003FFFF +#define LEDC_DIV_NUM_HSTIMER2_M ((LEDC_DIV_NUM_HSTIMER2_V)<<(LEDC_DIV_NUM_HSTIMER2_S)) +#define LEDC_DIV_NUM_HSTIMER2_V 0x3FFFF +#define LEDC_DIV_NUM_HSTIMER2_S 5 +/* LEDC_HSTIMER2_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: This register controls the range of the counter in high speed + timer2. the counter range is [0 2**reg_hstimer2_lim] the max bit width for counter is 20.*/ +#define LEDC_HSTIMER2_LIM 0x0000001F +#define LEDC_HSTIMER2_LIM_M ((LEDC_HSTIMER2_LIM_V)<<(LEDC_HSTIMER2_LIM_S)) +#define LEDC_HSTIMER2_LIM_V 0x1F +#define LEDC_HSTIMER2_LIM_S 0 + +#define LEDC_HSTIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0x0154) +/* LEDC_HSTIMER2_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: software can read this register to get the current counter value + in high speed timer2*/ +#define LEDC_HSTIMER2_CNT 0x000FFFFF +#define LEDC_HSTIMER2_CNT_M ((LEDC_HSTIMER2_CNT_V)<<(LEDC_HSTIMER2_CNT_S)) +#define LEDC_HSTIMER2_CNT_V 0xFFFFF +#define LEDC_HSTIMER2_CNT_S 0 + +#define LEDC_HSTIMER3_CONF_REG (DR_REG_LEDC_BASE + 0x0158) +/* LEDC_TICK_SEL_HSTIMER3 : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: This bit is used to choose apb_clk or ref_tick for high speed + timer3. 1'b1:apb_clk 0:ref_tick*/ +#define LEDC_TICK_SEL_HSTIMER3 (BIT(25)) +#define LEDC_TICK_SEL_HSTIMER3_M (BIT(25)) +#define LEDC_TICK_SEL_HSTIMER3_V 0x1 +#define LEDC_TICK_SEL_HSTIMER3_S 25 +/* LEDC_HSTIMER3_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: This bit is used to reset high speed timer3 the counter will be 0 after reset.*/ +#define LEDC_HSTIMER3_RST (BIT(24)) +#define LEDC_HSTIMER3_RST_M (BIT(24)) +#define LEDC_HSTIMER3_RST_V 0x1 +#define LEDC_HSTIMER3_RST_S 24 +/* LEDC_HSTIMER3_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: This bit is used to pause the counter in high speed timer3*/ +#define LEDC_HSTIMER3_PAUSE (BIT(23)) +#define LEDC_HSTIMER3_PAUSE_M (BIT(23)) +#define LEDC_HSTIMER3_PAUSE_V 0x1 +#define LEDC_HSTIMER3_PAUSE_S 23 +/* LEDC_DIV_NUM_HSTIMER3 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ +/*description: This register is used to configure parameter for divider in high + speed timer3 the least significant eight bits represent the decimal part.*/ +#define LEDC_DIV_NUM_HSTIMER3 0x0003FFFF +#define LEDC_DIV_NUM_HSTIMER3_M ((LEDC_DIV_NUM_HSTIMER3_V)<<(LEDC_DIV_NUM_HSTIMER3_S)) +#define LEDC_DIV_NUM_HSTIMER3_V 0x3FFFF +#define LEDC_DIV_NUM_HSTIMER3_S 5 +/* LEDC_HSTIMER3_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: This register controls the range of the counter in high speed + timer3. the counter range is [0 2**reg_hstimer3_lim] the max bit width for counter is 20.*/ +#define LEDC_HSTIMER3_LIM 0x0000001F +#define LEDC_HSTIMER3_LIM_M ((LEDC_HSTIMER3_LIM_V)<<(LEDC_HSTIMER3_LIM_S)) +#define LEDC_HSTIMER3_LIM_V 0x1F +#define LEDC_HSTIMER3_LIM_S 0 + +#define LEDC_HSTIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0x015C) +/* LEDC_HSTIMER3_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: software can read this register to get the current counter value + in high speed timer3*/ +#define LEDC_HSTIMER3_CNT 0x000FFFFF +#define LEDC_HSTIMER3_CNT_M ((LEDC_HSTIMER3_CNT_V)<<(LEDC_HSTIMER3_CNT_S)) +#define LEDC_HSTIMER3_CNT_V 0xFFFFF +#define LEDC_HSTIMER3_CNT_S 0 + +#define LEDC_LSTIMER0_CONF_REG (DR_REG_LEDC_BASE + 0x0160) +/* LEDC_LSTIMER0_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */ +/*description: Set this bit to update reg_div_num_lstime0 and reg_lstimer0_lim.*/ +#define LEDC_LSTIMER0_PARA_UP (BIT(26)) +#define LEDC_LSTIMER0_PARA_UP_M (BIT(26)) +#define LEDC_LSTIMER0_PARA_UP_V 0x1 +#define LEDC_LSTIMER0_PARA_UP_S 26 +/* LEDC_TICK_SEL_LSTIMER0 : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: This bit is used to choose slow_clk or ref_tick for low speed + timer0. 1'b1:slow_clk 0:ref_tick*/ +#define LEDC_TICK_SEL_LSTIMER0 (BIT(25)) +#define LEDC_TICK_SEL_LSTIMER0_M (BIT(25)) +#define LEDC_TICK_SEL_LSTIMER0_V 0x1 +#define LEDC_TICK_SEL_LSTIMER0_S 25 +/* LEDC_LSTIMER0_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: This bit is used to reset low speed timer0 the counter will be 0 after reset.*/ +#define LEDC_LSTIMER0_RST (BIT(24)) +#define LEDC_LSTIMER0_RST_M (BIT(24)) +#define LEDC_LSTIMER0_RST_V 0x1 +#define LEDC_LSTIMER0_RST_S 24 +/* LEDC_LSTIMER0_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: This bit is used to pause the counter in low speed timer0.*/ +#define LEDC_LSTIMER0_PAUSE (BIT(23)) +#define LEDC_LSTIMER0_PAUSE_M (BIT(23)) +#define LEDC_LSTIMER0_PAUSE_V 0x1 +#define LEDC_LSTIMER0_PAUSE_S 23 +/* LEDC_DIV_NUM_LSTIMER0 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ +/*description: This register is used to configure parameter for divider in low + speed timer0 the least significant eight bits represent the decimal part.*/ +#define LEDC_DIV_NUM_LSTIMER0 0x0003FFFF +#define LEDC_DIV_NUM_LSTIMER0_M ((LEDC_DIV_NUM_LSTIMER0_V)<<(LEDC_DIV_NUM_LSTIMER0_S)) +#define LEDC_DIV_NUM_LSTIMER0_V 0x3FFFF +#define LEDC_DIV_NUM_LSTIMER0_S 5 +/* LEDC_LSTIMER0_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: This register controls the range of the counter in low speed + timer0. the counter range is [0 2**reg_lstimer0_lim] the max bit width for counter is 20.*/ +#define LEDC_LSTIMER0_LIM 0x0000001F +#define LEDC_LSTIMER0_LIM_M ((LEDC_LSTIMER0_LIM_V)<<(LEDC_LSTIMER0_LIM_S)) +#define LEDC_LSTIMER0_LIM_V 0x1F +#define LEDC_LSTIMER0_LIM_S 0 + +#define LEDC_LSTIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0x0164) +/* LEDC_LSTIMER0_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: software can read this register to get the current counter value + in low speed timer0.*/ +#define LEDC_LSTIMER0_CNT 0x000FFFFF +#define LEDC_LSTIMER0_CNT_M ((LEDC_LSTIMER0_CNT_V)<<(LEDC_LSTIMER0_CNT_S)) +#define LEDC_LSTIMER0_CNT_V 0xFFFFF +#define LEDC_LSTIMER0_CNT_S 0 + +#define LEDC_LSTIMER1_CONF_REG (DR_REG_LEDC_BASE + 0x0168) +/* LEDC_LSTIMER1_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */ +/*description: Set this bit to update reg_div_num_lstime1 and reg_lstimer1_lim.*/ +#define LEDC_LSTIMER1_PARA_UP (BIT(26)) +#define LEDC_LSTIMER1_PARA_UP_M (BIT(26)) +#define LEDC_LSTIMER1_PARA_UP_V 0x1 +#define LEDC_LSTIMER1_PARA_UP_S 26 +/* LEDC_TICK_SEL_LSTIMER1 : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: This bit is used to choose slow_clk or ref_tick for low speed + timer1. 1'b1:slow_clk 0:ref_tick*/ +#define LEDC_TICK_SEL_LSTIMER1 (BIT(25)) +#define LEDC_TICK_SEL_LSTIMER1_M (BIT(25)) +#define LEDC_TICK_SEL_LSTIMER1_V 0x1 +#define LEDC_TICK_SEL_LSTIMER1_S 25 +/* LEDC_LSTIMER1_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: This bit is used to reset low speed timer1 the counter will be 0 after reset.*/ +#define LEDC_LSTIMER1_RST (BIT(24)) +#define LEDC_LSTIMER1_RST_M (BIT(24)) +#define LEDC_LSTIMER1_RST_V 0x1 +#define LEDC_LSTIMER1_RST_S 24 +/* LEDC_LSTIMER1_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: This bit is used to pause the counter in low speed timer1.*/ +#define LEDC_LSTIMER1_PAUSE (BIT(23)) +#define LEDC_LSTIMER1_PAUSE_M (BIT(23)) +#define LEDC_LSTIMER1_PAUSE_V 0x1 +#define LEDC_LSTIMER1_PAUSE_S 23 +/* LEDC_DIV_NUM_LSTIMER1 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ +/*description: This register is used to configure parameter for divider in low + speed timer1 the least significant eight bits represent the decimal part.*/ +#define LEDC_DIV_NUM_LSTIMER1 0x0003FFFF +#define LEDC_DIV_NUM_LSTIMER1_M ((LEDC_DIV_NUM_LSTIMER1_V)<<(LEDC_DIV_NUM_LSTIMER1_S)) +#define LEDC_DIV_NUM_LSTIMER1_V 0x3FFFF +#define LEDC_DIV_NUM_LSTIMER1_S 5 +/* LEDC_LSTIMER1_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: This register controls the range of the counter in low speed + timer1. the counter range is [0 2**reg_lstimer1_lim] the max bit width for counter is 20.*/ +#define LEDC_LSTIMER1_LIM 0x0000001F +#define LEDC_LSTIMER1_LIM_M ((LEDC_LSTIMER1_LIM_V)<<(LEDC_LSTIMER1_LIM_S)) +#define LEDC_LSTIMER1_LIM_V 0x1F +#define LEDC_LSTIMER1_LIM_S 0 + +#define LEDC_LSTIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0x016C) +/* LEDC_LSTIMER1_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: software can read this register to get the current counter value + in low speed timer1.*/ +#define LEDC_LSTIMER1_CNT 0x000FFFFF +#define LEDC_LSTIMER1_CNT_M ((LEDC_LSTIMER1_CNT_V)<<(LEDC_LSTIMER1_CNT_S)) +#define LEDC_LSTIMER1_CNT_V 0xFFFFF +#define LEDC_LSTIMER1_CNT_S 0 + +#define LEDC_LSTIMER2_CONF_REG (DR_REG_LEDC_BASE + 0x0170) +/* LEDC_LSTIMER2_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */ +/*description: Set this bit to update reg_div_num_lstime2 and reg_lstimer2_lim.*/ +#define LEDC_LSTIMER2_PARA_UP (BIT(26)) +#define LEDC_LSTIMER2_PARA_UP_M (BIT(26)) +#define LEDC_LSTIMER2_PARA_UP_V 0x1 +#define LEDC_LSTIMER2_PARA_UP_S 26 +/* LEDC_TICK_SEL_LSTIMER2 : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: This bit is used to choose slow_clk or ref_tick for low speed + timer2. 1'b1:slow_clk 0:ref_tick*/ +#define LEDC_TICK_SEL_LSTIMER2 (BIT(25)) +#define LEDC_TICK_SEL_LSTIMER2_M (BIT(25)) +#define LEDC_TICK_SEL_LSTIMER2_V 0x1 +#define LEDC_TICK_SEL_LSTIMER2_S 25 +/* LEDC_LSTIMER2_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: This bit is used to reset low speed timer2 the counter will be 0 after reset.*/ +#define LEDC_LSTIMER2_RST (BIT(24)) +#define LEDC_LSTIMER2_RST_M (BIT(24)) +#define LEDC_LSTIMER2_RST_V 0x1 +#define LEDC_LSTIMER2_RST_S 24 +/* LEDC_LSTIMER2_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: This bit is used to pause the counter in low speed timer2.*/ +#define LEDC_LSTIMER2_PAUSE (BIT(23)) +#define LEDC_LSTIMER2_PAUSE_M (BIT(23)) +#define LEDC_LSTIMER2_PAUSE_V 0x1 +#define LEDC_LSTIMER2_PAUSE_S 23 +/* LEDC_DIV_NUM_LSTIMER2 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ +/*description: This register is used to configure parameter for divider in low + speed timer2 the least significant eight bits represent the decimal part.*/ +#define LEDC_DIV_NUM_LSTIMER2 0x0003FFFF +#define LEDC_DIV_NUM_LSTIMER2_M ((LEDC_DIV_NUM_LSTIMER2_V)<<(LEDC_DIV_NUM_LSTIMER2_S)) +#define LEDC_DIV_NUM_LSTIMER2_V 0x3FFFF +#define LEDC_DIV_NUM_LSTIMER2_S 5 +/* LEDC_LSTIMER2_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: This register controls the range of the counter in low speed + timer2. the counter range is [0 2**reg_lstimer2_lim] the max bit width for counter is 20.*/ +#define LEDC_LSTIMER2_LIM 0x0000001F +#define LEDC_LSTIMER2_LIM_M ((LEDC_LSTIMER2_LIM_V)<<(LEDC_LSTIMER2_LIM_S)) +#define LEDC_LSTIMER2_LIM_V 0x1F +#define LEDC_LSTIMER2_LIM_S 0 + +#define LEDC_LSTIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0x0174) +/* LEDC_LSTIMER2_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: software can read this register to get the current counter value + in low speed timer2.*/ +#define LEDC_LSTIMER2_CNT 0x000FFFFF +#define LEDC_LSTIMER2_CNT_M ((LEDC_LSTIMER2_CNT_V)<<(LEDC_LSTIMER2_CNT_S)) +#define LEDC_LSTIMER2_CNT_V 0xFFFFF +#define LEDC_LSTIMER2_CNT_S 0 + +#define LEDC_LSTIMER3_CONF_REG (DR_REG_LEDC_BASE + 0x0178) +/* LEDC_LSTIMER3_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */ +/*description: Set this bit to update reg_div_num_lstime3 and reg_lstimer3_lim.*/ +#define LEDC_LSTIMER3_PARA_UP (BIT(26)) +#define LEDC_LSTIMER3_PARA_UP_M (BIT(26)) +#define LEDC_LSTIMER3_PARA_UP_V 0x1 +#define LEDC_LSTIMER3_PARA_UP_S 26 +/* LEDC_TICK_SEL_LSTIMER3 : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: This bit is used to choose slow_clk or ref_tick for low speed + timer3. 1'b1:slow_clk 0:ref_tick*/ +#define LEDC_TICK_SEL_LSTIMER3 (BIT(25)) +#define LEDC_TICK_SEL_LSTIMER3_M (BIT(25)) +#define LEDC_TICK_SEL_LSTIMER3_V 0x1 +#define LEDC_TICK_SEL_LSTIMER3_S 25 +/* LEDC_LSTIMER3_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: This bit is used to reset low speed timer3 the counter will be 0 after reset.*/ +#define LEDC_LSTIMER3_RST (BIT(24)) +#define LEDC_LSTIMER3_RST_M (BIT(24)) +#define LEDC_LSTIMER3_RST_V 0x1 +#define LEDC_LSTIMER3_RST_S 24 +/* LEDC_LSTIMER3_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: This bit is used to pause the counter in low speed timer3.*/ +#define LEDC_LSTIMER3_PAUSE (BIT(23)) +#define LEDC_LSTIMER3_PAUSE_M (BIT(23)) +#define LEDC_LSTIMER3_PAUSE_V 0x1 +#define LEDC_LSTIMER3_PAUSE_S 23 +/* LEDC_DIV_NUM_LSTIMER3 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ +/*description: This register is used to configure parameter for divider in low + speed timer3 the least significant eight bits represent the decimal part.*/ +#define LEDC_DIV_NUM_LSTIMER3 0x0003FFFF +#define LEDC_DIV_NUM_LSTIMER3_M ((LEDC_DIV_NUM_LSTIMER3_V)<<(LEDC_DIV_NUM_LSTIMER3_S)) +#define LEDC_DIV_NUM_LSTIMER3_V 0x3FFFF +#define LEDC_DIV_NUM_LSTIMER3_S 5 +/* LEDC_LSTIMER3_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +/*description: This register controls the range of the counter in low speed + timer3. the counter range is [0 2**reg_lstimer3_lim] the max bit width for counter is 20.*/ +#define LEDC_LSTIMER3_LIM 0x0000001F +#define LEDC_LSTIMER3_LIM_M ((LEDC_LSTIMER3_LIM_V)<<(LEDC_LSTIMER3_LIM_S)) +#define LEDC_LSTIMER3_LIM_V 0x1F +#define LEDC_LSTIMER3_LIM_S 0 + +#define LEDC_LSTIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0x017C) +/* LEDC_LSTIMER3_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: software can read this register to get the current counter value + in low speed timer3.*/ +#define LEDC_LSTIMER3_CNT 0x000FFFFF +#define LEDC_LSTIMER3_CNT_M ((LEDC_LSTIMER3_CNT_V)<<(LEDC_LSTIMER3_CNT_S)) +#define LEDC_LSTIMER3_CNT_V 0xFFFFF +#define LEDC_LSTIMER3_CNT_S 0 + +#define LEDC_INT_RAW_REG (DR_REG_LEDC_BASE + 0x0180) +/* LEDC_DUTY_CHNG_END_LSCH7_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel 7 duty change done.*/ +#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW (BIT(23)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_M (BIT(23)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_S 23 +/* LEDC_DUTY_CHNG_END_LSCH6_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel 6 duty change done.*/ +#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW (BIT(22)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_M (BIT(22)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_S 22 +/* LEDC_DUTY_CHNG_END_LSCH5_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel 5 duty change done.*/ +#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW (BIT(21)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_M (BIT(21)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_S 21 +/* LEDC_DUTY_CHNG_END_LSCH4_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel 4 duty change done.*/ +#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW (BIT(20)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_M (BIT(20)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_S 20 +/* LEDC_DUTY_CHNG_END_LSCH3_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel 3 duty change done.*/ +#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW (BIT(19)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_M (BIT(19)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_S 19 +/* LEDC_DUTY_CHNG_END_LSCH2_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel 2 duty change done.*/ +#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW (BIT(18)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_M (BIT(18)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_S 18 +/* LEDC_DUTY_CHNG_END_LSCH1_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel 1 duty change done.*/ +#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW (BIT(17)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_M (BIT(17)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_S 17 +/* LEDC_DUTY_CHNG_END_LSCH0_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel 0 duty change done.*/ +#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW (BIT(16)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_M (BIT(16)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_S 16 +/* LEDC_DUTY_CHNG_END_HSCH7_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel 7 duty change done.*/ +#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW (BIT(15)) +#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_M (BIT(15)) +#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_S 15 +/* LEDC_DUTY_CHNG_END_HSCH6_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel 6 duty change done.*/ +#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW (BIT(14)) +#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_M (BIT(14)) +#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_S 14 +/* LEDC_DUTY_CHNG_END_HSCH5_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel 5 duty change done.*/ +#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW (BIT(13)) +#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_M (BIT(13)) +#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_S 13 +/* LEDC_DUTY_CHNG_END_HSCH4_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel 4 duty change done.*/ +#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW (BIT(12)) +#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_M (BIT(12)) +#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_S 12 +/* LEDC_DUTY_CHNG_END_HSCH3_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel 3 duty change done.*/ +#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW (BIT(11)) +#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_M (BIT(11)) +#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_S 11 +/* LEDC_DUTY_CHNG_END_HSCH2_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel 2 duty change done.*/ +#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW (BIT(10)) +#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_M (BIT(10)) +#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_S 10 +/* LEDC_DUTY_CHNG_END_HSCH1_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel 1 duty change done.*/ +#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW (BIT(9)) +#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_M (BIT(9)) +#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_S 9 +/* LEDC_DUTY_CHNG_END_HSCH0_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel 0 duty change done.*/ +#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW (BIT(8)) +#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_M (BIT(8)) +#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_S 8 +/* LEDC_LSTIMER3_OVF_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel3 counter overflow.*/ +#define LEDC_LSTIMER3_OVF_INT_RAW (BIT(7)) +#define LEDC_LSTIMER3_OVF_INT_RAW_M (BIT(7)) +#define LEDC_LSTIMER3_OVF_INT_RAW_V 0x1 +#define LEDC_LSTIMER3_OVF_INT_RAW_S 7 +/* LEDC_LSTIMER2_OVF_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel2 counter overflow.*/ +#define LEDC_LSTIMER2_OVF_INT_RAW (BIT(6)) +#define LEDC_LSTIMER2_OVF_INT_RAW_M (BIT(6)) +#define LEDC_LSTIMER2_OVF_INT_RAW_V 0x1 +#define LEDC_LSTIMER2_OVF_INT_RAW_S 6 +/* LEDC_LSTIMER1_OVF_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel1 counter overflow.*/ +#define LEDC_LSTIMER1_OVF_INT_RAW (BIT(5)) +#define LEDC_LSTIMER1_OVF_INT_RAW_M (BIT(5)) +#define LEDC_LSTIMER1_OVF_INT_RAW_V 0x1 +#define LEDC_LSTIMER1_OVF_INT_RAW_S 5 +/* LEDC_LSTIMER0_OVF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for low speed channel0 counter overflow.*/ +#define LEDC_LSTIMER0_OVF_INT_RAW (BIT(4)) +#define LEDC_LSTIMER0_OVF_INT_RAW_M (BIT(4)) +#define LEDC_LSTIMER0_OVF_INT_RAW_V 0x1 +#define LEDC_LSTIMER0_OVF_INT_RAW_S 4 +/* LEDC_HSTIMER3_OVF_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel3 counter overflow.*/ +#define LEDC_HSTIMER3_OVF_INT_RAW (BIT(3)) +#define LEDC_HSTIMER3_OVF_INT_RAW_M (BIT(3)) +#define LEDC_HSTIMER3_OVF_INT_RAW_V 0x1 +#define LEDC_HSTIMER3_OVF_INT_RAW_S 3 +/* LEDC_HSTIMER2_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel2 counter overflow.*/ +#define LEDC_HSTIMER2_OVF_INT_RAW (BIT(2)) +#define LEDC_HSTIMER2_OVF_INT_RAW_M (BIT(2)) +#define LEDC_HSTIMER2_OVF_INT_RAW_V 0x1 +#define LEDC_HSTIMER2_OVF_INT_RAW_S 2 +/* LEDC_HSTIMER1_OVF_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel1 counter overflow.*/ +#define LEDC_HSTIMER1_OVF_INT_RAW (BIT(1)) +#define LEDC_HSTIMER1_OVF_INT_RAW_M (BIT(1)) +#define LEDC_HSTIMER1_OVF_INT_RAW_V 0x1 +#define LEDC_HSTIMER1_OVF_INT_RAW_S 1 +/* LEDC_HSTIMER0_OVF_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for high speed channel0 counter overflow.*/ +#define LEDC_HSTIMER0_OVF_INT_RAW (BIT(0)) +#define LEDC_HSTIMER0_OVF_INT_RAW_M (BIT(0)) +#define LEDC_HSTIMER0_OVF_INT_RAW_V 0x1 +#define LEDC_HSTIMER0_OVF_INT_RAW_S 0 + +#define LEDC_INT_ST_REG (DR_REG_LEDC_BASE + 0x0184) +/* LEDC_DUTY_CHNG_END_LSCH7_INT_ST : RO ;bitpos:[23] ;default: 1'h0 ; */ +/*description: The interrupt status bit for low speed channel 7 duty change done event*/ +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST (BIT(23)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_M (BIT(23)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_S 23 +/* LEDC_DUTY_CHNG_END_LSCH6_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel 6 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST (BIT(22)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_M (BIT(22)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_S 22 +/* LEDC_DUTY_CHNG_END_LSCH5_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel 5 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST (BIT(21)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_M (BIT(21)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_S 21 +/* LEDC_DUTY_CHNG_END_LSCH4_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel 4 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST (BIT(20)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_M (BIT(20)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_S 20 +/* LEDC_DUTY_CHNG_END_LSCH3_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel 3 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST (BIT(19)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_M (BIT(19)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_S 19 +/* LEDC_DUTY_CHNG_END_LSCH2_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel 2 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST (BIT(18)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_M (BIT(18)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_S 18 +/* LEDC_DUTY_CHNG_END_LSCH1_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel 1 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST (BIT(17)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_M (BIT(17)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_S 17 +/* LEDC_DUTY_CHNG_END_LSCH0_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel 0 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST (BIT(16)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_M (BIT(16)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_S 16 +/* LEDC_DUTY_CHNG_END_HSCH7_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel 7 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST (BIT(15)) +#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_M (BIT(15)) +#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_S 15 +/* LEDC_DUTY_CHNG_END_HSCH6_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel 6 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST (BIT(14)) +#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_M (BIT(14)) +#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_S 14 +/* LEDC_DUTY_CHNG_END_HSCH5_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel 5 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST (BIT(13)) +#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_M (BIT(13)) +#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_S 13 +/* LEDC_DUTY_CHNG_END_HSCH4_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel 4 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST (BIT(12)) +#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_M (BIT(12)) +#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_S 12 +/* LEDC_DUTY_CHNG_END_HSCH3_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel 3 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST (BIT(11)) +#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_M (BIT(11)) +#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_S 11 +/* LEDC_DUTY_CHNG_END_HSCH2_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel 2 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST (BIT(10)) +#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_M (BIT(10)) +#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_S 10 +/* LEDC_DUTY_CHNG_END_HSCH1_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel 1 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST (BIT(9)) +#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_M (BIT(9)) +#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_S 9 +/* LEDC_DUTY_CHNG_END_HSCH0_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel 0 duty change done event.*/ +#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST (BIT(8)) +#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_M (BIT(8)) +#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_S 8 +/* LEDC_LSTIMER3_OVF_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel3 counter overflow event.*/ +#define LEDC_LSTIMER3_OVF_INT_ST (BIT(7)) +#define LEDC_LSTIMER3_OVF_INT_ST_M (BIT(7)) +#define LEDC_LSTIMER3_OVF_INT_ST_V 0x1 +#define LEDC_LSTIMER3_OVF_INT_ST_S 7 +/* LEDC_LSTIMER2_OVF_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel2 counter overflow event.*/ +#define LEDC_LSTIMER2_OVF_INT_ST (BIT(6)) +#define LEDC_LSTIMER2_OVF_INT_ST_M (BIT(6)) +#define LEDC_LSTIMER2_OVF_INT_ST_V 0x1 +#define LEDC_LSTIMER2_OVF_INT_ST_S 6 +/* LEDC_LSTIMER1_OVF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel1 counter overflow event.*/ +#define LEDC_LSTIMER1_OVF_INT_ST (BIT(5)) +#define LEDC_LSTIMER1_OVF_INT_ST_M (BIT(5)) +#define LEDC_LSTIMER1_OVF_INT_ST_V 0x1 +#define LEDC_LSTIMER1_OVF_INT_ST_S 5 +/* LEDC_LSTIMER0_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt status bit for low speed channel0 counter overflow event.*/ +#define LEDC_LSTIMER0_OVF_INT_ST (BIT(4)) +#define LEDC_LSTIMER0_OVF_INT_ST_M (BIT(4)) +#define LEDC_LSTIMER0_OVF_INT_ST_V 0x1 +#define LEDC_LSTIMER0_OVF_INT_ST_S 4 +/* LEDC_HSTIMER3_OVF_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel3 counter overflow event.*/ +#define LEDC_HSTIMER3_OVF_INT_ST (BIT(3)) +#define LEDC_HSTIMER3_OVF_INT_ST_M (BIT(3)) +#define LEDC_HSTIMER3_OVF_INT_ST_V 0x1 +#define LEDC_HSTIMER3_OVF_INT_ST_S 3 +/* LEDC_HSTIMER2_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel2 counter overflow event.*/ +#define LEDC_HSTIMER2_OVF_INT_ST (BIT(2)) +#define LEDC_HSTIMER2_OVF_INT_ST_M (BIT(2)) +#define LEDC_HSTIMER2_OVF_INT_ST_V 0x1 +#define LEDC_HSTIMER2_OVF_INT_ST_S 2 +/* LEDC_HSTIMER1_OVF_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel1 counter overflow event.*/ +#define LEDC_HSTIMER1_OVF_INT_ST (BIT(1)) +#define LEDC_HSTIMER1_OVF_INT_ST_M (BIT(1)) +#define LEDC_HSTIMER1_OVF_INT_ST_V 0x1 +#define LEDC_HSTIMER1_OVF_INT_ST_S 1 +/* LEDC_HSTIMER0_OVF_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt status bit for high speed channel0 counter overflow event.*/ +#define LEDC_HSTIMER0_OVF_INT_ST (BIT(0)) +#define LEDC_HSTIMER0_OVF_INT_ST_M (BIT(0)) +#define LEDC_HSTIMER0_OVF_INT_ST_V 0x1 +#define LEDC_HSTIMER0_OVF_INT_ST_S 0 + +#define LEDC_INT_ENA_REG (DR_REG_LEDC_BASE + 0x0188) +/* LEDC_DUTY_CHNG_END_LSCH7_INT_ENA : R/W ;bitpos:[23] ;default: 1'h0 ; */ +/*description: The interrupt enable bit for low speed channel 7 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA (BIT(23)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_M (BIT(23)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_S 23 +/* LEDC_DUTY_CHNG_END_LSCH6_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel 6 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA (BIT(22)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_M (BIT(22)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_S 22 +/* LEDC_DUTY_CHNG_END_LSCH5_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel 5 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA (BIT(21)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_M (BIT(21)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_S 21 +/* LEDC_DUTY_CHNG_END_LSCH4_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel 4 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA (BIT(20)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_M (BIT(20)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_S 20 +/* LEDC_DUTY_CHNG_END_LSCH3_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel 3 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA (BIT(19)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_M (BIT(19)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_S 19 +/* LEDC_DUTY_CHNG_END_LSCH2_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel 2 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA (BIT(18)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_M (BIT(18)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_S 18 +/* LEDC_DUTY_CHNG_END_LSCH1_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel 1 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA (BIT(17)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_M (BIT(17)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_S 17 +/* LEDC_DUTY_CHNG_END_LSCH0_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel 0 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA (BIT(16)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_M (BIT(16)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S 16 +/* LEDC_DUTY_CHNG_END_HSCH7_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel 7 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA (BIT(15)) +#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_M (BIT(15)) +#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_S 15 +/* LEDC_DUTY_CHNG_END_HSCH6_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel 6 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA (BIT(14)) +#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_M (BIT(14)) +#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_S 14 +/* LEDC_DUTY_CHNG_END_HSCH5_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel 5 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA (BIT(13)) +#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_M (BIT(13)) +#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_S 13 +/* LEDC_DUTY_CHNG_END_HSCH4_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel 4 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA (BIT(12)) +#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_M (BIT(12)) +#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_S 12 +/* LEDC_DUTY_CHNG_END_HSCH3_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel 3 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA (BIT(11)) +#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_M (BIT(11)) +#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_S 11 +/* LEDC_DUTY_CHNG_END_HSCH2_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel 2 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA (BIT(10)) +#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_M (BIT(10)) +#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_S 10 +/* LEDC_DUTY_CHNG_END_HSCH1_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel 1 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA (BIT(9)) +#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_M (BIT(9)) +#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_S 9 +/* LEDC_DUTY_CHNG_END_HSCH0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel 0 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA (BIT(8)) +#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_M (BIT(8)) +#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_S 8 +/* LEDC_LSTIMER3_OVF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel3 counter overflow interrupt.*/ +#define LEDC_LSTIMER3_OVF_INT_ENA (BIT(7)) +#define LEDC_LSTIMER3_OVF_INT_ENA_M (BIT(7)) +#define LEDC_LSTIMER3_OVF_INT_ENA_V 0x1 +#define LEDC_LSTIMER3_OVF_INT_ENA_S 7 +/* LEDC_LSTIMER2_OVF_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel2 counter overflow interrupt.*/ +#define LEDC_LSTIMER2_OVF_INT_ENA (BIT(6)) +#define LEDC_LSTIMER2_OVF_INT_ENA_M (BIT(6)) +#define LEDC_LSTIMER2_OVF_INT_ENA_V 0x1 +#define LEDC_LSTIMER2_OVF_INT_ENA_S 6 +/* LEDC_LSTIMER1_OVF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel1 counter overflow interrupt.*/ +#define LEDC_LSTIMER1_OVF_INT_ENA (BIT(5)) +#define LEDC_LSTIMER1_OVF_INT_ENA_M (BIT(5)) +#define LEDC_LSTIMER1_OVF_INT_ENA_V 0x1 +#define LEDC_LSTIMER1_OVF_INT_ENA_S 5 +/* LEDC_LSTIMER0_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for low speed channel0 counter overflow interrupt.*/ +#define LEDC_LSTIMER0_OVF_INT_ENA (BIT(4)) +#define LEDC_LSTIMER0_OVF_INT_ENA_M (BIT(4)) +#define LEDC_LSTIMER0_OVF_INT_ENA_V 0x1 +#define LEDC_LSTIMER0_OVF_INT_ENA_S 4 +/* LEDC_HSTIMER3_OVF_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel3 counter overflow interrupt.*/ +#define LEDC_HSTIMER3_OVF_INT_ENA (BIT(3)) +#define LEDC_HSTIMER3_OVF_INT_ENA_M (BIT(3)) +#define LEDC_HSTIMER3_OVF_INT_ENA_V 0x1 +#define LEDC_HSTIMER3_OVF_INT_ENA_S 3 +/* LEDC_HSTIMER2_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel2 counter overflow interrupt.*/ +#define LEDC_HSTIMER2_OVF_INT_ENA (BIT(2)) +#define LEDC_HSTIMER2_OVF_INT_ENA_M (BIT(2)) +#define LEDC_HSTIMER2_OVF_INT_ENA_V 0x1 +#define LEDC_HSTIMER2_OVF_INT_ENA_S 2 +/* LEDC_HSTIMER1_OVF_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel1 counter overflow interrupt.*/ +#define LEDC_HSTIMER1_OVF_INT_ENA (BIT(1)) +#define LEDC_HSTIMER1_OVF_INT_ENA_M (BIT(1)) +#define LEDC_HSTIMER1_OVF_INT_ENA_V 0x1 +#define LEDC_HSTIMER1_OVF_INT_ENA_S 1 +/* LEDC_HSTIMER0_OVF_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for high speed channel0 counter overflow interrupt.*/ +#define LEDC_HSTIMER0_OVF_INT_ENA (BIT(0)) +#define LEDC_HSTIMER0_OVF_INT_ENA_M (BIT(0)) +#define LEDC_HSTIMER0_OVF_INT_ENA_V 0x1 +#define LEDC_HSTIMER0_OVF_INT_ENA_S 0 + +#define LEDC_INT_CLR_REG (DR_REG_LEDC_BASE + 0x018C) +/* LEDC_DUTY_CHNG_END_LSCH7_INT_CLR : WO ;bitpos:[23] ;default: 1'h0 ; */ +/*description: Set this bit to clear low speed channel 7 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR (BIT(23)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_M (BIT(23)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_S 23 +/* LEDC_DUTY_CHNG_END_LSCH6_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel 6 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR (BIT(22)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_M (BIT(22)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_S 22 +/* LEDC_DUTY_CHNG_END_LSCH5_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel 5 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR (BIT(21)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_M (BIT(21)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_S 21 +/* LEDC_DUTY_CHNG_END_LSCH4_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel 4 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR (BIT(20)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_M (BIT(20)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_S 20 +/* LEDC_DUTY_CHNG_END_LSCH3_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel 3 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR (BIT(19)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_M (BIT(19)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_S 19 +/* LEDC_DUTY_CHNG_END_LSCH2_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel 2 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR (BIT(18)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_M (BIT(18)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_S 18 +/* LEDC_DUTY_CHNG_END_LSCH1_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel 1 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR (BIT(17)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_M (BIT(17)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_S 17 +/* LEDC_DUTY_CHNG_END_LSCH0_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel 0 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR (BIT(16)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_M (BIT(16)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_S 16 +/* LEDC_DUTY_CHNG_END_HSCH7_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel 7 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR (BIT(15)) +#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_M (BIT(15)) +#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_S 15 +/* LEDC_DUTY_CHNG_END_HSCH6_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel 6 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR (BIT(14)) +#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_M (BIT(14)) +#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_S 14 +/* LEDC_DUTY_CHNG_END_HSCH5_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel 5 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR (BIT(13)) +#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_M (BIT(13)) +#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_S 13 +/* LEDC_DUTY_CHNG_END_HSCH4_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel 4 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR (BIT(12)) +#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_M (BIT(12)) +#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_S 12 +/* LEDC_DUTY_CHNG_END_HSCH3_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel 3 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR (BIT(11)) +#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_M (BIT(11)) +#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_S 11 +/* LEDC_DUTY_CHNG_END_HSCH2_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel 2 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR (BIT(10)) +#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_M (BIT(10)) +#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_S 10 +/* LEDC_DUTY_CHNG_END_HSCH1_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel 1 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR (BIT(9)) +#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_M (BIT(9)) +#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_S 9 +/* LEDC_DUTY_CHNG_END_HSCH0_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel 0 duty change done interrupt.*/ +#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR (BIT(8)) +#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_M (BIT(8)) +#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_S 8 +/* LEDC_LSTIMER3_OVF_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel3 counter overflow interrupt.*/ +#define LEDC_LSTIMER3_OVF_INT_CLR (BIT(7)) +#define LEDC_LSTIMER3_OVF_INT_CLR_M (BIT(7)) +#define LEDC_LSTIMER3_OVF_INT_CLR_V 0x1 +#define LEDC_LSTIMER3_OVF_INT_CLR_S 7 +/* LEDC_LSTIMER2_OVF_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel2 counter overflow interrupt.*/ +#define LEDC_LSTIMER2_OVF_INT_CLR (BIT(6)) +#define LEDC_LSTIMER2_OVF_INT_CLR_M (BIT(6)) +#define LEDC_LSTIMER2_OVF_INT_CLR_V 0x1 +#define LEDC_LSTIMER2_OVF_INT_CLR_S 6 +/* LEDC_LSTIMER1_OVF_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel1 counter overflow interrupt.*/ +#define LEDC_LSTIMER1_OVF_INT_CLR (BIT(5)) +#define LEDC_LSTIMER1_OVF_INT_CLR_M (BIT(5)) +#define LEDC_LSTIMER1_OVF_INT_CLR_V 0x1 +#define LEDC_LSTIMER1_OVF_INT_CLR_S 5 +/* LEDC_LSTIMER0_OVF_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to clear low speed channel0 counter overflow interrupt.*/ +#define LEDC_LSTIMER0_OVF_INT_CLR (BIT(4)) +#define LEDC_LSTIMER0_OVF_INT_CLR_M (BIT(4)) +#define LEDC_LSTIMER0_OVF_INT_CLR_V 0x1 +#define LEDC_LSTIMER0_OVF_INT_CLR_S 4 +/* LEDC_HSTIMER3_OVF_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel3 counter overflow interrupt.*/ +#define LEDC_HSTIMER3_OVF_INT_CLR (BIT(3)) +#define LEDC_HSTIMER3_OVF_INT_CLR_M (BIT(3)) +#define LEDC_HSTIMER3_OVF_INT_CLR_V 0x1 +#define LEDC_HSTIMER3_OVF_INT_CLR_S 3 +/* LEDC_HSTIMER2_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel2 counter overflow interrupt.*/ +#define LEDC_HSTIMER2_OVF_INT_CLR (BIT(2)) +#define LEDC_HSTIMER2_OVF_INT_CLR_M (BIT(2)) +#define LEDC_HSTIMER2_OVF_INT_CLR_V 0x1 +#define LEDC_HSTIMER2_OVF_INT_CLR_S 2 +/* LEDC_HSTIMER1_OVF_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel1 counter overflow interrupt.*/ +#define LEDC_HSTIMER1_OVF_INT_CLR (BIT(1)) +#define LEDC_HSTIMER1_OVF_INT_CLR_M (BIT(1)) +#define LEDC_HSTIMER1_OVF_INT_CLR_V 0x1 +#define LEDC_HSTIMER1_OVF_INT_CLR_S 1 +/* LEDC_HSTIMER0_OVF_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear high speed channel0 counter overflow interrupt.*/ +#define LEDC_HSTIMER0_OVF_INT_CLR (BIT(0)) +#define LEDC_HSTIMER0_OVF_INT_CLR_M (BIT(0)) +#define LEDC_HSTIMER0_OVF_INT_CLR_V 0x1 +#define LEDC_HSTIMER0_OVF_INT_CLR_S 0 + +#define LEDC_CONF_REG (DR_REG_LEDC_BASE + 0x0190) +/* LEDC_APB_CLK_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit is used to set the frequency of slow_clk. 1'b1:80mhz 1'b0:8mhz*/ +#define LEDC_APB_CLK_SEL (BIT(0)) +#define LEDC_APB_CLK_SEL_M (BIT(0)) +#define LEDC_APB_CLK_SEL_V 0x1 +#define LEDC_APB_CLK_SEL_S 0 + +#define LEDC_DATE_REG (DR_REG_LEDC_BASE + 0x01FC) +/* LEDC_DATE : R/W ;bitpos:[31:0] ;default: 32'h16031700 ; */ +/*description: This register represents the version .*/ +#define LEDC_DATE 0xFFFFFFFF +#define LEDC_DATE_M ((LEDC_DATE_V)<<(LEDC_DATE_S)) +#define LEDC_DATE_V 0xFFFFFFFF +#define LEDC_DATE_S 0 + + + + +#endif /*_SOC_LEDC_REG_H_ */ + + diff --git a/components/soc/esp32/include/soc/pcnt_reg.h b/components/soc/esp32/include/soc/pcnt_reg.h index 9809faf73..fa7dedc25 100644 --- a/components/soc/esp32/include/soc/pcnt_reg.h +++ b/components/soc/esp32/include/soc/pcnt_reg.h @@ -1,1526 +1,1526 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_PCNT_REG_H_ -#define _SOC_PCNT_REG_H_ - - -#include "soc.h" -#define PCNT_U0_CONF0_REG (DR_REG_PCNT_BASE + 0x0000) -/* PCNT_CH1_LCTRL_MODE_U0 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's low control - signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH1_LCTRL_MODE_U0 0x00000003 -#define PCNT_CH1_LCTRL_MODE_U0_M ((PCNT_CH1_LCTRL_MODE_U0_V)<<(PCNT_CH1_LCTRL_MODE_U0_S)) -#define PCNT_CH1_LCTRL_MODE_U0_V 0x3 -#define PCNT_CH1_LCTRL_MODE_U0_S 30 -/* PCNT_CH1_HCTRL_MODE_U0 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's high - control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH1_HCTRL_MODE_U0 0x00000003 -#define PCNT_CH1_HCTRL_MODE_U0_M ((PCNT_CH1_HCTRL_MODE_U0_V)<<(PCNT_CH1_HCTRL_MODE_U0_S)) -#define PCNT_CH1_HCTRL_MODE_U0_V 0x3 -#define PCNT_CH1_HCTRL_MODE_U0_S 28 -/* PCNT_CH1_POS_MODE_U0 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - posedge signal for unit0. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ -#define PCNT_CH1_POS_MODE_U0 0x00000003 -#define PCNT_CH1_POS_MODE_U0_M ((PCNT_CH1_POS_MODE_U0_V)<<(PCNT_CH1_POS_MODE_U0_S)) -#define PCNT_CH1_POS_MODE_U0_V 0x3 -#define PCNT_CH1_POS_MODE_U0_S 26 -/* PCNT_CH1_NEG_MODE_U0 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - negedge signal for unit0. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ -#define PCNT_CH1_NEG_MODE_U0 0x00000003 -#define PCNT_CH1_NEG_MODE_U0_M ((PCNT_CH1_NEG_MODE_U0_V)<<(PCNT_CH1_NEG_MODE_U0_S)) -#define PCNT_CH1_NEG_MODE_U0_V 0x3 -#define PCNT_CH1_NEG_MODE_U0_S 24 -/* PCNT_CH0_LCTRL_MODE_U0 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's low control - signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH0_LCTRL_MODE_U0 0x00000003 -#define PCNT_CH0_LCTRL_MODE_U0_M ((PCNT_CH0_LCTRL_MODE_U0_V)<<(PCNT_CH0_LCTRL_MODE_U0_S)) -#define PCNT_CH0_LCTRL_MODE_U0_V 0x3 -#define PCNT_CH0_LCTRL_MODE_U0_S 22 -/* PCNT_CH0_HCTRL_MODE_U0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's high - control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH0_HCTRL_MODE_U0 0x00000003 -#define PCNT_CH0_HCTRL_MODE_U0_M ((PCNT_CH0_HCTRL_MODE_U0_V)<<(PCNT_CH0_HCTRL_MODE_U0_S)) -#define PCNT_CH0_HCTRL_MODE_U0_V 0x3 -#define PCNT_CH0_HCTRL_MODE_U0_S 20 -/* PCNT_CH0_POS_MODE_U0 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - posedge signal for unit0. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ -#define PCNT_CH0_POS_MODE_U0 0x00000003 -#define PCNT_CH0_POS_MODE_U0_M ((PCNT_CH0_POS_MODE_U0_V)<<(PCNT_CH0_POS_MODE_U0_S)) -#define PCNT_CH0_POS_MODE_U0_V 0x3 -#define PCNT_CH0_POS_MODE_U0_S 18 -/* PCNT_CH0_NEG_MODE_U0 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - negedge signal for unit0. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ -#define PCNT_CH0_NEG_MODE_U0 0x00000003 -#define PCNT_CH0_NEG_MODE_U0_M ((PCNT_CH0_NEG_MODE_U0_V)<<(PCNT_CH0_NEG_MODE_U0_S)) -#define PCNT_CH0_NEG_MODE_U0_V 0x3 -#define PCNT_CH0_NEG_MODE_U0_S 16 -/* PCNT_THR_THRES1_EN_U0 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit0's count with thres1 value .*/ -#define PCNT_THR_THRES1_EN_U0 (BIT(15)) -#define PCNT_THR_THRES1_EN_U0_M (BIT(15)) -#define PCNT_THR_THRES1_EN_U0_V 0x1 -#define PCNT_THR_THRES1_EN_U0_S 15 -/* PCNT_THR_THRES0_EN_U0 : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit0's count with thres0 value.*/ -#define PCNT_THR_THRES0_EN_U0 (BIT(14)) -#define PCNT_THR_THRES0_EN_U0_M (BIT(14)) -#define PCNT_THR_THRES0_EN_U0_V 0x1 -#define PCNT_THR_THRES0_EN_U0_S 14 -/* PCNT_THR_L_LIM_EN_U0 : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit0's count with thr_l_lim value.*/ -#define PCNT_THR_L_LIM_EN_U0 (BIT(13)) -#define PCNT_THR_L_LIM_EN_U0_M (BIT(13)) -#define PCNT_THR_L_LIM_EN_U0_V 0x1 -#define PCNT_THR_L_LIM_EN_U0_S 13 -/* PCNT_THR_H_LIM_EN_U0 : R/W ;bitpos:[12] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit0's count with thr_h_lim value.*/ -#define PCNT_THR_H_LIM_EN_U0 (BIT(12)) -#define PCNT_THR_H_LIM_EN_U0_M (BIT(12)) -#define PCNT_THR_H_LIM_EN_U0_V 0x1 -#define PCNT_THR_H_LIM_EN_U0_S 12 -/* PCNT_THR_ZERO_EN_U0 : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit0's count with 0 value.*/ -#define PCNT_THR_ZERO_EN_U0 (BIT(11)) -#define PCNT_THR_ZERO_EN_U0_M (BIT(11)) -#define PCNT_THR_ZERO_EN_U0_V 0x1 -#define PCNT_THR_ZERO_EN_U0_S 11 -/* PCNT_FILTER_EN_U0 : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: This is the enable bit for filtering input signals for unit0.*/ -#define PCNT_FILTER_EN_U0 (BIT(10)) -#define PCNT_FILTER_EN_U0_M (BIT(10)) -#define PCNT_FILTER_EN_U0_V 0x1 -#define PCNT_FILTER_EN_U0_S 10 -/* PCNT_FILTER_THRES_U0 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ -/*description: This register is used to filter pluse whose width is smaller - than this value for unit0.*/ -#define PCNT_FILTER_THRES_U0 0x000003FF -#define PCNT_FILTER_THRES_U0_M ((PCNT_FILTER_THRES_U0_V)<<(PCNT_FILTER_THRES_U0_S)) -#define PCNT_FILTER_THRES_U0_V 0x3FF -#define PCNT_FILTER_THRES_U0_S 0 - -#define PCNT_U0_CONF1_REG (DR_REG_PCNT_BASE + 0x0004) -/* PCNT_CNT_THRES1_U0 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to configure thres1 value for unit0.*/ -#define PCNT_CNT_THRES1_U0 0x0000FFFF -#define PCNT_CNT_THRES1_U0_M ((PCNT_CNT_THRES1_U0_V)<<(PCNT_CNT_THRES1_U0_S)) -#define PCNT_CNT_THRES1_U0_V 0xFFFF -#define PCNT_CNT_THRES1_U0_S 16 -/* PCNT_CNT_THRES0_U0 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thres0 value for unit0.*/ -#define PCNT_CNT_THRES0_U0 0x0000FFFF -#define PCNT_CNT_THRES0_U0_M ((PCNT_CNT_THRES0_U0_V)<<(PCNT_CNT_THRES0_U0_S)) -#define PCNT_CNT_THRES0_U0_V 0xFFFF -#define PCNT_CNT_THRES0_U0_S 0 - -#define PCNT_U0_CONF2_REG (DR_REG_PCNT_BASE + 0x0008) -/* PCNT_CNT_L_LIM_U0 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to confiugre thr_l_lim value for unit0.*/ -#define PCNT_CNT_L_LIM_U0 0x0000FFFF -#define PCNT_CNT_L_LIM_U0_M ((PCNT_CNT_L_LIM_U0_V)<<(PCNT_CNT_L_LIM_U0_S)) -#define PCNT_CNT_L_LIM_U0_V 0xFFFF -#define PCNT_CNT_L_LIM_U0_S 16 -/* PCNT_CNT_H_LIM_U0 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thr_h_lim value for unit0.*/ -#define PCNT_CNT_H_LIM_U0 0x0000FFFF -#define PCNT_CNT_H_LIM_U0_M ((PCNT_CNT_H_LIM_U0_V)<<(PCNT_CNT_H_LIM_U0_S)) -#define PCNT_CNT_H_LIM_U0_V 0xFFFF -#define PCNT_CNT_H_LIM_U0_S 0 - -#define PCNT_U1_CONF0_REG (DR_REG_PCNT_BASE + 0x000c) -/* PCNT_CH1_LCTRL_MODE_U1 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's low control - signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH1_LCTRL_MODE_U1 0x00000003 -#define PCNT_CH1_LCTRL_MODE_U1_M ((PCNT_CH1_LCTRL_MODE_U1_V)<<(PCNT_CH1_LCTRL_MODE_U1_S)) -#define PCNT_CH1_LCTRL_MODE_U1_V 0x3 -#define PCNT_CH1_LCTRL_MODE_U1_S 30 -/* PCNT_CH1_HCTRL_MODE_U1 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's high - control signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH1_HCTRL_MODE_U1 0x00000003 -#define PCNT_CH1_HCTRL_MODE_U1_M ((PCNT_CH1_HCTRL_MODE_U1_V)<<(PCNT_CH1_HCTRL_MODE_U1_S)) -#define PCNT_CH1_HCTRL_MODE_U1_V 0x3 -#define PCNT_CH1_HCTRL_MODE_U1_S 28 -/* PCNT_CH1_POS_MODE_U1 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - posedge signal for unit1. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ -#define PCNT_CH1_POS_MODE_U1 0x00000003 -#define PCNT_CH1_POS_MODE_U1_M ((PCNT_CH1_POS_MODE_U1_V)<<(PCNT_CH1_POS_MODE_U1_S)) -#define PCNT_CH1_POS_MODE_U1_V 0x3 -#define PCNT_CH1_POS_MODE_U1_S 26 -/* PCNT_CH1_NEG_MODE_U1 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - negedge signal for unit1. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ -#define PCNT_CH1_NEG_MODE_U1 0x00000003 -#define PCNT_CH1_NEG_MODE_U1_M ((PCNT_CH1_NEG_MODE_U1_V)<<(PCNT_CH1_NEG_MODE_U1_S)) -#define PCNT_CH1_NEG_MODE_U1_V 0x3 -#define PCNT_CH1_NEG_MODE_U1_S 24 -/* PCNT_CH0_LCTRL_MODE_U1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's low control - signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH0_LCTRL_MODE_U1 0x00000003 -#define PCNT_CH0_LCTRL_MODE_U1_M ((PCNT_CH0_LCTRL_MODE_U1_V)<<(PCNT_CH0_LCTRL_MODE_U1_S)) -#define PCNT_CH0_LCTRL_MODE_U1_V 0x3 -#define PCNT_CH0_LCTRL_MODE_U1_S 22 -/* PCNT_CH0_HCTRL_MODE_U1 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's high - control signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH0_HCTRL_MODE_U1 0x00000003 -#define PCNT_CH0_HCTRL_MODE_U1_M ((PCNT_CH0_HCTRL_MODE_U1_V)<<(PCNT_CH0_HCTRL_MODE_U1_S)) -#define PCNT_CH0_HCTRL_MODE_U1_V 0x3 -#define PCNT_CH0_HCTRL_MODE_U1_S 20 -/* PCNT_CH0_POS_MODE_U1 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - posedge signal for unit1. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ -#define PCNT_CH0_POS_MODE_U1 0x00000003 -#define PCNT_CH0_POS_MODE_U1_M ((PCNT_CH0_POS_MODE_U1_V)<<(PCNT_CH0_POS_MODE_U1_S)) -#define PCNT_CH0_POS_MODE_U1_V 0x3 -#define PCNT_CH0_POS_MODE_U1_S 18 -/* PCNT_CH0_NEG_MODE_U1 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - negedge signal for unit1. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ -#define PCNT_CH0_NEG_MODE_U1 0x00000003 -#define PCNT_CH0_NEG_MODE_U1_M ((PCNT_CH0_NEG_MODE_U1_V)<<(PCNT_CH0_NEG_MODE_U1_S)) -#define PCNT_CH0_NEG_MODE_U1_V 0x3 -#define PCNT_CH0_NEG_MODE_U1_S 16 -/* PCNT_THR_THRES1_EN_U1 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit1's count with thres1 value .*/ -#define PCNT_THR_THRES1_EN_U1 (BIT(15)) -#define PCNT_THR_THRES1_EN_U1_M (BIT(15)) -#define PCNT_THR_THRES1_EN_U1_V 0x1 -#define PCNT_THR_THRES1_EN_U1_S 15 -/* PCNT_THR_THRES0_EN_U1 : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit1's count with thres0 value.*/ -#define PCNT_THR_THRES0_EN_U1 (BIT(14)) -#define PCNT_THR_THRES0_EN_U1_M (BIT(14)) -#define PCNT_THR_THRES0_EN_U1_V 0x1 -#define PCNT_THR_THRES0_EN_U1_S 14 -/* PCNT_THR_L_LIM_EN_U1 : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit1's count with thr_l_lim value.*/ -#define PCNT_THR_L_LIM_EN_U1 (BIT(13)) -#define PCNT_THR_L_LIM_EN_U1_M (BIT(13)) -#define PCNT_THR_L_LIM_EN_U1_V 0x1 -#define PCNT_THR_L_LIM_EN_U1_S 13 -/* PCNT_THR_H_LIM_EN_U1 : R/W ;bitpos:[12] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit1's count with thr_h_lim value.*/ -#define PCNT_THR_H_LIM_EN_U1 (BIT(12)) -#define PCNT_THR_H_LIM_EN_U1_M (BIT(12)) -#define PCNT_THR_H_LIM_EN_U1_V 0x1 -#define PCNT_THR_H_LIM_EN_U1_S 12 -/* PCNT_THR_ZERO_EN_U1 : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit1's count with 0 value.*/ -#define PCNT_THR_ZERO_EN_U1 (BIT(11)) -#define PCNT_THR_ZERO_EN_U1_M (BIT(11)) -#define PCNT_THR_ZERO_EN_U1_V 0x1 -#define PCNT_THR_ZERO_EN_U1_S 11 -/* PCNT_FILTER_EN_U1 : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: This is the enable bit for filtering input signals for unit1.*/ -#define PCNT_FILTER_EN_U1 (BIT(10)) -#define PCNT_FILTER_EN_U1_M (BIT(10)) -#define PCNT_FILTER_EN_U1_V 0x1 -#define PCNT_FILTER_EN_U1_S 10 -/* PCNT_FILTER_THRES_U1 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ -/*description: This register is used to filter pluse whose width is smaller - than this value for unit1.*/ -#define PCNT_FILTER_THRES_U1 0x000003FF -#define PCNT_FILTER_THRES_U1_M ((PCNT_FILTER_THRES_U1_V)<<(PCNT_FILTER_THRES_U1_S)) -#define PCNT_FILTER_THRES_U1_V 0x3FF -#define PCNT_FILTER_THRES_U1_S 0 - -#define PCNT_U1_CONF1_REG (DR_REG_PCNT_BASE + 0x0010) -/* PCNT_CNT_THRES1_U1 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to configure thres1 value for unit1.*/ -#define PCNT_CNT_THRES1_U1 0x0000FFFF -#define PCNT_CNT_THRES1_U1_M ((PCNT_CNT_THRES1_U1_V)<<(PCNT_CNT_THRES1_U1_S)) -#define PCNT_CNT_THRES1_U1_V 0xFFFF -#define PCNT_CNT_THRES1_U1_S 16 -/* PCNT_CNT_THRES0_U1 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thres0 value for unit1.*/ -#define PCNT_CNT_THRES0_U1 0x0000FFFF -#define PCNT_CNT_THRES0_U1_M ((PCNT_CNT_THRES0_U1_V)<<(PCNT_CNT_THRES0_U1_S)) -#define PCNT_CNT_THRES0_U1_V 0xFFFF -#define PCNT_CNT_THRES0_U1_S 0 - -#define PCNT_U1_CONF2_REG (DR_REG_PCNT_BASE + 0x0014) -/* PCNT_CNT_L_LIM_U1 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to confiugre thr_l_lim value for unit1.*/ -#define PCNT_CNT_L_LIM_U1 0x0000FFFF -#define PCNT_CNT_L_LIM_U1_M ((PCNT_CNT_L_LIM_U1_V)<<(PCNT_CNT_L_LIM_U1_S)) -#define PCNT_CNT_L_LIM_U1_V 0xFFFF -#define PCNT_CNT_L_LIM_U1_S 16 -/* PCNT_CNT_H_LIM_U1 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thr_h_lim value for unit1.*/ -#define PCNT_CNT_H_LIM_U1 0x0000FFFF -#define PCNT_CNT_H_LIM_U1_M ((PCNT_CNT_H_LIM_U1_V)<<(PCNT_CNT_H_LIM_U1_S)) -#define PCNT_CNT_H_LIM_U1_V 0xFFFF -#define PCNT_CNT_H_LIM_U1_S 0 - -#define PCNT_U2_CONF0_REG (DR_REG_PCNT_BASE + 0x0018) -/* PCNT_CH1_LCTRL_MODE_U2 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's low control - signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH1_LCTRL_MODE_U2 0x00000003 -#define PCNT_CH1_LCTRL_MODE_U2_M ((PCNT_CH1_LCTRL_MODE_U2_V)<<(PCNT_CH1_LCTRL_MODE_U2_S)) -#define PCNT_CH1_LCTRL_MODE_U2_V 0x3 -#define PCNT_CH1_LCTRL_MODE_U2_S 30 -/* PCNT_CH1_HCTRL_MODE_U2 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's high - control signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH1_HCTRL_MODE_U2 0x00000003 -#define PCNT_CH1_HCTRL_MODE_U2_M ((PCNT_CH1_HCTRL_MODE_U2_V)<<(PCNT_CH1_HCTRL_MODE_U2_S)) -#define PCNT_CH1_HCTRL_MODE_U2_V 0x3 -#define PCNT_CH1_HCTRL_MODE_U2_S 28 -/* PCNT_CH1_POS_MODE_U2 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - posedge signal for unit2. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ -#define PCNT_CH1_POS_MODE_U2 0x00000003 -#define PCNT_CH1_POS_MODE_U2_M ((PCNT_CH1_POS_MODE_U2_V)<<(PCNT_CH1_POS_MODE_U2_S)) -#define PCNT_CH1_POS_MODE_U2_V 0x3 -#define PCNT_CH1_POS_MODE_U2_S 26 -/* PCNT_CH1_NEG_MODE_U2 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - negedge signal for unit2. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ -#define PCNT_CH1_NEG_MODE_U2 0x00000003 -#define PCNT_CH1_NEG_MODE_U2_M ((PCNT_CH1_NEG_MODE_U2_V)<<(PCNT_CH1_NEG_MODE_U2_S)) -#define PCNT_CH1_NEG_MODE_U2_V 0x3 -#define PCNT_CH1_NEG_MODE_U2_S 24 -/* PCNT_CH0_LCTRL_MODE_U2 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's low control - signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH0_LCTRL_MODE_U2 0x00000003 -#define PCNT_CH0_LCTRL_MODE_U2_M ((PCNT_CH0_LCTRL_MODE_U2_V)<<(PCNT_CH0_LCTRL_MODE_U2_S)) -#define PCNT_CH0_LCTRL_MODE_U2_V 0x3 -#define PCNT_CH0_LCTRL_MODE_U2_S 22 -/* PCNT_CH0_HCTRL_MODE_U2 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's high - control signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH0_HCTRL_MODE_U2 0x00000003 -#define PCNT_CH0_HCTRL_MODE_U2_M ((PCNT_CH0_HCTRL_MODE_U2_V)<<(PCNT_CH0_HCTRL_MODE_U2_S)) -#define PCNT_CH0_HCTRL_MODE_U2_V 0x3 -#define PCNT_CH0_HCTRL_MODE_U2_S 20 -/* PCNT_CH0_POS_MODE_U2 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - posedge signal for unit2. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ -#define PCNT_CH0_POS_MODE_U2 0x00000003 -#define PCNT_CH0_POS_MODE_U2_M ((PCNT_CH0_POS_MODE_U2_V)<<(PCNT_CH0_POS_MODE_U2_S)) -#define PCNT_CH0_POS_MODE_U2_V 0x3 -#define PCNT_CH0_POS_MODE_U2_S 18 -/* PCNT_CH0_NEG_MODE_U2 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - negedge signal for unit2. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ -#define PCNT_CH0_NEG_MODE_U2 0x00000003 -#define PCNT_CH0_NEG_MODE_U2_M ((PCNT_CH0_NEG_MODE_U2_V)<<(PCNT_CH0_NEG_MODE_U2_S)) -#define PCNT_CH0_NEG_MODE_U2_V 0x3 -#define PCNT_CH0_NEG_MODE_U2_S 16 -/* PCNT_THR_THRES1_EN_U2 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit2's count with thres1 value .*/ -#define PCNT_THR_THRES1_EN_U2 (BIT(15)) -#define PCNT_THR_THRES1_EN_U2_M (BIT(15)) -#define PCNT_THR_THRES1_EN_U2_V 0x1 -#define PCNT_THR_THRES1_EN_U2_S 15 -/* PCNT_THR_THRES0_EN_U2 : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit2's count with thres0 value.*/ -#define PCNT_THR_THRES0_EN_U2 (BIT(14)) -#define PCNT_THR_THRES0_EN_U2_M (BIT(14)) -#define PCNT_THR_THRES0_EN_U2_V 0x1 -#define PCNT_THR_THRES0_EN_U2_S 14 -/* PCNT_THR_L_LIM_EN_U2 : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit2's count with thr_l_lim value.*/ -#define PCNT_THR_L_LIM_EN_U2 (BIT(13)) -#define PCNT_THR_L_LIM_EN_U2_M (BIT(13)) -#define PCNT_THR_L_LIM_EN_U2_V 0x1 -#define PCNT_THR_L_LIM_EN_U2_S 13 -/* PCNT_THR_H_LIM_EN_U2 : R/W ;bitpos:[12] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit2's count with thr_h_lim value.*/ -#define PCNT_THR_H_LIM_EN_U2 (BIT(12)) -#define PCNT_THR_H_LIM_EN_U2_M (BIT(12)) -#define PCNT_THR_H_LIM_EN_U2_V 0x1 -#define PCNT_THR_H_LIM_EN_U2_S 12 -/* PCNT_THR_ZERO_EN_U2 : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit2's count with 0 value.*/ -#define PCNT_THR_ZERO_EN_U2 (BIT(11)) -#define PCNT_THR_ZERO_EN_U2_M (BIT(11)) -#define PCNT_THR_ZERO_EN_U2_V 0x1 -#define PCNT_THR_ZERO_EN_U2_S 11 -/* PCNT_FILTER_EN_U2 : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: This is the enable bit for filtering input signals for unit2.*/ -#define PCNT_FILTER_EN_U2 (BIT(10)) -#define PCNT_FILTER_EN_U2_M (BIT(10)) -#define PCNT_FILTER_EN_U2_V 0x1 -#define PCNT_FILTER_EN_U2_S 10 -/* PCNT_FILTER_THRES_U2 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ -/*description: This register is used to filter pluse whose width is smaller - than this value for unit2.*/ -#define PCNT_FILTER_THRES_U2 0x000003FF -#define PCNT_FILTER_THRES_U2_M ((PCNT_FILTER_THRES_U2_V)<<(PCNT_FILTER_THRES_U2_S)) -#define PCNT_FILTER_THRES_U2_V 0x3FF -#define PCNT_FILTER_THRES_U2_S 0 - -#define PCNT_U2_CONF1_REG (DR_REG_PCNT_BASE + 0x001c) -/* PCNT_CNT_THRES1_U2 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to configure thres1 value for unit2.*/ -#define PCNT_CNT_THRES1_U2 0x0000FFFF -#define PCNT_CNT_THRES1_U2_M ((PCNT_CNT_THRES1_U2_V)<<(PCNT_CNT_THRES1_U2_S)) -#define PCNT_CNT_THRES1_U2_V 0xFFFF -#define PCNT_CNT_THRES1_U2_S 16 -/* PCNT_CNT_THRES0_U2 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thres0 value for unit2.*/ -#define PCNT_CNT_THRES0_U2 0x0000FFFF -#define PCNT_CNT_THRES0_U2_M ((PCNT_CNT_THRES0_U2_V)<<(PCNT_CNT_THRES0_U2_S)) -#define PCNT_CNT_THRES0_U2_V 0xFFFF -#define PCNT_CNT_THRES0_U2_S 0 - -#define PCNT_U2_CONF2_REG (DR_REG_PCNT_BASE + 0x0020) -/* PCNT_CNT_L_LIM_U2 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to confiugre thr_l_lim value for unit2.*/ -#define PCNT_CNT_L_LIM_U2 0x0000FFFF -#define PCNT_CNT_L_LIM_U2_M ((PCNT_CNT_L_LIM_U2_V)<<(PCNT_CNT_L_LIM_U2_S)) -#define PCNT_CNT_L_LIM_U2_V 0xFFFF -#define PCNT_CNT_L_LIM_U2_S 16 -/* PCNT_CNT_H_LIM_U2 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thr_h_lim value for unit2.*/ -#define PCNT_CNT_H_LIM_U2 0x0000FFFF -#define PCNT_CNT_H_LIM_U2_M ((PCNT_CNT_H_LIM_U2_V)<<(PCNT_CNT_H_LIM_U2_S)) -#define PCNT_CNT_H_LIM_U2_V 0xFFFF -#define PCNT_CNT_H_LIM_U2_S 0 - -#define PCNT_U3_CONF0_REG (DR_REG_PCNT_BASE + 0x0024) -/* PCNT_CH1_LCTRL_MODE_U3 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's low control - signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH1_LCTRL_MODE_U3 0x00000003 -#define PCNT_CH1_LCTRL_MODE_U3_M ((PCNT_CH1_LCTRL_MODE_U3_V)<<(PCNT_CH1_LCTRL_MODE_U3_S)) -#define PCNT_CH1_LCTRL_MODE_U3_V 0x3 -#define PCNT_CH1_LCTRL_MODE_U3_S 30 -/* PCNT_CH1_HCTRL_MODE_U3 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's high - control signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH1_HCTRL_MODE_U3 0x00000003 -#define PCNT_CH1_HCTRL_MODE_U3_M ((PCNT_CH1_HCTRL_MODE_U3_V)<<(PCNT_CH1_HCTRL_MODE_U3_S)) -#define PCNT_CH1_HCTRL_MODE_U3_V 0x3 -#define PCNT_CH1_HCTRL_MODE_U3_S 28 -/* PCNT_CH1_POS_MODE_U3 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - posedge signal for unit3. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ -#define PCNT_CH1_POS_MODE_U3 0x00000003 -#define PCNT_CH1_POS_MODE_U3_M ((PCNT_CH1_POS_MODE_U3_V)<<(PCNT_CH1_POS_MODE_U3_S)) -#define PCNT_CH1_POS_MODE_U3_V 0x3 -#define PCNT_CH1_POS_MODE_U3_S 26 -/* PCNT_CH1_NEG_MODE_U3 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - negedge signal for unit3. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ -#define PCNT_CH1_NEG_MODE_U3 0x00000003 -#define PCNT_CH1_NEG_MODE_U3_M ((PCNT_CH1_NEG_MODE_U3_V)<<(PCNT_CH1_NEG_MODE_U3_S)) -#define PCNT_CH1_NEG_MODE_U3_V 0x3 -#define PCNT_CH1_NEG_MODE_U3_S 24 -/* PCNT_CH0_LCTRL_MODE_U3 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's low control - signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH0_LCTRL_MODE_U3 0x00000003 -#define PCNT_CH0_LCTRL_MODE_U3_M ((PCNT_CH0_LCTRL_MODE_U3_V)<<(PCNT_CH0_LCTRL_MODE_U3_S)) -#define PCNT_CH0_LCTRL_MODE_U3_V 0x3 -#define PCNT_CH0_LCTRL_MODE_U3_S 22 -/* PCNT_CH0_HCTRL_MODE_U3 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's high - control signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH0_HCTRL_MODE_U3 0x00000003 -#define PCNT_CH0_HCTRL_MODE_U3_M ((PCNT_CH0_HCTRL_MODE_U3_V)<<(PCNT_CH0_HCTRL_MODE_U3_S)) -#define PCNT_CH0_HCTRL_MODE_U3_V 0x3 -#define PCNT_CH0_HCTRL_MODE_U3_S 20 -/* PCNT_CH0_POS_MODE_U3 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - posedge signal for unit3. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ -#define PCNT_CH0_POS_MODE_U3 0x00000003 -#define PCNT_CH0_POS_MODE_U3_M ((PCNT_CH0_POS_MODE_U3_V)<<(PCNT_CH0_POS_MODE_U3_S)) -#define PCNT_CH0_POS_MODE_U3_V 0x3 -#define PCNT_CH0_POS_MODE_U3_S 18 -/* PCNT_CH0_NEG_MODE_U3 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - negedge signal for unit3. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ -#define PCNT_CH0_NEG_MODE_U3 0x00000003 -#define PCNT_CH0_NEG_MODE_U3_M ((PCNT_CH0_NEG_MODE_U3_V)<<(PCNT_CH0_NEG_MODE_U3_S)) -#define PCNT_CH0_NEG_MODE_U3_V 0x3 -#define PCNT_CH0_NEG_MODE_U3_S 16 -/* PCNT_THR_THRES1_EN_U3 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit3's count with thres1 value .*/ -#define PCNT_THR_THRES1_EN_U3 (BIT(15)) -#define PCNT_THR_THRES1_EN_U3_M (BIT(15)) -#define PCNT_THR_THRES1_EN_U3_V 0x1 -#define PCNT_THR_THRES1_EN_U3_S 15 -/* PCNT_THR_THRES0_EN_U3 : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit3's count with thres0 value.*/ -#define PCNT_THR_THRES0_EN_U3 (BIT(14)) -#define PCNT_THR_THRES0_EN_U3_M (BIT(14)) -#define PCNT_THR_THRES0_EN_U3_V 0x1 -#define PCNT_THR_THRES0_EN_U3_S 14 -/* PCNT_THR_L_LIM_EN_U3 : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit3's count with thr_l_lim value.*/ -#define PCNT_THR_L_LIM_EN_U3 (BIT(13)) -#define PCNT_THR_L_LIM_EN_U3_M (BIT(13)) -#define PCNT_THR_L_LIM_EN_U3_V 0x1 -#define PCNT_THR_L_LIM_EN_U3_S 13 -/* PCNT_THR_H_LIM_EN_U3 : R/W ;bitpos:[12] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit3's count with thr_h_lim value.*/ -#define PCNT_THR_H_LIM_EN_U3 (BIT(12)) -#define PCNT_THR_H_LIM_EN_U3_M (BIT(12)) -#define PCNT_THR_H_LIM_EN_U3_V 0x1 -#define PCNT_THR_H_LIM_EN_U3_S 12 -/* PCNT_THR_ZERO_EN_U3 : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit3's count with 0 value.*/ -#define PCNT_THR_ZERO_EN_U3 (BIT(11)) -#define PCNT_THR_ZERO_EN_U3_M (BIT(11)) -#define PCNT_THR_ZERO_EN_U3_V 0x1 -#define PCNT_THR_ZERO_EN_U3_S 11 -/* PCNT_FILTER_EN_U3 : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: This is the enable bit for filtering input signals for unit3.*/ -#define PCNT_FILTER_EN_U3 (BIT(10)) -#define PCNT_FILTER_EN_U3_M (BIT(10)) -#define PCNT_FILTER_EN_U3_V 0x1 -#define PCNT_FILTER_EN_U3_S 10 -/* PCNT_FILTER_THRES_U3 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ -/*description: This register is used to filter pluse whose width is smaller - than this value for unit3.*/ -#define PCNT_FILTER_THRES_U3 0x000003FF -#define PCNT_FILTER_THRES_U3_M ((PCNT_FILTER_THRES_U3_V)<<(PCNT_FILTER_THRES_U3_S)) -#define PCNT_FILTER_THRES_U3_V 0x3FF -#define PCNT_FILTER_THRES_U3_S 0 - -#define PCNT_U3_CONF1_REG (DR_REG_PCNT_BASE + 0x0028) -/* PCNT_CNT_THRES1_U3 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to configure thres1 value for unit3.*/ -#define PCNT_CNT_THRES1_U3 0x0000FFFF -#define PCNT_CNT_THRES1_U3_M ((PCNT_CNT_THRES1_U3_V)<<(PCNT_CNT_THRES1_U3_S)) -#define PCNT_CNT_THRES1_U3_V 0xFFFF -#define PCNT_CNT_THRES1_U3_S 16 -/* PCNT_CNT_THRES0_U3 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thres0 value for unit3.*/ -#define PCNT_CNT_THRES0_U3 0x0000FFFF -#define PCNT_CNT_THRES0_U3_M ((PCNT_CNT_THRES0_U3_V)<<(PCNT_CNT_THRES0_U3_S)) -#define PCNT_CNT_THRES0_U3_V 0xFFFF -#define PCNT_CNT_THRES0_U3_S 0 - -#define PCNT_U3_CONF2_REG (DR_REG_PCNT_BASE + 0x002c) -/* PCNT_CNT_L_LIM_U3 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to confiugre thr_l_lim value for unit3.*/ -#define PCNT_CNT_L_LIM_U3 0x0000FFFF -#define PCNT_CNT_L_LIM_U3_M ((PCNT_CNT_L_LIM_U3_V)<<(PCNT_CNT_L_LIM_U3_S)) -#define PCNT_CNT_L_LIM_U3_V 0xFFFF -#define PCNT_CNT_L_LIM_U3_S 16 -/* PCNT_CNT_H_LIM_U3 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thr_h_lim value for unit3.*/ -#define PCNT_CNT_H_LIM_U3 0x0000FFFF -#define PCNT_CNT_H_LIM_U3_M ((PCNT_CNT_H_LIM_U3_V)<<(PCNT_CNT_H_LIM_U3_S)) -#define PCNT_CNT_H_LIM_U3_V 0xFFFF -#define PCNT_CNT_H_LIM_U3_S 0 - -#define PCNT_U4_CONF0_REG (DR_REG_PCNT_BASE + 0x0030) -/* PCNT_CH1_LCTRL_MODE_U4 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's low control - signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH1_LCTRL_MODE_U4 0x00000003 -#define PCNT_CH1_LCTRL_MODE_U4_M ((PCNT_CH1_LCTRL_MODE_U4_V)<<(PCNT_CH1_LCTRL_MODE_U4_S)) -#define PCNT_CH1_LCTRL_MODE_U4_V 0x3 -#define PCNT_CH1_LCTRL_MODE_U4_S 30 -/* PCNT_CH1_HCTRL_MODE_U4 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's high - control signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH1_HCTRL_MODE_U4 0x00000003 -#define PCNT_CH1_HCTRL_MODE_U4_M ((PCNT_CH1_HCTRL_MODE_U4_V)<<(PCNT_CH1_HCTRL_MODE_U4_S)) -#define PCNT_CH1_HCTRL_MODE_U4_V 0x3 -#define PCNT_CH1_HCTRL_MODE_U4_S 28 -/* PCNT_CH1_POS_MODE_U4 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - posedge signal for unit4. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ -#define PCNT_CH1_POS_MODE_U4 0x00000003 -#define PCNT_CH1_POS_MODE_U4_M ((PCNT_CH1_POS_MODE_U4_V)<<(PCNT_CH1_POS_MODE_U4_S)) -#define PCNT_CH1_POS_MODE_U4_V 0x3 -#define PCNT_CH1_POS_MODE_U4_S 26 -/* PCNT_CH1_NEG_MODE_U4 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - negedge signal for unit4. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ -#define PCNT_CH1_NEG_MODE_U4 0x00000003 -#define PCNT_CH1_NEG_MODE_U4_M ((PCNT_CH1_NEG_MODE_U4_V)<<(PCNT_CH1_NEG_MODE_U4_S)) -#define PCNT_CH1_NEG_MODE_U4_V 0x3 -#define PCNT_CH1_NEG_MODE_U4_S 24 -/* PCNT_CH0_LCTRL_MODE_U4 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's low control - signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH0_LCTRL_MODE_U4 0x00000003 -#define PCNT_CH0_LCTRL_MODE_U4_M ((PCNT_CH0_LCTRL_MODE_U4_V)<<(PCNT_CH0_LCTRL_MODE_U4_S)) -#define PCNT_CH0_LCTRL_MODE_U4_V 0x3 -#define PCNT_CH0_LCTRL_MODE_U4_S 22 -/* PCNT_CH0_HCTRL_MODE_U4 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's high - control signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH0_HCTRL_MODE_U4 0x00000003 -#define PCNT_CH0_HCTRL_MODE_U4_M ((PCNT_CH0_HCTRL_MODE_U4_V)<<(PCNT_CH0_HCTRL_MODE_U4_S)) -#define PCNT_CH0_HCTRL_MODE_U4_V 0x3 -#define PCNT_CH0_HCTRL_MODE_U4_S 20 -/* PCNT_CH0_POS_MODE_U4 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - posedge signal for unit4. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ -#define PCNT_CH0_POS_MODE_U4 0x00000003 -#define PCNT_CH0_POS_MODE_U4_M ((PCNT_CH0_POS_MODE_U4_V)<<(PCNT_CH0_POS_MODE_U4_S)) -#define PCNT_CH0_POS_MODE_U4_V 0x3 -#define PCNT_CH0_POS_MODE_U4_S 18 -/* PCNT_CH0_NEG_MODE_U4 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - negedge signal for unit4. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ -#define PCNT_CH0_NEG_MODE_U4 0x00000003 -#define PCNT_CH0_NEG_MODE_U4_M ((PCNT_CH0_NEG_MODE_U4_V)<<(PCNT_CH0_NEG_MODE_U4_S)) -#define PCNT_CH0_NEG_MODE_U4_V 0x3 -#define PCNT_CH0_NEG_MODE_U4_S 16 -/* PCNT_THR_THRES1_EN_U4 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit4's count with thres1 value .*/ -#define PCNT_THR_THRES1_EN_U4 (BIT(15)) -#define PCNT_THR_THRES1_EN_U4_M (BIT(15)) -#define PCNT_THR_THRES1_EN_U4_V 0x1 -#define PCNT_THR_THRES1_EN_U4_S 15 -/* PCNT_THR_THRES0_EN_U4 : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit4's count with thres0 value.*/ -#define PCNT_THR_THRES0_EN_U4 (BIT(14)) -#define PCNT_THR_THRES0_EN_U4_M (BIT(14)) -#define PCNT_THR_THRES0_EN_U4_V 0x1 -#define PCNT_THR_THRES0_EN_U4_S 14 -/* PCNT_THR_L_LIM_EN_U4 : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit4's count with thr_l_lim value.*/ -#define PCNT_THR_L_LIM_EN_U4 (BIT(13)) -#define PCNT_THR_L_LIM_EN_U4_M (BIT(13)) -#define PCNT_THR_L_LIM_EN_U4_V 0x1 -#define PCNT_THR_L_LIM_EN_U4_S 13 -/* PCNT_THR_H_LIM_EN_U4 : R/W ;bitpos:[12] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit4's count with thr_h_lim value.*/ -#define PCNT_THR_H_LIM_EN_U4 (BIT(12)) -#define PCNT_THR_H_LIM_EN_U4_M (BIT(12)) -#define PCNT_THR_H_LIM_EN_U4_V 0x1 -#define PCNT_THR_H_LIM_EN_U4_S 12 -/* PCNT_THR_ZERO_EN_U4 : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit4's count with 0 value.*/ -#define PCNT_THR_ZERO_EN_U4 (BIT(11)) -#define PCNT_THR_ZERO_EN_U4_M (BIT(11)) -#define PCNT_THR_ZERO_EN_U4_V 0x1 -#define PCNT_THR_ZERO_EN_U4_S 11 -/* PCNT_FILTER_EN_U4 : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: This is the enable bit for filtering input signals for unit4.*/ -#define PCNT_FILTER_EN_U4 (BIT(10)) -#define PCNT_FILTER_EN_U4_M (BIT(10)) -#define PCNT_FILTER_EN_U4_V 0x1 -#define PCNT_FILTER_EN_U4_S 10 -/* PCNT_FILTER_THRES_U4 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ -/*description: This register is used to filter pluse whose width is smaller - than this value for unit4.*/ -#define PCNT_FILTER_THRES_U4 0x000003FF -#define PCNT_FILTER_THRES_U4_M ((PCNT_FILTER_THRES_U4_V)<<(PCNT_FILTER_THRES_U4_S)) -#define PCNT_FILTER_THRES_U4_V 0x3FF -#define PCNT_FILTER_THRES_U4_S 0 - -#define PCNT_U4_CONF1_REG (DR_REG_PCNT_BASE + 0x0034) -/* PCNT_CNT_THRES1_U4 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to configure thres1 value for unit4.*/ -#define PCNT_CNT_THRES1_U4 0x0000FFFF -#define PCNT_CNT_THRES1_U4_M ((PCNT_CNT_THRES1_U4_V)<<(PCNT_CNT_THRES1_U4_S)) -#define PCNT_CNT_THRES1_U4_V 0xFFFF -#define PCNT_CNT_THRES1_U4_S 16 -/* PCNT_CNT_THRES0_U4 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thres0 value for unit4.*/ -#define PCNT_CNT_THRES0_U4 0x0000FFFF -#define PCNT_CNT_THRES0_U4_M ((PCNT_CNT_THRES0_U4_V)<<(PCNT_CNT_THRES0_U4_S)) -#define PCNT_CNT_THRES0_U4_V 0xFFFF -#define PCNT_CNT_THRES0_U4_S 0 - -#define PCNT_U4_CONF2_REG (DR_REG_PCNT_BASE + 0x0038) -/* PCNT_CNT_L_LIM_U4 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to confiugre thr_l_lim value for unit4.*/ -#define PCNT_CNT_L_LIM_U4 0x0000FFFF -#define PCNT_CNT_L_LIM_U4_M ((PCNT_CNT_L_LIM_U4_V)<<(PCNT_CNT_L_LIM_U4_S)) -#define PCNT_CNT_L_LIM_U4_V 0xFFFF -#define PCNT_CNT_L_LIM_U4_S 16 -/* PCNT_CNT_H_LIM_U4 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thr_h_lim value for unit4.*/ -#define PCNT_CNT_H_LIM_U4 0x0000FFFF -#define PCNT_CNT_H_LIM_U4_M ((PCNT_CNT_H_LIM_U4_V)<<(PCNT_CNT_H_LIM_U4_S)) -#define PCNT_CNT_H_LIM_U4_V 0xFFFF -#define PCNT_CNT_H_LIM_U4_S 0 - -#define PCNT_U5_CONF0_REG (DR_REG_PCNT_BASE + 0x003c) -/* PCNT_CH1_LCTRL_MODE_U5 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's low control - signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH1_LCTRL_MODE_U5 0x00000003 -#define PCNT_CH1_LCTRL_MODE_U5_M ((PCNT_CH1_LCTRL_MODE_U5_V)<<(PCNT_CH1_LCTRL_MODE_U5_S)) -#define PCNT_CH1_LCTRL_MODE_U5_V 0x3 -#define PCNT_CH1_LCTRL_MODE_U5_S 30 -/* PCNT_CH1_HCTRL_MODE_U5 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's high - control signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH1_HCTRL_MODE_U5 0x00000003 -#define PCNT_CH1_HCTRL_MODE_U5_M ((PCNT_CH1_HCTRL_MODE_U5_V)<<(PCNT_CH1_HCTRL_MODE_U5_S)) -#define PCNT_CH1_HCTRL_MODE_U5_V 0x3 -#define PCNT_CH1_HCTRL_MODE_U5_S 28 -/* PCNT_CH1_POS_MODE_U5 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - posedge signal for unit5. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ -#define PCNT_CH1_POS_MODE_U5 0x00000003 -#define PCNT_CH1_POS_MODE_U5_M ((PCNT_CH1_POS_MODE_U5_V)<<(PCNT_CH1_POS_MODE_U5_S)) -#define PCNT_CH1_POS_MODE_U5_V 0x3 -#define PCNT_CH1_POS_MODE_U5_S 26 -/* PCNT_CH1_NEG_MODE_U5 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - negedge signal for unit5. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ -#define PCNT_CH1_NEG_MODE_U5 0x00000003 -#define PCNT_CH1_NEG_MODE_U5_M ((PCNT_CH1_NEG_MODE_U5_V)<<(PCNT_CH1_NEG_MODE_U5_S)) -#define PCNT_CH1_NEG_MODE_U5_V 0x3 -#define PCNT_CH1_NEG_MODE_U5_S 24 -/* PCNT_CH0_LCTRL_MODE_U5 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's low control - signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH0_LCTRL_MODE_U5 0x00000003 -#define PCNT_CH0_LCTRL_MODE_U5_M ((PCNT_CH0_LCTRL_MODE_U5_V)<<(PCNT_CH0_LCTRL_MODE_U5_S)) -#define PCNT_CH0_LCTRL_MODE_U5_V 0x3 -#define PCNT_CH0_LCTRL_MODE_U5_S 22 -/* PCNT_CH0_HCTRL_MODE_U5 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's high - control signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH0_HCTRL_MODE_U5 0x00000003 -#define PCNT_CH0_HCTRL_MODE_U5_M ((PCNT_CH0_HCTRL_MODE_U5_V)<<(PCNT_CH0_HCTRL_MODE_U5_S)) -#define PCNT_CH0_HCTRL_MODE_U5_V 0x3 -#define PCNT_CH0_HCTRL_MODE_U5_S 20 -/* PCNT_CH0_POS_MODE_U5 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - posedge signal for unit5. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ -#define PCNT_CH0_POS_MODE_U5 0x00000003 -#define PCNT_CH0_POS_MODE_U5_M ((PCNT_CH0_POS_MODE_U5_V)<<(PCNT_CH0_POS_MODE_U5_S)) -#define PCNT_CH0_POS_MODE_U5_V 0x3 -#define PCNT_CH0_POS_MODE_U5_S 18 -/* PCNT_CH0_NEG_MODE_U5 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - negedge signal for unit5. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ -#define PCNT_CH0_NEG_MODE_U5 0x00000003 -#define PCNT_CH0_NEG_MODE_U5_M ((PCNT_CH0_NEG_MODE_U5_V)<<(PCNT_CH0_NEG_MODE_U5_S)) -#define PCNT_CH0_NEG_MODE_U5_V 0x3 -#define PCNT_CH0_NEG_MODE_U5_S 16 -/* PCNT_THR_THRES1_EN_U5 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit5's count with thres1 value .*/ -#define PCNT_THR_THRES1_EN_U5 (BIT(15)) -#define PCNT_THR_THRES1_EN_U5_M (BIT(15)) -#define PCNT_THR_THRES1_EN_U5_V 0x1 -#define PCNT_THR_THRES1_EN_U5_S 15 -/* PCNT_THR_THRES0_EN_U5 : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit5's count with thres0 value.*/ -#define PCNT_THR_THRES0_EN_U5 (BIT(14)) -#define PCNT_THR_THRES0_EN_U5_M (BIT(14)) -#define PCNT_THR_THRES0_EN_U5_V 0x1 -#define PCNT_THR_THRES0_EN_U5_S 14 -/* PCNT_THR_L_LIM_EN_U5 : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit5's count with thr_l_lim value.*/ -#define PCNT_THR_L_LIM_EN_U5 (BIT(13)) -#define PCNT_THR_L_LIM_EN_U5_M (BIT(13)) -#define PCNT_THR_L_LIM_EN_U5_V 0x1 -#define PCNT_THR_L_LIM_EN_U5_S 13 -/* PCNT_THR_H_LIM_EN_U5 : R/W ;bitpos:[12] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit5's count with thr_h_lim value.*/ -#define PCNT_THR_H_LIM_EN_U5 (BIT(12)) -#define PCNT_THR_H_LIM_EN_U5_M (BIT(12)) -#define PCNT_THR_H_LIM_EN_U5_V 0x1 -#define PCNT_THR_H_LIM_EN_U5_S 12 -/* PCNT_THR_ZERO_EN_U5 : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit5's count with 0 value.*/ -#define PCNT_THR_ZERO_EN_U5 (BIT(11)) -#define PCNT_THR_ZERO_EN_U5_M (BIT(11)) -#define PCNT_THR_ZERO_EN_U5_V 0x1 -#define PCNT_THR_ZERO_EN_U5_S 11 -/* PCNT_FILTER_EN_U5 : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: This is the enable bit for filtering input signals for unit5.*/ -#define PCNT_FILTER_EN_U5 (BIT(10)) -#define PCNT_FILTER_EN_U5_M (BIT(10)) -#define PCNT_FILTER_EN_U5_V 0x1 -#define PCNT_FILTER_EN_U5_S 10 -/* PCNT_FILTER_THRES_U5 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ -/*description: This register is used to filter pluse whose width is smaller - than this value for unit5.*/ -#define PCNT_FILTER_THRES_U5 0x000003FF -#define PCNT_FILTER_THRES_U5_M ((PCNT_FILTER_THRES_U5_V)<<(PCNT_FILTER_THRES_U5_S)) -#define PCNT_FILTER_THRES_U5_V 0x3FF -#define PCNT_FILTER_THRES_U5_S 0 - -#define PCNT_U5_CONF1_REG (DR_REG_PCNT_BASE + 0x0040) -/* PCNT_CNT_THRES1_U5 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to configure thres1 value for unit5.*/ -#define PCNT_CNT_THRES1_U5 0x0000FFFF -#define PCNT_CNT_THRES1_U5_M ((PCNT_CNT_THRES1_U5_V)<<(PCNT_CNT_THRES1_U5_S)) -#define PCNT_CNT_THRES1_U5_V 0xFFFF -#define PCNT_CNT_THRES1_U5_S 16 -/* PCNT_CNT_THRES0_U5 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thres0 value for unit5.*/ -#define PCNT_CNT_THRES0_U5 0x0000FFFF -#define PCNT_CNT_THRES0_U5_M ((PCNT_CNT_THRES0_U5_V)<<(PCNT_CNT_THRES0_U5_S)) -#define PCNT_CNT_THRES0_U5_V 0xFFFF -#define PCNT_CNT_THRES0_U5_S 0 - -#define PCNT_U5_CONF2_REG (DR_REG_PCNT_BASE + 0x0044) -/* PCNT_CNT_L_LIM_U5 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to confiugre thr_l_lim value for unit5.*/ -#define PCNT_CNT_L_LIM_U5 0x0000FFFF -#define PCNT_CNT_L_LIM_U5_M ((PCNT_CNT_L_LIM_U5_V)<<(PCNT_CNT_L_LIM_U5_S)) -#define PCNT_CNT_L_LIM_U5_V 0xFFFF -#define PCNT_CNT_L_LIM_U5_S 16 -/* PCNT_CNT_H_LIM_U5 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thr_h_lim value for unit5.*/ -#define PCNT_CNT_H_LIM_U5 0x0000FFFF -#define PCNT_CNT_H_LIM_U5_M ((PCNT_CNT_H_LIM_U5_V)<<(PCNT_CNT_H_LIM_U5_S)) -#define PCNT_CNT_H_LIM_U5_V 0xFFFF -#define PCNT_CNT_H_LIM_U5_S 0 - -#define PCNT_U6_CONF0_REG (DR_REG_PCNT_BASE + 0x0048) -/* PCNT_CH1_LCTRL_MODE_U6 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's low control - signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH1_LCTRL_MODE_U6 0x00000003 -#define PCNT_CH1_LCTRL_MODE_U6_M ((PCNT_CH1_LCTRL_MODE_U6_V)<<(PCNT_CH1_LCTRL_MODE_U6_S)) -#define PCNT_CH1_LCTRL_MODE_U6_V 0x3 -#define PCNT_CH1_LCTRL_MODE_U6_S 30 -/* PCNT_CH1_HCTRL_MODE_U6 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's high - control signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH1_HCTRL_MODE_U6 0x00000003 -#define PCNT_CH1_HCTRL_MODE_U6_M ((PCNT_CH1_HCTRL_MODE_U6_V)<<(PCNT_CH1_HCTRL_MODE_U6_S)) -#define PCNT_CH1_HCTRL_MODE_U6_V 0x3 -#define PCNT_CH1_HCTRL_MODE_U6_S 28 -/* PCNT_CH1_POS_MODE_U6 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - posedge signal for unit6. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ -#define PCNT_CH1_POS_MODE_U6 0x00000003 -#define PCNT_CH1_POS_MODE_U6_M ((PCNT_CH1_POS_MODE_U6_V)<<(PCNT_CH1_POS_MODE_U6_S)) -#define PCNT_CH1_POS_MODE_U6_V 0x3 -#define PCNT_CH1_POS_MODE_U6_S 26 -/* PCNT_CH1_NEG_MODE_U6 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - negedge signal for unit6. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ -#define PCNT_CH1_NEG_MODE_U6 0x00000003 -#define PCNT_CH1_NEG_MODE_U6_M ((PCNT_CH1_NEG_MODE_U6_V)<<(PCNT_CH1_NEG_MODE_U6_S)) -#define PCNT_CH1_NEG_MODE_U6_V 0x3 -#define PCNT_CH1_NEG_MODE_U6_S 24 -/* PCNT_CH0_LCTRL_MODE_U6 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's low control - signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH0_LCTRL_MODE_U6 0x00000003 -#define PCNT_CH0_LCTRL_MODE_U6_M ((PCNT_CH0_LCTRL_MODE_U6_V)<<(PCNT_CH0_LCTRL_MODE_U6_S)) -#define PCNT_CH0_LCTRL_MODE_U6_V 0x3 -#define PCNT_CH0_LCTRL_MODE_U6_S 22 -/* PCNT_CH0_HCTRL_MODE_U6 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's high - control signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH0_HCTRL_MODE_U6 0x00000003 -#define PCNT_CH0_HCTRL_MODE_U6_M ((PCNT_CH0_HCTRL_MODE_U6_V)<<(PCNT_CH0_HCTRL_MODE_U6_S)) -#define PCNT_CH0_HCTRL_MODE_U6_V 0x3 -#define PCNT_CH0_HCTRL_MODE_U6_S 20 -/* PCNT_CH0_POS_MODE_U6 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - posedge signal for unit6. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ -#define PCNT_CH0_POS_MODE_U6 0x00000003 -#define PCNT_CH0_POS_MODE_U6_M ((PCNT_CH0_POS_MODE_U6_V)<<(PCNT_CH0_POS_MODE_U6_S)) -#define PCNT_CH0_POS_MODE_U6_V 0x3 -#define PCNT_CH0_POS_MODE_U6_S 18 -/* PCNT_CH0_NEG_MODE_U6 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - negedge signal for unit6. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ -#define PCNT_CH0_NEG_MODE_U6 0x00000003 -#define PCNT_CH0_NEG_MODE_U6_M ((PCNT_CH0_NEG_MODE_U6_V)<<(PCNT_CH0_NEG_MODE_U6_S)) -#define PCNT_CH0_NEG_MODE_U6_V 0x3 -#define PCNT_CH0_NEG_MODE_U6_S 16 -/* PCNT_THR_THRES1_EN_U6 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit6's count with thres1 value .*/ -#define PCNT_THR_THRES1_EN_U6 (BIT(15)) -#define PCNT_THR_THRES1_EN_U6_M (BIT(15)) -#define PCNT_THR_THRES1_EN_U6_V 0x1 -#define PCNT_THR_THRES1_EN_U6_S 15 -/* PCNT_THR_THRES0_EN_U6 : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit6's count with thres0 value.*/ -#define PCNT_THR_THRES0_EN_U6 (BIT(14)) -#define PCNT_THR_THRES0_EN_U6_M (BIT(14)) -#define PCNT_THR_THRES0_EN_U6_V 0x1 -#define PCNT_THR_THRES0_EN_U6_S 14 -/* PCNT_THR_L_LIM_EN_U6 : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit6's count with thr_l_lim value.*/ -#define PCNT_THR_L_LIM_EN_U6 (BIT(13)) -#define PCNT_THR_L_LIM_EN_U6_M (BIT(13)) -#define PCNT_THR_L_LIM_EN_U6_V 0x1 -#define PCNT_THR_L_LIM_EN_U6_S 13 -/* PCNT_THR_H_LIM_EN_U6 : R/W ;bitpos:[12] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit6's count with thr_h_lim value.*/ -#define PCNT_THR_H_LIM_EN_U6 (BIT(12)) -#define PCNT_THR_H_LIM_EN_U6_M (BIT(12)) -#define PCNT_THR_H_LIM_EN_U6_V 0x1 -#define PCNT_THR_H_LIM_EN_U6_S 12 -/* PCNT_THR_ZERO_EN_U6 : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit6's count with 0 value.*/ -#define PCNT_THR_ZERO_EN_U6 (BIT(11)) -#define PCNT_THR_ZERO_EN_U6_M (BIT(11)) -#define PCNT_THR_ZERO_EN_U6_V 0x1 -#define PCNT_THR_ZERO_EN_U6_S 11 -/* PCNT_FILTER_EN_U6 : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: This is the enable bit for filtering input signals for unit6.*/ -#define PCNT_FILTER_EN_U6 (BIT(10)) -#define PCNT_FILTER_EN_U6_M (BIT(10)) -#define PCNT_FILTER_EN_U6_V 0x1 -#define PCNT_FILTER_EN_U6_S 10 -/* PCNT_FILTER_THRES_U6 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ -/*description: This register is used to filter pluse whose width is smaller - than this value for unit6.*/ -#define PCNT_FILTER_THRES_U6 0x000003FF -#define PCNT_FILTER_THRES_U6_M ((PCNT_FILTER_THRES_U6_V)<<(PCNT_FILTER_THRES_U6_S)) -#define PCNT_FILTER_THRES_U6_V 0x3FF -#define PCNT_FILTER_THRES_U6_S 0 - -#define PCNT_U6_CONF1_REG (DR_REG_PCNT_BASE + 0x004c) -/* PCNT_CNT_THRES1_U6 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to configure thres1 value for unit6.*/ -#define PCNT_CNT_THRES1_U6 0x0000FFFF -#define PCNT_CNT_THRES1_U6_M ((PCNT_CNT_THRES1_U6_V)<<(PCNT_CNT_THRES1_U6_S)) -#define PCNT_CNT_THRES1_U6_V 0xFFFF -#define PCNT_CNT_THRES1_U6_S 16 -/* PCNT_CNT_THRES0_U6 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thres0 value for unit6.*/ -#define PCNT_CNT_THRES0_U6 0x0000FFFF -#define PCNT_CNT_THRES0_U6_M ((PCNT_CNT_THRES0_U6_V)<<(PCNT_CNT_THRES0_U6_S)) -#define PCNT_CNT_THRES0_U6_V 0xFFFF -#define PCNT_CNT_THRES0_U6_S 0 - -#define PCNT_U6_CONF2_REG (DR_REG_PCNT_BASE + 0x0050) -/* PCNT_CNT_L_LIM_U6 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to confiugre thr_l_lim value for unit6.*/ -#define PCNT_CNT_L_LIM_U6 0x0000FFFF -#define PCNT_CNT_L_LIM_U6_M ((PCNT_CNT_L_LIM_U6_V)<<(PCNT_CNT_L_LIM_U6_S)) -#define PCNT_CNT_L_LIM_U6_V 0xFFFF -#define PCNT_CNT_L_LIM_U6_S 16 -/* PCNT_CNT_H_LIM_U6 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thr_h_lim value for unit6.*/ -#define PCNT_CNT_H_LIM_U6 0x0000FFFF -#define PCNT_CNT_H_LIM_U6_M ((PCNT_CNT_H_LIM_U6_V)<<(PCNT_CNT_H_LIM_U6_S)) -#define PCNT_CNT_H_LIM_U6_V 0xFFFF -#define PCNT_CNT_H_LIM_U6_S 0 - -#define PCNT_U7_CONF0_REG (DR_REG_PCNT_BASE + 0x0054) -/* PCNT_CH1_LCTRL_MODE_U7 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's low control - signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH1_LCTRL_MODE_U7 0x00000003 -#define PCNT_CH1_LCTRL_MODE_U7_M ((PCNT_CH1_LCTRL_MODE_U7_V)<<(PCNT_CH1_LCTRL_MODE_U7_S)) -#define PCNT_CH1_LCTRL_MODE_U7_V 0x3 -#define PCNT_CH1_LCTRL_MODE_U7_S 30 -/* PCNT_CH1_HCTRL_MODE_U7 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's high - control signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH1_HCTRL_MODE_U7 0x00000003 -#define PCNT_CH1_HCTRL_MODE_U7_M ((PCNT_CH1_HCTRL_MODE_U7_V)<<(PCNT_CH1_HCTRL_MODE_U7_S)) -#define PCNT_CH1_HCTRL_MODE_U7_V 0x3 -#define PCNT_CH1_HCTRL_MODE_U7_S 28 -/* PCNT_CH1_POS_MODE_U7 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - posedge signal for unit7. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ -#define PCNT_CH1_POS_MODE_U7 0x00000003 -#define PCNT_CH1_POS_MODE_U7_M ((PCNT_CH1_POS_MODE_U7_V)<<(PCNT_CH1_POS_MODE_U7_S)) -#define PCNT_CH1_POS_MODE_U7_V 0x3 -#define PCNT_CH1_POS_MODE_U7_S 26 -/* PCNT_CH1_NEG_MODE_U7 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - negedge signal for unit7. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ -#define PCNT_CH1_NEG_MODE_U7 0x00000003 -#define PCNT_CH1_NEG_MODE_U7_M ((PCNT_CH1_NEG_MODE_U7_V)<<(PCNT_CH1_NEG_MODE_U7_S)) -#define PCNT_CH1_NEG_MODE_U7_V 0x3 -#define PCNT_CH1_NEG_MODE_U7_S 24 -/* PCNT_CH0_LCTRL_MODE_U7 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's low control - signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH0_LCTRL_MODE_U7 0x00000003 -#define PCNT_CH0_LCTRL_MODE_U7_M ((PCNT_CH0_LCTRL_MODE_U7_V)<<(PCNT_CH0_LCTRL_MODE_U7_S)) -#define PCNT_CH0_LCTRL_MODE_U7_V 0x3 -#define PCNT_CH0_LCTRL_MODE_U7_S 22 -/* PCNT_CH0_HCTRL_MODE_U7 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's high - control signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH0_HCTRL_MODE_U7 0x00000003 -#define PCNT_CH0_HCTRL_MODE_U7_M ((PCNT_CH0_HCTRL_MODE_U7_V)<<(PCNT_CH0_HCTRL_MODE_U7_S)) -#define PCNT_CH0_HCTRL_MODE_U7_V 0x3 -#define PCNT_CH0_HCTRL_MODE_U7_S 20 -/* PCNT_CH0_POS_MODE_U7 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - posedge signal for unit7. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ -#define PCNT_CH0_POS_MODE_U7 0x00000003 -#define PCNT_CH0_POS_MODE_U7_M ((PCNT_CH0_POS_MODE_U7_V)<<(PCNT_CH0_POS_MODE_U7_S)) -#define PCNT_CH0_POS_MODE_U7_V 0x3 -#define PCNT_CH0_POS_MODE_U7_S 18 -/* PCNT_CH0_NEG_MODE_U7 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - negedge signal for unit7. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ -#define PCNT_CH0_NEG_MODE_U7 0x00000003 -#define PCNT_CH0_NEG_MODE_U7_M ((PCNT_CH0_NEG_MODE_U7_V)<<(PCNT_CH0_NEG_MODE_U7_S)) -#define PCNT_CH0_NEG_MODE_U7_V 0x3 -#define PCNT_CH0_NEG_MODE_U7_S 16 -/* PCNT_THR_THRES1_EN_U7 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit7's count with thres1 value .*/ -#define PCNT_THR_THRES1_EN_U7 (BIT(15)) -#define PCNT_THR_THRES1_EN_U7_M (BIT(15)) -#define PCNT_THR_THRES1_EN_U7_V 0x1 -#define PCNT_THR_THRES1_EN_U7_S 15 -/* PCNT_THR_THRES0_EN_U7 : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit7's count with thres0 value.*/ -#define PCNT_THR_THRES0_EN_U7 (BIT(14)) -#define PCNT_THR_THRES0_EN_U7_M (BIT(14)) -#define PCNT_THR_THRES0_EN_U7_V 0x1 -#define PCNT_THR_THRES0_EN_U7_S 14 -/* PCNT_THR_L_LIM_EN_U7 : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit7's count with thr_l_lim value.*/ -#define PCNT_THR_L_LIM_EN_U7 (BIT(13)) -#define PCNT_THR_L_LIM_EN_U7_M (BIT(13)) -#define PCNT_THR_L_LIM_EN_U7_V 0x1 -#define PCNT_THR_L_LIM_EN_U7_S 13 -/* PCNT_THR_H_LIM_EN_U7 : R/W ;bitpos:[12] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit7's count with thr_h_lim value.*/ -#define PCNT_THR_H_LIM_EN_U7 (BIT(12)) -#define PCNT_THR_H_LIM_EN_U7_M (BIT(12)) -#define PCNT_THR_H_LIM_EN_U7_V 0x1 -#define PCNT_THR_H_LIM_EN_U7_S 12 -/* PCNT_THR_ZERO_EN_U7 : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit7's count with 0 value.*/ -#define PCNT_THR_ZERO_EN_U7 (BIT(11)) -#define PCNT_THR_ZERO_EN_U7_M (BIT(11)) -#define PCNT_THR_ZERO_EN_U7_V 0x1 -#define PCNT_THR_ZERO_EN_U7_S 11 -/* PCNT_FILTER_EN_U7 : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: This is the enable bit for filtering input signals for unit7.*/ -#define PCNT_FILTER_EN_U7 (BIT(10)) -#define PCNT_FILTER_EN_U7_M (BIT(10)) -#define PCNT_FILTER_EN_U7_V 0x1 -#define PCNT_FILTER_EN_U7_S 10 -/* PCNT_FILTER_THRES_U7 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ -/*description: This register is used to filter pluse whose width is smaller - than this value for unit7.*/ -#define PCNT_FILTER_THRES_U7 0x000003FF -#define PCNT_FILTER_THRES_U7_M ((PCNT_FILTER_THRES_U7_V)<<(PCNT_FILTER_THRES_U7_S)) -#define PCNT_FILTER_THRES_U7_V 0x3FF -#define PCNT_FILTER_THRES_U7_S 0 - -#define PCNT_U7_CONF1_REG (DR_REG_PCNT_BASE + 0x0058) -/* PCNT_CNT_THRES1_U7 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to configure thres1 value for unit7.*/ -#define PCNT_CNT_THRES1_U7 0x0000FFFF -#define PCNT_CNT_THRES1_U7_M ((PCNT_CNT_THRES1_U7_V)<<(PCNT_CNT_THRES1_U7_S)) -#define PCNT_CNT_THRES1_U7_V 0xFFFF -#define PCNT_CNT_THRES1_U7_S 16 -/* PCNT_CNT_THRES0_U7 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thres0 value for unit7.*/ -#define PCNT_CNT_THRES0_U7 0x0000FFFF -#define PCNT_CNT_THRES0_U7_M ((PCNT_CNT_THRES0_U7_V)<<(PCNT_CNT_THRES0_U7_S)) -#define PCNT_CNT_THRES0_U7_V 0xFFFF -#define PCNT_CNT_THRES0_U7_S 0 - -#define PCNT_U7_CONF2_REG (DR_REG_PCNT_BASE + 0x005c) -/* PCNT_CNT_L_LIM_U7 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to confiugre thr_l_lim value for unit7.*/ -#define PCNT_CNT_L_LIM_U7 0x0000FFFF -#define PCNT_CNT_L_LIM_U7_M ((PCNT_CNT_L_LIM_U7_V)<<(PCNT_CNT_L_LIM_U7_S)) -#define PCNT_CNT_L_LIM_U7_V 0xFFFF -#define PCNT_CNT_L_LIM_U7_S 16 -/* PCNT_CNT_H_LIM_U7 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thr_h_lim value for unit7.*/ -#define PCNT_CNT_H_LIM_U7 0x0000FFFF -#define PCNT_CNT_H_LIM_U7_M ((PCNT_CNT_H_LIM_U7_V)<<(PCNT_CNT_H_LIM_U7_S)) -#define PCNT_CNT_H_LIM_U7_V 0xFFFF -#define PCNT_CNT_H_LIM_U7_S 0 - -#define PCNT_U0_CNT_REG (DR_REG_PCNT_BASE + 0x0060) -/* PCNT_PLUS_CNT_U0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: This register stores the current pulse count value for unit0.*/ -#define PCNT_PLUS_CNT_U0 0x0000FFFF -#define PCNT_PLUS_CNT_U0_M ((PCNT_PLUS_CNT_U0_V)<<(PCNT_PLUS_CNT_U0_S)) -#define PCNT_PLUS_CNT_U0_V 0xFFFF -#define PCNT_PLUS_CNT_U0_S 0 - -#define PCNT_U1_CNT_REG (DR_REG_PCNT_BASE + 0x0064) -/* PCNT_PLUS_CNT_U1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: This register stores the current pulse count value for unit1.*/ -#define PCNT_PLUS_CNT_U1 0x0000FFFF -#define PCNT_PLUS_CNT_U1_M ((PCNT_PLUS_CNT_U1_V)<<(PCNT_PLUS_CNT_U1_S)) -#define PCNT_PLUS_CNT_U1_V 0xFFFF -#define PCNT_PLUS_CNT_U1_S 0 - -#define PCNT_U2_CNT_REG (DR_REG_PCNT_BASE + 0x0068) -/* PCNT_PLUS_CNT_U2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: This register stores the current pulse count value for unit2.*/ -#define PCNT_PLUS_CNT_U2 0x0000FFFF -#define PCNT_PLUS_CNT_U2_M ((PCNT_PLUS_CNT_U2_V)<<(PCNT_PLUS_CNT_U2_S)) -#define PCNT_PLUS_CNT_U2_V 0xFFFF -#define PCNT_PLUS_CNT_U2_S 0 - -#define PCNT_U3_CNT_REG (DR_REG_PCNT_BASE + 0x006c) -/* PCNT_PLUS_CNT_U3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: This register stores the current pulse count value for unit3.*/ -#define PCNT_PLUS_CNT_U3 0x0000FFFF -#define PCNT_PLUS_CNT_U3_M ((PCNT_PLUS_CNT_U3_V)<<(PCNT_PLUS_CNT_U3_S)) -#define PCNT_PLUS_CNT_U3_V 0xFFFF -#define PCNT_PLUS_CNT_U3_S 0 - -#define PCNT_U4_CNT_REG (DR_REG_PCNT_BASE + 0x0070) -/* PCNT_PLUS_CNT_U4 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: This register stores the current pulse count value for unit4.*/ -#define PCNT_PLUS_CNT_U4 0x0000FFFF -#define PCNT_PLUS_CNT_U4_M ((PCNT_PLUS_CNT_U4_V)<<(PCNT_PLUS_CNT_U4_S)) -#define PCNT_PLUS_CNT_U4_V 0xFFFF -#define PCNT_PLUS_CNT_U4_S 0 - -#define PCNT_U5_CNT_REG (DR_REG_PCNT_BASE + 0x0074) -/* PCNT_PLUS_CNT_U5 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: This register stores the current pulse count value for unit5.*/ -#define PCNT_PLUS_CNT_U5 0x0000FFFF -#define PCNT_PLUS_CNT_U5_M ((PCNT_PLUS_CNT_U5_V)<<(PCNT_PLUS_CNT_U5_S)) -#define PCNT_PLUS_CNT_U5_V 0xFFFF -#define PCNT_PLUS_CNT_U5_S 0 - -#define PCNT_U6_CNT_REG (DR_REG_PCNT_BASE + 0x0078) -/* PCNT_PLUS_CNT_U6 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: This register stores the current pulse count value for unit6.*/ -#define PCNT_PLUS_CNT_U6 0x0000FFFF -#define PCNT_PLUS_CNT_U6_M ((PCNT_PLUS_CNT_U6_V)<<(PCNT_PLUS_CNT_U6_S)) -#define PCNT_PLUS_CNT_U6_V 0xFFFF -#define PCNT_PLUS_CNT_U6_S 0 - -#define PCNT_U7_CNT_REG (DR_REG_PCNT_BASE + 0x007c) -/* PCNT_PLUS_CNT_U7 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: This register stores the current pulse count value for unit7.*/ -#define PCNT_PLUS_CNT_U7 0x0000FFFF -#define PCNT_PLUS_CNT_U7_M ((PCNT_PLUS_CNT_U7_V)<<(PCNT_PLUS_CNT_U7_S)) -#define PCNT_PLUS_CNT_U7_V 0xFFFF -#define PCNT_PLUS_CNT_U7_S 0 - -#define PCNT_INT_RAW_REG (DR_REG_PCNT_BASE + 0x0080) -/* PCNT_CNT_THR_EVENT_U7_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: This is the interrupt raw bit for channel7 event.*/ -#define PCNT_CNT_THR_EVENT_U7_INT_RAW (BIT(7)) -#define PCNT_CNT_THR_EVENT_U7_INT_RAW_M (BIT(7)) -#define PCNT_CNT_THR_EVENT_U7_INT_RAW_V 0x1 -#define PCNT_CNT_THR_EVENT_U7_INT_RAW_S 7 -/* PCNT_CNT_THR_EVENT_U6_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: This is the interrupt raw bit for channel6 event.*/ -#define PCNT_CNT_THR_EVENT_U6_INT_RAW (BIT(6)) -#define PCNT_CNT_THR_EVENT_U6_INT_RAW_M (BIT(6)) -#define PCNT_CNT_THR_EVENT_U6_INT_RAW_V 0x1 -#define PCNT_CNT_THR_EVENT_U6_INT_RAW_S 6 -/* PCNT_CNT_THR_EVENT_U5_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This is the interrupt raw bit for channel5 event.*/ -#define PCNT_CNT_THR_EVENT_U5_INT_RAW (BIT(5)) -#define PCNT_CNT_THR_EVENT_U5_INT_RAW_M (BIT(5)) -#define PCNT_CNT_THR_EVENT_U5_INT_RAW_V 0x1 -#define PCNT_CNT_THR_EVENT_U5_INT_RAW_S 5 -/* PCNT_CNT_THR_EVENT_U4_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This is the interrupt raw bit for channel4 event.*/ -#define PCNT_CNT_THR_EVENT_U4_INT_RAW (BIT(4)) -#define PCNT_CNT_THR_EVENT_U4_INT_RAW_M (BIT(4)) -#define PCNT_CNT_THR_EVENT_U4_INT_RAW_V 0x1 -#define PCNT_CNT_THR_EVENT_U4_INT_RAW_S 4 -/* PCNT_CNT_THR_EVENT_U3_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This is the interrupt raw bit for channel3 event.*/ -#define PCNT_CNT_THR_EVENT_U3_INT_RAW (BIT(3)) -#define PCNT_CNT_THR_EVENT_U3_INT_RAW_M (BIT(3)) -#define PCNT_CNT_THR_EVENT_U3_INT_RAW_V 0x1 -#define PCNT_CNT_THR_EVENT_U3_INT_RAW_S 3 -/* PCNT_CNT_THR_EVENT_U2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the interrupt raw bit for channel2 event.*/ -#define PCNT_CNT_THR_EVENT_U2_INT_RAW (BIT(2)) -#define PCNT_CNT_THR_EVENT_U2_INT_RAW_M (BIT(2)) -#define PCNT_CNT_THR_EVENT_U2_INT_RAW_V 0x1 -#define PCNT_CNT_THR_EVENT_U2_INT_RAW_S 2 -/* PCNT_CNT_THR_EVENT_U1_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: This is the interrupt raw bit for channel1 event.*/ -#define PCNT_CNT_THR_EVENT_U1_INT_RAW (BIT(1)) -#define PCNT_CNT_THR_EVENT_U1_INT_RAW_M (BIT(1)) -#define PCNT_CNT_THR_EVENT_U1_INT_RAW_V 0x1 -#define PCNT_CNT_THR_EVENT_U1_INT_RAW_S 1 -/* PCNT_CNT_THR_EVENT_U0_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This is the interrupt raw bit for channel0 event.*/ -#define PCNT_CNT_THR_EVENT_U0_INT_RAW (BIT(0)) -#define PCNT_CNT_THR_EVENT_U0_INT_RAW_M (BIT(0)) -#define PCNT_CNT_THR_EVENT_U0_INT_RAW_V 0x1 -#define PCNT_CNT_THR_EVENT_U0_INT_RAW_S 0 - -#define PCNT_INT_ST_REG (DR_REG_PCNT_BASE + 0x0084) -/* PCNT_CNT_THR_EVENT_U7_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: This is the interrupt status bit for channel7 event.*/ -#define PCNT_CNT_THR_EVENT_U7_INT_ST (BIT(7)) -#define PCNT_CNT_THR_EVENT_U7_INT_ST_M (BIT(7)) -#define PCNT_CNT_THR_EVENT_U7_INT_ST_V 0x1 -#define PCNT_CNT_THR_EVENT_U7_INT_ST_S 7 -/* PCNT_CNT_THR_EVENT_U6_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: This is the interrupt status bit for channel6 event.*/ -#define PCNT_CNT_THR_EVENT_U6_INT_ST (BIT(6)) -#define PCNT_CNT_THR_EVENT_U6_INT_ST_M (BIT(6)) -#define PCNT_CNT_THR_EVENT_U6_INT_ST_V 0x1 -#define PCNT_CNT_THR_EVENT_U6_INT_ST_S 6 -/* PCNT_CNT_THR_EVENT_U5_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This is the interrupt status bit for channel5 event.*/ -#define PCNT_CNT_THR_EVENT_U5_INT_ST (BIT(5)) -#define PCNT_CNT_THR_EVENT_U5_INT_ST_M (BIT(5)) -#define PCNT_CNT_THR_EVENT_U5_INT_ST_V 0x1 -#define PCNT_CNT_THR_EVENT_U5_INT_ST_S 5 -/* PCNT_CNT_THR_EVENT_U4_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This is the interrupt status bit for channel4 event.*/ -#define PCNT_CNT_THR_EVENT_U4_INT_ST (BIT(4)) -#define PCNT_CNT_THR_EVENT_U4_INT_ST_M (BIT(4)) -#define PCNT_CNT_THR_EVENT_U4_INT_ST_V 0x1 -#define PCNT_CNT_THR_EVENT_U4_INT_ST_S 4 -/* PCNT_CNT_THR_EVENT_U3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This is the interrupt status bit for channel3 event.*/ -#define PCNT_CNT_THR_EVENT_U3_INT_ST (BIT(3)) -#define PCNT_CNT_THR_EVENT_U3_INT_ST_M (BIT(3)) -#define PCNT_CNT_THR_EVENT_U3_INT_ST_V 0x1 -#define PCNT_CNT_THR_EVENT_U3_INT_ST_S 3 -/* PCNT_CNT_THR_EVENT_U2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the interrupt status bit for channel2 event.*/ -#define PCNT_CNT_THR_EVENT_U2_INT_ST (BIT(2)) -#define PCNT_CNT_THR_EVENT_U2_INT_ST_M (BIT(2)) -#define PCNT_CNT_THR_EVENT_U2_INT_ST_V 0x1 -#define PCNT_CNT_THR_EVENT_U2_INT_ST_S 2 -/* PCNT_CNT_THR_EVENT_U1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: This is the interrupt status bit for channel1 event.*/ -#define PCNT_CNT_THR_EVENT_U1_INT_ST (BIT(1)) -#define PCNT_CNT_THR_EVENT_U1_INT_ST_M (BIT(1)) -#define PCNT_CNT_THR_EVENT_U1_INT_ST_V 0x1 -#define PCNT_CNT_THR_EVENT_U1_INT_ST_S 1 -/* PCNT_CNT_THR_EVENT_U0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This is the interrupt status bit for channel0 event.*/ -#define PCNT_CNT_THR_EVENT_U0_INT_ST (BIT(0)) -#define PCNT_CNT_THR_EVENT_U0_INT_ST_M (BIT(0)) -#define PCNT_CNT_THR_EVENT_U0_INT_ST_V 0x1 -#define PCNT_CNT_THR_EVENT_U0_INT_ST_S 0 - -#define PCNT_INT_ENA_REG (DR_REG_PCNT_BASE + 0x0088) -/* PCNT_CNT_THR_EVENT_U7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: This is the interrupt enable bit for channel7 event.*/ -#define PCNT_CNT_THR_EVENT_U7_INT_ENA (BIT(7)) -#define PCNT_CNT_THR_EVENT_U7_INT_ENA_M (BIT(7)) -#define PCNT_CNT_THR_EVENT_U7_INT_ENA_V 0x1 -#define PCNT_CNT_THR_EVENT_U7_INT_ENA_S 7 -/* PCNT_CNT_THR_EVENT_U6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: This is the interrupt enable bit for channel6 event.*/ -#define PCNT_CNT_THR_EVENT_U6_INT_ENA (BIT(6)) -#define PCNT_CNT_THR_EVENT_U6_INT_ENA_M (BIT(6)) -#define PCNT_CNT_THR_EVENT_U6_INT_ENA_V 0x1 -#define PCNT_CNT_THR_EVENT_U6_INT_ENA_S 6 -/* PCNT_CNT_THR_EVENT_U5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This is the interrupt enable bit for channel5 event.*/ -#define PCNT_CNT_THR_EVENT_U5_INT_ENA (BIT(5)) -#define PCNT_CNT_THR_EVENT_U5_INT_ENA_M (BIT(5)) -#define PCNT_CNT_THR_EVENT_U5_INT_ENA_V 0x1 -#define PCNT_CNT_THR_EVENT_U5_INT_ENA_S 5 -/* PCNT_CNT_THR_EVENT_U4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This is the interrupt enable bit for channel4 event.*/ -#define PCNT_CNT_THR_EVENT_U4_INT_ENA (BIT(4)) -#define PCNT_CNT_THR_EVENT_U4_INT_ENA_M (BIT(4)) -#define PCNT_CNT_THR_EVENT_U4_INT_ENA_V 0x1 -#define PCNT_CNT_THR_EVENT_U4_INT_ENA_S 4 -/* PCNT_CNT_THR_EVENT_U3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This is the interrupt enable bit for channel3 event.*/ -#define PCNT_CNT_THR_EVENT_U3_INT_ENA (BIT(3)) -#define PCNT_CNT_THR_EVENT_U3_INT_ENA_M (BIT(3)) -#define PCNT_CNT_THR_EVENT_U3_INT_ENA_V 0x1 -#define PCNT_CNT_THR_EVENT_U3_INT_ENA_S 3 -/* PCNT_CNT_THR_EVENT_U2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the interrupt enable bit for channel2 event.*/ -#define PCNT_CNT_THR_EVENT_U2_INT_ENA (BIT(2)) -#define PCNT_CNT_THR_EVENT_U2_INT_ENA_M (BIT(2)) -#define PCNT_CNT_THR_EVENT_U2_INT_ENA_V 0x1 -#define PCNT_CNT_THR_EVENT_U2_INT_ENA_S 2 -/* PCNT_CNT_THR_EVENT_U1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: This is the interrupt enable bit for channel1 event.*/ -#define PCNT_CNT_THR_EVENT_U1_INT_ENA (BIT(1)) -#define PCNT_CNT_THR_EVENT_U1_INT_ENA_M (BIT(1)) -#define PCNT_CNT_THR_EVENT_U1_INT_ENA_V 0x1 -#define PCNT_CNT_THR_EVENT_U1_INT_ENA_S 1 -/* PCNT_CNT_THR_EVENT_U0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This is the interrupt enable bit for channel0 event.*/ -#define PCNT_CNT_THR_EVENT_U0_INT_ENA (BIT(0)) -#define PCNT_CNT_THR_EVENT_U0_INT_ENA_M (BIT(0)) -#define PCNT_CNT_THR_EVENT_U0_INT_ENA_V 0x1 -#define PCNT_CNT_THR_EVENT_U0_INT_ENA_S 0 - -#define PCNT_INT_CLR_REG (DR_REG_PCNT_BASE + 0x008c) -/* PCNT_CNT_THR_EVENT_U7_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to clear channel7 event interrupt.*/ -#define PCNT_CNT_THR_EVENT_U7_INT_CLR (BIT(7)) -#define PCNT_CNT_THR_EVENT_U7_INT_CLR_M (BIT(7)) -#define PCNT_CNT_THR_EVENT_U7_INT_CLR_V 0x1 -#define PCNT_CNT_THR_EVENT_U7_INT_CLR_S 7 -/* PCNT_CNT_THR_EVENT_U6_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to clear channel6 event interrupt.*/ -#define PCNT_CNT_THR_EVENT_U6_INT_CLR (BIT(6)) -#define PCNT_CNT_THR_EVENT_U6_INT_CLR_M (BIT(6)) -#define PCNT_CNT_THR_EVENT_U6_INT_CLR_V 0x1 -#define PCNT_CNT_THR_EVENT_U6_INT_CLR_S 6 -/* PCNT_CNT_THR_EVENT_U5_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to clear channel5 event interrupt.*/ -#define PCNT_CNT_THR_EVENT_U5_INT_CLR (BIT(5)) -#define PCNT_CNT_THR_EVENT_U5_INT_CLR_M (BIT(5)) -#define PCNT_CNT_THR_EVENT_U5_INT_CLR_V 0x1 -#define PCNT_CNT_THR_EVENT_U5_INT_CLR_S 5 -/* PCNT_CNT_THR_EVENT_U4_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to clear channel4 event interrupt.*/ -#define PCNT_CNT_THR_EVENT_U4_INT_CLR (BIT(4)) -#define PCNT_CNT_THR_EVENT_U4_INT_CLR_M (BIT(4)) -#define PCNT_CNT_THR_EVENT_U4_INT_CLR_V 0x1 -#define PCNT_CNT_THR_EVENT_U4_INT_CLR_S 4 -/* PCNT_CNT_THR_EVENT_U3_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to clear channel3 event interrupt.*/ -#define PCNT_CNT_THR_EVENT_U3_INT_CLR (BIT(3)) -#define PCNT_CNT_THR_EVENT_U3_INT_CLR_M (BIT(3)) -#define PCNT_CNT_THR_EVENT_U3_INT_CLR_V 0x1 -#define PCNT_CNT_THR_EVENT_U3_INT_CLR_S 3 -/* PCNT_CNT_THR_EVENT_U2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to clear channel2 event interrupt.*/ -#define PCNT_CNT_THR_EVENT_U2_INT_CLR (BIT(2)) -#define PCNT_CNT_THR_EVENT_U2_INT_CLR_M (BIT(2)) -#define PCNT_CNT_THR_EVENT_U2_INT_CLR_V 0x1 -#define PCNT_CNT_THR_EVENT_U2_INT_CLR_S 2 -/* PCNT_CNT_THR_EVENT_U1_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to clear channel1 event interrupt.*/ -#define PCNT_CNT_THR_EVENT_U1_INT_CLR (BIT(1)) -#define PCNT_CNT_THR_EVENT_U1_INT_CLR_M (BIT(1)) -#define PCNT_CNT_THR_EVENT_U1_INT_CLR_V 0x1 -#define PCNT_CNT_THR_EVENT_U1_INT_CLR_S 1 -/* PCNT_CNT_THR_EVENT_U0_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to clear channel0 event interrupt.*/ -#define PCNT_CNT_THR_EVENT_U0_INT_CLR (BIT(0)) -#define PCNT_CNT_THR_EVENT_U0_INT_CLR_M (BIT(0)) -#define PCNT_CNT_THR_EVENT_U0_INT_CLR_V 0x1 -#define PCNT_CNT_THR_EVENT_U0_INT_CLR_S 0 - -#define PCNT_U0_STATUS_REG (DR_REG_PCNT_BASE + 0x0090) -/* PCNT_CORE_STATUS_U0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define PCNT_CORE_STATUS_U0 0xFFFFFFFF -#define PCNT_CORE_STATUS_U0_M ((PCNT_CORE_STATUS_U0_V)<<(PCNT_CORE_STATUS_U0_S)) -#define PCNT_CORE_STATUS_U0_V 0xFFFFFFFF -#define PCNT_CORE_STATUS_U0_S 0 -/*0: positive value to zero; 1: negative value to zero; 2: counter value negative ; 3: counter value positive*/ -#define PCNT_STATUS_CNT_MODE 0x3 -#define PCNT_STATUS_CNT_MODE_M ((PCNT_STATUS_CNT_MODE_V)<<(PCNT_STATUS_CNT_MODE_S)) -#define PCNT_STATUS_CNT_MODE_V 0x3 -#define PCNT_STATUS_CNT_MODE_S 0 -/* counter value equals to thresh1*/ -#define PCNT_STATUS_THRES1 BIT(2) -#define PCNT_STATUS_THRES1_M BIT(2) -#define PCNT_STATUS_THRES1_V 0x1 -#define PCNT_STATUS_THRES1_S 2 -/* counter value equals to thresh0*/ -#define PCNT_STATUS_THRES0 BIT(3) -#define PCNT_STATUS_THRES0_M BIT(3) -#define PCNT_STATUS_THRES0_V 0x1 -#define PCNT_STATUS_THRES0_S 3 -/* counter value reaches h_lim*/ -#define PCNT_STATUS_L_LIM BIT(4) -#define PCNT_STATUS_L_LIM_M BIT(4) -#define PCNT_STATUS_L_LIM_V 0x1 -#define PCNT_STATUS_L_LIM_S 4 -/* counter value reaches l_lim*/ -#define PCNT_STATUS_H_LIM BIT(5) -#define PCNT_STATUS_H_LIM_M BIT(5) -#define PCNT_STATUS_H_LIM_V 0x1 -#define PCNT_STATUS_H_LIM_S 5 -/* counter value equals to zero*/ -#define PCNT_STATUS_ZERO BIT(6) -#define PCNT_STATUS_ZERO_M BIT(6) -#define PCNT_STATUS_ZERO_V 0x1 -#define PCNT_STATUS_ZERO_S 6 - -#define PCNT_U1_STATUS_REG (DR_REG_PCNT_BASE + 0x0094) -/* PCNT_CORE_STATUS_U1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define PCNT_CORE_STATUS_U1 0xFFFFFFFF -#define PCNT_CORE_STATUS_U1_M ((PCNT_CORE_STATUS_U1_V)<<(PCNT_CORE_STATUS_U1_S)) -#define PCNT_CORE_STATUS_U1_V 0xFFFFFFFF -#define PCNT_CORE_STATUS_U1_S 0 - -#define PCNT_U2_STATUS_REG (DR_REG_PCNT_BASE + 0x0098) -/* PCNT_CORE_STATUS_U2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define PCNT_CORE_STATUS_U2 0xFFFFFFFF -#define PCNT_CORE_STATUS_U2_M ((PCNT_CORE_STATUS_U2_V)<<(PCNT_CORE_STATUS_U2_S)) -#define PCNT_CORE_STATUS_U2_V 0xFFFFFFFF -#define PCNT_CORE_STATUS_U2_S 0 - -#define PCNT_U3_STATUS_REG (DR_REG_PCNT_BASE + 0x009c) -/* PCNT_CORE_STATUS_U3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define PCNT_CORE_STATUS_U3 0xFFFFFFFF -#define PCNT_CORE_STATUS_U3_M ((PCNT_CORE_STATUS_U3_V)<<(PCNT_CORE_STATUS_U3_S)) -#define PCNT_CORE_STATUS_U3_V 0xFFFFFFFF -#define PCNT_CORE_STATUS_U3_S 0 - -#define PCNT_U4_STATUS_REG (DR_REG_PCNT_BASE + 0x00a0) -/* PCNT_CORE_STATUS_U4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define PCNT_CORE_STATUS_U4 0xFFFFFFFF -#define PCNT_CORE_STATUS_U4_M ((PCNT_CORE_STATUS_U4_V)<<(PCNT_CORE_STATUS_U4_S)) -#define PCNT_CORE_STATUS_U4_V 0xFFFFFFFF -#define PCNT_CORE_STATUS_U4_S 0 - -#define PCNT_U5_STATUS_REG (DR_REG_PCNT_BASE + 0x00a4) -/* PCNT_CORE_STATUS_U5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define PCNT_CORE_STATUS_U5 0xFFFFFFFF -#define PCNT_CORE_STATUS_U5_M ((PCNT_CORE_STATUS_U5_V)<<(PCNT_CORE_STATUS_U5_S)) -#define PCNT_CORE_STATUS_U5_V 0xFFFFFFFF -#define PCNT_CORE_STATUS_U5_S 0 - -#define PCNT_U6_STATUS_REG (DR_REG_PCNT_BASE + 0x00a8) -/* PCNT_CORE_STATUS_U6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define PCNT_CORE_STATUS_U6 0xFFFFFFFF -#define PCNT_CORE_STATUS_U6_M ((PCNT_CORE_STATUS_U6_V)<<(PCNT_CORE_STATUS_U6_S)) -#define PCNT_CORE_STATUS_U6_V 0xFFFFFFFF -#define PCNT_CORE_STATUS_U6_S 0 - -#define PCNT_U7_STATUS_REG (DR_REG_PCNT_BASE + 0x00ac) -/* PCNT_CORE_STATUS_U7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define PCNT_CORE_STATUS_U7 0xFFFFFFFF -#define PCNT_CORE_STATUS_U7_M ((PCNT_CORE_STATUS_U7_V)<<(PCNT_CORE_STATUS_U7_S)) -#define PCNT_CORE_STATUS_U7_V 0xFFFFFFFF -#define PCNT_CORE_STATUS_U7_S 0 - -#define PCNT_CTRL_REG (DR_REG_PCNT_BASE + 0x00b0) -/* PCNT_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CLK_EN (BIT(16)) -#define PCNT_CLK_EN_M (BIT(16)) -#define PCNT_CLK_EN_V 0x1 -#define PCNT_CLK_EN_S 16 -/* PCNT_CNT_PAUSE_U7 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: Set this bit to pause unit7's counter.*/ -#define PCNT_CNT_PAUSE_U7 (BIT(15)) -#define PCNT_CNT_PAUSE_U7_M (BIT(15)) -#define PCNT_CNT_PAUSE_U7_V 0x1 -#define PCNT_CNT_PAUSE_U7_S 15 -/* PCNT_PLUS_CNT_RST_U7 : R/W ;bitpos:[14] ;default: 1'b1 ; */ -/*description: Set this bit to clear unit7's counter.*/ -#define PCNT_PLUS_CNT_RST_U7 (BIT(14)) -#define PCNT_PLUS_CNT_RST_U7_M (BIT(14)) -#define PCNT_PLUS_CNT_RST_U7_V 0x1 -#define PCNT_PLUS_CNT_RST_U7_S 14 -/* PCNT_CNT_PAUSE_U6 : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Set this bit to pause unit6's counter.*/ -#define PCNT_CNT_PAUSE_U6 (BIT(13)) -#define PCNT_CNT_PAUSE_U6_M (BIT(13)) -#define PCNT_CNT_PAUSE_U6_V 0x1 -#define PCNT_CNT_PAUSE_U6_S 13 -/* PCNT_PLUS_CNT_RST_U6 : R/W ;bitpos:[12] ;default: 1'b1 ; */ -/*description: Set this bit to clear unit6's counter.*/ -#define PCNT_PLUS_CNT_RST_U6 (BIT(12)) -#define PCNT_PLUS_CNT_RST_U6_M (BIT(12)) -#define PCNT_PLUS_CNT_RST_U6_V 0x1 -#define PCNT_PLUS_CNT_RST_U6_S 12 -/* PCNT_CNT_PAUSE_U5 : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Set this bit to pause unit5's counter.*/ -#define PCNT_CNT_PAUSE_U5 (BIT(11)) -#define PCNT_CNT_PAUSE_U5_M (BIT(11)) -#define PCNT_CNT_PAUSE_U5_V 0x1 -#define PCNT_CNT_PAUSE_U5_S 11 -/* PCNT_PLUS_CNT_RST_U5 : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: Set this bit to clear unit5's counter.*/ -#define PCNT_PLUS_CNT_RST_U5 (BIT(10)) -#define PCNT_PLUS_CNT_RST_U5_M (BIT(10)) -#define PCNT_PLUS_CNT_RST_U5_V 0x1 -#define PCNT_PLUS_CNT_RST_U5_S 10 -/* PCNT_CNT_PAUSE_U4 : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to pause unit4's counter.*/ -#define PCNT_CNT_PAUSE_U4 (BIT(9)) -#define PCNT_CNT_PAUSE_U4_M (BIT(9)) -#define PCNT_CNT_PAUSE_U4_V 0x1 -#define PCNT_CNT_PAUSE_U4_S 9 -/* PCNT_PLUS_CNT_RST_U4 : R/W ;bitpos:[8] ;default: 1'b1 ; */ -/*description: Set this bit to clear unit4's counter.*/ -#define PCNT_PLUS_CNT_RST_U4 (BIT(8)) -#define PCNT_PLUS_CNT_RST_U4_M (BIT(8)) -#define PCNT_PLUS_CNT_RST_U4_V 0x1 -#define PCNT_PLUS_CNT_RST_U4_S 8 -/* PCNT_CNT_PAUSE_U3 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to pause unit3's counter.*/ -#define PCNT_CNT_PAUSE_U3 (BIT(7)) -#define PCNT_CNT_PAUSE_U3_M (BIT(7)) -#define PCNT_CNT_PAUSE_U3_V 0x1 -#define PCNT_CNT_PAUSE_U3_S 7 -/* PCNT_PLUS_CNT_RST_U3 : R/W ;bitpos:[6] ;default: 1'b1 ; */ -/*description: Set this bit to clear unit3's counter.*/ -#define PCNT_PLUS_CNT_RST_U3 (BIT(6)) -#define PCNT_PLUS_CNT_RST_U3_M (BIT(6)) -#define PCNT_PLUS_CNT_RST_U3_V 0x1 -#define PCNT_PLUS_CNT_RST_U3_S 6 -/* PCNT_CNT_PAUSE_U2 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to pause unit2's counter.*/ -#define PCNT_CNT_PAUSE_U2 (BIT(5)) -#define PCNT_CNT_PAUSE_U2_M (BIT(5)) -#define PCNT_CNT_PAUSE_U2_V 0x1 -#define PCNT_CNT_PAUSE_U2_S 5 -/* PCNT_PLUS_CNT_RST_U2 : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: Set this bit to clear unit2's counter.*/ -#define PCNT_PLUS_CNT_RST_U2 (BIT(4)) -#define PCNT_PLUS_CNT_RST_U2_M (BIT(4)) -#define PCNT_PLUS_CNT_RST_U2_V 0x1 -#define PCNT_PLUS_CNT_RST_U2_S 4 -/* PCNT_CNT_PAUSE_U1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to pause unit1's counter.*/ -#define PCNT_CNT_PAUSE_U1 (BIT(3)) -#define PCNT_CNT_PAUSE_U1_M (BIT(3)) -#define PCNT_CNT_PAUSE_U1_V 0x1 -#define PCNT_CNT_PAUSE_U1_S 3 -/* PCNT_PLUS_CNT_RST_U1 : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: Set this bit to clear unit1's counter.*/ -#define PCNT_PLUS_CNT_RST_U1 (BIT(2)) -#define PCNT_PLUS_CNT_RST_U1_M (BIT(2)) -#define PCNT_PLUS_CNT_RST_U1_V 0x1 -#define PCNT_PLUS_CNT_RST_U1_S 2 -/* PCNT_CNT_PAUSE_U0 : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to pause unit0's counter.*/ -#define PCNT_CNT_PAUSE_U0 (BIT(1)) -#define PCNT_CNT_PAUSE_U0_M (BIT(1)) -#define PCNT_CNT_PAUSE_U0_V 0x1 -#define PCNT_CNT_PAUSE_U0_S 1 -/* PCNT_PLUS_CNT_RST_U0 : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: Set this bit to clear unit0's counter.*/ -#define PCNT_PLUS_CNT_RST_U0 (BIT(0)) -#define PCNT_PLUS_CNT_RST_U0_M (BIT(0)) -#define PCNT_PLUS_CNT_RST_U0_V 0x1 -#define PCNT_PLUS_CNT_RST_U0_S 0 - -#define PCNT_DATE_REG (DR_REG_PCNT_BASE + 0x00fc) -/* PCNT_DATE : R/W ;bitpos:[31:0] ;default: 32'h14122600 ; */ -/*description: */ -#define PCNT_DATE 0xFFFFFFFF -#define PCNT_DATE_M ((PCNT_DATE_V)<<(PCNT_DATE_S)) -#define PCNT_DATE_V 0xFFFFFFFF -#define PCNT_DATE_S 0 - - - - -#endif /*_SOC_PCNT_REG_H_ */ - - +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_PCNT_REG_H_ +#define _SOC_PCNT_REG_H_ + + +#include "soc.h" +#define PCNT_U0_CONF0_REG (DR_REG_PCNT_BASE + 0x0000) +/* PCNT_CH1_LCTRL_MODE_U0 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's low control + signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_LCTRL_MODE_U0 0x00000003 +#define PCNT_CH1_LCTRL_MODE_U0_M ((PCNT_CH1_LCTRL_MODE_U0_V)<<(PCNT_CH1_LCTRL_MODE_U0_S)) +#define PCNT_CH1_LCTRL_MODE_U0_V 0x3 +#define PCNT_CH1_LCTRL_MODE_U0_S 30 +/* PCNT_CH1_HCTRL_MODE_U0 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's high + control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_HCTRL_MODE_U0 0x00000003 +#define PCNT_CH1_HCTRL_MODE_U0_M ((PCNT_CH1_HCTRL_MODE_U0_V)<<(PCNT_CH1_HCTRL_MODE_U0_S)) +#define PCNT_CH1_HCTRL_MODE_U0_V 0x3 +#define PCNT_CH1_HCTRL_MODE_U0_S 28 +/* PCNT_CH1_POS_MODE_U0 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + posedge signal for unit0. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH1_POS_MODE_U0 0x00000003 +#define PCNT_CH1_POS_MODE_U0_M ((PCNT_CH1_POS_MODE_U0_V)<<(PCNT_CH1_POS_MODE_U0_S)) +#define PCNT_CH1_POS_MODE_U0_V 0x3 +#define PCNT_CH1_POS_MODE_U0_S 26 +/* PCNT_CH1_NEG_MODE_U0 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + negedge signal for unit0. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH1_NEG_MODE_U0 0x00000003 +#define PCNT_CH1_NEG_MODE_U0_M ((PCNT_CH1_NEG_MODE_U0_V)<<(PCNT_CH1_NEG_MODE_U0_S)) +#define PCNT_CH1_NEG_MODE_U0_V 0x3 +#define PCNT_CH1_NEG_MODE_U0_S 24 +/* PCNT_CH0_LCTRL_MODE_U0 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's low control + signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_LCTRL_MODE_U0 0x00000003 +#define PCNT_CH0_LCTRL_MODE_U0_M ((PCNT_CH0_LCTRL_MODE_U0_V)<<(PCNT_CH0_LCTRL_MODE_U0_S)) +#define PCNT_CH0_LCTRL_MODE_U0_V 0x3 +#define PCNT_CH0_LCTRL_MODE_U0_S 22 +/* PCNT_CH0_HCTRL_MODE_U0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's high + control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_HCTRL_MODE_U0 0x00000003 +#define PCNT_CH0_HCTRL_MODE_U0_M ((PCNT_CH0_HCTRL_MODE_U0_V)<<(PCNT_CH0_HCTRL_MODE_U0_S)) +#define PCNT_CH0_HCTRL_MODE_U0_V 0x3 +#define PCNT_CH0_HCTRL_MODE_U0_S 20 +/* PCNT_CH0_POS_MODE_U0 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + posedge signal for unit0. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH0_POS_MODE_U0 0x00000003 +#define PCNT_CH0_POS_MODE_U0_M ((PCNT_CH0_POS_MODE_U0_V)<<(PCNT_CH0_POS_MODE_U0_S)) +#define PCNT_CH0_POS_MODE_U0_V 0x3 +#define PCNT_CH0_POS_MODE_U0_S 18 +/* PCNT_CH0_NEG_MODE_U0 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + negedge signal for unit0. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH0_NEG_MODE_U0 0x00000003 +#define PCNT_CH0_NEG_MODE_U0_M ((PCNT_CH0_NEG_MODE_U0_V)<<(PCNT_CH0_NEG_MODE_U0_S)) +#define PCNT_CH0_NEG_MODE_U0_V 0x3 +#define PCNT_CH0_NEG_MODE_U0_S 16 +/* PCNT_THR_THRES1_EN_U0 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit0's count with thres1 value .*/ +#define PCNT_THR_THRES1_EN_U0 (BIT(15)) +#define PCNT_THR_THRES1_EN_U0_M (BIT(15)) +#define PCNT_THR_THRES1_EN_U0_V 0x1 +#define PCNT_THR_THRES1_EN_U0_S 15 +/* PCNT_THR_THRES0_EN_U0 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit0's count with thres0 value.*/ +#define PCNT_THR_THRES0_EN_U0 (BIT(14)) +#define PCNT_THR_THRES0_EN_U0_M (BIT(14)) +#define PCNT_THR_THRES0_EN_U0_V 0x1 +#define PCNT_THR_THRES0_EN_U0_S 14 +/* PCNT_THR_L_LIM_EN_U0 : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit0's count with thr_l_lim value.*/ +#define PCNT_THR_L_LIM_EN_U0 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U0_M (BIT(13)) +#define PCNT_THR_L_LIM_EN_U0_V 0x1 +#define PCNT_THR_L_LIM_EN_U0_S 13 +/* PCNT_THR_H_LIM_EN_U0 : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit0's count with thr_h_lim value.*/ +#define PCNT_THR_H_LIM_EN_U0 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U0_M (BIT(12)) +#define PCNT_THR_H_LIM_EN_U0_V 0x1 +#define PCNT_THR_H_LIM_EN_U0_S 12 +/* PCNT_THR_ZERO_EN_U0 : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit0's count with 0 value.*/ +#define PCNT_THR_ZERO_EN_U0 (BIT(11)) +#define PCNT_THR_ZERO_EN_U0_M (BIT(11)) +#define PCNT_THR_ZERO_EN_U0_V 0x1 +#define PCNT_THR_ZERO_EN_U0_S 11 +/* PCNT_FILTER_EN_U0 : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: This is the enable bit for filtering input signals for unit0.*/ +#define PCNT_FILTER_EN_U0 (BIT(10)) +#define PCNT_FILTER_EN_U0_M (BIT(10)) +#define PCNT_FILTER_EN_U0_V 0x1 +#define PCNT_FILTER_EN_U0_S 10 +/* PCNT_FILTER_THRES_U0 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ +/*description: This register is used to filter pluse whose width is smaller + than this value for unit0.*/ +#define PCNT_FILTER_THRES_U0 0x000003FF +#define PCNT_FILTER_THRES_U0_M ((PCNT_FILTER_THRES_U0_V)<<(PCNT_FILTER_THRES_U0_S)) +#define PCNT_FILTER_THRES_U0_V 0x3FF +#define PCNT_FILTER_THRES_U0_S 0 + +#define PCNT_U0_CONF1_REG (DR_REG_PCNT_BASE + 0x0004) +/* PCNT_CNT_THRES1_U0 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to configure thres1 value for unit0.*/ +#define PCNT_CNT_THRES1_U0 0x0000FFFF +#define PCNT_CNT_THRES1_U0_M ((PCNT_CNT_THRES1_U0_V)<<(PCNT_CNT_THRES1_U0_S)) +#define PCNT_CNT_THRES1_U0_V 0xFFFF +#define PCNT_CNT_THRES1_U0_S 16 +/* PCNT_CNT_THRES0_U0 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thres0 value for unit0.*/ +#define PCNT_CNT_THRES0_U0 0x0000FFFF +#define PCNT_CNT_THRES0_U0_M ((PCNT_CNT_THRES0_U0_V)<<(PCNT_CNT_THRES0_U0_S)) +#define PCNT_CNT_THRES0_U0_V 0xFFFF +#define PCNT_CNT_THRES0_U0_S 0 + +#define PCNT_U0_CONF2_REG (DR_REG_PCNT_BASE + 0x0008) +/* PCNT_CNT_L_LIM_U0 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to confiugre thr_l_lim value for unit0.*/ +#define PCNT_CNT_L_LIM_U0 0x0000FFFF +#define PCNT_CNT_L_LIM_U0_M ((PCNT_CNT_L_LIM_U0_V)<<(PCNT_CNT_L_LIM_U0_S)) +#define PCNT_CNT_L_LIM_U0_V 0xFFFF +#define PCNT_CNT_L_LIM_U0_S 16 +/* PCNT_CNT_H_LIM_U0 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thr_h_lim value for unit0.*/ +#define PCNT_CNT_H_LIM_U0 0x0000FFFF +#define PCNT_CNT_H_LIM_U0_M ((PCNT_CNT_H_LIM_U0_V)<<(PCNT_CNT_H_LIM_U0_S)) +#define PCNT_CNT_H_LIM_U0_V 0xFFFF +#define PCNT_CNT_H_LIM_U0_S 0 + +#define PCNT_U1_CONF0_REG (DR_REG_PCNT_BASE + 0x000c) +/* PCNT_CH1_LCTRL_MODE_U1 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's low control + signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_LCTRL_MODE_U1 0x00000003 +#define PCNT_CH1_LCTRL_MODE_U1_M ((PCNT_CH1_LCTRL_MODE_U1_V)<<(PCNT_CH1_LCTRL_MODE_U1_S)) +#define PCNT_CH1_LCTRL_MODE_U1_V 0x3 +#define PCNT_CH1_LCTRL_MODE_U1_S 30 +/* PCNT_CH1_HCTRL_MODE_U1 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's high + control signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_HCTRL_MODE_U1 0x00000003 +#define PCNT_CH1_HCTRL_MODE_U1_M ((PCNT_CH1_HCTRL_MODE_U1_V)<<(PCNT_CH1_HCTRL_MODE_U1_S)) +#define PCNT_CH1_HCTRL_MODE_U1_V 0x3 +#define PCNT_CH1_HCTRL_MODE_U1_S 28 +/* PCNT_CH1_POS_MODE_U1 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + posedge signal for unit1. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH1_POS_MODE_U1 0x00000003 +#define PCNT_CH1_POS_MODE_U1_M ((PCNT_CH1_POS_MODE_U1_V)<<(PCNT_CH1_POS_MODE_U1_S)) +#define PCNT_CH1_POS_MODE_U1_V 0x3 +#define PCNT_CH1_POS_MODE_U1_S 26 +/* PCNT_CH1_NEG_MODE_U1 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + negedge signal for unit1. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH1_NEG_MODE_U1 0x00000003 +#define PCNT_CH1_NEG_MODE_U1_M ((PCNT_CH1_NEG_MODE_U1_V)<<(PCNT_CH1_NEG_MODE_U1_S)) +#define PCNT_CH1_NEG_MODE_U1_V 0x3 +#define PCNT_CH1_NEG_MODE_U1_S 24 +/* PCNT_CH0_LCTRL_MODE_U1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's low control + signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_LCTRL_MODE_U1 0x00000003 +#define PCNT_CH0_LCTRL_MODE_U1_M ((PCNT_CH0_LCTRL_MODE_U1_V)<<(PCNT_CH0_LCTRL_MODE_U1_S)) +#define PCNT_CH0_LCTRL_MODE_U1_V 0x3 +#define PCNT_CH0_LCTRL_MODE_U1_S 22 +/* PCNT_CH0_HCTRL_MODE_U1 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's high + control signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_HCTRL_MODE_U1 0x00000003 +#define PCNT_CH0_HCTRL_MODE_U1_M ((PCNT_CH0_HCTRL_MODE_U1_V)<<(PCNT_CH0_HCTRL_MODE_U1_S)) +#define PCNT_CH0_HCTRL_MODE_U1_V 0x3 +#define PCNT_CH0_HCTRL_MODE_U1_S 20 +/* PCNT_CH0_POS_MODE_U1 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + posedge signal for unit1. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH0_POS_MODE_U1 0x00000003 +#define PCNT_CH0_POS_MODE_U1_M ((PCNT_CH0_POS_MODE_U1_V)<<(PCNT_CH0_POS_MODE_U1_S)) +#define PCNT_CH0_POS_MODE_U1_V 0x3 +#define PCNT_CH0_POS_MODE_U1_S 18 +/* PCNT_CH0_NEG_MODE_U1 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + negedge signal for unit1. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH0_NEG_MODE_U1 0x00000003 +#define PCNT_CH0_NEG_MODE_U1_M ((PCNT_CH0_NEG_MODE_U1_V)<<(PCNT_CH0_NEG_MODE_U1_S)) +#define PCNT_CH0_NEG_MODE_U1_V 0x3 +#define PCNT_CH0_NEG_MODE_U1_S 16 +/* PCNT_THR_THRES1_EN_U1 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit1's count with thres1 value .*/ +#define PCNT_THR_THRES1_EN_U1 (BIT(15)) +#define PCNT_THR_THRES1_EN_U1_M (BIT(15)) +#define PCNT_THR_THRES1_EN_U1_V 0x1 +#define PCNT_THR_THRES1_EN_U1_S 15 +/* PCNT_THR_THRES0_EN_U1 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit1's count with thres0 value.*/ +#define PCNT_THR_THRES0_EN_U1 (BIT(14)) +#define PCNT_THR_THRES0_EN_U1_M (BIT(14)) +#define PCNT_THR_THRES0_EN_U1_V 0x1 +#define PCNT_THR_THRES0_EN_U1_S 14 +/* PCNT_THR_L_LIM_EN_U1 : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit1's count with thr_l_lim value.*/ +#define PCNT_THR_L_LIM_EN_U1 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U1_M (BIT(13)) +#define PCNT_THR_L_LIM_EN_U1_V 0x1 +#define PCNT_THR_L_LIM_EN_U1_S 13 +/* PCNT_THR_H_LIM_EN_U1 : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit1's count with thr_h_lim value.*/ +#define PCNT_THR_H_LIM_EN_U1 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U1_M (BIT(12)) +#define PCNT_THR_H_LIM_EN_U1_V 0x1 +#define PCNT_THR_H_LIM_EN_U1_S 12 +/* PCNT_THR_ZERO_EN_U1 : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit1's count with 0 value.*/ +#define PCNT_THR_ZERO_EN_U1 (BIT(11)) +#define PCNT_THR_ZERO_EN_U1_M (BIT(11)) +#define PCNT_THR_ZERO_EN_U1_V 0x1 +#define PCNT_THR_ZERO_EN_U1_S 11 +/* PCNT_FILTER_EN_U1 : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: This is the enable bit for filtering input signals for unit1.*/ +#define PCNT_FILTER_EN_U1 (BIT(10)) +#define PCNT_FILTER_EN_U1_M (BIT(10)) +#define PCNT_FILTER_EN_U1_V 0x1 +#define PCNT_FILTER_EN_U1_S 10 +/* PCNT_FILTER_THRES_U1 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ +/*description: This register is used to filter pluse whose width is smaller + than this value for unit1.*/ +#define PCNT_FILTER_THRES_U1 0x000003FF +#define PCNT_FILTER_THRES_U1_M ((PCNT_FILTER_THRES_U1_V)<<(PCNT_FILTER_THRES_U1_S)) +#define PCNT_FILTER_THRES_U1_V 0x3FF +#define PCNT_FILTER_THRES_U1_S 0 + +#define PCNT_U1_CONF1_REG (DR_REG_PCNT_BASE + 0x0010) +/* PCNT_CNT_THRES1_U1 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to configure thres1 value for unit1.*/ +#define PCNT_CNT_THRES1_U1 0x0000FFFF +#define PCNT_CNT_THRES1_U1_M ((PCNT_CNT_THRES1_U1_V)<<(PCNT_CNT_THRES1_U1_S)) +#define PCNT_CNT_THRES1_U1_V 0xFFFF +#define PCNT_CNT_THRES1_U1_S 16 +/* PCNT_CNT_THRES0_U1 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thres0 value for unit1.*/ +#define PCNT_CNT_THRES0_U1 0x0000FFFF +#define PCNT_CNT_THRES0_U1_M ((PCNT_CNT_THRES0_U1_V)<<(PCNT_CNT_THRES0_U1_S)) +#define PCNT_CNT_THRES0_U1_V 0xFFFF +#define PCNT_CNT_THRES0_U1_S 0 + +#define PCNT_U1_CONF2_REG (DR_REG_PCNT_BASE + 0x0014) +/* PCNT_CNT_L_LIM_U1 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to confiugre thr_l_lim value for unit1.*/ +#define PCNT_CNT_L_LIM_U1 0x0000FFFF +#define PCNT_CNT_L_LIM_U1_M ((PCNT_CNT_L_LIM_U1_V)<<(PCNT_CNT_L_LIM_U1_S)) +#define PCNT_CNT_L_LIM_U1_V 0xFFFF +#define PCNT_CNT_L_LIM_U1_S 16 +/* PCNT_CNT_H_LIM_U1 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thr_h_lim value for unit1.*/ +#define PCNT_CNT_H_LIM_U1 0x0000FFFF +#define PCNT_CNT_H_LIM_U1_M ((PCNT_CNT_H_LIM_U1_V)<<(PCNT_CNT_H_LIM_U1_S)) +#define PCNT_CNT_H_LIM_U1_V 0xFFFF +#define PCNT_CNT_H_LIM_U1_S 0 + +#define PCNT_U2_CONF0_REG (DR_REG_PCNT_BASE + 0x0018) +/* PCNT_CH1_LCTRL_MODE_U2 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's low control + signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_LCTRL_MODE_U2 0x00000003 +#define PCNT_CH1_LCTRL_MODE_U2_M ((PCNT_CH1_LCTRL_MODE_U2_V)<<(PCNT_CH1_LCTRL_MODE_U2_S)) +#define PCNT_CH1_LCTRL_MODE_U2_V 0x3 +#define PCNT_CH1_LCTRL_MODE_U2_S 30 +/* PCNT_CH1_HCTRL_MODE_U2 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's high + control signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_HCTRL_MODE_U2 0x00000003 +#define PCNT_CH1_HCTRL_MODE_U2_M ((PCNT_CH1_HCTRL_MODE_U2_V)<<(PCNT_CH1_HCTRL_MODE_U2_S)) +#define PCNT_CH1_HCTRL_MODE_U2_V 0x3 +#define PCNT_CH1_HCTRL_MODE_U2_S 28 +/* PCNT_CH1_POS_MODE_U2 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + posedge signal for unit2. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH1_POS_MODE_U2 0x00000003 +#define PCNT_CH1_POS_MODE_U2_M ((PCNT_CH1_POS_MODE_U2_V)<<(PCNT_CH1_POS_MODE_U2_S)) +#define PCNT_CH1_POS_MODE_U2_V 0x3 +#define PCNT_CH1_POS_MODE_U2_S 26 +/* PCNT_CH1_NEG_MODE_U2 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + negedge signal for unit2. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH1_NEG_MODE_U2 0x00000003 +#define PCNT_CH1_NEG_MODE_U2_M ((PCNT_CH1_NEG_MODE_U2_V)<<(PCNT_CH1_NEG_MODE_U2_S)) +#define PCNT_CH1_NEG_MODE_U2_V 0x3 +#define PCNT_CH1_NEG_MODE_U2_S 24 +/* PCNT_CH0_LCTRL_MODE_U2 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's low control + signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_LCTRL_MODE_U2 0x00000003 +#define PCNT_CH0_LCTRL_MODE_U2_M ((PCNT_CH0_LCTRL_MODE_U2_V)<<(PCNT_CH0_LCTRL_MODE_U2_S)) +#define PCNT_CH0_LCTRL_MODE_U2_V 0x3 +#define PCNT_CH0_LCTRL_MODE_U2_S 22 +/* PCNT_CH0_HCTRL_MODE_U2 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's high + control signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_HCTRL_MODE_U2 0x00000003 +#define PCNT_CH0_HCTRL_MODE_U2_M ((PCNT_CH0_HCTRL_MODE_U2_V)<<(PCNT_CH0_HCTRL_MODE_U2_S)) +#define PCNT_CH0_HCTRL_MODE_U2_V 0x3 +#define PCNT_CH0_HCTRL_MODE_U2_S 20 +/* PCNT_CH0_POS_MODE_U2 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + posedge signal for unit2. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH0_POS_MODE_U2 0x00000003 +#define PCNT_CH0_POS_MODE_U2_M ((PCNT_CH0_POS_MODE_U2_V)<<(PCNT_CH0_POS_MODE_U2_S)) +#define PCNT_CH0_POS_MODE_U2_V 0x3 +#define PCNT_CH0_POS_MODE_U2_S 18 +/* PCNT_CH0_NEG_MODE_U2 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + negedge signal for unit2. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH0_NEG_MODE_U2 0x00000003 +#define PCNT_CH0_NEG_MODE_U2_M ((PCNT_CH0_NEG_MODE_U2_V)<<(PCNT_CH0_NEG_MODE_U2_S)) +#define PCNT_CH0_NEG_MODE_U2_V 0x3 +#define PCNT_CH0_NEG_MODE_U2_S 16 +/* PCNT_THR_THRES1_EN_U2 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit2's count with thres1 value .*/ +#define PCNT_THR_THRES1_EN_U2 (BIT(15)) +#define PCNT_THR_THRES1_EN_U2_M (BIT(15)) +#define PCNT_THR_THRES1_EN_U2_V 0x1 +#define PCNT_THR_THRES1_EN_U2_S 15 +/* PCNT_THR_THRES0_EN_U2 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit2's count with thres0 value.*/ +#define PCNT_THR_THRES0_EN_U2 (BIT(14)) +#define PCNT_THR_THRES0_EN_U2_M (BIT(14)) +#define PCNT_THR_THRES0_EN_U2_V 0x1 +#define PCNT_THR_THRES0_EN_U2_S 14 +/* PCNT_THR_L_LIM_EN_U2 : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit2's count with thr_l_lim value.*/ +#define PCNT_THR_L_LIM_EN_U2 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U2_M (BIT(13)) +#define PCNT_THR_L_LIM_EN_U2_V 0x1 +#define PCNT_THR_L_LIM_EN_U2_S 13 +/* PCNT_THR_H_LIM_EN_U2 : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit2's count with thr_h_lim value.*/ +#define PCNT_THR_H_LIM_EN_U2 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U2_M (BIT(12)) +#define PCNT_THR_H_LIM_EN_U2_V 0x1 +#define PCNT_THR_H_LIM_EN_U2_S 12 +/* PCNT_THR_ZERO_EN_U2 : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit2's count with 0 value.*/ +#define PCNT_THR_ZERO_EN_U2 (BIT(11)) +#define PCNT_THR_ZERO_EN_U2_M (BIT(11)) +#define PCNT_THR_ZERO_EN_U2_V 0x1 +#define PCNT_THR_ZERO_EN_U2_S 11 +/* PCNT_FILTER_EN_U2 : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: This is the enable bit for filtering input signals for unit2.*/ +#define PCNT_FILTER_EN_U2 (BIT(10)) +#define PCNT_FILTER_EN_U2_M (BIT(10)) +#define PCNT_FILTER_EN_U2_V 0x1 +#define PCNT_FILTER_EN_U2_S 10 +/* PCNT_FILTER_THRES_U2 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ +/*description: This register is used to filter pluse whose width is smaller + than this value for unit2.*/ +#define PCNT_FILTER_THRES_U2 0x000003FF +#define PCNT_FILTER_THRES_U2_M ((PCNT_FILTER_THRES_U2_V)<<(PCNT_FILTER_THRES_U2_S)) +#define PCNT_FILTER_THRES_U2_V 0x3FF +#define PCNT_FILTER_THRES_U2_S 0 + +#define PCNT_U2_CONF1_REG (DR_REG_PCNT_BASE + 0x001c) +/* PCNT_CNT_THRES1_U2 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to configure thres1 value for unit2.*/ +#define PCNT_CNT_THRES1_U2 0x0000FFFF +#define PCNT_CNT_THRES1_U2_M ((PCNT_CNT_THRES1_U2_V)<<(PCNT_CNT_THRES1_U2_S)) +#define PCNT_CNT_THRES1_U2_V 0xFFFF +#define PCNT_CNT_THRES1_U2_S 16 +/* PCNT_CNT_THRES0_U2 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thres0 value for unit2.*/ +#define PCNT_CNT_THRES0_U2 0x0000FFFF +#define PCNT_CNT_THRES0_U2_M ((PCNT_CNT_THRES0_U2_V)<<(PCNT_CNT_THRES0_U2_S)) +#define PCNT_CNT_THRES0_U2_V 0xFFFF +#define PCNT_CNT_THRES0_U2_S 0 + +#define PCNT_U2_CONF2_REG (DR_REG_PCNT_BASE + 0x0020) +/* PCNT_CNT_L_LIM_U2 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to confiugre thr_l_lim value for unit2.*/ +#define PCNT_CNT_L_LIM_U2 0x0000FFFF +#define PCNT_CNT_L_LIM_U2_M ((PCNT_CNT_L_LIM_U2_V)<<(PCNT_CNT_L_LIM_U2_S)) +#define PCNT_CNT_L_LIM_U2_V 0xFFFF +#define PCNT_CNT_L_LIM_U2_S 16 +/* PCNT_CNT_H_LIM_U2 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thr_h_lim value for unit2.*/ +#define PCNT_CNT_H_LIM_U2 0x0000FFFF +#define PCNT_CNT_H_LIM_U2_M ((PCNT_CNT_H_LIM_U2_V)<<(PCNT_CNT_H_LIM_U2_S)) +#define PCNT_CNT_H_LIM_U2_V 0xFFFF +#define PCNT_CNT_H_LIM_U2_S 0 + +#define PCNT_U3_CONF0_REG (DR_REG_PCNT_BASE + 0x0024) +/* PCNT_CH1_LCTRL_MODE_U3 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's low control + signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_LCTRL_MODE_U3 0x00000003 +#define PCNT_CH1_LCTRL_MODE_U3_M ((PCNT_CH1_LCTRL_MODE_U3_V)<<(PCNT_CH1_LCTRL_MODE_U3_S)) +#define PCNT_CH1_LCTRL_MODE_U3_V 0x3 +#define PCNT_CH1_LCTRL_MODE_U3_S 30 +/* PCNT_CH1_HCTRL_MODE_U3 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's high + control signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_HCTRL_MODE_U3 0x00000003 +#define PCNT_CH1_HCTRL_MODE_U3_M ((PCNT_CH1_HCTRL_MODE_U3_V)<<(PCNT_CH1_HCTRL_MODE_U3_S)) +#define PCNT_CH1_HCTRL_MODE_U3_V 0x3 +#define PCNT_CH1_HCTRL_MODE_U3_S 28 +/* PCNT_CH1_POS_MODE_U3 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + posedge signal for unit3. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH1_POS_MODE_U3 0x00000003 +#define PCNT_CH1_POS_MODE_U3_M ((PCNT_CH1_POS_MODE_U3_V)<<(PCNT_CH1_POS_MODE_U3_S)) +#define PCNT_CH1_POS_MODE_U3_V 0x3 +#define PCNT_CH1_POS_MODE_U3_S 26 +/* PCNT_CH1_NEG_MODE_U3 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + negedge signal for unit3. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH1_NEG_MODE_U3 0x00000003 +#define PCNT_CH1_NEG_MODE_U3_M ((PCNT_CH1_NEG_MODE_U3_V)<<(PCNT_CH1_NEG_MODE_U3_S)) +#define PCNT_CH1_NEG_MODE_U3_V 0x3 +#define PCNT_CH1_NEG_MODE_U3_S 24 +/* PCNT_CH0_LCTRL_MODE_U3 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's low control + signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_LCTRL_MODE_U3 0x00000003 +#define PCNT_CH0_LCTRL_MODE_U3_M ((PCNT_CH0_LCTRL_MODE_U3_V)<<(PCNT_CH0_LCTRL_MODE_U3_S)) +#define PCNT_CH0_LCTRL_MODE_U3_V 0x3 +#define PCNT_CH0_LCTRL_MODE_U3_S 22 +/* PCNT_CH0_HCTRL_MODE_U3 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's high + control signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_HCTRL_MODE_U3 0x00000003 +#define PCNT_CH0_HCTRL_MODE_U3_M ((PCNT_CH0_HCTRL_MODE_U3_V)<<(PCNT_CH0_HCTRL_MODE_U3_S)) +#define PCNT_CH0_HCTRL_MODE_U3_V 0x3 +#define PCNT_CH0_HCTRL_MODE_U3_S 20 +/* PCNT_CH0_POS_MODE_U3 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + posedge signal for unit3. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH0_POS_MODE_U3 0x00000003 +#define PCNT_CH0_POS_MODE_U3_M ((PCNT_CH0_POS_MODE_U3_V)<<(PCNT_CH0_POS_MODE_U3_S)) +#define PCNT_CH0_POS_MODE_U3_V 0x3 +#define PCNT_CH0_POS_MODE_U3_S 18 +/* PCNT_CH0_NEG_MODE_U3 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + negedge signal for unit3. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH0_NEG_MODE_U3 0x00000003 +#define PCNT_CH0_NEG_MODE_U3_M ((PCNT_CH0_NEG_MODE_U3_V)<<(PCNT_CH0_NEG_MODE_U3_S)) +#define PCNT_CH0_NEG_MODE_U3_V 0x3 +#define PCNT_CH0_NEG_MODE_U3_S 16 +/* PCNT_THR_THRES1_EN_U3 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit3's count with thres1 value .*/ +#define PCNT_THR_THRES1_EN_U3 (BIT(15)) +#define PCNT_THR_THRES1_EN_U3_M (BIT(15)) +#define PCNT_THR_THRES1_EN_U3_V 0x1 +#define PCNT_THR_THRES1_EN_U3_S 15 +/* PCNT_THR_THRES0_EN_U3 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit3's count with thres0 value.*/ +#define PCNT_THR_THRES0_EN_U3 (BIT(14)) +#define PCNT_THR_THRES0_EN_U3_M (BIT(14)) +#define PCNT_THR_THRES0_EN_U3_V 0x1 +#define PCNT_THR_THRES0_EN_U3_S 14 +/* PCNT_THR_L_LIM_EN_U3 : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit3's count with thr_l_lim value.*/ +#define PCNT_THR_L_LIM_EN_U3 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U3_M (BIT(13)) +#define PCNT_THR_L_LIM_EN_U3_V 0x1 +#define PCNT_THR_L_LIM_EN_U3_S 13 +/* PCNT_THR_H_LIM_EN_U3 : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit3's count with thr_h_lim value.*/ +#define PCNT_THR_H_LIM_EN_U3 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U3_M (BIT(12)) +#define PCNT_THR_H_LIM_EN_U3_V 0x1 +#define PCNT_THR_H_LIM_EN_U3_S 12 +/* PCNT_THR_ZERO_EN_U3 : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit3's count with 0 value.*/ +#define PCNT_THR_ZERO_EN_U3 (BIT(11)) +#define PCNT_THR_ZERO_EN_U3_M (BIT(11)) +#define PCNT_THR_ZERO_EN_U3_V 0x1 +#define PCNT_THR_ZERO_EN_U3_S 11 +/* PCNT_FILTER_EN_U3 : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: This is the enable bit for filtering input signals for unit3.*/ +#define PCNT_FILTER_EN_U3 (BIT(10)) +#define PCNT_FILTER_EN_U3_M (BIT(10)) +#define PCNT_FILTER_EN_U3_V 0x1 +#define PCNT_FILTER_EN_U3_S 10 +/* PCNT_FILTER_THRES_U3 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ +/*description: This register is used to filter pluse whose width is smaller + than this value for unit3.*/ +#define PCNT_FILTER_THRES_U3 0x000003FF +#define PCNT_FILTER_THRES_U3_M ((PCNT_FILTER_THRES_U3_V)<<(PCNT_FILTER_THRES_U3_S)) +#define PCNT_FILTER_THRES_U3_V 0x3FF +#define PCNT_FILTER_THRES_U3_S 0 + +#define PCNT_U3_CONF1_REG (DR_REG_PCNT_BASE + 0x0028) +/* PCNT_CNT_THRES1_U3 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to configure thres1 value for unit3.*/ +#define PCNT_CNT_THRES1_U3 0x0000FFFF +#define PCNT_CNT_THRES1_U3_M ((PCNT_CNT_THRES1_U3_V)<<(PCNT_CNT_THRES1_U3_S)) +#define PCNT_CNT_THRES1_U3_V 0xFFFF +#define PCNT_CNT_THRES1_U3_S 16 +/* PCNT_CNT_THRES0_U3 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thres0 value for unit3.*/ +#define PCNT_CNT_THRES0_U3 0x0000FFFF +#define PCNT_CNT_THRES0_U3_M ((PCNT_CNT_THRES0_U3_V)<<(PCNT_CNT_THRES0_U3_S)) +#define PCNT_CNT_THRES0_U3_V 0xFFFF +#define PCNT_CNT_THRES0_U3_S 0 + +#define PCNT_U3_CONF2_REG (DR_REG_PCNT_BASE + 0x002c) +/* PCNT_CNT_L_LIM_U3 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to confiugre thr_l_lim value for unit3.*/ +#define PCNT_CNT_L_LIM_U3 0x0000FFFF +#define PCNT_CNT_L_LIM_U3_M ((PCNT_CNT_L_LIM_U3_V)<<(PCNT_CNT_L_LIM_U3_S)) +#define PCNT_CNT_L_LIM_U3_V 0xFFFF +#define PCNT_CNT_L_LIM_U3_S 16 +/* PCNT_CNT_H_LIM_U3 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thr_h_lim value for unit3.*/ +#define PCNT_CNT_H_LIM_U3 0x0000FFFF +#define PCNT_CNT_H_LIM_U3_M ((PCNT_CNT_H_LIM_U3_V)<<(PCNT_CNT_H_LIM_U3_S)) +#define PCNT_CNT_H_LIM_U3_V 0xFFFF +#define PCNT_CNT_H_LIM_U3_S 0 + +#define PCNT_U4_CONF0_REG (DR_REG_PCNT_BASE + 0x0030) +/* PCNT_CH1_LCTRL_MODE_U4 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's low control + signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_LCTRL_MODE_U4 0x00000003 +#define PCNT_CH1_LCTRL_MODE_U4_M ((PCNT_CH1_LCTRL_MODE_U4_V)<<(PCNT_CH1_LCTRL_MODE_U4_S)) +#define PCNT_CH1_LCTRL_MODE_U4_V 0x3 +#define PCNT_CH1_LCTRL_MODE_U4_S 30 +/* PCNT_CH1_HCTRL_MODE_U4 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's high + control signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_HCTRL_MODE_U4 0x00000003 +#define PCNT_CH1_HCTRL_MODE_U4_M ((PCNT_CH1_HCTRL_MODE_U4_V)<<(PCNT_CH1_HCTRL_MODE_U4_S)) +#define PCNT_CH1_HCTRL_MODE_U4_V 0x3 +#define PCNT_CH1_HCTRL_MODE_U4_S 28 +/* PCNT_CH1_POS_MODE_U4 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + posedge signal for unit4. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH1_POS_MODE_U4 0x00000003 +#define PCNT_CH1_POS_MODE_U4_M ((PCNT_CH1_POS_MODE_U4_V)<<(PCNT_CH1_POS_MODE_U4_S)) +#define PCNT_CH1_POS_MODE_U4_V 0x3 +#define PCNT_CH1_POS_MODE_U4_S 26 +/* PCNT_CH1_NEG_MODE_U4 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + negedge signal for unit4. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH1_NEG_MODE_U4 0x00000003 +#define PCNT_CH1_NEG_MODE_U4_M ((PCNT_CH1_NEG_MODE_U4_V)<<(PCNT_CH1_NEG_MODE_U4_S)) +#define PCNT_CH1_NEG_MODE_U4_V 0x3 +#define PCNT_CH1_NEG_MODE_U4_S 24 +/* PCNT_CH0_LCTRL_MODE_U4 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's low control + signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_LCTRL_MODE_U4 0x00000003 +#define PCNT_CH0_LCTRL_MODE_U4_M ((PCNT_CH0_LCTRL_MODE_U4_V)<<(PCNT_CH0_LCTRL_MODE_U4_S)) +#define PCNT_CH0_LCTRL_MODE_U4_V 0x3 +#define PCNT_CH0_LCTRL_MODE_U4_S 22 +/* PCNT_CH0_HCTRL_MODE_U4 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's high + control signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_HCTRL_MODE_U4 0x00000003 +#define PCNT_CH0_HCTRL_MODE_U4_M ((PCNT_CH0_HCTRL_MODE_U4_V)<<(PCNT_CH0_HCTRL_MODE_U4_S)) +#define PCNT_CH0_HCTRL_MODE_U4_V 0x3 +#define PCNT_CH0_HCTRL_MODE_U4_S 20 +/* PCNT_CH0_POS_MODE_U4 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + posedge signal for unit4. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH0_POS_MODE_U4 0x00000003 +#define PCNT_CH0_POS_MODE_U4_M ((PCNT_CH0_POS_MODE_U4_V)<<(PCNT_CH0_POS_MODE_U4_S)) +#define PCNT_CH0_POS_MODE_U4_V 0x3 +#define PCNT_CH0_POS_MODE_U4_S 18 +/* PCNT_CH0_NEG_MODE_U4 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + negedge signal for unit4. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH0_NEG_MODE_U4 0x00000003 +#define PCNT_CH0_NEG_MODE_U4_M ((PCNT_CH0_NEG_MODE_U4_V)<<(PCNT_CH0_NEG_MODE_U4_S)) +#define PCNT_CH0_NEG_MODE_U4_V 0x3 +#define PCNT_CH0_NEG_MODE_U4_S 16 +/* PCNT_THR_THRES1_EN_U4 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit4's count with thres1 value .*/ +#define PCNT_THR_THRES1_EN_U4 (BIT(15)) +#define PCNT_THR_THRES1_EN_U4_M (BIT(15)) +#define PCNT_THR_THRES1_EN_U4_V 0x1 +#define PCNT_THR_THRES1_EN_U4_S 15 +/* PCNT_THR_THRES0_EN_U4 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit4's count with thres0 value.*/ +#define PCNT_THR_THRES0_EN_U4 (BIT(14)) +#define PCNT_THR_THRES0_EN_U4_M (BIT(14)) +#define PCNT_THR_THRES0_EN_U4_V 0x1 +#define PCNT_THR_THRES0_EN_U4_S 14 +/* PCNT_THR_L_LIM_EN_U4 : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit4's count with thr_l_lim value.*/ +#define PCNT_THR_L_LIM_EN_U4 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U4_M (BIT(13)) +#define PCNT_THR_L_LIM_EN_U4_V 0x1 +#define PCNT_THR_L_LIM_EN_U4_S 13 +/* PCNT_THR_H_LIM_EN_U4 : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit4's count with thr_h_lim value.*/ +#define PCNT_THR_H_LIM_EN_U4 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U4_M (BIT(12)) +#define PCNT_THR_H_LIM_EN_U4_V 0x1 +#define PCNT_THR_H_LIM_EN_U4_S 12 +/* PCNT_THR_ZERO_EN_U4 : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit4's count with 0 value.*/ +#define PCNT_THR_ZERO_EN_U4 (BIT(11)) +#define PCNT_THR_ZERO_EN_U4_M (BIT(11)) +#define PCNT_THR_ZERO_EN_U4_V 0x1 +#define PCNT_THR_ZERO_EN_U4_S 11 +/* PCNT_FILTER_EN_U4 : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: This is the enable bit for filtering input signals for unit4.*/ +#define PCNT_FILTER_EN_U4 (BIT(10)) +#define PCNT_FILTER_EN_U4_M (BIT(10)) +#define PCNT_FILTER_EN_U4_V 0x1 +#define PCNT_FILTER_EN_U4_S 10 +/* PCNT_FILTER_THRES_U4 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ +/*description: This register is used to filter pluse whose width is smaller + than this value for unit4.*/ +#define PCNT_FILTER_THRES_U4 0x000003FF +#define PCNT_FILTER_THRES_U4_M ((PCNT_FILTER_THRES_U4_V)<<(PCNT_FILTER_THRES_U4_S)) +#define PCNT_FILTER_THRES_U4_V 0x3FF +#define PCNT_FILTER_THRES_U4_S 0 + +#define PCNT_U4_CONF1_REG (DR_REG_PCNT_BASE + 0x0034) +/* PCNT_CNT_THRES1_U4 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to configure thres1 value for unit4.*/ +#define PCNT_CNT_THRES1_U4 0x0000FFFF +#define PCNT_CNT_THRES1_U4_M ((PCNT_CNT_THRES1_U4_V)<<(PCNT_CNT_THRES1_U4_S)) +#define PCNT_CNT_THRES1_U4_V 0xFFFF +#define PCNT_CNT_THRES1_U4_S 16 +/* PCNT_CNT_THRES0_U4 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thres0 value for unit4.*/ +#define PCNT_CNT_THRES0_U4 0x0000FFFF +#define PCNT_CNT_THRES0_U4_M ((PCNT_CNT_THRES0_U4_V)<<(PCNT_CNT_THRES0_U4_S)) +#define PCNT_CNT_THRES0_U4_V 0xFFFF +#define PCNT_CNT_THRES0_U4_S 0 + +#define PCNT_U4_CONF2_REG (DR_REG_PCNT_BASE + 0x0038) +/* PCNT_CNT_L_LIM_U4 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to confiugre thr_l_lim value for unit4.*/ +#define PCNT_CNT_L_LIM_U4 0x0000FFFF +#define PCNT_CNT_L_LIM_U4_M ((PCNT_CNT_L_LIM_U4_V)<<(PCNT_CNT_L_LIM_U4_S)) +#define PCNT_CNT_L_LIM_U4_V 0xFFFF +#define PCNT_CNT_L_LIM_U4_S 16 +/* PCNT_CNT_H_LIM_U4 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thr_h_lim value for unit4.*/ +#define PCNT_CNT_H_LIM_U4 0x0000FFFF +#define PCNT_CNT_H_LIM_U4_M ((PCNT_CNT_H_LIM_U4_V)<<(PCNT_CNT_H_LIM_U4_S)) +#define PCNT_CNT_H_LIM_U4_V 0xFFFF +#define PCNT_CNT_H_LIM_U4_S 0 + +#define PCNT_U5_CONF0_REG (DR_REG_PCNT_BASE + 0x003c) +/* PCNT_CH1_LCTRL_MODE_U5 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's low control + signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_LCTRL_MODE_U5 0x00000003 +#define PCNT_CH1_LCTRL_MODE_U5_M ((PCNT_CH1_LCTRL_MODE_U5_V)<<(PCNT_CH1_LCTRL_MODE_U5_S)) +#define PCNT_CH1_LCTRL_MODE_U5_V 0x3 +#define PCNT_CH1_LCTRL_MODE_U5_S 30 +/* PCNT_CH1_HCTRL_MODE_U5 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's high + control signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_HCTRL_MODE_U5 0x00000003 +#define PCNT_CH1_HCTRL_MODE_U5_M ((PCNT_CH1_HCTRL_MODE_U5_V)<<(PCNT_CH1_HCTRL_MODE_U5_S)) +#define PCNT_CH1_HCTRL_MODE_U5_V 0x3 +#define PCNT_CH1_HCTRL_MODE_U5_S 28 +/* PCNT_CH1_POS_MODE_U5 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + posedge signal for unit5. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH1_POS_MODE_U5 0x00000003 +#define PCNT_CH1_POS_MODE_U5_M ((PCNT_CH1_POS_MODE_U5_V)<<(PCNT_CH1_POS_MODE_U5_S)) +#define PCNT_CH1_POS_MODE_U5_V 0x3 +#define PCNT_CH1_POS_MODE_U5_S 26 +/* PCNT_CH1_NEG_MODE_U5 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + negedge signal for unit5. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH1_NEG_MODE_U5 0x00000003 +#define PCNT_CH1_NEG_MODE_U5_M ((PCNT_CH1_NEG_MODE_U5_V)<<(PCNT_CH1_NEG_MODE_U5_S)) +#define PCNT_CH1_NEG_MODE_U5_V 0x3 +#define PCNT_CH1_NEG_MODE_U5_S 24 +/* PCNT_CH0_LCTRL_MODE_U5 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's low control + signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_LCTRL_MODE_U5 0x00000003 +#define PCNT_CH0_LCTRL_MODE_U5_M ((PCNT_CH0_LCTRL_MODE_U5_V)<<(PCNT_CH0_LCTRL_MODE_U5_S)) +#define PCNT_CH0_LCTRL_MODE_U5_V 0x3 +#define PCNT_CH0_LCTRL_MODE_U5_S 22 +/* PCNT_CH0_HCTRL_MODE_U5 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's high + control signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_HCTRL_MODE_U5 0x00000003 +#define PCNT_CH0_HCTRL_MODE_U5_M ((PCNT_CH0_HCTRL_MODE_U5_V)<<(PCNT_CH0_HCTRL_MODE_U5_S)) +#define PCNT_CH0_HCTRL_MODE_U5_V 0x3 +#define PCNT_CH0_HCTRL_MODE_U5_S 20 +/* PCNT_CH0_POS_MODE_U5 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + posedge signal for unit5. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH0_POS_MODE_U5 0x00000003 +#define PCNT_CH0_POS_MODE_U5_M ((PCNT_CH0_POS_MODE_U5_V)<<(PCNT_CH0_POS_MODE_U5_S)) +#define PCNT_CH0_POS_MODE_U5_V 0x3 +#define PCNT_CH0_POS_MODE_U5_S 18 +/* PCNT_CH0_NEG_MODE_U5 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + negedge signal for unit5. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH0_NEG_MODE_U5 0x00000003 +#define PCNT_CH0_NEG_MODE_U5_M ((PCNT_CH0_NEG_MODE_U5_V)<<(PCNT_CH0_NEG_MODE_U5_S)) +#define PCNT_CH0_NEG_MODE_U5_V 0x3 +#define PCNT_CH0_NEG_MODE_U5_S 16 +/* PCNT_THR_THRES1_EN_U5 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit5's count with thres1 value .*/ +#define PCNT_THR_THRES1_EN_U5 (BIT(15)) +#define PCNT_THR_THRES1_EN_U5_M (BIT(15)) +#define PCNT_THR_THRES1_EN_U5_V 0x1 +#define PCNT_THR_THRES1_EN_U5_S 15 +/* PCNT_THR_THRES0_EN_U5 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit5's count with thres0 value.*/ +#define PCNT_THR_THRES0_EN_U5 (BIT(14)) +#define PCNT_THR_THRES0_EN_U5_M (BIT(14)) +#define PCNT_THR_THRES0_EN_U5_V 0x1 +#define PCNT_THR_THRES0_EN_U5_S 14 +/* PCNT_THR_L_LIM_EN_U5 : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit5's count with thr_l_lim value.*/ +#define PCNT_THR_L_LIM_EN_U5 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U5_M (BIT(13)) +#define PCNT_THR_L_LIM_EN_U5_V 0x1 +#define PCNT_THR_L_LIM_EN_U5_S 13 +/* PCNT_THR_H_LIM_EN_U5 : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit5's count with thr_h_lim value.*/ +#define PCNT_THR_H_LIM_EN_U5 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U5_M (BIT(12)) +#define PCNT_THR_H_LIM_EN_U5_V 0x1 +#define PCNT_THR_H_LIM_EN_U5_S 12 +/* PCNT_THR_ZERO_EN_U5 : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit5's count with 0 value.*/ +#define PCNT_THR_ZERO_EN_U5 (BIT(11)) +#define PCNT_THR_ZERO_EN_U5_M (BIT(11)) +#define PCNT_THR_ZERO_EN_U5_V 0x1 +#define PCNT_THR_ZERO_EN_U5_S 11 +/* PCNT_FILTER_EN_U5 : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: This is the enable bit for filtering input signals for unit5.*/ +#define PCNT_FILTER_EN_U5 (BIT(10)) +#define PCNT_FILTER_EN_U5_M (BIT(10)) +#define PCNT_FILTER_EN_U5_V 0x1 +#define PCNT_FILTER_EN_U5_S 10 +/* PCNT_FILTER_THRES_U5 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ +/*description: This register is used to filter pluse whose width is smaller + than this value for unit5.*/ +#define PCNT_FILTER_THRES_U5 0x000003FF +#define PCNT_FILTER_THRES_U5_M ((PCNT_FILTER_THRES_U5_V)<<(PCNT_FILTER_THRES_U5_S)) +#define PCNT_FILTER_THRES_U5_V 0x3FF +#define PCNT_FILTER_THRES_U5_S 0 + +#define PCNT_U5_CONF1_REG (DR_REG_PCNT_BASE + 0x0040) +/* PCNT_CNT_THRES1_U5 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to configure thres1 value for unit5.*/ +#define PCNT_CNT_THRES1_U5 0x0000FFFF +#define PCNT_CNT_THRES1_U5_M ((PCNT_CNT_THRES1_U5_V)<<(PCNT_CNT_THRES1_U5_S)) +#define PCNT_CNT_THRES1_U5_V 0xFFFF +#define PCNT_CNT_THRES1_U5_S 16 +/* PCNT_CNT_THRES0_U5 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thres0 value for unit5.*/ +#define PCNT_CNT_THRES0_U5 0x0000FFFF +#define PCNT_CNT_THRES0_U5_M ((PCNT_CNT_THRES0_U5_V)<<(PCNT_CNT_THRES0_U5_S)) +#define PCNT_CNT_THRES0_U5_V 0xFFFF +#define PCNT_CNT_THRES0_U5_S 0 + +#define PCNT_U5_CONF2_REG (DR_REG_PCNT_BASE + 0x0044) +/* PCNT_CNT_L_LIM_U5 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to confiugre thr_l_lim value for unit5.*/ +#define PCNT_CNT_L_LIM_U5 0x0000FFFF +#define PCNT_CNT_L_LIM_U5_M ((PCNT_CNT_L_LIM_U5_V)<<(PCNT_CNT_L_LIM_U5_S)) +#define PCNT_CNT_L_LIM_U5_V 0xFFFF +#define PCNT_CNT_L_LIM_U5_S 16 +/* PCNT_CNT_H_LIM_U5 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thr_h_lim value for unit5.*/ +#define PCNT_CNT_H_LIM_U5 0x0000FFFF +#define PCNT_CNT_H_LIM_U5_M ((PCNT_CNT_H_LIM_U5_V)<<(PCNT_CNT_H_LIM_U5_S)) +#define PCNT_CNT_H_LIM_U5_V 0xFFFF +#define PCNT_CNT_H_LIM_U5_S 0 + +#define PCNT_U6_CONF0_REG (DR_REG_PCNT_BASE + 0x0048) +/* PCNT_CH1_LCTRL_MODE_U6 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's low control + signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_LCTRL_MODE_U6 0x00000003 +#define PCNT_CH1_LCTRL_MODE_U6_M ((PCNT_CH1_LCTRL_MODE_U6_V)<<(PCNT_CH1_LCTRL_MODE_U6_S)) +#define PCNT_CH1_LCTRL_MODE_U6_V 0x3 +#define PCNT_CH1_LCTRL_MODE_U6_S 30 +/* PCNT_CH1_HCTRL_MODE_U6 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's high + control signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_HCTRL_MODE_U6 0x00000003 +#define PCNT_CH1_HCTRL_MODE_U6_M ((PCNT_CH1_HCTRL_MODE_U6_V)<<(PCNT_CH1_HCTRL_MODE_U6_S)) +#define PCNT_CH1_HCTRL_MODE_U6_V 0x3 +#define PCNT_CH1_HCTRL_MODE_U6_S 28 +/* PCNT_CH1_POS_MODE_U6 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + posedge signal for unit6. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH1_POS_MODE_U6 0x00000003 +#define PCNT_CH1_POS_MODE_U6_M ((PCNT_CH1_POS_MODE_U6_V)<<(PCNT_CH1_POS_MODE_U6_S)) +#define PCNT_CH1_POS_MODE_U6_V 0x3 +#define PCNT_CH1_POS_MODE_U6_S 26 +/* PCNT_CH1_NEG_MODE_U6 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + negedge signal for unit6. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH1_NEG_MODE_U6 0x00000003 +#define PCNT_CH1_NEG_MODE_U6_M ((PCNT_CH1_NEG_MODE_U6_V)<<(PCNT_CH1_NEG_MODE_U6_S)) +#define PCNT_CH1_NEG_MODE_U6_V 0x3 +#define PCNT_CH1_NEG_MODE_U6_S 24 +/* PCNT_CH0_LCTRL_MODE_U6 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's low control + signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_LCTRL_MODE_U6 0x00000003 +#define PCNT_CH0_LCTRL_MODE_U6_M ((PCNT_CH0_LCTRL_MODE_U6_V)<<(PCNT_CH0_LCTRL_MODE_U6_S)) +#define PCNT_CH0_LCTRL_MODE_U6_V 0x3 +#define PCNT_CH0_LCTRL_MODE_U6_S 22 +/* PCNT_CH0_HCTRL_MODE_U6 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's high + control signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_HCTRL_MODE_U6 0x00000003 +#define PCNT_CH0_HCTRL_MODE_U6_M ((PCNT_CH0_HCTRL_MODE_U6_V)<<(PCNT_CH0_HCTRL_MODE_U6_S)) +#define PCNT_CH0_HCTRL_MODE_U6_V 0x3 +#define PCNT_CH0_HCTRL_MODE_U6_S 20 +/* PCNT_CH0_POS_MODE_U6 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + posedge signal for unit6. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH0_POS_MODE_U6 0x00000003 +#define PCNT_CH0_POS_MODE_U6_M ((PCNT_CH0_POS_MODE_U6_V)<<(PCNT_CH0_POS_MODE_U6_S)) +#define PCNT_CH0_POS_MODE_U6_V 0x3 +#define PCNT_CH0_POS_MODE_U6_S 18 +/* PCNT_CH0_NEG_MODE_U6 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + negedge signal for unit6. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH0_NEG_MODE_U6 0x00000003 +#define PCNT_CH0_NEG_MODE_U6_M ((PCNT_CH0_NEG_MODE_U6_V)<<(PCNT_CH0_NEG_MODE_U6_S)) +#define PCNT_CH0_NEG_MODE_U6_V 0x3 +#define PCNT_CH0_NEG_MODE_U6_S 16 +/* PCNT_THR_THRES1_EN_U6 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit6's count with thres1 value .*/ +#define PCNT_THR_THRES1_EN_U6 (BIT(15)) +#define PCNT_THR_THRES1_EN_U6_M (BIT(15)) +#define PCNT_THR_THRES1_EN_U6_V 0x1 +#define PCNT_THR_THRES1_EN_U6_S 15 +/* PCNT_THR_THRES0_EN_U6 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit6's count with thres0 value.*/ +#define PCNT_THR_THRES0_EN_U6 (BIT(14)) +#define PCNT_THR_THRES0_EN_U6_M (BIT(14)) +#define PCNT_THR_THRES0_EN_U6_V 0x1 +#define PCNT_THR_THRES0_EN_U6_S 14 +/* PCNT_THR_L_LIM_EN_U6 : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit6's count with thr_l_lim value.*/ +#define PCNT_THR_L_LIM_EN_U6 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U6_M (BIT(13)) +#define PCNT_THR_L_LIM_EN_U6_V 0x1 +#define PCNT_THR_L_LIM_EN_U6_S 13 +/* PCNT_THR_H_LIM_EN_U6 : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit6's count with thr_h_lim value.*/ +#define PCNT_THR_H_LIM_EN_U6 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U6_M (BIT(12)) +#define PCNT_THR_H_LIM_EN_U6_V 0x1 +#define PCNT_THR_H_LIM_EN_U6_S 12 +/* PCNT_THR_ZERO_EN_U6 : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit6's count with 0 value.*/ +#define PCNT_THR_ZERO_EN_U6 (BIT(11)) +#define PCNT_THR_ZERO_EN_U6_M (BIT(11)) +#define PCNT_THR_ZERO_EN_U6_V 0x1 +#define PCNT_THR_ZERO_EN_U6_S 11 +/* PCNT_FILTER_EN_U6 : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: This is the enable bit for filtering input signals for unit6.*/ +#define PCNT_FILTER_EN_U6 (BIT(10)) +#define PCNT_FILTER_EN_U6_M (BIT(10)) +#define PCNT_FILTER_EN_U6_V 0x1 +#define PCNT_FILTER_EN_U6_S 10 +/* PCNT_FILTER_THRES_U6 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ +/*description: This register is used to filter pluse whose width is smaller + than this value for unit6.*/ +#define PCNT_FILTER_THRES_U6 0x000003FF +#define PCNT_FILTER_THRES_U6_M ((PCNT_FILTER_THRES_U6_V)<<(PCNT_FILTER_THRES_U6_S)) +#define PCNT_FILTER_THRES_U6_V 0x3FF +#define PCNT_FILTER_THRES_U6_S 0 + +#define PCNT_U6_CONF1_REG (DR_REG_PCNT_BASE + 0x004c) +/* PCNT_CNT_THRES1_U6 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to configure thres1 value for unit6.*/ +#define PCNT_CNT_THRES1_U6 0x0000FFFF +#define PCNT_CNT_THRES1_U6_M ((PCNT_CNT_THRES1_U6_V)<<(PCNT_CNT_THRES1_U6_S)) +#define PCNT_CNT_THRES1_U6_V 0xFFFF +#define PCNT_CNT_THRES1_U6_S 16 +/* PCNT_CNT_THRES0_U6 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thres0 value for unit6.*/ +#define PCNT_CNT_THRES0_U6 0x0000FFFF +#define PCNT_CNT_THRES0_U6_M ((PCNT_CNT_THRES0_U6_V)<<(PCNT_CNT_THRES0_U6_S)) +#define PCNT_CNT_THRES0_U6_V 0xFFFF +#define PCNT_CNT_THRES0_U6_S 0 + +#define PCNT_U6_CONF2_REG (DR_REG_PCNT_BASE + 0x0050) +/* PCNT_CNT_L_LIM_U6 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to confiugre thr_l_lim value for unit6.*/ +#define PCNT_CNT_L_LIM_U6 0x0000FFFF +#define PCNT_CNT_L_LIM_U6_M ((PCNT_CNT_L_LIM_U6_V)<<(PCNT_CNT_L_LIM_U6_S)) +#define PCNT_CNT_L_LIM_U6_V 0xFFFF +#define PCNT_CNT_L_LIM_U6_S 16 +/* PCNT_CNT_H_LIM_U6 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thr_h_lim value for unit6.*/ +#define PCNT_CNT_H_LIM_U6 0x0000FFFF +#define PCNT_CNT_H_LIM_U6_M ((PCNT_CNT_H_LIM_U6_V)<<(PCNT_CNT_H_LIM_U6_S)) +#define PCNT_CNT_H_LIM_U6_V 0xFFFF +#define PCNT_CNT_H_LIM_U6_S 0 + +#define PCNT_U7_CONF0_REG (DR_REG_PCNT_BASE + 0x0054) +/* PCNT_CH1_LCTRL_MODE_U7 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's low control + signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_LCTRL_MODE_U7 0x00000003 +#define PCNT_CH1_LCTRL_MODE_U7_M ((PCNT_CH1_LCTRL_MODE_U7_V)<<(PCNT_CH1_LCTRL_MODE_U7_S)) +#define PCNT_CH1_LCTRL_MODE_U7_V 0x3 +#define PCNT_CH1_LCTRL_MODE_U7_S 30 +/* PCNT_CH1_HCTRL_MODE_U7 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's high + control signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH1_HCTRL_MODE_U7 0x00000003 +#define PCNT_CH1_HCTRL_MODE_U7_M ((PCNT_CH1_HCTRL_MODE_U7_V)<<(PCNT_CH1_HCTRL_MODE_U7_S)) +#define PCNT_CH1_HCTRL_MODE_U7_V 0x3 +#define PCNT_CH1_HCTRL_MODE_U7_S 28 +/* PCNT_CH1_POS_MODE_U7 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + posedge signal for unit7. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH1_POS_MODE_U7 0x00000003 +#define PCNT_CH1_POS_MODE_U7_M ((PCNT_CH1_POS_MODE_U7_V)<<(PCNT_CH1_POS_MODE_U7_S)) +#define PCNT_CH1_POS_MODE_U7_V 0x3 +#define PCNT_CH1_POS_MODE_U7_S 26 +/* PCNT_CH1_NEG_MODE_U7 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel1's input + negedge signal for unit7. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH1_NEG_MODE_U7 0x00000003 +#define PCNT_CH1_NEG_MODE_U7_M ((PCNT_CH1_NEG_MODE_U7_V)<<(PCNT_CH1_NEG_MODE_U7_S)) +#define PCNT_CH1_NEG_MODE_U7_V 0x3 +#define PCNT_CH1_NEG_MODE_U7_S 24 +/* PCNT_CH0_LCTRL_MODE_U7 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's low control + signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_LCTRL_MODE_U7 0x00000003 +#define PCNT_CH0_LCTRL_MODE_U7_M ((PCNT_CH0_LCTRL_MODE_U7_V)<<(PCNT_CH0_LCTRL_MODE_U7_S)) +#define PCNT_CH0_LCTRL_MODE_U7_V 0x3 +#define PCNT_CH0_LCTRL_MODE_U7_S 22 +/* PCNT_CH0_HCTRL_MODE_U7 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's high + control signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +#define PCNT_CH0_HCTRL_MODE_U7 0x00000003 +#define PCNT_CH0_HCTRL_MODE_U7_M ((PCNT_CH0_HCTRL_MODE_U7_V)<<(PCNT_CH0_HCTRL_MODE_U7_S)) +#define PCNT_CH0_HCTRL_MODE_U7_V 0x3 +#define PCNT_CH0_HCTRL_MODE_U7_S 20 +/* PCNT_CH0_POS_MODE_U7 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + posedge signal for unit7. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +#define PCNT_CH0_POS_MODE_U7 0x00000003 +#define PCNT_CH0_POS_MODE_U7_M ((PCNT_CH0_POS_MODE_U7_V)<<(PCNT_CH0_POS_MODE_U7_S)) +#define PCNT_CH0_POS_MODE_U7_V 0x3 +#define PCNT_CH0_POS_MODE_U7_S 18 +/* PCNT_CH0_NEG_MODE_U7 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: This register is used to control the mode of channel0's input + negedge signal for unit7. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +#define PCNT_CH0_NEG_MODE_U7 0x00000003 +#define PCNT_CH0_NEG_MODE_U7_M ((PCNT_CH0_NEG_MODE_U7_V)<<(PCNT_CH0_NEG_MODE_U7_S)) +#define PCNT_CH0_NEG_MODE_U7_V 0x3 +#define PCNT_CH0_NEG_MODE_U7_S 16 +/* PCNT_THR_THRES1_EN_U7 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit7's count with thres1 value .*/ +#define PCNT_THR_THRES1_EN_U7 (BIT(15)) +#define PCNT_THR_THRES1_EN_U7_M (BIT(15)) +#define PCNT_THR_THRES1_EN_U7_V 0x1 +#define PCNT_THR_THRES1_EN_U7_S 15 +/* PCNT_THR_THRES0_EN_U7 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the enable bit for comparing unit7's count with thres0 value.*/ +#define PCNT_THR_THRES0_EN_U7 (BIT(14)) +#define PCNT_THR_THRES0_EN_U7_M (BIT(14)) +#define PCNT_THR_THRES0_EN_U7_V 0x1 +#define PCNT_THR_THRES0_EN_U7_S 14 +/* PCNT_THR_L_LIM_EN_U7 : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit7's count with thr_l_lim value.*/ +#define PCNT_THR_L_LIM_EN_U7 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U7_M (BIT(13)) +#define PCNT_THR_L_LIM_EN_U7_V 0x1 +#define PCNT_THR_L_LIM_EN_U7_S 13 +/* PCNT_THR_H_LIM_EN_U7 : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit7's count with thr_h_lim value.*/ +#define PCNT_THR_H_LIM_EN_U7 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U7_M (BIT(12)) +#define PCNT_THR_H_LIM_EN_U7_V 0x1 +#define PCNT_THR_H_LIM_EN_U7_S 12 +/* PCNT_THR_ZERO_EN_U7 : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: This is the enable bit for comparing unit7's count with 0 value.*/ +#define PCNT_THR_ZERO_EN_U7 (BIT(11)) +#define PCNT_THR_ZERO_EN_U7_M (BIT(11)) +#define PCNT_THR_ZERO_EN_U7_V 0x1 +#define PCNT_THR_ZERO_EN_U7_S 11 +/* PCNT_FILTER_EN_U7 : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: This is the enable bit for filtering input signals for unit7.*/ +#define PCNT_FILTER_EN_U7 (BIT(10)) +#define PCNT_FILTER_EN_U7_M (BIT(10)) +#define PCNT_FILTER_EN_U7_V 0x1 +#define PCNT_FILTER_EN_U7_S 10 +/* PCNT_FILTER_THRES_U7 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ +/*description: This register is used to filter pluse whose width is smaller + than this value for unit7.*/ +#define PCNT_FILTER_THRES_U7 0x000003FF +#define PCNT_FILTER_THRES_U7_M ((PCNT_FILTER_THRES_U7_V)<<(PCNT_FILTER_THRES_U7_S)) +#define PCNT_FILTER_THRES_U7_V 0x3FF +#define PCNT_FILTER_THRES_U7_S 0 + +#define PCNT_U7_CONF1_REG (DR_REG_PCNT_BASE + 0x0058) +/* PCNT_CNT_THRES1_U7 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to configure thres1 value for unit7.*/ +#define PCNT_CNT_THRES1_U7 0x0000FFFF +#define PCNT_CNT_THRES1_U7_M ((PCNT_CNT_THRES1_U7_V)<<(PCNT_CNT_THRES1_U7_S)) +#define PCNT_CNT_THRES1_U7_V 0xFFFF +#define PCNT_CNT_THRES1_U7_S 16 +/* PCNT_CNT_THRES0_U7 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thres0 value for unit7.*/ +#define PCNT_CNT_THRES0_U7 0x0000FFFF +#define PCNT_CNT_THRES0_U7_M ((PCNT_CNT_THRES0_U7_V)<<(PCNT_CNT_THRES0_U7_S)) +#define PCNT_CNT_THRES0_U7_V 0xFFFF +#define PCNT_CNT_THRES0_U7_S 0 + +#define PCNT_U7_CONF2_REG (DR_REG_PCNT_BASE + 0x005c) +/* PCNT_CNT_L_LIM_U7 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: This register is used to confiugre thr_l_lim value for unit7.*/ +#define PCNT_CNT_L_LIM_U7 0x0000FFFF +#define PCNT_CNT_L_LIM_U7_M ((PCNT_CNT_L_LIM_U7_V)<<(PCNT_CNT_L_LIM_U7_S)) +#define PCNT_CNT_L_LIM_U7_V 0xFFFF +#define PCNT_CNT_L_LIM_U7_S 16 +/* PCNT_CNT_H_LIM_U7 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: This register is used to configure thr_h_lim value for unit7.*/ +#define PCNT_CNT_H_LIM_U7 0x0000FFFF +#define PCNT_CNT_H_LIM_U7_M ((PCNT_CNT_H_LIM_U7_V)<<(PCNT_CNT_H_LIM_U7_S)) +#define PCNT_CNT_H_LIM_U7_V 0xFFFF +#define PCNT_CNT_H_LIM_U7_S 0 + +#define PCNT_U0_CNT_REG (DR_REG_PCNT_BASE + 0x0060) +/* PCNT_PLUS_CNT_U0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: This register stores the current pulse count value for unit0.*/ +#define PCNT_PLUS_CNT_U0 0x0000FFFF +#define PCNT_PLUS_CNT_U0_M ((PCNT_PLUS_CNT_U0_V)<<(PCNT_PLUS_CNT_U0_S)) +#define PCNT_PLUS_CNT_U0_V 0xFFFF +#define PCNT_PLUS_CNT_U0_S 0 + +#define PCNT_U1_CNT_REG (DR_REG_PCNT_BASE + 0x0064) +/* PCNT_PLUS_CNT_U1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: This register stores the current pulse count value for unit1.*/ +#define PCNT_PLUS_CNT_U1 0x0000FFFF +#define PCNT_PLUS_CNT_U1_M ((PCNT_PLUS_CNT_U1_V)<<(PCNT_PLUS_CNT_U1_S)) +#define PCNT_PLUS_CNT_U1_V 0xFFFF +#define PCNT_PLUS_CNT_U1_S 0 + +#define PCNT_U2_CNT_REG (DR_REG_PCNT_BASE + 0x0068) +/* PCNT_PLUS_CNT_U2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: This register stores the current pulse count value for unit2.*/ +#define PCNT_PLUS_CNT_U2 0x0000FFFF +#define PCNT_PLUS_CNT_U2_M ((PCNT_PLUS_CNT_U2_V)<<(PCNT_PLUS_CNT_U2_S)) +#define PCNT_PLUS_CNT_U2_V 0xFFFF +#define PCNT_PLUS_CNT_U2_S 0 + +#define PCNT_U3_CNT_REG (DR_REG_PCNT_BASE + 0x006c) +/* PCNT_PLUS_CNT_U3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: This register stores the current pulse count value for unit3.*/ +#define PCNT_PLUS_CNT_U3 0x0000FFFF +#define PCNT_PLUS_CNT_U3_M ((PCNT_PLUS_CNT_U3_V)<<(PCNT_PLUS_CNT_U3_S)) +#define PCNT_PLUS_CNT_U3_V 0xFFFF +#define PCNT_PLUS_CNT_U3_S 0 + +#define PCNT_U4_CNT_REG (DR_REG_PCNT_BASE + 0x0070) +/* PCNT_PLUS_CNT_U4 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: This register stores the current pulse count value for unit4.*/ +#define PCNT_PLUS_CNT_U4 0x0000FFFF +#define PCNT_PLUS_CNT_U4_M ((PCNT_PLUS_CNT_U4_V)<<(PCNT_PLUS_CNT_U4_S)) +#define PCNT_PLUS_CNT_U4_V 0xFFFF +#define PCNT_PLUS_CNT_U4_S 0 + +#define PCNT_U5_CNT_REG (DR_REG_PCNT_BASE + 0x0074) +/* PCNT_PLUS_CNT_U5 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: This register stores the current pulse count value for unit5.*/ +#define PCNT_PLUS_CNT_U5 0x0000FFFF +#define PCNT_PLUS_CNT_U5_M ((PCNT_PLUS_CNT_U5_V)<<(PCNT_PLUS_CNT_U5_S)) +#define PCNT_PLUS_CNT_U5_V 0xFFFF +#define PCNT_PLUS_CNT_U5_S 0 + +#define PCNT_U6_CNT_REG (DR_REG_PCNT_BASE + 0x0078) +/* PCNT_PLUS_CNT_U6 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: This register stores the current pulse count value for unit6.*/ +#define PCNT_PLUS_CNT_U6 0x0000FFFF +#define PCNT_PLUS_CNT_U6_M ((PCNT_PLUS_CNT_U6_V)<<(PCNT_PLUS_CNT_U6_S)) +#define PCNT_PLUS_CNT_U6_V 0xFFFF +#define PCNT_PLUS_CNT_U6_S 0 + +#define PCNT_U7_CNT_REG (DR_REG_PCNT_BASE + 0x007c) +/* PCNT_PLUS_CNT_U7 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: This register stores the current pulse count value for unit7.*/ +#define PCNT_PLUS_CNT_U7 0x0000FFFF +#define PCNT_PLUS_CNT_U7_M ((PCNT_PLUS_CNT_U7_V)<<(PCNT_PLUS_CNT_U7_S)) +#define PCNT_PLUS_CNT_U7_V 0xFFFF +#define PCNT_PLUS_CNT_U7_S 0 + +#define PCNT_INT_RAW_REG (DR_REG_PCNT_BASE + 0x0080) +/* PCNT_CNT_THR_EVENT_U7_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the interrupt raw bit for channel7 event.*/ +#define PCNT_CNT_THR_EVENT_U7_INT_RAW (BIT(7)) +#define PCNT_CNT_THR_EVENT_U7_INT_RAW_M (BIT(7)) +#define PCNT_CNT_THR_EVENT_U7_INT_RAW_V 0x1 +#define PCNT_CNT_THR_EVENT_U7_INT_RAW_S 7 +/* PCNT_CNT_THR_EVENT_U6_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This is the interrupt raw bit for channel6 event.*/ +#define PCNT_CNT_THR_EVENT_U6_INT_RAW (BIT(6)) +#define PCNT_CNT_THR_EVENT_U6_INT_RAW_M (BIT(6)) +#define PCNT_CNT_THR_EVENT_U6_INT_RAW_V 0x1 +#define PCNT_CNT_THR_EVENT_U6_INT_RAW_S 6 +/* PCNT_CNT_THR_EVENT_U5_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This is the interrupt raw bit for channel5 event.*/ +#define PCNT_CNT_THR_EVENT_U5_INT_RAW (BIT(5)) +#define PCNT_CNT_THR_EVENT_U5_INT_RAW_M (BIT(5)) +#define PCNT_CNT_THR_EVENT_U5_INT_RAW_V 0x1 +#define PCNT_CNT_THR_EVENT_U5_INT_RAW_S 5 +/* PCNT_CNT_THR_EVENT_U4_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This is the interrupt raw bit for channel4 event.*/ +#define PCNT_CNT_THR_EVENT_U4_INT_RAW (BIT(4)) +#define PCNT_CNT_THR_EVENT_U4_INT_RAW_M (BIT(4)) +#define PCNT_CNT_THR_EVENT_U4_INT_RAW_V 0x1 +#define PCNT_CNT_THR_EVENT_U4_INT_RAW_S 4 +/* PCNT_CNT_THR_EVENT_U3_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This is the interrupt raw bit for channel3 event.*/ +#define PCNT_CNT_THR_EVENT_U3_INT_RAW (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_RAW_M (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_RAW_V 0x1 +#define PCNT_CNT_THR_EVENT_U3_INT_RAW_S 3 +/* PCNT_CNT_THR_EVENT_U2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the interrupt raw bit for channel2 event.*/ +#define PCNT_CNT_THR_EVENT_U2_INT_RAW (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_RAW_M (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_RAW_V 0x1 +#define PCNT_CNT_THR_EVENT_U2_INT_RAW_S 2 +/* PCNT_CNT_THR_EVENT_U1_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: This is the interrupt raw bit for channel1 event.*/ +#define PCNT_CNT_THR_EVENT_U1_INT_RAW (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_RAW_M (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_RAW_V 0x1 +#define PCNT_CNT_THR_EVENT_U1_INT_RAW_S 1 +/* PCNT_CNT_THR_EVENT_U0_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This is the interrupt raw bit for channel0 event.*/ +#define PCNT_CNT_THR_EVENT_U0_INT_RAW (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_RAW_M (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_RAW_V 0x1 +#define PCNT_CNT_THR_EVENT_U0_INT_RAW_S 0 + +#define PCNT_INT_ST_REG (DR_REG_PCNT_BASE + 0x0084) +/* PCNT_CNT_THR_EVENT_U7_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the interrupt status bit for channel7 event.*/ +#define PCNT_CNT_THR_EVENT_U7_INT_ST (BIT(7)) +#define PCNT_CNT_THR_EVENT_U7_INT_ST_M (BIT(7)) +#define PCNT_CNT_THR_EVENT_U7_INT_ST_V 0x1 +#define PCNT_CNT_THR_EVENT_U7_INT_ST_S 7 +/* PCNT_CNT_THR_EVENT_U6_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This is the interrupt status bit for channel6 event.*/ +#define PCNT_CNT_THR_EVENT_U6_INT_ST (BIT(6)) +#define PCNT_CNT_THR_EVENT_U6_INT_ST_M (BIT(6)) +#define PCNT_CNT_THR_EVENT_U6_INT_ST_V 0x1 +#define PCNT_CNT_THR_EVENT_U6_INT_ST_S 6 +/* PCNT_CNT_THR_EVENT_U5_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This is the interrupt status bit for channel5 event.*/ +#define PCNT_CNT_THR_EVENT_U5_INT_ST (BIT(5)) +#define PCNT_CNT_THR_EVENT_U5_INT_ST_M (BIT(5)) +#define PCNT_CNT_THR_EVENT_U5_INT_ST_V 0x1 +#define PCNT_CNT_THR_EVENT_U5_INT_ST_S 5 +/* PCNT_CNT_THR_EVENT_U4_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This is the interrupt status bit for channel4 event.*/ +#define PCNT_CNT_THR_EVENT_U4_INT_ST (BIT(4)) +#define PCNT_CNT_THR_EVENT_U4_INT_ST_M (BIT(4)) +#define PCNT_CNT_THR_EVENT_U4_INT_ST_V 0x1 +#define PCNT_CNT_THR_EVENT_U4_INT_ST_S 4 +/* PCNT_CNT_THR_EVENT_U3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This is the interrupt status bit for channel3 event.*/ +#define PCNT_CNT_THR_EVENT_U3_INT_ST (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_ST_M (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_ST_V 0x1 +#define PCNT_CNT_THR_EVENT_U3_INT_ST_S 3 +/* PCNT_CNT_THR_EVENT_U2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the interrupt status bit for channel2 event.*/ +#define PCNT_CNT_THR_EVENT_U2_INT_ST (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_ST_M (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_ST_V 0x1 +#define PCNT_CNT_THR_EVENT_U2_INT_ST_S 2 +/* PCNT_CNT_THR_EVENT_U1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: This is the interrupt status bit for channel1 event.*/ +#define PCNT_CNT_THR_EVENT_U1_INT_ST (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_ST_M (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_ST_V 0x1 +#define PCNT_CNT_THR_EVENT_U1_INT_ST_S 1 +/* PCNT_CNT_THR_EVENT_U0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This is the interrupt status bit for channel0 event.*/ +#define PCNT_CNT_THR_EVENT_U0_INT_ST (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_ST_M (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_ST_V 0x1 +#define PCNT_CNT_THR_EVENT_U0_INT_ST_S 0 + +#define PCNT_INT_ENA_REG (DR_REG_PCNT_BASE + 0x0088) +/* PCNT_CNT_THR_EVENT_U7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the interrupt enable bit for channel7 event.*/ +#define PCNT_CNT_THR_EVENT_U7_INT_ENA (BIT(7)) +#define PCNT_CNT_THR_EVENT_U7_INT_ENA_M (BIT(7)) +#define PCNT_CNT_THR_EVENT_U7_INT_ENA_V 0x1 +#define PCNT_CNT_THR_EVENT_U7_INT_ENA_S 7 +/* PCNT_CNT_THR_EVENT_U6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This is the interrupt enable bit for channel6 event.*/ +#define PCNT_CNT_THR_EVENT_U6_INT_ENA (BIT(6)) +#define PCNT_CNT_THR_EVENT_U6_INT_ENA_M (BIT(6)) +#define PCNT_CNT_THR_EVENT_U6_INT_ENA_V 0x1 +#define PCNT_CNT_THR_EVENT_U6_INT_ENA_S 6 +/* PCNT_CNT_THR_EVENT_U5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This is the interrupt enable bit for channel5 event.*/ +#define PCNT_CNT_THR_EVENT_U5_INT_ENA (BIT(5)) +#define PCNT_CNT_THR_EVENT_U5_INT_ENA_M (BIT(5)) +#define PCNT_CNT_THR_EVENT_U5_INT_ENA_V 0x1 +#define PCNT_CNT_THR_EVENT_U5_INT_ENA_S 5 +/* PCNT_CNT_THR_EVENT_U4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This is the interrupt enable bit for channel4 event.*/ +#define PCNT_CNT_THR_EVENT_U4_INT_ENA (BIT(4)) +#define PCNT_CNT_THR_EVENT_U4_INT_ENA_M (BIT(4)) +#define PCNT_CNT_THR_EVENT_U4_INT_ENA_V 0x1 +#define PCNT_CNT_THR_EVENT_U4_INT_ENA_S 4 +/* PCNT_CNT_THR_EVENT_U3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This is the interrupt enable bit for channel3 event.*/ +#define PCNT_CNT_THR_EVENT_U3_INT_ENA (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_ENA_M (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_ENA_V 0x1 +#define PCNT_CNT_THR_EVENT_U3_INT_ENA_S 3 +/* PCNT_CNT_THR_EVENT_U2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the interrupt enable bit for channel2 event.*/ +#define PCNT_CNT_THR_EVENT_U2_INT_ENA (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_ENA_M (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_ENA_V 0x1 +#define PCNT_CNT_THR_EVENT_U2_INT_ENA_S 2 +/* PCNT_CNT_THR_EVENT_U1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: This is the interrupt enable bit for channel1 event.*/ +#define PCNT_CNT_THR_EVENT_U1_INT_ENA (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_ENA_M (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_ENA_V 0x1 +#define PCNT_CNT_THR_EVENT_U1_INT_ENA_S 1 +/* PCNT_CNT_THR_EVENT_U0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This is the interrupt enable bit for channel0 event.*/ +#define PCNT_CNT_THR_EVENT_U0_INT_ENA (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_ENA_M (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_ENA_V 0x1 +#define PCNT_CNT_THR_EVENT_U0_INT_ENA_S 0 + +#define PCNT_INT_CLR_REG (DR_REG_PCNT_BASE + 0x008c) +/* PCNT_CNT_THR_EVENT_U7_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to clear channel7 event interrupt.*/ +#define PCNT_CNT_THR_EVENT_U7_INT_CLR (BIT(7)) +#define PCNT_CNT_THR_EVENT_U7_INT_CLR_M (BIT(7)) +#define PCNT_CNT_THR_EVENT_U7_INT_CLR_V 0x1 +#define PCNT_CNT_THR_EVENT_U7_INT_CLR_S 7 +/* PCNT_CNT_THR_EVENT_U6_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to clear channel6 event interrupt.*/ +#define PCNT_CNT_THR_EVENT_U6_INT_CLR (BIT(6)) +#define PCNT_CNT_THR_EVENT_U6_INT_CLR_M (BIT(6)) +#define PCNT_CNT_THR_EVENT_U6_INT_CLR_V 0x1 +#define PCNT_CNT_THR_EVENT_U6_INT_CLR_S 6 +/* PCNT_CNT_THR_EVENT_U5_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to clear channel5 event interrupt.*/ +#define PCNT_CNT_THR_EVENT_U5_INT_CLR (BIT(5)) +#define PCNT_CNT_THR_EVENT_U5_INT_CLR_M (BIT(5)) +#define PCNT_CNT_THR_EVENT_U5_INT_CLR_V 0x1 +#define PCNT_CNT_THR_EVENT_U5_INT_CLR_S 5 +/* PCNT_CNT_THR_EVENT_U4_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to clear channel4 event interrupt.*/ +#define PCNT_CNT_THR_EVENT_U4_INT_CLR (BIT(4)) +#define PCNT_CNT_THR_EVENT_U4_INT_CLR_M (BIT(4)) +#define PCNT_CNT_THR_EVENT_U4_INT_CLR_V 0x1 +#define PCNT_CNT_THR_EVENT_U4_INT_CLR_S 4 +/* PCNT_CNT_THR_EVENT_U3_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear channel3 event interrupt.*/ +#define PCNT_CNT_THR_EVENT_U3_INT_CLR (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_CLR_M (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_CLR_V 0x1 +#define PCNT_CNT_THR_EVENT_U3_INT_CLR_S 3 +/* PCNT_CNT_THR_EVENT_U2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear channel2 event interrupt.*/ +#define PCNT_CNT_THR_EVENT_U2_INT_CLR (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_CLR_M (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_CLR_V 0x1 +#define PCNT_CNT_THR_EVENT_U2_INT_CLR_S 2 +/* PCNT_CNT_THR_EVENT_U1_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear channel1 event interrupt.*/ +#define PCNT_CNT_THR_EVENT_U1_INT_CLR (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_CLR_M (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_CLR_V 0x1 +#define PCNT_CNT_THR_EVENT_U1_INT_CLR_S 1 +/* PCNT_CNT_THR_EVENT_U0_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear channel0 event interrupt.*/ +#define PCNT_CNT_THR_EVENT_U0_INT_CLR (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_CLR_M (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_CLR_V 0x1 +#define PCNT_CNT_THR_EVENT_U0_INT_CLR_S 0 + +#define PCNT_U0_STATUS_REG (DR_REG_PCNT_BASE + 0x0090) +/* PCNT_CORE_STATUS_U0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define PCNT_CORE_STATUS_U0 0xFFFFFFFF +#define PCNT_CORE_STATUS_U0_M ((PCNT_CORE_STATUS_U0_V)<<(PCNT_CORE_STATUS_U0_S)) +#define PCNT_CORE_STATUS_U0_V 0xFFFFFFFF +#define PCNT_CORE_STATUS_U0_S 0 +/*0: positive value to zero; 1: negative value to zero; 2: counter value negative ; 3: counter value positive*/ +#define PCNT_STATUS_CNT_MODE 0x3 +#define PCNT_STATUS_CNT_MODE_M ((PCNT_STATUS_CNT_MODE_V)<<(PCNT_STATUS_CNT_MODE_S)) +#define PCNT_STATUS_CNT_MODE_V 0x3 +#define PCNT_STATUS_CNT_MODE_S 0 +/* counter value equals to thresh1*/ +#define PCNT_STATUS_THRES1 BIT(2) +#define PCNT_STATUS_THRES1_M BIT(2) +#define PCNT_STATUS_THRES1_V 0x1 +#define PCNT_STATUS_THRES1_S 2 +/* counter value equals to thresh0*/ +#define PCNT_STATUS_THRES0 BIT(3) +#define PCNT_STATUS_THRES0_M BIT(3) +#define PCNT_STATUS_THRES0_V 0x1 +#define PCNT_STATUS_THRES0_S 3 +/* counter value reaches h_lim*/ +#define PCNT_STATUS_L_LIM BIT(4) +#define PCNT_STATUS_L_LIM_M BIT(4) +#define PCNT_STATUS_L_LIM_V 0x1 +#define PCNT_STATUS_L_LIM_S 4 +/* counter value reaches l_lim*/ +#define PCNT_STATUS_H_LIM BIT(5) +#define PCNT_STATUS_H_LIM_M BIT(5) +#define PCNT_STATUS_H_LIM_V 0x1 +#define PCNT_STATUS_H_LIM_S 5 +/* counter value equals to zero*/ +#define PCNT_STATUS_ZERO BIT(6) +#define PCNT_STATUS_ZERO_M BIT(6) +#define PCNT_STATUS_ZERO_V 0x1 +#define PCNT_STATUS_ZERO_S 6 + +#define PCNT_U1_STATUS_REG (DR_REG_PCNT_BASE + 0x0094) +/* PCNT_CORE_STATUS_U1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define PCNT_CORE_STATUS_U1 0xFFFFFFFF +#define PCNT_CORE_STATUS_U1_M ((PCNT_CORE_STATUS_U1_V)<<(PCNT_CORE_STATUS_U1_S)) +#define PCNT_CORE_STATUS_U1_V 0xFFFFFFFF +#define PCNT_CORE_STATUS_U1_S 0 + +#define PCNT_U2_STATUS_REG (DR_REG_PCNT_BASE + 0x0098) +/* PCNT_CORE_STATUS_U2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define PCNT_CORE_STATUS_U2 0xFFFFFFFF +#define PCNT_CORE_STATUS_U2_M ((PCNT_CORE_STATUS_U2_V)<<(PCNT_CORE_STATUS_U2_S)) +#define PCNT_CORE_STATUS_U2_V 0xFFFFFFFF +#define PCNT_CORE_STATUS_U2_S 0 + +#define PCNT_U3_STATUS_REG (DR_REG_PCNT_BASE + 0x009c) +/* PCNT_CORE_STATUS_U3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define PCNT_CORE_STATUS_U3 0xFFFFFFFF +#define PCNT_CORE_STATUS_U3_M ((PCNT_CORE_STATUS_U3_V)<<(PCNT_CORE_STATUS_U3_S)) +#define PCNT_CORE_STATUS_U3_V 0xFFFFFFFF +#define PCNT_CORE_STATUS_U3_S 0 + +#define PCNT_U4_STATUS_REG (DR_REG_PCNT_BASE + 0x00a0) +/* PCNT_CORE_STATUS_U4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define PCNT_CORE_STATUS_U4 0xFFFFFFFF +#define PCNT_CORE_STATUS_U4_M ((PCNT_CORE_STATUS_U4_V)<<(PCNT_CORE_STATUS_U4_S)) +#define PCNT_CORE_STATUS_U4_V 0xFFFFFFFF +#define PCNT_CORE_STATUS_U4_S 0 + +#define PCNT_U5_STATUS_REG (DR_REG_PCNT_BASE + 0x00a4) +/* PCNT_CORE_STATUS_U5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define PCNT_CORE_STATUS_U5 0xFFFFFFFF +#define PCNT_CORE_STATUS_U5_M ((PCNT_CORE_STATUS_U5_V)<<(PCNT_CORE_STATUS_U5_S)) +#define PCNT_CORE_STATUS_U5_V 0xFFFFFFFF +#define PCNT_CORE_STATUS_U5_S 0 + +#define PCNT_U6_STATUS_REG (DR_REG_PCNT_BASE + 0x00a8) +/* PCNT_CORE_STATUS_U6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define PCNT_CORE_STATUS_U6 0xFFFFFFFF +#define PCNT_CORE_STATUS_U6_M ((PCNT_CORE_STATUS_U6_V)<<(PCNT_CORE_STATUS_U6_S)) +#define PCNT_CORE_STATUS_U6_V 0xFFFFFFFF +#define PCNT_CORE_STATUS_U6_S 0 + +#define PCNT_U7_STATUS_REG (DR_REG_PCNT_BASE + 0x00ac) +/* PCNT_CORE_STATUS_U7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define PCNT_CORE_STATUS_U7 0xFFFFFFFF +#define PCNT_CORE_STATUS_U7_M ((PCNT_CORE_STATUS_U7_V)<<(PCNT_CORE_STATUS_U7_S)) +#define PCNT_CORE_STATUS_U7_V 0xFFFFFFFF +#define PCNT_CORE_STATUS_U7_S 0 + +#define PCNT_CTRL_REG (DR_REG_PCNT_BASE + 0x00b0) +/* PCNT_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CLK_EN (BIT(16)) +#define PCNT_CLK_EN_M (BIT(16)) +#define PCNT_CLK_EN_V 0x1 +#define PCNT_CLK_EN_S 16 +/* PCNT_CNT_PAUSE_U7 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: Set this bit to pause unit7's counter.*/ +#define PCNT_CNT_PAUSE_U7 (BIT(15)) +#define PCNT_CNT_PAUSE_U7_M (BIT(15)) +#define PCNT_CNT_PAUSE_U7_V 0x1 +#define PCNT_CNT_PAUSE_U7_S 15 +/* PCNT_PLUS_CNT_RST_U7 : R/W ;bitpos:[14] ;default: 1'b1 ; */ +/*description: Set this bit to clear unit7's counter.*/ +#define PCNT_PLUS_CNT_RST_U7 (BIT(14)) +#define PCNT_PLUS_CNT_RST_U7_M (BIT(14)) +#define PCNT_PLUS_CNT_RST_U7_V 0x1 +#define PCNT_PLUS_CNT_RST_U7_S 14 +/* PCNT_CNT_PAUSE_U6 : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Set this bit to pause unit6's counter.*/ +#define PCNT_CNT_PAUSE_U6 (BIT(13)) +#define PCNT_CNT_PAUSE_U6_M (BIT(13)) +#define PCNT_CNT_PAUSE_U6_V 0x1 +#define PCNT_CNT_PAUSE_U6_S 13 +/* PCNT_PLUS_CNT_RST_U6 : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: Set this bit to clear unit6's counter.*/ +#define PCNT_PLUS_CNT_RST_U6 (BIT(12)) +#define PCNT_PLUS_CNT_RST_U6_M (BIT(12)) +#define PCNT_PLUS_CNT_RST_U6_V 0x1 +#define PCNT_PLUS_CNT_RST_U6_S 12 +/* PCNT_CNT_PAUSE_U5 : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Set this bit to pause unit5's counter.*/ +#define PCNT_CNT_PAUSE_U5 (BIT(11)) +#define PCNT_CNT_PAUSE_U5_M (BIT(11)) +#define PCNT_CNT_PAUSE_U5_V 0x1 +#define PCNT_CNT_PAUSE_U5_S 11 +/* PCNT_PLUS_CNT_RST_U5 : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: Set this bit to clear unit5's counter.*/ +#define PCNT_PLUS_CNT_RST_U5 (BIT(10)) +#define PCNT_PLUS_CNT_RST_U5_M (BIT(10)) +#define PCNT_PLUS_CNT_RST_U5_V 0x1 +#define PCNT_PLUS_CNT_RST_U5_S 10 +/* PCNT_CNT_PAUSE_U4 : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to pause unit4's counter.*/ +#define PCNT_CNT_PAUSE_U4 (BIT(9)) +#define PCNT_CNT_PAUSE_U4_M (BIT(9)) +#define PCNT_CNT_PAUSE_U4_V 0x1 +#define PCNT_CNT_PAUSE_U4_S 9 +/* PCNT_PLUS_CNT_RST_U4 : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: Set this bit to clear unit4's counter.*/ +#define PCNT_PLUS_CNT_RST_U4 (BIT(8)) +#define PCNT_PLUS_CNT_RST_U4_M (BIT(8)) +#define PCNT_PLUS_CNT_RST_U4_V 0x1 +#define PCNT_PLUS_CNT_RST_U4_S 8 +/* PCNT_CNT_PAUSE_U3 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to pause unit3's counter.*/ +#define PCNT_CNT_PAUSE_U3 (BIT(7)) +#define PCNT_CNT_PAUSE_U3_M (BIT(7)) +#define PCNT_CNT_PAUSE_U3_V 0x1 +#define PCNT_CNT_PAUSE_U3_S 7 +/* PCNT_PLUS_CNT_RST_U3 : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: Set this bit to clear unit3's counter.*/ +#define PCNT_PLUS_CNT_RST_U3 (BIT(6)) +#define PCNT_PLUS_CNT_RST_U3_M (BIT(6)) +#define PCNT_PLUS_CNT_RST_U3_V 0x1 +#define PCNT_PLUS_CNT_RST_U3_S 6 +/* PCNT_CNT_PAUSE_U2 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to pause unit2's counter.*/ +#define PCNT_CNT_PAUSE_U2 (BIT(5)) +#define PCNT_CNT_PAUSE_U2_M (BIT(5)) +#define PCNT_CNT_PAUSE_U2_V 0x1 +#define PCNT_CNT_PAUSE_U2_S 5 +/* PCNT_PLUS_CNT_RST_U2 : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: Set this bit to clear unit2's counter.*/ +#define PCNT_PLUS_CNT_RST_U2 (BIT(4)) +#define PCNT_PLUS_CNT_RST_U2_M (BIT(4)) +#define PCNT_PLUS_CNT_RST_U2_V 0x1 +#define PCNT_PLUS_CNT_RST_U2_S 4 +/* PCNT_CNT_PAUSE_U1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to pause unit1's counter.*/ +#define PCNT_CNT_PAUSE_U1 (BIT(3)) +#define PCNT_CNT_PAUSE_U1_M (BIT(3)) +#define PCNT_CNT_PAUSE_U1_V 0x1 +#define PCNT_CNT_PAUSE_U1_S 3 +/* PCNT_PLUS_CNT_RST_U1 : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: Set this bit to clear unit1's counter.*/ +#define PCNT_PLUS_CNT_RST_U1 (BIT(2)) +#define PCNT_PLUS_CNT_RST_U1_M (BIT(2)) +#define PCNT_PLUS_CNT_RST_U1_V 0x1 +#define PCNT_PLUS_CNT_RST_U1_S 2 +/* PCNT_CNT_PAUSE_U0 : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to pause unit0's counter.*/ +#define PCNT_CNT_PAUSE_U0 (BIT(1)) +#define PCNT_CNT_PAUSE_U0_M (BIT(1)) +#define PCNT_CNT_PAUSE_U0_V 0x1 +#define PCNT_CNT_PAUSE_U0_S 1 +/* PCNT_PLUS_CNT_RST_U0 : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: Set this bit to clear unit0's counter.*/ +#define PCNT_PLUS_CNT_RST_U0 (BIT(0)) +#define PCNT_PLUS_CNT_RST_U0_M (BIT(0)) +#define PCNT_PLUS_CNT_RST_U0_V 0x1 +#define PCNT_PLUS_CNT_RST_U0_S 0 + +#define PCNT_DATE_REG (DR_REG_PCNT_BASE + 0x00fc) +/* PCNT_DATE : R/W ;bitpos:[31:0] ;default: 32'h14122600 ; */ +/*description: */ +#define PCNT_DATE 0xFFFFFFFF +#define PCNT_DATE_M ((PCNT_DATE_V)<<(PCNT_DATE_S)) +#define PCNT_DATE_V 0xFFFFFFFF +#define PCNT_DATE_S 0 + + + + +#endif /*_SOC_PCNT_REG_H_ */ + + diff --git a/components/soc/esp32/include/soc/rmt_reg.h b/components/soc/esp32/include/soc/rmt_reg.h index 07ba24ac7..59756fa24 100644 --- a/components/soc/esp32/include/soc/rmt_reg.h +++ b/components/soc/esp32/include/soc/rmt_reg.h @@ -1,2172 +1,2172 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_RMT_REG_H_ -#define _SOC_RMT_REG_H_ - -#include "soc.h" -#define RMT_CH0DATA_REG (DR_REG_RMT_BASE + 0x0000) - -#define RMT_CH1DATA_REG (DR_REG_RMT_BASE + 0x0004) - -#define RMT_CH2DATA_REG (DR_REG_RMT_BASE + 0x0008) - -#define RMT_CH3DATA_REG (DR_REG_RMT_BASE + 0x000c) - -#define RMT_CH4DATA_REG (DR_REG_RMT_BASE + 0x0010) - -#define RMT_CH5DATA_REG (DR_REG_RMT_BASE + 0x0014) - -#define RMT_CH6DATA_REG (DR_REG_RMT_BASE + 0x0018) - -#define RMT_CH7DATA_REG (DR_REG_RMT_BASE + 0x001c) - -#define RMT_CH0CONF0_REG (DR_REG_RMT_BASE + 0x0020) -/* RMT_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ -/*description: This bit is used to control clock.when software config RMT - internal registers it controls the register clock.*/ -#define RMT_CLK_EN (BIT(31)) -#define RMT_CLK_EN_M (BIT(31)) -#define RMT_CLK_EN_V 0x1 -#define RMT_CLK_EN_S 31 -/* RMT_MEM_PD : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: This bit is used to reduce power consumed by mem. 1:mem is in low power state.*/ -#define RMT_MEM_PD (BIT(30)) -#define RMT_MEM_PD_M (BIT(30)) -#define RMT_MEM_PD_V 0x1 -#define RMT_MEM_PD_S 30 -/* RMT_CARRIER_OUT_LV_CH0 : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: This bit is used to configure the way carrier wave is modulated - for channel0.1'b1:transmit on low output level 1'b0:transmit on high output level.*/ -#define RMT_CARRIER_OUT_LV_CH0 (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH0_M (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH0_V 0x1 -#define RMT_CARRIER_OUT_LV_CH0_S 29 -/* RMT_CARRIER_EN_CH0 : R/W ;bitpos:[28] ;default: 1'b1 ; */ -/*description: This is the carrier modulation enable control bit for channel0.*/ -#define RMT_CARRIER_EN_CH0 (BIT(28)) -#define RMT_CARRIER_EN_CH0_M (BIT(28)) -#define RMT_CARRIER_EN_CH0_V 0x1 -#define RMT_CARRIER_EN_CH0_S 28 -/* RMT_MEM_SIZE_CH0 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ -/*description: This register is used to configure the the amount of memory blocks - allocated to channel0.*/ -#define RMT_MEM_SIZE_CH0 0x0000000F -#define RMT_MEM_SIZE_CH0_M ((RMT_MEM_SIZE_CH0_V)<<(RMT_MEM_SIZE_CH0_S)) -#define RMT_MEM_SIZE_CH0_V 0xF -#define RMT_MEM_SIZE_CH0_S 24 -/* RMT_IDLE_THRES_CH0 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ -/*description: In receive mode when no edge is detected on the input signal - for longer than reg_idle_thres_ch0 then the receive process is done.*/ -#define RMT_IDLE_THRES_CH0 0x0000FFFF -#define RMT_IDLE_THRES_CH0_M ((RMT_IDLE_THRES_CH0_V)<<(RMT_IDLE_THRES_CH0_S)) -#define RMT_IDLE_THRES_CH0_V 0xFFFF -#define RMT_IDLE_THRES_CH0_S 8 -/* RMT_DIV_CNT_CH0 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ -/*description: This register is used to configure the frequency divider's factor in channel0.*/ -#define RMT_DIV_CNT_CH0 0x000000FF -#define RMT_DIV_CNT_CH0_M ((RMT_DIV_CNT_CH0_V)<<(RMT_DIV_CNT_CH0_S)) -#define RMT_DIV_CNT_CH0_V 0xFF -#define RMT_DIV_CNT_CH0_S 0 - -#define RMT_CH0CONF1_REG (DR_REG_RMT_BASE + 0x0024) -/* RMT_IDLE_OUT_EN_CH0 : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for channel0 in IDLE state.*/ -#define RMT_IDLE_OUT_EN_CH0 (BIT(19)) -#define RMT_IDLE_OUT_EN_CH0_M (BIT(19)) -#define RMT_IDLE_OUT_EN_CH0_V 0x1 -#define RMT_IDLE_OUT_EN_CH0_S 19 -/* RMT_IDLE_OUT_LV_CH0 : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: This bit configures the output signal's level for channel0 in IDLE state.*/ -#define RMT_IDLE_OUT_LV_CH0 (BIT(18)) -#define RMT_IDLE_OUT_LV_CH0_M (BIT(18)) -#define RMT_IDLE_OUT_LV_CH0_V 0x1 -#define RMT_IDLE_OUT_LV_CH0_S 18 -/* RMT_REF_ALWAYS_ON_CH0 : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ -#define RMT_REF_ALWAYS_ON_CH0 (BIT(17)) -#define RMT_REF_ALWAYS_ON_CH0_M (BIT(17)) -#define RMT_REF_ALWAYS_ON_CH0_V 0x1 -#define RMT_REF_ALWAYS_ON_CH0_S 17 -/* RMT_REF_CNT_RST_CH0 : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: This bit is used to reset divider in channel0.*/ -#define RMT_REF_CNT_RST_CH0 (BIT(16)) -#define RMT_REF_CNT_RST_CH0_M (BIT(16)) -#define RMT_REF_CNT_RST_CH0_V 0x1 -#define RMT_REF_CNT_RST_CH0_S 16 -/* RMT_RX_FILTER_THRES_CH0 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ -/*description: in receive mode channel0 ignore input pulse when the pulse width - is smaller then this value.*/ -#define RMT_RX_FILTER_THRES_CH0 0x000000FF -#define RMT_RX_FILTER_THRES_CH0_M ((RMT_RX_FILTER_THRES_CH0_V)<<(RMT_RX_FILTER_THRES_CH0_S)) -#define RMT_RX_FILTER_THRES_CH0_V 0xFF -#define RMT_RX_FILTER_THRES_CH0_S 8 -/* RMT_RX_FILTER_EN_CH0 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: This is the receive filter enable bit for channel0.*/ -#define RMT_RX_FILTER_EN_CH0 (BIT(7)) -#define RMT_RX_FILTER_EN_CH0_M (BIT(7)) -#define RMT_RX_FILTER_EN_CH0_V 0x1 -#define RMT_RX_FILTER_EN_CH0_S 7 -/* RMT_TX_CONTI_MODE_CH0 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to continue sending from the first data to the - last data in channel0 again and again.*/ -#define RMT_TX_CONTI_MODE_CH0 (BIT(6)) -#define RMT_TX_CONTI_MODE_CH0_M (BIT(6)) -#define RMT_TX_CONTI_MODE_CH0_V 0x1 -#define RMT_TX_CONTI_MODE_CH0_S 6 -/* RMT_MEM_OWNER_CH0 : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: This is the mark of channel0's ram usage right.1'b1：receiver - uses the ram 0：transmitter uses the ram*/ -#define RMT_MEM_OWNER_CH0 (BIT(5)) -#define RMT_MEM_OWNER_CH0_M (BIT(5)) -#define RMT_MEM_OWNER_CH0_V 0x1 -#define RMT_MEM_OWNER_CH0_S 5 -/* RMT_APB_MEM_RST_CH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to reset W/R ram address for channel0 by apb fifo access*/ -#define RMT_APB_MEM_RST_CH0 (BIT(4)) -#define RMT_APB_MEM_RST_CH0_M (BIT(4)) -#define RMT_APB_MEM_RST_CH0_V 0x1 -#define RMT_APB_MEM_RST_CH0_S 4 -/* RMT_MEM_RD_RST_CH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to reset read ram address for channel0 by transmitter access.*/ -#define RMT_MEM_RD_RST_CH0 (BIT(3)) -#define RMT_MEM_RD_RST_CH0_M (BIT(3)) -#define RMT_MEM_RD_RST_CH0_V 0x1 -#define RMT_MEM_RD_RST_CH0_S 3 -/* RMT_MEM_WR_RST_CH0 : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: Set this bit to reset write ram address for channel0 by receiver access.*/ -#define RMT_MEM_WR_RST_CH0 (BIT(2)) -#define RMT_MEM_WR_RST_CH0_M (BIT(2)) -#define RMT_MEM_WR_RST_CH0_V 0x1 -#define RMT_MEM_WR_RST_CH0_S 2 -/* RMT_RX_EN_CH0 : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: Set this bit to enbale receving data for channel0.*/ -#define RMT_RX_EN_CH0 (BIT(1)) -#define RMT_RX_EN_CH0_M (BIT(1)) -#define RMT_RX_EN_CH0_V 0x1 -#define RMT_RX_EN_CH0_S 1 -/* RMT_TX_START_CH0 : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: Set this bit to start sending data for channel0.*/ -#define RMT_TX_START_CH0 (BIT(0)) -#define RMT_TX_START_CH0_M (BIT(0)) -#define RMT_TX_START_CH0_V 0x1 -#define RMT_TX_START_CH0_S 0 - -#define RMT_CH1CONF0_REG (DR_REG_RMT_BASE + 0x0028) -/* RMT_CARRIER_OUT_LV_CH1 : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: This bit is used to configure the way carrier wave is modulated - for channel1.1'b1:transmit on low output level 1'b0:transmit on high output level.*/ -#define RMT_CARRIER_OUT_LV_CH1 (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH1_M (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH1_V 0x1 -#define RMT_CARRIER_OUT_LV_CH1_S 29 -/* RMT_CARRIER_EN_CH1 : R/W ;bitpos:[28] ;default: 1'b1 ; */ -/*description: This is the carrier modulation enable control bit for channel1.*/ -#define RMT_CARRIER_EN_CH1 (BIT(28)) -#define RMT_CARRIER_EN_CH1_M (BIT(28)) -#define RMT_CARRIER_EN_CH1_V 0x1 -#define RMT_CARRIER_EN_CH1_S 28 -/* RMT_MEM_SIZE_CH1 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ -/*description: This register is used to configure the the amount of memory blocks - allocated to channel1.*/ -#define RMT_MEM_SIZE_CH1 0x0000000F -#define RMT_MEM_SIZE_CH1_M ((RMT_MEM_SIZE_CH1_V)<<(RMT_MEM_SIZE_CH1_S)) -#define RMT_MEM_SIZE_CH1_V 0xF -#define RMT_MEM_SIZE_CH1_S 24 -/* RMT_IDLE_THRES_CH1 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ -/*description: This register is used to configure the the amount of memory blocks - allocated to channel1.*/ -#define RMT_IDLE_THRES_CH1 0x0000FFFF -#define RMT_IDLE_THRES_CH1_M ((RMT_IDLE_THRES_CH1_V)<<(RMT_IDLE_THRES_CH1_S)) -#define RMT_IDLE_THRES_CH1_V 0xFFFF -#define RMT_IDLE_THRES_CH1_S 8 -/* RMT_DIV_CNT_CH1 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ -/*description: This register is used to configure the frequency divider's factor in channel1.*/ -#define RMT_DIV_CNT_CH1 0x000000FF -#define RMT_DIV_CNT_CH1_M ((RMT_DIV_CNT_CH1_V)<<(RMT_DIV_CNT_CH1_S)) -#define RMT_DIV_CNT_CH1_V 0xFF -#define RMT_DIV_CNT_CH1_S 0 - -#define RMT_CH1CONF1_REG (DR_REG_RMT_BASE + 0x002c) -/* RMT_IDLE_OUT_EN_CH1 : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for channel1 in IDLE state.*/ -#define RMT_IDLE_OUT_EN_CH1 (BIT(19)) -#define RMT_IDLE_OUT_EN_CH1_M (BIT(19)) -#define RMT_IDLE_OUT_EN_CH1_V 0x1 -#define RMT_IDLE_OUT_EN_CH1_S 19 -/* RMT_IDLE_OUT_LV_CH1 : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: This bit configures the output signal's level for channel1 in IDLE state.*/ -#define RMT_IDLE_OUT_LV_CH1 (BIT(18)) -#define RMT_IDLE_OUT_LV_CH1_M (BIT(18)) -#define RMT_IDLE_OUT_LV_CH1_V 0x1 -#define RMT_IDLE_OUT_LV_CH1_S 18 -/* RMT_REF_ALWAYS_ON_CH1 : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ -#define RMT_REF_ALWAYS_ON_CH1 (BIT(17)) -#define RMT_REF_ALWAYS_ON_CH1_M (BIT(17)) -#define RMT_REF_ALWAYS_ON_CH1_V 0x1 -#define RMT_REF_ALWAYS_ON_CH1_S 17 -/* RMT_REF_CNT_RST_CH1 : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: This bit is used to reset divider in channel1.*/ -#define RMT_REF_CNT_RST_CH1 (BIT(16)) -#define RMT_REF_CNT_RST_CH1_M (BIT(16)) -#define RMT_REF_CNT_RST_CH1_V 0x1 -#define RMT_REF_CNT_RST_CH1_S 16 -/* RMT_RX_FILTER_THRES_CH1 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ -/*description: in receive mode channel1 ignore input pulse when the pulse width - is smaller then this value.*/ -#define RMT_RX_FILTER_THRES_CH1 0x000000FF -#define RMT_RX_FILTER_THRES_CH1_M ((RMT_RX_FILTER_THRES_CH1_V)<<(RMT_RX_FILTER_THRES_CH1_S)) -#define RMT_RX_FILTER_THRES_CH1_V 0xFF -#define RMT_RX_FILTER_THRES_CH1_S 8 -/* RMT_RX_FILTER_EN_CH1 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: This is the receive filter enable bit for channel1.*/ -#define RMT_RX_FILTER_EN_CH1 (BIT(7)) -#define RMT_RX_FILTER_EN_CH1_M (BIT(7)) -#define RMT_RX_FILTER_EN_CH1_V 0x1 -#define RMT_RX_FILTER_EN_CH1_S 7 -/* RMT_TX_CONTI_MODE_CH1 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to continue sending from the first data to the - last data in channel1 again and again.*/ -#define RMT_TX_CONTI_MODE_CH1 (BIT(6)) -#define RMT_TX_CONTI_MODE_CH1_M (BIT(6)) -#define RMT_TX_CONTI_MODE_CH1_V 0x1 -#define RMT_TX_CONTI_MODE_CH1_S 6 -/* RMT_MEM_OWNER_CH1 : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: This is the mark of channel1's ram usage right.1'b1：receiver - uses the ram 0：transmitter uses the ram*/ -#define RMT_MEM_OWNER_CH1 (BIT(5)) -#define RMT_MEM_OWNER_CH1_M (BIT(5)) -#define RMT_MEM_OWNER_CH1_V 0x1 -#define RMT_MEM_OWNER_CH1_S 5 -/* RMT_APB_MEM_RST_CH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to reset W/R ram address for channel1 by apb fifo access*/ -#define RMT_APB_MEM_RST_CH1 (BIT(4)) -#define RMT_APB_MEM_RST_CH1_M (BIT(4)) -#define RMT_APB_MEM_RST_CH1_V 0x1 -#define RMT_APB_MEM_RST_CH1_S 4 -/* RMT_MEM_RD_RST_CH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to reset read ram address for channel1 by transmitter access.*/ -#define RMT_MEM_RD_RST_CH1 (BIT(3)) -#define RMT_MEM_RD_RST_CH1_M (BIT(3)) -#define RMT_MEM_RD_RST_CH1_V 0x1 -#define RMT_MEM_RD_RST_CH1_S 3 -/* RMT_MEM_WR_RST_CH1 : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: Set this bit to reset write ram address for channel1 by receiver access.*/ -#define RMT_MEM_WR_RST_CH1 (BIT(2)) -#define RMT_MEM_WR_RST_CH1_M (BIT(2)) -#define RMT_MEM_WR_RST_CH1_V 0x1 -#define RMT_MEM_WR_RST_CH1_S 2 -/* RMT_RX_EN_CH1 : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: Set this bit to enbale receving data for channel1.*/ -#define RMT_RX_EN_CH1 (BIT(1)) -#define RMT_RX_EN_CH1_M (BIT(1)) -#define RMT_RX_EN_CH1_V 0x1 -#define RMT_RX_EN_CH1_S 1 -/* RMT_TX_START_CH1 : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: Set this bit to start sending data for channel1.*/ -#define RMT_TX_START_CH1 (BIT(0)) -#define RMT_TX_START_CH1_M (BIT(0)) -#define RMT_TX_START_CH1_V 0x1 -#define RMT_TX_START_CH1_S 0 - -#define RMT_CH2CONF0_REG (DR_REG_RMT_BASE + 0x0030) -/* RMT_CARRIER_OUT_LV_CH2 : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: This bit is used to configure carrier wave's position for channel2.1'b1:add - on low level 1'b0:add on high level.*/ -#define RMT_CARRIER_OUT_LV_CH2 (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH2_M (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH2_V 0x1 -#define RMT_CARRIER_OUT_LV_CH2_S 29 -/* RMT_CARRIER_EN_CH2 : R/W ;bitpos:[28] ;default: 1'b1 ; */ -/*description: This is the carrier modulation enable control bit for channel2.*/ -#define RMT_CARRIER_EN_CH2 (BIT(28)) -#define RMT_CARRIER_EN_CH2_M (BIT(28)) -#define RMT_CARRIER_EN_CH2_V 0x1 -#define RMT_CARRIER_EN_CH2_S 28 -/* RMT_MEM_SIZE_CH2 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ -/*description: This register is used to configure the the amount of memory blocks - allocated to channel2.*/ -#define RMT_MEM_SIZE_CH2 0x0000000F -#define RMT_MEM_SIZE_CH2_M ((RMT_MEM_SIZE_CH2_V)<<(RMT_MEM_SIZE_CH2_S)) -#define RMT_MEM_SIZE_CH2_V 0xF -#define RMT_MEM_SIZE_CH2_S 24 -/* RMT_IDLE_THRES_CH2 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ -/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch2 - then the receive process is done.*/ -#define RMT_IDLE_THRES_CH2 0x0000FFFF -#define RMT_IDLE_THRES_CH2_M ((RMT_IDLE_THRES_CH2_V)<<(RMT_IDLE_THRES_CH2_S)) -#define RMT_IDLE_THRES_CH2_V 0xFFFF -#define RMT_IDLE_THRES_CH2_S 8 -/* RMT_DIV_CNT_CH2 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ -/*description: This register is used to configure the frequency divider's factor in channel2.*/ -#define RMT_DIV_CNT_CH2 0x000000FF -#define RMT_DIV_CNT_CH2_M ((RMT_DIV_CNT_CH2_V)<<(RMT_DIV_CNT_CH2_S)) -#define RMT_DIV_CNT_CH2_V 0xFF -#define RMT_DIV_CNT_CH2_S 0 - -#define RMT_CH2CONF1_REG (DR_REG_RMT_BASE + 0x0034) -/* RMT_IDLE_OUT_EN_CH2 : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for channel2 in IDLE state.*/ -#define RMT_IDLE_OUT_EN_CH2 (BIT(19)) -#define RMT_IDLE_OUT_EN_CH2_M (BIT(19)) -#define RMT_IDLE_OUT_EN_CH2_V 0x1 -#define RMT_IDLE_OUT_EN_CH2_S 19 -/* RMT_IDLE_OUT_LV_CH2 : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: This bit configures the output signal's level for channel2 in IDLE state.*/ -#define RMT_IDLE_OUT_LV_CH2 (BIT(18)) -#define RMT_IDLE_OUT_LV_CH2_M (BIT(18)) -#define RMT_IDLE_OUT_LV_CH2_V 0x1 -#define RMT_IDLE_OUT_LV_CH2_S 18 -/* RMT_REF_ALWAYS_ON_CH2 : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ -#define RMT_REF_ALWAYS_ON_CH2 (BIT(17)) -#define RMT_REF_ALWAYS_ON_CH2_M (BIT(17)) -#define RMT_REF_ALWAYS_ON_CH2_V 0x1 -#define RMT_REF_ALWAYS_ON_CH2_S 17 -/* RMT_REF_CNT_RST_CH2 : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: This bit is used to reset divider in channel2.*/ -#define RMT_REF_CNT_RST_CH2 (BIT(16)) -#define RMT_REF_CNT_RST_CH2_M (BIT(16)) -#define RMT_REF_CNT_RST_CH2_V 0x1 -#define RMT_REF_CNT_RST_CH2_S 16 -/* RMT_RX_FILTER_THRES_CH2 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ -/*description: in receive mode channel2 ignore input pulse when the pulse width - is smaller then this value.*/ -#define RMT_RX_FILTER_THRES_CH2 0x000000FF -#define RMT_RX_FILTER_THRES_CH2_M ((RMT_RX_FILTER_THRES_CH2_V)<<(RMT_RX_FILTER_THRES_CH2_S)) -#define RMT_RX_FILTER_THRES_CH2_V 0xFF -#define RMT_RX_FILTER_THRES_CH2_S 8 -/* RMT_RX_FILTER_EN_CH2 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: This is the receive filter enable bit for channel2.*/ -#define RMT_RX_FILTER_EN_CH2 (BIT(7)) -#define RMT_RX_FILTER_EN_CH2_M (BIT(7)) -#define RMT_RX_FILTER_EN_CH2_V 0x1 -#define RMT_RX_FILTER_EN_CH2_S 7 -/* RMT_TX_CONTI_MODE_CH2 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to continue sending from the first data to the - last data in channel2.*/ -#define RMT_TX_CONTI_MODE_CH2 (BIT(6)) -#define RMT_TX_CONTI_MODE_CH2_M (BIT(6)) -#define RMT_TX_CONTI_MODE_CH2_V 0x1 -#define RMT_TX_CONTI_MODE_CH2_S 6 -/* RMT_MEM_OWNER_CH2 : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: This is the mark of channel2's ram usage right.1'b1：receiver - uses the ram 0：transmitter uses the ram*/ -#define RMT_MEM_OWNER_CH2 (BIT(5)) -#define RMT_MEM_OWNER_CH2_M (BIT(5)) -#define RMT_MEM_OWNER_CH2_V 0x1 -#define RMT_MEM_OWNER_CH2_S 5 -/* RMT_APB_MEM_RST_CH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to reset W/R ram address for channel2 by apb fifo access*/ -#define RMT_APB_MEM_RST_CH2 (BIT(4)) -#define RMT_APB_MEM_RST_CH2_M (BIT(4)) -#define RMT_APB_MEM_RST_CH2_V 0x1 -#define RMT_APB_MEM_RST_CH2_S 4 -/* RMT_MEM_RD_RST_CH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to reset read ram address for channel2 by transmitter access.*/ -#define RMT_MEM_RD_RST_CH2 (BIT(3)) -#define RMT_MEM_RD_RST_CH2_M (BIT(3)) -#define RMT_MEM_RD_RST_CH2_V 0x1 -#define RMT_MEM_RD_RST_CH2_S 3 -/* RMT_MEM_WR_RST_CH2 : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: Set this bit to reset write ram address for channel2 by receiver access.*/ -#define RMT_MEM_WR_RST_CH2 (BIT(2)) -#define RMT_MEM_WR_RST_CH2_M (BIT(2)) -#define RMT_MEM_WR_RST_CH2_V 0x1 -#define RMT_MEM_WR_RST_CH2_S 2 -/* RMT_RX_EN_CH2 : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: Set this bit to enbale receving data for channel2.*/ -#define RMT_RX_EN_CH2 (BIT(1)) -#define RMT_RX_EN_CH2_M (BIT(1)) -#define RMT_RX_EN_CH2_V 0x1 -#define RMT_RX_EN_CH2_S 1 -/* RMT_TX_START_CH2 : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: Set this bit to start sending data for channel2.*/ -#define RMT_TX_START_CH2 (BIT(0)) -#define RMT_TX_START_CH2_M (BIT(0)) -#define RMT_TX_START_CH2_V 0x1 -#define RMT_TX_START_CH2_S 0 - -#define RMT_CH3CONF0_REG (DR_REG_RMT_BASE + 0x0038) -/* RMT_CARRIER_OUT_LV_CH3 : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: This bit is used to configure carrier wave's position for channel3.1'b1:add - on low level 1'b0:add on high level.*/ -#define RMT_CARRIER_OUT_LV_CH3 (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH3_M (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH3_V 0x1 -#define RMT_CARRIER_OUT_LV_CH3_S 29 -/* RMT_CARRIER_EN_CH3 : R/W ;bitpos:[28] ;default: 1'b1 ; */ -/*description: This is the carrier modulation enable control bit for channel3.*/ -#define RMT_CARRIER_EN_CH3 (BIT(28)) -#define RMT_CARRIER_EN_CH3_M (BIT(28)) -#define RMT_CARRIER_EN_CH3_V 0x1 -#define RMT_CARRIER_EN_CH3_S 28 -/* RMT_MEM_SIZE_CH3 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ -/*description: This register is used to configure the the amount of memory blocks - allocated to channel3.*/ -#define RMT_MEM_SIZE_CH3 0x0000000F -#define RMT_MEM_SIZE_CH3_M ((RMT_MEM_SIZE_CH3_V)<<(RMT_MEM_SIZE_CH3_S)) -#define RMT_MEM_SIZE_CH3_V 0xF -#define RMT_MEM_SIZE_CH3_S 24 -/* RMT_IDLE_THRES_CH3 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ -/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch3 - then the receive process is done.*/ -#define RMT_IDLE_THRES_CH3 0x0000FFFF -#define RMT_IDLE_THRES_CH3_M ((RMT_IDLE_THRES_CH3_V)<<(RMT_IDLE_THRES_CH3_S)) -#define RMT_IDLE_THRES_CH3_V 0xFFFF -#define RMT_IDLE_THRES_CH3_S 8 -/* RMT_DIV_CNT_CH3 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ -/*description: This register is used to configure the frequency divider's factor in channel3.*/ -#define RMT_DIV_CNT_CH3 0x000000FF -#define RMT_DIV_CNT_CH3_M ((RMT_DIV_CNT_CH3_V)<<(RMT_DIV_CNT_CH3_S)) -#define RMT_DIV_CNT_CH3_V 0xFF -#define RMT_DIV_CNT_CH3_S 0 - -#define RMT_CH3CONF1_REG (DR_REG_RMT_BASE + 0x003c) -/* RMT_IDLE_OUT_EN_CH3 : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for channel3 in IDLE state.*/ -#define RMT_IDLE_OUT_EN_CH3 (BIT(19)) -#define RMT_IDLE_OUT_EN_CH3_M (BIT(19)) -#define RMT_IDLE_OUT_EN_CH3_V 0x1 -#define RMT_IDLE_OUT_EN_CH3_S 19 -/* RMT_IDLE_OUT_LV_CH3 : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: This bit configures the output signal's level for channel3 in IDLE state.*/ -#define RMT_IDLE_OUT_LV_CH3 (BIT(18)) -#define RMT_IDLE_OUT_LV_CH3_M (BIT(18)) -#define RMT_IDLE_OUT_LV_CH3_V 0x1 -#define RMT_IDLE_OUT_LV_CH3_S 18 -/* RMT_REF_ALWAYS_ON_CH3 : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ -#define RMT_REF_ALWAYS_ON_CH3 (BIT(17)) -#define RMT_REF_ALWAYS_ON_CH3_M (BIT(17)) -#define RMT_REF_ALWAYS_ON_CH3_V 0x1 -#define RMT_REF_ALWAYS_ON_CH3_S 17 -/* RMT_REF_CNT_RST_CH3 : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: This bit is used to reset divider in channel3.*/ -#define RMT_REF_CNT_RST_CH3 (BIT(16)) -#define RMT_REF_CNT_RST_CH3_M (BIT(16)) -#define RMT_REF_CNT_RST_CH3_V 0x1 -#define RMT_REF_CNT_RST_CH3_S 16 -/* RMT_RX_FILTER_THRES_CH3 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ -/*description: in receive mode channel3 ignore input pulse when the pulse width - is smaller then this value.*/ -#define RMT_RX_FILTER_THRES_CH3 0x000000FF -#define RMT_RX_FILTER_THRES_CH3_M ((RMT_RX_FILTER_THRES_CH3_V)<<(RMT_RX_FILTER_THRES_CH3_S)) -#define RMT_RX_FILTER_THRES_CH3_V 0xFF -#define RMT_RX_FILTER_THRES_CH3_S 8 -/* RMT_RX_FILTER_EN_CH3 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: This is the receive filter enable bit for channel3.*/ -#define RMT_RX_FILTER_EN_CH3 (BIT(7)) -#define RMT_RX_FILTER_EN_CH3_M (BIT(7)) -#define RMT_RX_FILTER_EN_CH3_V 0x1 -#define RMT_RX_FILTER_EN_CH3_S 7 -/* RMT_TX_CONTI_MODE_CH3 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to continue sending from the first data to the - last data in channel3.*/ -#define RMT_TX_CONTI_MODE_CH3 (BIT(6)) -#define RMT_TX_CONTI_MODE_CH3_M (BIT(6)) -#define RMT_TX_CONTI_MODE_CH3_V 0x1 -#define RMT_TX_CONTI_MODE_CH3_S 6 -/* RMT_MEM_OWNER_CH3 : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: This is the mark of channel3's ram usage right.1'b1：receiver - uses the ram 0：transmitter uses the ram*/ -#define RMT_MEM_OWNER_CH3 (BIT(5)) -#define RMT_MEM_OWNER_CH3_M (BIT(5)) -#define RMT_MEM_OWNER_CH3_V 0x1 -#define RMT_MEM_OWNER_CH3_S 5 -/* RMT_APB_MEM_RST_CH3 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to reset W/R ram address for channel3 by apb fifo access*/ -#define RMT_APB_MEM_RST_CH3 (BIT(4)) -#define RMT_APB_MEM_RST_CH3_M (BIT(4)) -#define RMT_APB_MEM_RST_CH3_V 0x1 -#define RMT_APB_MEM_RST_CH3_S 4 -/* RMT_MEM_RD_RST_CH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to reset read ram address for channel3 by transmitter access.*/ -#define RMT_MEM_RD_RST_CH3 (BIT(3)) -#define RMT_MEM_RD_RST_CH3_M (BIT(3)) -#define RMT_MEM_RD_RST_CH3_V 0x1 -#define RMT_MEM_RD_RST_CH3_S 3 -/* RMT_MEM_WR_RST_CH3 : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: Set this bit to reset write ram address for channel3 by receiver access.*/ -#define RMT_MEM_WR_RST_CH3 (BIT(2)) -#define RMT_MEM_WR_RST_CH3_M (BIT(2)) -#define RMT_MEM_WR_RST_CH3_V 0x1 -#define RMT_MEM_WR_RST_CH3_S 2 -/* RMT_RX_EN_CH3 : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: Set this bit to enbale receving data for channel3.*/ -#define RMT_RX_EN_CH3 (BIT(1)) -#define RMT_RX_EN_CH3_M (BIT(1)) -#define RMT_RX_EN_CH3_V 0x1 -#define RMT_RX_EN_CH3_S 1 -/* RMT_TX_START_CH3 : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: Set this bit to start sending data for channel3.*/ -#define RMT_TX_START_CH3 (BIT(0)) -#define RMT_TX_START_CH3_M (BIT(0)) -#define RMT_TX_START_CH3_V 0x1 -#define RMT_TX_START_CH3_S 0 - -#define RMT_CH4CONF0_REG (DR_REG_RMT_BASE + 0x0040) -/* RMT_CARRIER_OUT_LV_CH4 : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: This bit is used to configure carrier wave's position for channel4.1'b1:add - on low level 1'b0:add on high level.*/ -#define RMT_CARRIER_OUT_LV_CH4 (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH4_M (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH4_V 0x1 -#define RMT_CARRIER_OUT_LV_CH4_S 29 -/* RMT_CARRIER_EN_CH4 : R/W ;bitpos:[28] ;default: 1'b1 ; */ -/*description: This is the carrier modulation enable control bit for channel4.*/ -#define RMT_CARRIER_EN_CH4 (BIT(28)) -#define RMT_CARRIER_EN_CH4_M (BIT(28)) -#define RMT_CARRIER_EN_CH4_V 0x1 -#define RMT_CARRIER_EN_CH4_S 28 -/* RMT_MEM_SIZE_CH4 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ -/*description: This register is used to configure the the amount of memory blocks - allocated to channel4.*/ -#define RMT_MEM_SIZE_CH4 0x0000000F -#define RMT_MEM_SIZE_CH4_M ((RMT_MEM_SIZE_CH4_V)<<(RMT_MEM_SIZE_CH4_S)) -#define RMT_MEM_SIZE_CH4_V 0xF -#define RMT_MEM_SIZE_CH4_S 24 -/* RMT_IDLE_THRES_CH4 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ -/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch4 - then the receive process is done.*/ -#define RMT_IDLE_THRES_CH4 0x0000FFFF -#define RMT_IDLE_THRES_CH4_M ((RMT_IDLE_THRES_CH4_V)<<(RMT_IDLE_THRES_CH4_S)) -#define RMT_IDLE_THRES_CH4_V 0xFFFF -#define RMT_IDLE_THRES_CH4_S 8 -/* RMT_DIV_CNT_CH4 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ -/*description: This register is used to configure the frequency divider's factor in channel4.*/ -#define RMT_DIV_CNT_CH4 0x000000FF -#define RMT_DIV_CNT_CH4_M ((RMT_DIV_CNT_CH4_V)<<(RMT_DIV_CNT_CH4_S)) -#define RMT_DIV_CNT_CH4_V 0xFF -#define RMT_DIV_CNT_CH4_S 0 - -#define RMT_CH4CONF1_REG (DR_REG_RMT_BASE + 0x0044) -/* RMT_IDLE_OUT_EN_CH4 : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for channel4 in IDLE state.*/ -#define RMT_IDLE_OUT_EN_CH4 (BIT(19)) -#define RMT_IDLE_OUT_EN_CH4_M (BIT(19)) -#define RMT_IDLE_OUT_EN_CH4_V 0x1 -#define RMT_IDLE_OUT_EN_CH4_S 19 -/* RMT_IDLE_OUT_LV_CH4 : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: This bit configures the output signal's level for channel4 in IDLE state.*/ -#define RMT_IDLE_OUT_LV_CH4 (BIT(18)) -#define RMT_IDLE_OUT_LV_CH4_M (BIT(18)) -#define RMT_IDLE_OUT_LV_CH4_V 0x1 -#define RMT_IDLE_OUT_LV_CH4_S 18 -/* RMT_REF_ALWAYS_ON_CH4 : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ -#define RMT_REF_ALWAYS_ON_CH4 (BIT(17)) -#define RMT_REF_ALWAYS_ON_CH4_M (BIT(17)) -#define RMT_REF_ALWAYS_ON_CH4_V 0x1 -#define RMT_REF_ALWAYS_ON_CH4_S 17 -/* RMT_REF_CNT_RST_CH4 : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: This bit is used to reset divider in channel4.*/ -#define RMT_REF_CNT_RST_CH4 (BIT(16)) -#define RMT_REF_CNT_RST_CH4_M (BIT(16)) -#define RMT_REF_CNT_RST_CH4_V 0x1 -#define RMT_REF_CNT_RST_CH4_S 16 -/* RMT_RX_FILTER_THRES_CH4 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ -/*description: in receive mode channel4 ignore input pulse when the pulse width - is smaller then this value.*/ -#define RMT_RX_FILTER_THRES_CH4 0x000000FF -#define RMT_RX_FILTER_THRES_CH4_M ((RMT_RX_FILTER_THRES_CH4_V)<<(RMT_RX_FILTER_THRES_CH4_S)) -#define RMT_RX_FILTER_THRES_CH4_V 0xFF -#define RMT_RX_FILTER_THRES_CH4_S 8 -/* RMT_RX_FILTER_EN_CH4 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: This is the receive filter enable bit for channel4.*/ -#define RMT_RX_FILTER_EN_CH4 (BIT(7)) -#define RMT_RX_FILTER_EN_CH4_M (BIT(7)) -#define RMT_RX_FILTER_EN_CH4_V 0x1 -#define RMT_RX_FILTER_EN_CH4_S 7 -/* RMT_TX_CONTI_MODE_CH4 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to continue sending from the first data to the - last data in channel4.*/ -#define RMT_TX_CONTI_MODE_CH4 (BIT(6)) -#define RMT_TX_CONTI_MODE_CH4_M (BIT(6)) -#define RMT_TX_CONTI_MODE_CH4_V 0x1 -#define RMT_TX_CONTI_MODE_CH4_S 6 -/* RMT_MEM_OWNER_CH4 : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: This is the mark of channel4's ram usage right.1'b1：receiver - uses the ram 0：transmitter uses the ram*/ -#define RMT_MEM_OWNER_CH4 (BIT(5)) -#define RMT_MEM_OWNER_CH4_M (BIT(5)) -#define RMT_MEM_OWNER_CH4_V 0x1 -#define RMT_MEM_OWNER_CH4_S 5 -/* RMT_APB_MEM_RST_CH4 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to reset W/R ram address for channel4 by apb fifo access*/ -#define RMT_APB_MEM_RST_CH4 (BIT(4)) -#define RMT_APB_MEM_RST_CH4_M (BIT(4)) -#define RMT_APB_MEM_RST_CH4_V 0x1 -#define RMT_APB_MEM_RST_CH4_S 4 -/* RMT_MEM_RD_RST_CH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to reset read ram address for channel4 by transmitter access.*/ -#define RMT_MEM_RD_RST_CH4 (BIT(3)) -#define RMT_MEM_RD_RST_CH4_M (BIT(3)) -#define RMT_MEM_RD_RST_CH4_V 0x1 -#define RMT_MEM_RD_RST_CH4_S 3 -/* RMT_MEM_WR_RST_CH4 : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: Set this bit to reset write ram address for channel4 by receiver access.*/ -#define RMT_MEM_WR_RST_CH4 (BIT(2)) -#define RMT_MEM_WR_RST_CH4_M (BIT(2)) -#define RMT_MEM_WR_RST_CH4_V 0x1 -#define RMT_MEM_WR_RST_CH4_S 2 -/* RMT_RX_EN_CH4 : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: Set this bit to enbale receving data for channel4.*/ -#define RMT_RX_EN_CH4 (BIT(1)) -#define RMT_RX_EN_CH4_M (BIT(1)) -#define RMT_RX_EN_CH4_V 0x1 -#define RMT_RX_EN_CH4_S 1 -/* RMT_TX_START_CH4 : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: Set this bit to start sending data for channel4.*/ -#define RMT_TX_START_CH4 (BIT(0)) -#define RMT_TX_START_CH4_M (BIT(0)) -#define RMT_TX_START_CH4_V 0x1 -#define RMT_TX_START_CH4_S 0 - -#define RMT_CH5CONF0_REG (DR_REG_RMT_BASE + 0x0048) -/* RMT_CARRIER_OUT_LV_CH5 : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: This bit is used to configure carrier wave's position for channel5.1'b1:add - on low level 1'b0:add on high level.*/ -#define RMT_CARRIER_OUT_LV_CH5 (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH5_M (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH5_V 0x1 -#define RMT_CARRIER_OUT_LV_CH5_S 29 -/* RMT_CARRIER_EN_CH5 : R/W ;bitpos:[28] ;default: 1'b1 ; */ -/*description: This is the carrier modulation enable control bit for channel5.*/ -#define RMT_CARRIER_EN_CH5 (BIT(28)) -#define RMT_CARRIER_EN_CH5_M (BIT(28)) -#define RMT_CARRIER_EN_CH5_V 0x1 -#define RMT_CARRIER_EN_CH5_S 28 -/* RMT_MEM_SIZE_CH5 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ -/*description: This register is used to configure the the amount of memory blocks - allocated to channel5.*/ -#define RMT_MEM_SIZE_CH5 0x0000000F -#define RMT_MEM_SIZE_CH5_M ((RMT_MEM_SIZE_CH5_V)<<(RMT_MEM_SIZE_CH5_S)) -#define RMT_MEM_SIZE_CH5_V 0xF -#define RMT_MEM_SIZE_CH5_S 24 -/* RMT_IDLE_THRES_CH5 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ -/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch5 - then the receive process is done.*/ -#define RMT_IDLE_THRES_CH5 0x0000FFFF -#define RMT_IDLE_THRES_CH5_M ((RMT_IDLE_THRES_CH5_V)<<(RMT_IDLE_THRES_CH5_S)) -#define RMT_IDLE_THRES_CH5_V 0xFFFF -#define RMT_IDLE_THRES_CH5_S 8 -/* RMT_DIV_CNT_CH5 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ -/*description: This register is used to configure the frequency divider's factor in channel5.*/ -#define RMT_DIV_CNT_CH5 0x000000FF -#define RMT_DIV_CNT_CH5_M ((RMT_DIV_CNT_CH5_V)<<(RMT_DIV_CNT_CH5_S)) -#define RMT_DIV_CNT_CH5_V 0xFF -#define RMT_DIV_CNT_CH5_S 0 - -#define RMT_CH5CONF1_REG (DR_REG_RMT_BASE + 0x004c) -/* RMT_IDLE_OUT_EN_CH5 : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for channel5 in IDLE state.*/ -#define RMT_IDLE_OUT_EN_CH5 (BIT(19)) -#define RMT_IDLE_OUT_EN_CH5_M (BIT(19)) -#define RMT_IDLE_OUT_EN_CH5_V 0x1 -#define RMT_IDLE_OUT_EN_CH5_S 19 -/* RMT_IDLE_OUT_LV_CH5 : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: This bit configures the output signal's level for channel5 in IDLE state.*/ -#define RMT_IDLE_OUT_LV_CH5 (BIT(18)) -#define RMT_IDLE_OUT_LV_CH5_M (BIT(18)) -#define RMT_IDLE_OUT_LV_CH5_V 0x1 -#define RMT_IDLE_OUT_LV_CH5_S 18 -/* RMT_REF_ALWAYS_ON_CH5 : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ -#define RMT_REF_ALWAYS_ON_CH5 (BIT(17)) -#define RMT_REF_ALWAYS_ON_CH5_M (BIT(17)) -#define RMT_REF_ALWAYS_ON_CH5_V 0x1 -#define RMT_REF_ALWAYS_ON_CH5_S 17 -/* RMT_REF_CNT_RST_CH5 : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: This bit is used to reset divider in channel5.*/ -#define RMT_REF_CNT_RST_CH5 (BIT(16)) -#define RMT_REF_CNT_RST_CH5_M (BIT(16)) -#define RMT_REF_CNT_RST_CH5_V 0x1 -#define RMT_REF_CNT_RST_CH5_S 16 -/* RMT_RX_FILTER_THRES_CH5 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ -/*description: in receive mode channel5 ignore input pulse when the pulse width - is smaller then this value.*/ -#define RMT_RX_FILTER_THRES_CH5 0x000000FF -#define RMT_RX_FILTER_THRES_CH5_M ((RMT_RX_FILTER_THRES_CH5_V)<<(RMT_RX_FILTER_THRES_CH5_S)) -#define RMT_RX_FILTER_THRES_CH5_V 0xFF -#define RMT_RX_FILTER_THRES_CH5_S 8 -/* RMT_RX_FILTER_EN_CH5 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: This is the receive filter enable bit for channel5.*/ -#define RMT_RX_FILTER_EN_CH5 (BIT(7)) -#define RMT_RX_FILTER_EN_CH5_M (BIT(7)) -#define RMT_RX_FILTER_EN_CH5_V 0x1 -#define RMT_RX_FILTER_EN_CH5_S 7 -/* RMT_TX_CONTI_MODE_CH5 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to continue sending from the first data to the - last data in channel5.*/ -#define RMT_TX_CONTI_MODE_CH5 (BIT(6)) -#define RMT_TX_CONTI_MODE_CH5_M (BIT(6)) -#define RMT_TX_CONTI_MODE_CH5_V 0x1 -#define RMT_TX_CONTI_MODE_CH5_S 6 -/* RMT_MEM_OWNER_CH5 : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: This is the mark of channel5's ram usage right.1'b1：receiver - uses the ram 0：transmitter uses the ram*/ -#define RMT_MEM_OWNER_CH5 (BIT(5)) -#define RMT_MEM_OWNER_CH5_M (BIT(5)) -#define RMT_MEM_OWNER_CH5_V 0x1 -#define RMT_MEM_OWNER_CH5_S 5 -/* RMT_APB_MEM_RST_CH5 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to reset W/R ram address for channel5 by apb fifo access*/ -#define RMT_APB_MEM_RST_CH5 (BIT(4)) -#define RMT_APB_MEM_RST_CH5_M (BIT(4)) -#define RMT_APB_MEM_RST_CH5_V 0x1 -#define RMT_APB_MEM_RST_CH5_S 4 -/* RMT_MEM_RD_RST_CH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to reset read ram address for channel5 by transmitter access.*/ -#define RMT_MEM_RD_RST_CH5 (BIT(3)) -#define RMT_MEM_RD_RST_CH5_M (BIT(3)) -#define RMT_MEM_RD_RST_CH5_V 0x1 -#define RMT_MEM_RD_RST_CH5_S 3 -/* RMT_MEM_WR_RST_CH5 : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: Set this bit to reset write ram address for channel5 by receiver access.*/ -#define RMT_MEM_WR_RST_CH5 (BIT(2)) -#define RMT_MEM_WR_RST_CH5_M (BIT(2)) -#define RMT_MEM_WR_RST_CH5_V 0x1 -#define RMT_MEM_WR_RST_CH5_S 2 -/* RMT_RX_EN_CH5 : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: Set this bit to enbale receving data for channel5.*/ -#define RMT_RX_EN_CH5 (BIT(1)) -#define RMT_RX_EN_CH5_M (BIT(1)) -#define RMT_RX_EN_CH5_V 0x1 -#define RMT_RX_EN_CH5_S 1 -/* RMT_TX_START_CH5 : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: Set this bit to start sending data for channel5.*/ -#define RMT_TX_START_CH5 (BIT(0)) -#define RMT_TX_START_CH5_M (BIT(0)) -#define RMT_TX_START_CH5_V 0x1 -#define RMT_TX_START_CH5_S 0 - -#define RMT_CH6CONF0_REG (DR_REG_RMT_BASE + 0x0050) -/* RMT_CARRIER_OUT_LV_CH6 : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: This bit is used to configure carrier wave's position for channel6.1'b1:add - on low level 1'b0:add on high level.*/ -#define RMT_CARRIER_OUT_LV_CH6 (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH6_M (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH6_V 0x1 -#define RMT_CARRIER_OUT_LV_CH6_S 29 -/* RMT_CARRIER_EN_CH6 : R/W ;bitpos:[28] ;default: 1'b1 ; */ -/*description: This is the carrier modulation enable control bit for channel6.*/ -#define RMT_CARRIER_EN_CH6 (BIT(28)) -#define RMT_CARRIER_EN_CH6_M (BIT(28)) -#define RMT_CARRIER_EN_CH6_V 0x1 -#define RMT_CARRIER_EN_CH6_S 28 -/* RMT_MEM_SIZE_CH6 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ -/*description: This register is used to configure the the amount of memory blocks - allocated to channel6.*/ -#define RMT_MEM_SIZE_CH6 0x0000000F -#define RMT_MEM_SIZE_CH6_M ((RMT_MEM_SIZE_CH6_V)<<(RMT_MEM_SIZE_CH6_S)) -#define RMT_MEM_SIZE_CH6_V 0xF -#define RMT_MEM_SIZE_CH6_S 24 -/* RMT_IDLE_THRES_CH6 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ -/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch6 - then the receive process is done.*/ -#define RMT_IDLE_THRES_CH6 0x0000FFFF -#define RMT_IDLE_THRES_CH6_M ((RMT_IDLE_THRES_CH6_V)<<(RMT_IDLE_THRES_CH6_S)) -#define RMT_IDLE_THRES_CH6_V 0xFFFF -#define RMT_IDLE_THRES_CH6_S 8 -/* RMT_DIV_CNT_CH6 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ -/*description: This register is used to configure the frequency divider's factor in channel6.*/ -#define RMT_DIV_CNT_CH6 0x000000FF -#define RMT_DIV_CNT_CH6_M ((RMT_DIV_CNT_CH6_V)<<(RMT_DIV_CNT_CH6_S)) -#define RMT_DIV_CNT_CH6_V 0xFF -#define RMT_DIV_CNT_CH6_S 0 - -#define RMT_CH6CONF1_REG (DR_REG_RMT_BASE + 0x0054) -/* RMT_IDLE_OUT_EN_CH6 : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for channel6 in IDLE state.*/ -#define RMT_IDLE_OUT_EN_CH6 (BIT(19)) -#define RMT_IDLE_OUT_EN_CH6_M (BIT(19)) -#define RMT_IDLE_OUT_EN_CH6_V 0x1 -#define RMT_IDLE_OUT_EN_CH6_S 19 -/* RMT_IDLE_OUT_LV_CH6 : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: This bit configures the output signal's level for channel6 in IDLE state.*/ -#define RMT_IDLE_OUT_LV_CH6 (BIT(18)) -#define RMT_IDLE_OUT_LV_CH6_M (BIT(18)) -#define RMT_IDLE_OUT_LV_CH6_V 0x1 -#define RMT_IDLE_OUT_LV_CH6_S 18 -/* RMT_REF_ALWAYS_ON_CH6 : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ -#define RMT_REF_ALWAYS_ON_CH6 (BIT(17)) -#define RMT_REF_ALWAYS_ON_CH6_M (BIT(17)) -#define RMT_REF_ALWAYS_ON_CH6_V 0x1 -#define RMT_REF_ALWAYS_ON_CH6_S 17 -/* RMT_REF_CNT_RST_CH6 : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: This bit is used to reset divider in channel6.*/ -#define RMT_REF_CNT_RST_CH6 (BIT(16)) -#define RMT_REF_CNT_RST_CH6_M (BIT(16)) -#define RMT_REF_CNT_RST_CH6_V 0x1 -#define RMT_REF_CNT_RST_CH6_S 16 -/* RMT_RX_FILTER_THRES_CH6 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ -/*description: in receive mode channel6 ignore input pulse when the pulse width - is smaller then this value.*/ -#define RMT_RX_FILTER_THRES_CH6 0x000000FF -#define RMT_RX_FILTER_THRES_CH6_M ((RMT_RX_FILTER_THRES_CH6_V)<<(RMT_RX_FILTER_THRES_CH6_S)) -#define RMT_RX_FILTER_THRES_CH6_V 0xFF -#define RMT_RX_FILTER_THRES_CH6_S 8 -/* RMT_RX_FILTER_EN_CH6 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: This is the receive filter enable bit for channel6.*/ -#define RMT_RX_FILTER_EN_CH6 (BIT(7)) -#define RMT_RX_FILTER_EN_CH6_M (BIT(7)) -#define RMT_RX_FILTER_EN_CH6_V 0x1 -#define RMT_RX_FILTER_EN_CH6_S 7 -/* RMT_TX_CONTI_MODE_CH6 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to continue sending from the first data to the - last data in channel6.*/ -#define RMT_TX_CONTI_MODE_CH6 (BIT(6)) -#define RMT_TX_CONTI_MODE_CH6_M (BIT(6)) -#define RMT_TX_CONTI_MODE_CH6_V 0x1 -#define RMT_TX_CONTI_MODE_CH6_S 6 -/* RMT_MEM_OWNER_CH6 : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: This is the mark of channel6's ram usage right.1'b1：receiver - uses the ram 0：transmitter uses the ram*/ -#define RMT_MEM_OWNER_CH6 (BIT(5)) -#define RMT_MEM_OWNER_CH6_M (BIT(5)) -#define RMT_MEM_OWNER_CH6_V 0x1 -#define RMT_MEM_OWNER_CH6_S 5 -/* RMT_APB_MEM_RST_CH6 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to reset W/R ram address for channel6 by apb fifo access*/ -#define RMT_APB_MEM_RST_CH6 (BIT(4)) -#define RMT_APB_MEM_RST_CH6_M (BIT(4)) -#define RMT_APB_MEM_RST_CH6_V 0x1 -#define RMT_APB_MEM_RST_CH6_S 4 -/* RMT_MEM_RD_RST_CH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to reset read ram address for channel6 by transmitter access.*/ -#define RMT_MEM_RD_RST_CH6 (BIT(3)) -#define RMT_MEM_RD_RST_CH6_M (BIT(3)) -#define RMT_MEM_RD_RST_CH6_V 0x1 -#define RMT_MEM_RD_RST_CH6_S 3 -/* RMT_MEM_WR_RST_CH6 : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: Set this bit to reset write ram address for channel6 by receiver access.*/ -#define RMT_MEM_WR_RST_CH6 (BIT(2)) -#define RMT_MEM_WR_RST_CH6_M (BIT(2)) -#define RMT_MEM_WR_RST_CH6_V 0x1 -#define RMT_MEM_WR_RST_CH6_S 2 -/* RMT_RX_EN_CH6 : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: Set this bit to enbale receving data for channel6.*/ -#define RMT_RX_EN_CH6 (BIT(1)) -#define RMT_RX_EN_CH6_M (BIT(1)) -#define RMT_RX_EN_CH6_V 0x1 -#define RMT_RX_EN_CH6_S 1 -/* RMT_TX_START_CH6 : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: Set this bit to start sending data for channel6.*/ -#define RMT_TX_START_CH6 (BIT(0)) -#define RMT_TX_START_CH6_M (BIT(0)) -#define RMT_TX_START_CH6_V 0x1 -#define RMT_TX_START_CH6_S 0 - -#define RMT_CH7CONF0_REG (DR_REG_RMT_BASE + 0x0058) -/* RMT_CARRIER_OUT_LV_CH7 : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: This bit is used to configure carrier wave's position for channel7.1'b1:add - on low level 1'b0:add on high level.*/ -#define RMT_CARRIER_OUT_LV_CH7 (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH7_M (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH7_V 0x1 -#define RMT_CARRIER_OUT_LV_CH7_S 29 -/* RMT_CARRIER_EN_CH7 : R/W ;bitpos:[28] ;default: 1'b1 ; */ -/*description: This is the carrier modulation enable control bit for channel7.*/ -#define RMT_CARRIER_EN_CH7 (BIT(28)) -#define RMT_CARRIER_EN_CH7_M (BIT(28)) -#define RMT_CARRIER_EN_CH7_V 0x1 -#define RMT_CARRIER_EN_CH7_S 28 -/* RMT_MEM_SIZE_CH7 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ -/*description: This register is used to configure the the amount of memory blocks - allocated to channel7.*/ -#define RMT_MEM_SIZE_CH7 0x0000000F -#define RMT_MEM_SIZE_CH7_M ((RMT_MEM_SIZE_CH7_V)<<(RMT_MEM_SIZE_CH7_S)) -#define RMT_MEM_SIZE_CH7_V 0xF -#define RMT_MEM_SIZE_CH7_S 24 -/* RMT_IDLE_THRES_CH7 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ -/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch7 - then the receive process is done.*/ -#define RMT_IDLE_THRES_CH7 0x0000FFFF -#define RMT_IDLE_THRES_CH7_M ((RMT_IDLE_THRES_CH7_V)<<(RMT_IDLE_THRES_CH7_S)) -#define RMT_IDLE_THRES_CH7_V 0xFFFF -#define RMT_IDLE_THRES_CH7_S 8 -/* RMT_DIV_CNT_CH7 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ -/*description: This register is used to configure the frequency divider's factor in channel7.*/ -#define RMT_DIV_CNT_CH7 0x000000FF -#define RMT_DIV_CNT_CH7_M ((RMT_DIV_CNT_CH7_V)<<(RMT_DIV_CNT_CH7_S)) -#define RMT_DIV_CNT_CH7_V 0xFF -#define RMT_DIV_CNT_CH7_S 0 - -#define RMT_CH7CONF1_REG (DR_REG_RMT_BASE + 0x005c) -/* RMT_IDLE_OUT_EN_CH7 : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for channel6 in IDLE state.*/ -#define RMT_IDLE_OUT_EN_CH7 (BIT(19)) -#define RMT_IDLE_OUT_EN_CH7_M (BIT(19)) -#define RMT_IDLE_OUT_EN_CH7_V 0x1 -#define RMT_IDLE_OUT_EN_CH7_S 19 -/* RMT_IDLE_OUT_LV_CH7 : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: This bit configures the output signal's level for channel7 in IDLE state.*/ -#define RMT_IDLE_OUT_LV_CH7 (BIT(18)) -#define RMT_IDLE_OUT_LV_CH7_M (BIT(18)) -#define RMT_IDLE_OUT_LV_CH7_V 0x1 -#define RMT_IDLE_OUT_LV_CH7_S 18 -/* RMT_REF_ALWAYS_ON_CH7 : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ -#define RMT_REF_ALWAYS_ON_CH7 (BIT(17)) -#define RMT_REF_ALWAYS_ON_CH7_M (BIT(17)) -#define RMT_REF_ALWAYS_ON_CH7_V 0x1 -#define RMT_REF_ALWAYS_ON_CH7_S 17 -/* RMT_REF_CNT_RST_CH7 : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: This bit is used to reset divider in channel7.*/ -#define RMT_REF_CNT_RST_CH7 (BIT(16)) -#define RMT_REF_CNT_RST_CH7_M (BIT(16)) -#define RMT_REF_CNT_RST_CH7_V 0x1 -#define RMT_REF_CNT_RST_CH7_S 16 -/* RMT_RX_FILTER_THRES_CH7 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ -/*description: in receive mode channel7 ignore input pulse when the pulse width - is smaller then this value.*/ -#define RMT_RX_FILTER_THRES_CH7 0x000000FF -#define RMT_RX_FILTER_THRES_CH7_M ((RMT_RX_FILTER_THRES_CH7_V)<<(RMT_RX_FILTER_THRES_CH7_S)) -#define RMT_RX_FILTER_THRES_CH7_V 0xFF -#define RMT_RX_FILTER_THRES_CH7_S 8 -/* RMT_RX_FILTER_EN_CH7 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: This is the receive filter enable bit for channel7.*/ -#define RMT_RX_FILTER_EN_CH7 (BIT(7)) -#define RMT_RX_FILTER_EN_CH7_M (BIT(7)) -#define RMT_RX_FILTER_EN_CH7_V 0x1 -#define RMT_RX_FILTER_EN_CH7_S 7 -/* RMT_TX_CONTI_MODE_CH7 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to continue sending from the first data to the - last data in channel7.*/ -#define RMT_TX_CONTI_MODE_CH7 (BIT(6)) -#define RMT_TX_CONTI_MODE_CH7_M (BIT(6)) -#define RMT_TX_CONTI_MODE_CH7_V 0x1 -#define RMT_TX_CONTI_MODE_CH7_S 6 -/* RMT_MEM_OWNER_CH7 : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: This is the mark of channel7's ram usage right.1'b1：receiver - uses the ram 0：transmitter uses the ram*/ -#define RMT_MEM_OWNER_CH7 (BIT(5)) -#define RMT_MEM_OWNER_CH7_M (BIT(5)) -#define RMT_MEM_OWNER_CH7_V 0x1 -#define RMT_MEM_OWNER_CH7_S 5 -/* RMT_APB_MEM_RST_CH7 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to reset W/R ram address for channel7 by apb fifo access*/ -#define RMT_APB_MEM_RST_CH7 (BIT(4)) -#define RMT_APB_MEM_RST_CH7_M (BIT(4)) -#define RMT_APB_MEM_RST_CH7_V 0x1 -#define RMT_APB_MEM_RST_CH7_S 4 -/* RMT_MEM_RD_RST_CH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to reset read ram address for channel7 by transmitter access.*/ -#define RMT_MEM_RD_RST_CH7 (BIT(3)) -#define RMT_MEM_RD_RST_CH7_M (BIT(3)) -#define RMT_MEM_RD_RST_CH7_V 0x1 -#define RMT_MEM_RD_RST_CH7_S 3 -/* RMT_MEM_WR_RST_CH7 : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: Set this bit to reset write ram address for channel7 by receiver access.*/ -#define RMT_MEM_WR_RST_CH7 (BIT(2)) -#define RMT_MEM_WR_RST_CH7_M (BIT(2)) -#define RMT_MEM_WR_RST_CH7_V 0x1 -#define RMT_MEM_WR_RST_CH7_S 2 -/* RMT_RX_EN_CH7 : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: Set this bit to enbale receving data for channel7.*/ -#define RMT_RX_EN_CH7 (BIT(1)) -#define RMT_RX_EN_CH7_M (BIT(1)) -#define RMT_RX_EN_CH7_V 0x1 -#define RMT_RX_EN_CH7_S 1 -/* RMT_TX_START_CH7 : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: Set this bit to start sending data for channel7.*/ -#define RMT_TX_START_CH7 (BIT(0)) -#define RMT_TX_START_CH7_M (BIT(0)) -#define RMT_TX_START_CH7_V 0x1 -#define RMT_TX_START_CH7_S 0 - -#define RMT_CH0STATUS_REG (DR_REG_RMT_BASE + 0x0060) -/* RMT_STATUS_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The status for channel0*/ -#define RMT_STATUS_CH0 0xFFFFFFFF -#define RMT_STATUS_CH0_M ((RMT_STATUS_CH0_V)<<(RMT_STATUS_CH0_S)) -#define RMT_STATUS_CH0_V 0xFFFFFFFF -#define RMT_STATUS_CH0_S 0 - -#define RMT_CH1STATUS_REG (DR_REG_RMT_BASE + 0x0064) -/* RMT_STATUS_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The status for channel1*/ -#define RMT_STATUS_CH1 0xFFFFFFFF -#define RMT_STATUS_CH1_M ((RMT_STATUS_CH1_V)<<(RMT_STATUS_CH1_S)) -#define RMT_STATUS_CH1_V 0xFFFFFFFF -#define RMT_STATUS_CH1_S 0 - -#define RMT_CH2STATUS_REG (DR_REG_RMT_BASE + 0x0068) -/* RMT_STATUS_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The status for channel2*/ -#define RMT_STATUS_CH2 0xFFFFFFFF -#define RMT_STATUS_CH2_M ((RMT_STATUS_CH2_V)<<(RMT_STATUS_CH2_S)) -#define RMT_STATUS_CH2_V 0xFFFFFFFF -#define RMT_STATUS_CH2_S 0 - -#define RMT_CH3STATUS_REG (DR_REG_RMT_BASE + 0x006c) -/* RMT_STATUS_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The status for channel3*/ -#define RMT_STATUS_CH3 0xFFFFFFFF -#define RMT_STATUS_CH3_M ((RMT_STATUS_CH3_V)<<(RMT_STATUS_CH3_S)) -#define RMT_STATUS_CH3_V 0xFFFFFFFF -#define RMT_STATUS_CH3_S 0 - -#define RMT_CH4STATUS_REG (DR_REG_RMT_BASE + 0x0070) -/* RMT_STATUS_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The status for channel4*/ -#define RMT_STATUS_CH4 0xFFFFFFFF -#define RMT_STATUS_CH4_M ((RMT_STATUS_CH4_V)<<(RMT_STATUS_CH4_S)) -#define RMT_STATUS_CH4_V 0xFFFFFFFF -#define RMT_STATUS_CH4_S 0 - -#define RMT_CH5STATUS_REG (DR_REG_RMT_BASE + 0x0074) -/* RMT_STATUS_CH5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The status for channel5*/ -#define RMT_STATUS_CH5 0xFFFFFFFF -#define RMT_STATUS_CH5_M ((RMT_STATUS_CH5_V)<<(RMT_STATUS_CH5_S)) -#define RMT_STATUS_CH5_V 0xFFFFFFFF -#define RMT_STATUS_CH5_S 0 - -#define RMT_CH6STATUS_REG (DR_REG_RMT_BASE + 0x0078) -/* RMT_STATUS_CH6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The status for channel6*/ -#define RMT_STATUS_CH6 0xFFFFFFFF -#define RMT_STATUS_CH6_M ((RMT_STATUS_CH6_V)<<(RMT_STATUS_CH6_S)) -#define RMT_STATUS_CH6_V 0xFFFFFFFF -#define RMT_STATUS_CH6_S 0 - -#define RMT_CH7STATUS_REG (DR_REG_RMT_BASE + 0x007c) -/* RMT_STATUS_CH7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The status for channel7*/ -#define RMT_STATUS_CH7 0xFFFFFFFF -#define RMT_STATUS_CH7_M ((RMT_STATUS_CH7_V)<<(RMT_STATUS_CH7_S)) -#define RMT_STATUS_CH7_V 0xFFFFFFFF -#define RMT_STATUS_CH7_S 0 - -#define RMT_CH0ADDR_REG (DR_REG_RMT_BASE + 0x0080) -/* RMT_APB_MEM_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The ram relative address in channel0 by apb fifo access*/ -#define RMT_APB_MEM_ADDR_CH0 0xFFFFFFFF -#define RMT_APB_MEM_ADDR_CH0_M ((RMT_APB_MEM_ADDR_CH0_V)<<(RMT_APB_MEM_ADDR_CH0_S)) -#define RMT_APB_MEM_ADDR_CH0_V 0xFFFFFFFF -#define RMT_APB_MEM_ADDR_CH0_S 0 - -#define RMT_CH1ADDR_REG (DR_REG_RMT_BASE + 0x0084) -/* RMT_APB_MEM_ADDR_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The ram relative address in channel1 by apb fifo access*/ -#define RMT_APB_MEM_ADDR_CH1 0xFFFFFFFF -#define RMT_APB_MEM_ADDR_CH1_M ((RMT_APB_MEM_ADDR_CH1_V)<<(RMT_APB_MEM_ADDR_CH1_S)) -#define RMT_APB_MEM_ADDR_CH1_V 0xFFFFFFFF -#define RMT_APB_MEM_ADDR_CH1_S 0 - -#define RMT_CH2ADDR_REG (DR_REG_RMT_BASE + 0x0088) -/* RMT_APB_MEM_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The ram relative address in channel2 by apb fifo access*/ -#define RMT_APB_MEM_ADDR_CH2 0xFFFFFFFF -#define RMT_APB_MEM_ADDR_CH2_M ((RMT_APB_MEM_ADDR_CH2_V)<<(RMT_APB_MEM_ADDR_CH2_S)) -#define RMT_APB_MEM_ADDR_CH2_V 0xFFFFFFFF -#define RMT_APB_MEM_ADDR_CH2_S 0 - -#define RMT_CH3ADDR_REG (DR_REG_RMT_BASE + 0x008c) -/* RMT_APB_MEM_ADDR_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The ram relative address in channel3 by apb fifo access*/ -#define RMT_APB_MEM_ADDR_CH3 0xFFFFFFFF -#define RMT_APB_MEM_ADDR_CH3_M ((RMT_APB_MEM_ADDR_CH3_V)<<(RMT_APB_MEM_ADDR_CH3_S)) -#define RMT_APB_MEM_ADDR_CH3_V 0xFFFFFFFF -#define RMT_APB_MEM_ADDR_CH3_S 0 - -#define RMT_CH4ADDR_REG (DR_REG_RMT_BASE + 0x0090) -/* RMT_APB_MEM_ADDR_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The ram relative address in channel4 by apb fifo access*/ -#define RMT_APB_MEM_ADDR_CH4 0xFFFFFFFF -#define RMT_APB_MEM_ADDR_CH4_M ((RMT_APB_MEM_ADDR_CH4_V)<<(RMT_APB_MEM_ADDR_CH4_S)) -#define RMT_APB_MEM_ADDR_CH4_V 0xFFFFFFFF -#define RMT_APB_MEM_ADDR_CH4_S 0 - -#define RMT_CH5ADDR_REG (DR_REG_RMT_BASE + 0x0094) -/* RMT_APB_MEM_ADDR_CH5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The ram relative address in channel5 by apb fifo access*/ -#define RMT_APB_MEM_ADDR_CH5 0xFFFFFFFF -#define RMT_APB_MEM_ADDR_CH5_M ((RMT_APB_MEM_ADDR_CH5_V)<<(RMT_APB_MEM_ADDR_CH5_S)) -#define RMT_APB_MEM_ADDR_CH5_V 0xFFFFFFFF -#define RMT_APB_MEM_ADDR_CH5_S 0 - -#define RMT_CH6ADDR_REG (DR_REG_RMT_BASE + 0x0098) -/* RMT_APB_MEM_ADDR_CH6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The ram relative address in channel6 by apb fifo access*/ -#define RMT_APB_MEM_ADDR_CH6 0xFFFFFFFF -#define RMT_APB_MEM_ADDR_CH6_M ((RMT_APB_MEM_ADDR_CH6_V)<<(RMT_APB_MEM_ADDR_CH6_S)) -#define RMT_APB_MEM_ADDR_CH6_V 0xFFFFFFFF -#define RMT_APB_MEM_ADDR_CH6_S 0 - -#define RMT_CH7ADDR_REG (DR_REG_RMT_BASE + 0x009c) -/* RMT_APB_MEM_ADDR_CH7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: The ram relative address in channel7 by apb fifo access*/ -#define RMT_APB_MEM_ADDR_CH7 0xFFFFFFFF -#define RMT_APB_MEM_ADDR_CH7_M ((RMT_APB_MEM_ADDR_CH7_V)<<(RMT_APB_MEM_ADDR_CH7_S)) -#define RMT_APB_MEM_ADDR_CH7_V 0xFFFFFFFF -#define RMT_APB_MEM_ADDR_CH7_S 0 - -#define RMT_INT_RAW_REG (DR_REG_RMT_BASE + 0x00a0) -/* RMT_CH7_TX_THR_EVENT_INT_RAW : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 7 turns to high level when - transmitter in channle7 have send datas more than reg_rmt_tx_lim_ch7 after detecting this interrupt software can updata the old datas with new datas.*/ -#define RMT_CH7_TX_THR_EVENT_INT_RAW (BIT(31)) -#define RMT_CH7_TX_THR_EVENT_INT_RAW_M (BIT(31)) -#define RMT_CH7_TX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH7_TX_THR_EVENT_INT_RAW_S 31 -/* RMT_CH6_TX_THR_EVENT_INT_RAW : RO ;bitpos:[30] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 6 turns to high level when - transmitter in channle6 have send datas more than reg_rmt_tx_lim_ch6 after detecting this interrupt software can updata the old datas with new datas.*/ -#define RMT_CH6_TX_THR_EVENT_INT_RAW (BIT(30)) -#define RMT_CH6_TX_THR_EVENT_INT_RAW_M (BIT(30)) -#define RMT_CH6_TX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH6_TX_THR_EVENT_INT_RAW_S 30 -/* RMT_CH5_TX_THR_EVENT_INT_RAW : RO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 5 turns to high level when - transmitter in channle5 have send datas more than reg_rmt_tx_lim_ch5 after detecting this interrupt software can updata the old datas with new datas.*/ -#define RMT_CH5_TX_THR_EVENT_INT_RAW (BIT(29)) -#define RMT_CH5_TX_THR_EVENT_INT_RAW_M (BIT(29)) -#define RMT_CH5_TX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH5_TX_THR_EVENT_INT_RAW_S 29 -/* RMT_CH4_TX_THR_EVENT_INT_RAW : RO ;bitpos:[28] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 4 turns to high level when - transmitter in channle4 have send datas more than reg_rmt_tx_lim_ch4 after detecting this interrupt software can updata the old datas with new datas.*/ -#define RMT_CH4_TX_THR_EVENT_INT_RAW (BIT(28)) -#define RMT_CH4_TX_THR_EVENT_INT_RAW_M (BIT(28)) -#define RMT_CH4_TX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH4_TX_THR_EVENT_INT_RAW_S 28 -/* RMT_CH3_TX_THR_EVENT_INT_RAW : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 3 turns to high level when - transmitter in channle3 have send datas more than reg_rmt_tx_lim_ch3 after detecting this interrupt software can updata the old datas with new datas.*/ -#define RMT_CH3_TX_THR_EVENT_INT_RAW (BIT(27)) -#define RMT_CH3_TX_THR_EVENT_INT_RAW_M (BIT(27)) -#define RMT_CH3_TX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH3_TX_THR_EVENT_INT_RAW_S 27 -/* RMT_CH2_TX_THR_EVENT_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 2 turns to high level when - transmitter in channle2 have send datas more than reg_rmt_tx_lim_ch2 after detecting this interrupt software can updata the old datas with new datas.*/ -#define RMT_CH2_TX_THR_EVENT_INT_RAW (BIT(26)) -#define RMT_CH2_TX_THR_EVENT_INT_RAW_M (BIT(26)) -#define RMT_CH2_TX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH2_TX_THR_EVENT_INT_RAW_S 26 -/* RMT_CH1_TX_THR_EVENT_INT_RAW : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 1 turns to high level when - transmitter in channle1 have send datas more than reg_rmt_tx_lim_ch1 after detecting this interrupt software can updata the old datas with new datas.*/ -#define RMT_CH1_TX_THR_EVENT_INT_RAW (BIT(25)) -#define RMT_CH1_TX_THR_EVENT_INT_RAW_M (BIT(25)) -#define RMT_CH1_TX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH1_TX_THR_EVENT_INT_RAW_S 25 -/* RMT_CH0_TX_THR_EVENT_INT_RAW : RO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 0 turns to high level when - transmitter in channle0 have send datas more than reg_rmt_tx_lim_ch0 after detecting this interrupt software can updata the old datas with new datas.*/ -#define RMT_CH0_TX_THR_EVENT_INT_RAW (BIT(24)) -#define RMT_CH0_TX_THR_EVENT_INT_RAW_M (BIT(24)) -#define RMT_CH0_TX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH0_TX_THR_EVENT_INT_RAW_S 24 -/* RMT_CH7_ERR_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 7 turns to high level when - channle 7 detects some errors.*/ -#define RMT_CH7_ERR_INT_RAW (BIT(23)) -#define RMT_CH7_ERR_INT_RAW_M (BIT(23)) -#define RMT_CH7_ERR_INT_RAW_V 0x1 -#define RMT_CH7_ERR_INT_RAW_S 23 -/* RMT_CH7_RX_END_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 7 turns to high level when - the receive process is done.*/ -#define RMT_CH7_RX_END_INT_RAW (BIT(22)) -#define RMT_CH7_RX_END_INT_RAW_M (BIT(22)) -#define RMT_CH7_RX_END_INT_RAW_V 0x1 -#define RMT_CH7_RX_END_INT_RAW_S 22 -/* RMT_CH7_TX_END_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 7 turns to high level when - the transmit process is done.*/ -#define RMT_CH7_TX_END_INT_RAW (BIT(21)) -#define RMT_CH7_TX_END_INT_RAW_M (BIT(21)) -#define RMT_CH7_TX_END_INT_RAW_V 0x1 -#define RMT_CH7_TX_END_INT_RAW_S 21 -/* RMT_CH6_ERR_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 6 turns to high level when - channle 6 detects some errors.*/ -#define RMT_CH6_ERR_INT_RAW (BIT(20)) -#define RMT_CH6_ERR_INT_RAW_M (BIT(20)) -#define RMT_CH6_ERR_INT_RAW_V 0x1 -#define RMT_CH6_ERR_INT_RAW_S 20 -/* RMT_CH6_RX_END_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 6 turns to high level when - the receive process is done.*/ -#define RMT_CH6_RX_END_INT_RAW (BIT(19)) -#define RMT_CH6_RX_END_INT_RAW_M (BIT(19)) -#define RMT_CH6_RX_END_INT_RAW_V 0x1 -#define RMT_CH6_RX_END_INT_RAW_S 19 -/* RMT_CH6_TX_END_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 6 turns to high level when - the transmit process is done.*/ -#define RMT_CH6_TX_END_INT_RAW (BIT(18)) -#define RMT_CH6_TX_END_INT_RAW_M (BIT(18)) -#define RMT_CH6_TX_END_INT_RAW_V 0x1 -#define RMT_CH6_TX_END_INT_RAW_S 18 -/* RMT_CH5_ERR_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 5 turns to high level when - channle 5 detects some errors.*/ -#define RMT_CH5_ERR_INT_RAW (BIT(17)) -#define RMT_CH5_ERR_INT_RAW_M (BIT(17)) -#define RMT_CH5_ERR_INT_RAW_V 0x1 -#define RMT_CH5_ERR_INT_RAW_S 17 -/* RMT_CH5_RX_END_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 5 turns to high level when - the receive process is done.*/ -#define RMT_CH5_RX_END_INT_RAW (BIT(16)) -#define RMT_CH5_RX_END_INT_RAW_M (BIT(16)) -#define RMT_CH5_RX_END_INT_RAW_V 0x1 -#define RMT_CH5_RX_END_INT_RAW_S 16 -/* RMT_CH5_TX_END_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 5 turns to high level when - the transmit process is done.*/ -#define RMT_CH5_TX_END_INT_RAW (BIT(15)) -#define RMT_CH5_TX_END_INT_RAW_M (BIT(15)) -#define RMT_CH5_TX_END_INT_RAW_V 0x1 -#define RMT_CH5_TX_END_INT_RAW_S 15 -/* RMT_CH4_ERR_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 4 turns to high level when - channle 4 detects some errors.*/ -#define RMT_CH4_ERR_INT_RAW (BIT(14)) -#define RMT_CH4_ERR_INT_RAW_M (BIT(14)) -#define RMT_CH4_ERR_INT_RAW_V 0x1 -#define RMT_CH4_ERR_INT_RAW_S 14 -/* RMT_CH4_RX_END_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 4 turns to high level when - the receive process is done.*/ -#define RMT_CH4_RX_END_INT_RAW (BIT(13)) -#define RMT_CH4_RX_END_INT_RAW_M (BIT(13)) -#define RMT_CH4_RX_END_INT_RAW_V 0x1 -#define RMT_CH4_RX_END_INT_RAW_S 13 -/* RMT_CH4_TX_END_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 4 turns to high level when - the transmit process is done.*/ -#define RMT_CH4_TX_END_INT_RAW (BIT(12)) -#define RMT_CH4_TX_END_INT_RAW_M (BIT(12)) -#define RMT_CH4_TX_END_INT_RAW_V 0x1 -#define RMT_CH4_TX_END_INT_RAW_S 12 -/* RMT_CH3_ERR_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 3 turns to high level when - channle 3 detects some errors.*/ -#define RMT_CH3_ERR_INT_RAW (BIT(11)) -#define RMT_CH3_ERR_INT_RAW_M (BIT(11)) -#define RMT_CH3_ERR_INT_RAW_V 0x1 -#define RMT_CH3_ERR_INT_RAW_S 11 -/* RMT_CH3_RX_END_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 3 turns to high level when - the receive process is done.*/ -#define RMT_CH3_RX_END_INT_RAW (BIT(10)) -#define RMT_CH3_RX_END_INT_RAW_M (BIT(10)) -#define RMT_CH3_RX_END_INT_RAW_V 0x1 -#define RMT_CH3_RX_END_INT_RAW_S 10 -/* RMT_CH3_TX_END_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 3 turns to high level when - the transmit process is done.*/ -#define RMT_CH3_TX_END_INT_RAW (BIT(9)) -#define RMT_CH3_TX_END_INT_RAW_M (BIT(9)) -#define RMT_CH3_TX_END_INT_RAW_V 0x1 -#define RMT_CH3_TX_END_INT_RAW_S 9 -/* RMT_CH2_ERR_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 2 turns to high level when - channle 2 detects some errors.*/ -#define RMT_CH2_ERR_INT_RAW (BIT(8)) -#define RMT_CH2_ERR_INT_RAW_M (BIT(8)) -#define RMT_CH2_ERR_INT_RAW_V 0x1 -#define RMT_CH2_ERR_INT_RAW_S 8 -/* RMT_CH2_RX_END_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 2 turns to high level when - the receive process is done.*/ -#define RMT_CH2_RX_END_INT_RAW (BIT(7)) -#define RMT_CH2_RX_END_INT_RAW_M (BIT(7)) -#define RMT_CH2_RX_END_INT_RAW_V 0x1 -#define RMT_CH2_RX_END_INT_RAW_S 7 -/* RMT_CH2_TX_END_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 2 turns to high level when - the transmit process is done.*/ -#define RMT_CH2_TX_END_INT_RAW (BIT(6)) -#define RMT_CH2_TX_END_INT_RAW_M (BIT(6)) -#define RMT_CH2_TX_END_INT_RAW_V 0x1 -#define RMT_CH2_TX_END_INT_RAW_S 6 -/* RMT_CH1_ERR_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 1 turns to high level when - channle 1 detects some errors.*/ -#define RMT_CH1_ERR_INT_RAW (BIT(5)) -#define RMT_CH1_ERR_INT_RAW_M (BIT(5)) -#define RMT_CH1_ERR_INT_RAW_V 0x1 -#define RMT_CH1_ERR_INT_RAW_S 5 -/* RMT_CH1_RX_END_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 1 turns to high level when - the receive process is done.*/ -#define RMT_CH1_RX_END_INT_RAW (BIT(4)) -#define RMT_CH1_RX_END_INT_RAW_M (BIT(4)) -#define RMT_CH1_RX_END_INT_RAW_V 0x1 -#define RMT_CH1_RX_END_INT_RAW_S 4 -/* RMT_CH1_TX_END_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 1 turns to high level when - the transmit process is done.*/ -#define RMT_CH1_TX_END_INT_RAW (BIT(3)) -#define RMT_CH1_TX_END_INT_RAW_M (BIT(3)) -#define RMT_CH1_TX_END_INT_RAW_V 0x1 -#define RMT_CH1_TX_END_INT_RAW_S 3 -/* RMT_CH0_ERR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 0 turns to high level when - channle 0 detects some errors.*/ -#define RMT_CH0_ERR_INT_RAW (BIT(2)) -#define RMT_CH0_ERR_INT_RAW_M (BIT(2)) -#define RMT_CH0_ERR_INT_RAW_V 0x1 -#define RMT_CH0_ERR_INT_RAW_S 2 -/* RMT_CH0_RX_END_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 0 turns to high level when - the receive process is done.*/ -#define RMT_CH0_RX_END_INT_RAW (BIT(1)) -#define RMT_CH0_RX_END_INT_RAW_M (BIT(1)) -#define RMT_CH0_RX_END_INT_RAW_V 0x1 -#define RMT_CH0_RX_END_INT_RAW_S 1 -/* RMT_CH0_TX_END_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for channel 0 turns to high level when - the transmit process is done.*/ -#define RMT_CH0_TX_END_INT_RAW (BIT(0)) -#define RMT_CH0_TX_END_INT_RAW_M (BIT(0)) -#define RMT_CH0_TX_END_INT_RAW_V 0x1 -#define RMT_CH0_TX_END_INT_RAW_S 0 - -#define RMT_INT_ST_REG (DR_REG_RMT_BASE + 0x00a4) -/* RMT_CH7_TX_THR_EVENT_INT_ST : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 7's rmt_ch7_tx_thr_event_int_raw - when mt_ch7_tx_thr_event_int_ena is set to 1.*/ -#define RMT_CH7_TX_THR_EVENT_INT_ST (BIT(31)) -#define RMT_CH7_TX_THR_EVENT_INT_ST_M (BIT(31)) -#define RMT_CH7_TX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH7_TX_THR_EVENT_INT_ST_S 31 -/* RMT_CH6_TX_THR_EVENT_INT_ST : RO ;bitpos:[30] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 6's rmt_ch6_tx_thr_event_int_raw - when mt_ch6_tx_thr_event_int_ena is set to 1.*/ -#define RMT_CH6_TX_THR_EVENT_INT_ST (BIT(30)) -#define RMT_CH6_TX_THR_EVENT_INT_ST_M (BIT(30)) -#define RMT_CH6_TX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH6_TX_THR_EVENT_INT_ST_S 30 -/* RMT_CH5_TX_THR_EVENT_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 5's rmt_ch5_tx_thr_event_int_raw - when mt_ch5_tx_thr_event_int_ena is set to 1.*/ -#define RMT_CH5_TX_THR_EVENT_INT_ST (BIT(29)) -#define RMT_CH5_TX_THR_EVENT_INT_ST_M (BIT(29)) -#define RMT_CH5_TX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH5_TX_THR_EVENT_INT_ST_S 29 -/* RMT_CH4_TX_THR_EVENT_INT_ST : RO ;bitpos:[28] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 4's rmt_ch4_tx_thr_event_int_raw - when mt_ch4_tx_thr_event_int_ena is set to 1.*/ -#define RMT_CH4_TX_THR_EVENT_INT_ST (BIT(28)) -#define RMT_CH4_TX_THR_EVENT_INT_ST_M (BIT(28)) -#define RMT_CH4_TX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH4_TX_THR_EVENT_INT_ST_S 28 -/* RMT_CH3_TX_THR_EVENT_INT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 3's rmt_ch3_tx_thr_event_int_raw - when mt_ch3_tx_thr_event_int_ena is set to 1.*/ -#define RMT_CH3_TX_THR_EVENT_INT_ST (BIT(27)) -#define RMT_CH3_TX_THR_EVENT_INT_ST_M (BIT(27)) -#define RMT_CH3_TX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH3_TX_THR_EVENT_INT_ST_S 27 -/* RMT_CH2_TX_THR_EVENT_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 2's rmt_ch2_tx_thr_event_int_raw - when mt_ch2_tx_thr_event_int_ena is set to 1.*/ -#define RMT_CH2_TX_THR_EVENT_INT_ST (BIT(26)) -#define RMT_CH2_TX_THR_EVENT_INT_ST_M (BIT(26)) -#define RMT_CH2_TX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH2_TX_THR_EVENT_INT_ST_S 26 -/* RMT_CH1_TX_THR_EVENT_INT_ST : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 1's rmt_ch1_tx_thr_event_int_raw - when mt_ch1_tx_thr_event_int_ena is set to 1.*/ -#define RMT_CH1_TX_THR_EVENT_INT_ST (BIT(25)) -#define RMT_CH1_TX_THR_EVENT_INT_ST_M (BIT(25)) -#define RMT_CH1_TX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH1_TX_THR_EVENT_INT_ST_S 25 -/* RMT_CH0_TX_THR_EVENT_INT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 0's rmt_ch0_tx_thr_event_int_raw - when mt_ch0_tx_thr_event_int_ena is set to 1.*/ -#define RMT_CH0_TX_THR_EVENT_INT_ST (BIT(24)) -#define RMT_CH0_TX_THR_EVENT_INT_ST_M (BIT(24)) -#define RMT_CH0_TX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH0_TX_THR_EVENT_INT_ST_S 24 -/* RMT_CH7_ERR_INT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 7's rmt_ch7_err_int_raw - when rmt_ch7_err_int_ena is set to 1.*/ -#define RMT_CH7_ERR_INT_ST (BIT(23)) -#define RMT_CH7_ERR_INT_ST_M (BIT(23)) -#define RMT_CH7_ERR_INT_ST_V 0x1 -#define RMT_CH7_ERR_INT_ST_S 23 -/* RMT_CH7_RX_END_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 7's rmt_ch7_rx_end_int_raw - when rmt_ch7_rx_end_int_ena is set to 1.*/ -#define RMT_CH7_RX_END_INT_ST (BIT(22)) -#define RMT_CH7_RX_END_INT_ST_M (BIT(22)) -#define RMT_CH7_RX_END_INT_ST_V 0x1 -#define RMT_CH7_RX_END_INT_ST_S 22 -/* RMT_CH7_TX_END_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 7's mt_ch7_tx_end_int_raw - when mt_ch7_tx_end_int_ena is set to 1.*/ -#define RMT_CH7_TX_END_INT_ST (BIT(21)) -#define RMT_CH7_TX_END_INT_ST_M (BIT(21)) -#define RMT_CH7_TX_END_INT_ST_V 0x1 -#define RMT_CH7_TX_END_INT_ST_S 21 -/* RMT_CH6_ERR_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 6's rmt_ch6_err_int_raw - when rmt_ch6_err_int_ena is set to 1.*/ -#define RMT_CH6_ERR_INT_ST (BIT(20)) -#define RMT_CH6_ERR_INT_ST_M (BIT(20)) -#define RMT_CH6_ERR_INT_ST_V 0x1 -#define RMT_CH6_ERR_INT_ST_S 20 -/* RMT_CH6_RX_END_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 6's rmt_ch6_rx_end_int_raw - when rmt_ch6_rx_end_int_ena is set to 1.*/ -#define RMT_CH6_RX_END_INT_ST (BIT(19)) -#define RMT_CH6_RX_END_INT_ST_M (BIT(19)) -#define RMT_CH6_RX_END_INT_ST_V 0x1 -#define RMT_CH6_RX_END_INT_ST_S 19 -/* RMT_CH6_TX_END_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 6's mt_ch6_tx_end_int_raw - when mt_ch6_tx_end_int_ena is set to 1.*/ -#define RMT_CH6_TX_END_INT_ST (BIT(18)) -#define RMT_CH6_TX_END_INT_ST_M (BIT(18)) -#define RMT_CH6_TX_END_INT_ST_V 0x1 -#define RMT_CH6_TX_END_INT_ST_S 18 -/* RMT_CH5_ERR_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 5's rmt_ch5_err_int_raw - when rmt_ch5_err_int_ena is set to 1.*/ -#define RMT_CH5_ERR_INT_ST (BIT(17)) -#define RMT_CH5_ERR_INT_ST_M (BIT(17)) -#define RMT_CH5_ERR_INT_ST_V 0x1 -#define RMT_CH5_ERR_INT_ST_S 17 -/* RMT_CH5_RX_END_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 5's rmt_ch5_rx_end_int_raw - when rmt_ch5_rx_end_int_ena is set to 1.*/ -#define RMT_CH5_RX_END_INT_ST (BIT(16)) -#define RMT_CH5_RX_END_INT_ST_M (BIT(16)) -#define RMT_CH5_RX_END_INT_ST_V 0x1 -#define RMT_CH5_RX_END_INT_ST_S 16 -/* RMT_CH5_TX_END_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 5's mt_ch5_tx_end_int_raw - when mt_ch5_tx_end_int_ena is set to 1.*/ -#define RMT_CH5_TX_END_INT_ST (BIT(15)) -#define RMT_CH5_TX_END_INT_ST_M (BIT(15)) -#define RMT_CH5_TX_END_INT_ST_V 0x1 -#define RMT_CH5_TX_END_INT_ST_S 15 -/* RMT_CH4_ERR_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 4's rmt_ch4_err_int_raw - when rmt_ch4_err_int_ena is set to 1.*/ -#define RMT_CH4_ERR_INT_ST (BIT(14)) -#define RMT_CH4_ERR_INT_ST_M (BIT(14)) -#define RMT_CH4_ERR_INT_ST_V 0x1 -#define RMT_CH4_ERR_INT_ST_S 14 -/* RMT_CH4_RX_END_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 4's rmt_ch4_rx_end_int_raw - when rmt_ch4_rx_end_int_ena is set to 1.*/ -#define RMT_CH4_RX_END_INT_ST (BIT(13)) -#define RMT_CH4_RX_END_INT_ST_M (BIT(13)) -#define RMT_CH4_RX_END_INT_ST_V 0x1 -#define RMT_CH4_RX_END_INT_ST_S 13 -/* RMT_CH4_TX_END_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 4's mt_ch4_tx_end_int_raw - when mt_ch4_tx_end_int_ena is set to 1.*/ -#define RMT_CH4_TX_END_INT_ST (BIT(12)) -#define RMT_CH4_TX_END_INT_ST_M (BIT(12)) -#define RMT_CH4_TX_END_INT_ST_V 0x1 -#define RMT_CH4_TX_END_INT_ST_S 12 -/* RMT_CH3_ERR_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 3's rmt_ch3_err_int_raw - when rmt_ch3_err_int_ena is set to 1.*/ -#define RMT_CH3_ERR_INT_ST (BIT(11)) -#define RMT_CH3_ERR_INT_ST_M (BIT(11)) -#define RMT_CH3_ERR_INT_ST_V 0x1 -#define RMT_CH3_ERR_INT_ST_S 11 -/* RMT_CH3_RX_END_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 3's rmt_ch3_rx_end_int_raw - when rmt_ch3_rx_end_int_ena is set to 1.*/ -#define RMT_CH3_RX_END_INT_ST (BIT(10)) -#define RMT_CH3_RX_END_INT_ST_M (BIT(10)) -#define RMT_CH3_RX_END_INT_ST_V 0x1 -#define RMT_CH3_RX_END_INT_ST_S 10 -/* RMT_CH3_TX_END_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 3's mt_ch3_tx_end_int_raw - when mt_ch3_tx_end_int_ena is set to 1.*/ -#define RMT_CH3_TX_END_INT_ST (BIT(9)) -#define RMT_CH3_TX_END_INT_ST_M (BIT(9)) -#define RMT_CH3_TX_END_INT_ST_V 0x1 -#define RMT_CH3_TX_END_INT_ST_S 9 -/* RMT_CH2_ERR_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 2's rmt_ch2_err_int_raw - when rmt_ch2_err_int_ena is set to 1.*/ -#define RMT_CH2_ERR_INT_ST (BIT(8)) -#define RMT_CH2_ERR_INT_ST_M (BIT(8)) -#define RMT_CH2_ERR_INT_ST_V 0x1 -#define RMT_CH2_ERR_INT_ST_S 8 -/* RMT_CH2_RX_END_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 2's rmt_ch2_rx_end_int_raw - when rmt_ch2_rx_end_int_ena is set to 1.*/ -#define RMT_CH2_RX_END_INT_ST (BIT(7)) -#define RMT_CH2_RX_END_INT_ST_M (BIT(7)) -#define RMT_CH2_RX_END_INT_ST_V 0x1 -#define RMT_CH2_RX_END_INT_ST_S 7 -/* RMT_CH2_TX_END_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 2's mt_ch2_tx_end_int_raw - when mt_ch2_tx_end_int_ena is set to 1.*/ -#define RMT_CH2_TX_END_INT_ST (BIT(6)) -#define RMT_CH2_TX_END_INT_ST_M (BIT(6)) -#define RMT_CH2_TX_END_INT_ST_V 0x1 -#define RMT_CH2_TX_END_INT_ST_S 6 -/* RMT_CH1_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 1's rmt_ch1_err_int_raw - when rmt_ch1_err_int_ena is set to 1.*/ -#define RMT_CH1_ERR_INT_ST (BIT(5)) -#define RMT_CH1_ERR_INT_ST_M (BIT(5)) -#define RMT_CH1_ERR_INT_ST_V 0x1 -#define RMT_CH1_ERR_INT_ST_S 5 -/* RMT_CH1_RX_END_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 1's rmt_ch1_rx_end_int_raw - when rmt_ch1_rx_end_int_ena is set to 1.*/ -#define RMT_CH1_RX_END_INT_ST (BIT(4)) -#define RMT_CH1_RX_END_INT_ST_M (BIT(4)) -#define RMT_CH1_RX_END_INT_ST_V 0x1 -#define RMT_CH1_RX_END_INT_ST_S 4 -/* RMT_CH1_TX_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 1's mt_ch1_tx_end_int_raw - when mt_ch1_tx_end_int_ena is set to 1.*/ -#define RMT_CH1_TX_END_INT_ST (BIT(3)) -#define RMT_CH1_TX_END_INT_ST_M (BIT(3)) -#define RMT_CH1_TX_END_INT_ST_V 0x1 -#define RMT_CH1_TX_END_INT_ST_S 3 -/* RMT_CH0_ERR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 0's rmt_ch0_err_int_raw - when rmt_ch0_err_int_ena is set to 0.*/ -#define RMT_CH0_ERR_INT_ST (BIT(2)) -#define RMT_CH0_ERR_INT_ST_M (BIT(2)) -#define RMT_CH0_ERR_INT_ST_V 0x1 -#define RMT_CH0_ERR_INT_ST_S 2 -/* RMT_CH0_RX_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 0's rmt_ch0_rx_end_int_raw - when rmt_ch0_rx_end_int_ena is set to 0.*/ -#define RMT_CH0_RX_END_INT_ST (BIT(1)) -#define RMT_CH0_RX_END_INT_ST_M (BIT(1)) -#define RMT_CH0_RX_END_INT_ST_V 0x1 -#define RMT_CH0_RX_END_INT_ST_S 1 -/* RMT_CH0_TX_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The interrupt state bit for channel 0's mt_ch0_tx_end_int_raw - when mt_ch0_tx_end_int_ena is set to 0.*/ -#define RMT_CH0_TX_END_INT_ST (BIT(0)) -#define RMT_CH0_TX_END_INT_ST_M (BIT(0)) -#define RMT_CH0_TX_END_INT_ST_V 0x1 -#define RMT_CH0_TX_END_INT_ST_S 0 - -#define RMT_INT_ENA_REG (DR_REG_RMT_BASE + 0x00a8) -/* RMT_CH7_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch7_tx_thr_event_int_st.*/ -#define RMT_CH7_TX_THR_EVENT_INT_ENA (BIT(31)) -#define RMT_CH7_TX_THR_EVENT_INT_ENA_M (BIT(31)) -#define RMT_CH7_TX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH7_TX_THR_EVENT_INT_ENA_S 31 -/* RMT_CH6_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch6_tx_thr_event_int_st.*/ -#define RMT_CH6_TX_THR_EVENT_INT_ENA (BIT(30)) -#define RMT_CH6_TX_THR_EVENT_INT_ENA_M (BIT(30)) -#define RMT_CH6_TX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH6_TX_THR_EVENT_INT_ENA_S 30 -/* RMT_CH5_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch5_tx_thr_event_int_st.*/ -#define RMT_CH5_TX_THR_EVENT_INT_ENA (BIT(29)) -#define RMT_CH5_TX_THR_EVENT_INT_ENA_M (BIT(29)) -#define RMT_CH5_TX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH5_TX_THR_EVENT_INT_ENA_S 29 -/* RMT_CH4_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch4_tx_thr_event_int_st.*/ -#define RMT_CH4_TX_THR_EVENT_INT_ENA (BIT(28)) -#define RMT_CH4_TX_THR_EVENT_INT_ENA_M (BIT(28)) -#define RMT_CH4_TX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH4_TX_THR_EVENT_INT_ENA_S 28 -/* RMT_CH3_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch3_tx_thr_event_int_st.*/ -#define RMT_CH3_TX_THR_EVENT_INT_ENA (BIT(27)) -#define RMT_CH3_TX_THR_EVENT_INT_ENA_M (BIT(27)) -#define RMT_CH3_TX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH3_TX_THR_EVENT_INT_ENA_S 27 -/* RMT_CH2_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch2_tx_thr_event_int_st.*/ -#define RMT_CH2_TX_THR_EVENT_INT_ENA (BIT(26)) -#define RMT_CH2_TX_THR_EVENT_INT_ENA_M (BIT(26)) -#define RMT_CH2_TX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH2_TX_THR_EVENT_INT_ENA_S 26 -/* RMT_CH1_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch1_tx_thr_event_int_st.*/ -#define RMT_CH1_TX_THR_EVENT_INT_ENA (BIT(25)) -#define RMT_CH1_TX_THR_EVENT_INT_ENA_M (BIT(25)) -#define RMT_CH1_TX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH1_TX_THR_EVENT_INT_ENA_S 25 -/* RMT_CH0_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch0_tx_thr_event_int_st.*/ -#define RMT_CH0_TX_THR_EVENT_INT_ENA (BIT(24)) -#define RMT_CH0_TX_THR_EVENT_INT_ENA_M (BIT(24)) -#define RMT_CH0_TX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH0_TX_THR_EVENT_INT_ENA_S 24 -/* RMT_CH7_ERR_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch7_err_int_st.*/ -#define RMT_CH7_ERR_INT_ENA (BIT(23)) -#define RMT_CH7_ERR_INT_ENA_M (BIT(23)) -#define RMT_CH7_ERR_INT_ENA_V 0x1 -#define RMT_CH7_ERR_INT_ENA_S 23 -/* RMT_CH7_RX_END_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch7_rx_end_int_st.*/ -#define RMT_CH7_RX_END_INT_ENA (BIT(22)) -#define RMT_CH7_RX_END_INT_ENA_M (BIT(22)) -#define RMT_CH7_RX_END_INT_ENA_V 0x1 -#define RMT_CH7_RX_END_INT_ENA_S 22 -/* RMT_CH7_TX_END_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch7_tx_end_int_st.*/ -#define RMT_CH7_TX_END_INT_ENA (BIT(21)) -#define RMT_CH7_TX_END_INT_ENA_M (BIT(21)) -#define RMT_CH7_TX_END_INT_ENA_V 0x1 -#define RMT_CH7_TX_END_INT_ENA_S 21 -/* RMT_CH6_ERR_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch6_err_int_st.*/ -#define RMT_CH6_ERR_INT_ENA (BIT(20)) -#define RMT_CH6_ERR_INT_ENA_M (BIT(20)) -#define RMT_CH6_ERR_INT_ENA_V 0x1 -#define RMT_CH6_ERR_INT_ENA_S 20 -/* RMT_CH6_RX_END_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch6_rx_end_int_st.*/ -#define RMT_CH6_RX_END_INT_ENA (BIT(19)) -#define RMT_CH6_RX_END_INT_ENA_M (BIT(19)) -#define RMT_CH6_RX_END_INT_ENA_V 0x1 -#define RMT_CH6_RX_END_INT_ENA_S 19 -/* RMT_CH6_TX_END_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch6_tx_end_int_st.*/ -#define RMT_CH6_TX_END_INT_ENA (BIT(18)) -#define RMT_CH6_TX_END_INT_ENA_M (BIT(18)) -#define RMT_CH6_TX_END_INT_ENA_V 0x1 -#define RMT_CH6_TX_END_INT_ENA_S 18 -/* RMT_CH5_ERR_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch5_err_int_st.*/ -#define RMT_CH5_ERR_INT_ENA (BIT(17)) -#define RMT_CH5_ERR_INT_ENA_M (BIT(17)) -#define RMT_CH5_ERR_INT_ENA_V 0x1 -#define RMT_CH5_ERR_INT_ENA_S 17 -/* RMT_CH5_RX_END_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch5_rx_end_int_st.*/ -#define RMT_CH5_RX_END_INT_ENA (BIT(16)) -#define RMT_CH5_RX_END_INT_ENA_M (BIT(16)) -#define RMT_CH5_RX_END_INT_ENA_V 0x1 -#define RMT_CH5_RX_END_INT_ENA_S 16 -/* RMT_CH5_TX_END_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch5_tx_end_int_st.*/ -#define RMT_CH5_TX_END_INT_ENA (BIT(15)) -#define RMT_CH5_TX_END_INT_ENA_M (BIT(15)) -#define RMT_CH5_TX_END_INT_ENA_V 0x1 -#define RMT_CH5_TX_END_INT_ENA_S 15 -/* RMT_CH4_ERR_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch4_err_int_st.*/ -#define RMT_CH4_ERR_INT_ENA (BIT(14)) -#define RMT_CH4_ERR_INT_ENA_M (BIT(14)) -#define RMT_CH4_ERR_INT_ENA_V 0x1 -#define RMT_CH4_ERR_INT_ENA_S 14 -/* RMT_CH4_RX_END_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch4_rx_end_int_st.*/ -#define RMT_CH4_RX_END_INT_ENA (BIT(13)) -#define RMT_CH4_RX_END_INT_ENA_M (BIT(13)) -#define RMT_CH4_RX_END_INT_ENA_V 0x1 -#define RMT_CH4_RX_END_INT_ENA_S 13 -/* RMT_CH4_TX_END_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch4_tx_end_int_st.*/ -#define RMT_CH4_TX_END_INT_ENA (BIT(12)) -#define RMT_CH4_TX_END_INT_ENA_M (BIT(12)) -#define RMT_CH4_TX_END_INT_ENA_V 0x1 -#define RMT_CH4_TX_END_INT_ENA_S 12 -/* RMT_CH3_ERR_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch3_err_int_st.*/ -#define RMT_CH3_ERR_INT_ENA (BIT(11)) -#define RMT_CH3_ERR_INT_ENA_M (BIT(11)) -#define RMT_CH3_ERR_INT_ENA_V 0x1 -#define RMT_CH3_ERR_INT_ENA_S 11 -/* RMT_CH3_RX_END_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch3_rx_end_int_st.*/ -#define RMT_CH3_RX_END_INT_ENA (BIT(10)) -#define RMT_CH3_RX_END_INT_ENA_M (BIT(10)) -#define RMT_CH3_RX_END_INT_ENA_V 0x1 -#define RMT_CH3_RX_END_INT_ENA_S 10 -/* RMT_CH3_TX_END_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch3_tx_end_int_st.*/ -#define RMT_CH3_TX_END_INT_ENA (BIT(9)) -#define RMT_CH3_TX_END_INT_ENA_M (BIT(9)) -#define RMT_CH3_TX_END_INT_ENA_V 0x1 -#define RMT_CH3_TX_END_INT_ENA_S 9 -/* RMT_CH2_ERR_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch2_err_int_st.*/ -#define RMT_CH2_ERR_INT_ENA (BIT(8)) -#define RMT_CH2_ERR_INT_ENA_M (BIT(8)) -#define RMT_CH2_ERR_INT_ENA_V 0x1 -#define RMT_CH2_ERR_INT_ENA_S 8 -/* RMT_CH2_RX_END_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch2_rx_end_int_st.*/ -#define RMT_CH2_RX_END_INT_ENA (BIT(7)) -#define RMT_CH2_RX_END_INT_ENA_M (BIT(7)) -#define RMT_CH2_RX_END_INT_ENA_V 0x1 -#define RMT_CH2_RX_END_INT_ENA_S 7 -/* RMT_CH2_TX_END_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch2_tx_end_int_st.*/ -#define RMT_CH2_TX_END_INT_ENA (BIT(6)) -#define RMT_CH2_TX_END_INT_ENA_M (BIT(6)) -#define RMT_CH2_TX_END_INT_ENA_V 0x1 -#define RMT_CH2_TX_END_INT_ENA_S 6 -/* RMT_CH1_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch1_err_int_st.*/ -#define RMT_CH1_ERR_INT_ENA (BIT(5)) -#define RMT_CH1_ERR_INT_ENA_M (BIT(5)) -#define RMT_CH1_ERR_INT_ENA_V 0x1 -#define RMT_CH1_ERR_INT_ENA_S 5 -/* RMT_CH1_RX_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch1_rx_end_int_st.*/ -#define RMT_CH1_RX_END_INT_ENA (BIT(4)) -#define RMT_CH1_RX_END_INT_ENA_M (BIT(4)) -#define RMT_CH1_RX_END_INT_ENA_V 0x1 -#define RMT_CH1_RX_END_INT_ENA_S 4 -/* RMT_CH1_TX_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch1_tx_end_int_st.*/ -#define RMT_CH1_TX_END_INT_ENA (BIT(3)) -#define RMT_CH1_TX_END_INT_ENA_M (BIT(3)) -#define RMT_CH1_TX_END_INT_ENA_V 0x1 -#define RMT_CH1_TX_END_INT_ENA_S 3 -/* RMT_CH0_ERR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch0_err_int_st.*/ -#define RMT_CH0_ERR_INT_ENA (BIT(2)) -#define RMT_CH0_ERR_INT_ENA_M (BIT(2)) -#define RMT_CH0_ERR_INT_ENA_V 0x1 -#define RMT_CH0_ERR_INT_ENA_S 2 -/* RMT_CH0_RX_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch0_rx_end_int_st.*/ -#define RMT_CH0_RX_END_INT_ENA (BIT(1)) -#define RMT_CH0_RX_END_INT_ENA_M (BIT(1)) -#define RMT_CH0_RX_END_INT_ENA_V 0x1 -#define RMT_CH0_RX_END_INT_ENA_S 1 -/* RMT_CH0_TX_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to enable rmt_ch0_tx_end_int_st.*/ -#define RMT_CH0_TX_END_INT_ENA (BIT(0)) -#define RMT_CH0_TX_END_INT_ENA_M (BIT(0)) -#define RMT_CH0_TX_END_INT_ENA_V 0x1 -#define RMT_CH0_TX_END_INT_ENA_S 0 - -#define RMT_INT_CLR_REG (DR_REG_RMT_BASE + 0x00ac) -/* RMT_CH7_TX_THR_EVENT_INT_CLR : WO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch7_tx_thr_event_int_raw interrupt.*/ -#define RMT_CH7_TX_THR_EVENT_INT_CLR (BIT(31)) -#define RMT_CH7_TX_THR_EVENT_INT_CLR_M (BIT(31)) -#define RMT_CH7_TX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH7_TX_THR_EVENT_INT_CLR_S 31 -/* RMT_CH6_TX_THR_EVENT_INT_CLR : WO ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch6_tx_thr_event_int_raw interrupt.*/ -#define RMT_CH6_TX_THR_EVENT_INT_CLR (BIT(30)) -#define RMT_CH6_TX_THR_EVENT_INT_CLR_M (BIT(30)) -#define RMT_CH6_TX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH6_TX_THR_EVENT_INT_CLR_S 30 -/* RMT_CH5_TX_THR_EVENT_INT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch5_tx_thr_event_int_raw interrupt.*/ -#define RMT_CH5_TX_THR_EVENT_INT_CLR (BIT(29)) -#define RMT_CH5_TX_THR_EVENT_INT_CLR_M (BIT(29)) -#define RMT_CH5_TX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH5_TX_THR_EVENT_INT_CLR_S 29 -/* RMT_CH4_TX_THR_EVENT_INT_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch4_tx_thr_event_int_raw interrupt.*/ -#define RMT_CH4_TX_THR_EVENT_INT_CLR (BIT(28)) -#define RMT_CH4_TX_THR_EVENT_INT_CLR_M (BIT(28)) -#define RMT_CH4_TX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH4_TX_THR_EVENT_INT_CLR_S 28 -/* RMT_CH3_TX_THR_EVENT_INT_CLR : WO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch3_tx_thr_event_int_raw interrupt.*/ -#define RMT_CH3_TX_THR_EVENT_INT_CLR (BIT(27)) -#define RMT_CH3_TX_THR_EVENT_INT_CLR_M (BIT(27)) -#define RMT_CH3_TX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH3_TX_THR_EVENT_INT_CLR_S 27 -/* RMT_CH2_TX_THR_EVENT_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch2_tx_thr_event_int_raw interrupt.*/ -#define RMT_CH2_TX_THR_EVENT_INT_CLR (BIT(26)) -#define RMT_CH2_TX_THR_EVENT_INT_CLR_M (BIT(26)) -#define RMT_CH2_TX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH2_TX_THR_EVENT_INT_CLR_S 26 -/* RMT_CH1_TX_THR_EVENT_INT_CLR : WO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch1_tx_thr_event_int_raw interrupt.*/ -#define RMT_CH1_TX_THR_EVENT_INT_CLR (BIT(25)) -#define RMT_CH1_TX_THR_EVENT_INT_CLR_M (BIT(25)) -#define RMT_CH1_TX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH1_TX_THR_EVENT_INT_CLR_S 25 -/* RMT_CH0_TX_THR_EVENT_INT_CLR : WO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch0_tx_thr_event_int_raw interrupt.*/ -#define RMT_CH0_TX_THR_EVENT_INT_CLR (BIT(24)) -#define RMT_CH0_TX_THR_EVENT_INT_CLR_M (BIT(24)) -#define RMT_CH0_TX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH0_TX_THR_EVENT_INT_CLR_S 24 -/* RMT_CH7_ERR_INT_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch7_err_int_raw.*/ -#define RMT_CH7_ERR_INT_CLR (BIT(23)) -#define RMT_CH7_ERR_INT_CLR_M (BIT(23)) -#define RMT_CH7_ERR_INT_CLR_V 0x1 -#define RMT_CH7_ERR_INT_CLR_S 23 -/* RMT_CH7_RX_END_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch7_tx_end_int_raw.*/ -#define RMT_CH7_RX_END_INT_CLR (BIT(22)) -#define RMT_CH7_RX_END_INT_CLR_M (BIT(22)) -#define RMT_CH7_RX_END_INT_CLR_V 0x1 -#define RMT_CH7_RX_END_INT_CLR_S 22 -/* RMT_CH7_TX_END_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch7_rx_end_int_raw..*/ -#define RMT_CH7_TX_END_INT_CLR (BIT(21)) -#define RMT_CH7_TX_END_INT_CLR_M (BIT(21)) -#define RMT_CH7_TX_END_INT_CLR_V 0x1 -#define RMT_CH7_TX_END_INT_CLR_S 21 -/* RMT_CH6_ERR_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch6_err_int_raw.*/ -#define RMT_CH6_ERR_INT_CLR (BIT(20)) -#define RMT_CH6_ERR_INT_CLR_M (BIT(20)) -#define RMT_CH6_ERR_INT_CLR_V 0x1 -#define RMT_CH6_ERR_INT_CLR_S 20 -/* RMT_CH6_RX_END_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch6_tx_end_int_raw.*/ -#define RMT_CH6_RX_END_INT_CLR (BIT(19)) -#define RMT_CH6_RX_END_INT_CLR_M (BIT(19)) -#define RMT_CH6_RX_END_INT_CLR_V 0x1 -#define RMT_CH6_RX_END_INT_CLR_S 19 -/* RMT_CH6_TX_END_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch6_rx_end_int_raw..*/ -#define RMT_CH6_TX_END_INT_CLR (BIT(18)) -#define RMT_CH6_TX_END_INT_CLR_M (BIT(18)) -#define RMT_CH6_TX_END_INT_CLR_V 0x1 -#define RMT_CH6_TX_END_INT_CLR_S 18 -/* RMT_CH5_ERR_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch5_err_int_raw.*/ -#define RMT_CH5_ERR_INT_CLR (BIT(17)) -#define RMT_CH5_ERR_INT_CLR_M (BIT(17)) -#define RMT_CH5_ERR_INT_CLR_V 0x1 -#define RMT_CH5_ERR_INT_CLR_S 17 -/* RMT_CH5_RX_END_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch5_tx_end_int_raw.*/ -#define RMT_CH5_RX_END_INT_CLR (BIT(16)) -#define RMT_CH5_RX_END_INT_CLR_M (BIT(16)) -#define RMT_CH5_RX_END_INT_CLR_V 0x1 -#define RMT_CH5_RX_END_INT_CLR_S 16 -/* RMT_CH5_TX_END_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch5_rx_end_int_raw..*/ -#define RMT_CH5_TX_END_INT_CLR (BIT(15)) -#define RMT_CH5_TX_END_INT_CLR_M (BIT(15)) -#define RMT_CH5_TX_END_INT_CLR_V 0x1 -#define RMT_CH5_TX_END_INT_CLR_S 15 -/* RMT_CH4_ERR_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch4_err_int_raw.*/ -#define RMT_CH4_ERR_INT_CLR (BIT(14)) -#define RMT_CH4_ERR_INT_CLR_M (BIT(14)) -#define RMT_CH4_ERR_INT_CLR_V 0x1 -#define RMT_CH4_ERR_INT_CLR_S 14 -/* RMT_CH4_RX_END_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch4_tx_end_int_raw.*/ -#define RMT_CH4_RX_END_INT_CLR (BIT(13)) -#define RMT_CH4_RX_END_INT_CLR_M (BIT(13)) -#define RMT_CH4_RX_END_INT_CLR_V 0x1 -#define RMT_CH4_RX_END_INT_CLR_S 13 -/* RMT_CH4_TX_END_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch4_rx_end_int_raw..*/ -#define RMT_CH4_TX_END_INT_CLR (BIT(12)) -#define RMT_CH4_TX_END_INT_CLR_M (BIT(12)) -#define RMT_CH4_TX_END_INT_CLR_V 0x1 -#define RMT_CH4_TX_END_INT_CLR_S 12 -/* RMT_CH3_ERR_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch3_err_int_raw.*/ -#define RMT_CH3_ERR_INT_CLR (BIT(11)) -#define RMT_CH3_ERR_INT_CLR_M (BIT(11)) -#define RMT_CH3_ERR_INT_CLR_V 0x1 -#define RMT_CH3_ERR_INT_CLR_S 11 -/* RMT_CH3_RX_END_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch3_tx_end_int_raw.*/ -#define RMT_CH3_RX_END_INT_CLR (BIT(10)) -#define RMT_CH3_RX_END_INT_CLR_M (BIT(10)) -#define RMT_CH3_RX_END_INT_CLR_V 0x1 -#define RMT_CH3_RX_END_INT_CLR_S 10 -/* RMT_CH3_TX_END_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch3_rx_end_int_raw..*/ -#define RMT_CH3_TX_END_INT_CLR (BIT(9)) -#define RMT_CH3_TX_END_INT_CLR_M (BIT(9)) -#define RMT_CH3_TX_END_INT_CLR_V 0x1 -#define RMT_CH3_TX_END_INT_CLR_S 9 -/* RMT_CH2_ERR_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch2_err_int_raw.*/ -#define RMT_CH2_ERR_INT_CLR (BIT(8)) -#define RMT_CH2_ERR_INT_CLR_M (BIT(8)) -#define RMT_CH2_ERR_INT_CLR_V 0x1 -#define RMT_CH2_ERR_INT_CLR_S 8 -/* RMT_CH2_RX_END_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch2_tx_end_int_raw.*/ -#define RMT_CH2_RX_END_INT_CLR (BIT(7)) -#define RMT_CH2_RX_END_INT_CLR_M (BIT(7)) -#define RMT_CH2_RX_END_INT_CLR_V 0x1 -#define RMT_CH2_RX_END_INT_CLR_S 7 -/* RMT_CH2_TX_END_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch2_rx_end_int_raw..*/ -#define RMT_CH2_TX_END_INT_CLR (BIT(6)) -#define RMT_CH2_TX_END_INT_CLR_M (BIT(6)) -#define RMT_CH2_TX_END_INT_CLR_V 0x1 -#define RMT_CH2_TX_END_INT_CLR_S 6 -/* RMT_CH1_ERR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch1_err_int_raw.*/ -#define RMT_CH1_ERR_INT_CLR (BIT(5)) -#define RMT_CH1_ERR_INT_CLR_M (BIT(5)) -#define RMT_CH1_ERR_INT_CLR_V 0x1 -#define RMT_CH1_ERR_INT_CLR_S 5 -/* RMT_CH1_RX_END_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch1_tx_end_int_raw.*/ -#define RMT_CH1_RX_END_INT_CLR (BIT(4)) -#define RMT_CH1_RX_END_INT_CLR_M (BIT(4)) -#define RMT_CH1_RX_END_INT_CLR_V 0x1 -#define RMT_CH1_RX_END_INT_CLR_S 4 -/* RMT_CH1_TX_END_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch1_rx_end_int_raw..*/ -#define RMT_CH1_TX_END_INT_CLR (BIT(3)) -#define RMT_CH1_TX_END_INT_CLR_M (BIT(3)) -#define RMT_CH1_TX_END_INT_CLR_V 0x1 -#define RMT_CH1_TX_END_INT_CLR_S 3 -/* RMT_CH0_ERR_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch0_err_int_raw.*/ -#define RMT_CH0_ERR_INT_CLR (BIT(2)) -#define RMT_CH0_ERR_INT_CLR_M (BIT(2)) -#define RMT_CH0_ERR_INT_CLR_V 0x1 -#define RMT_CH0_ERR_INT_CLR_S 2 -/* RMT_CH0_RX_END_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch0_tx_end_int_raw.*/ -#define RMT_CH0_RX_END_INT_CLR (BIT(1)) -#define RMT_CH0_RX_END_INT_CLR_M (BIT(1)) -#define RMT_CH0_RX_END_INT_CLR_V 0x1 -#define RMT_CH0_RX_END_INT_CLR_S 1 -/* RMT_CH0_TX_END_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rmt_ch0_rx_end_int_raw..*/ -#define RMT_CH0_TX_END_INT_CLR (BIT(0)) -#define RMT_CH0_TX_END_INT_CLR_M (BIT(0)) -#define RMT_CH0_TX_END_INT_CLR_V 0x1 -#define RMT_CH0_TX_END_INT_CLR_S 0 - -#define RMT_CH0CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00b0) -/* RMT_CARRIER_HIGH_CH0 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ -/*description: This register is used to configure carrier wave's high level value for channel0.*/ -#define RMT_CARRIER_HIGH_CH0 0x0000FFFF -#define RMT_CARRIER_HIGH_CH0_M ((RMT_CARRIER_HIGH_CH0_V)<<(RMT_CARRIER_HIGH_CH0_S)) -#define RMT_CARRIER_HIGH_CH0_V 0xFFFF -#define RMT_CARRIER_HIGH_CH0_S 16 -/* RMT_CARRIER_LOW_CH0 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ -/*description: This register is used to configure carrier wave's low level value for channel0.*/ -#define RMT_CARRIER_LOW_CH0 0x0000FFFF -#define RMT_CARRIER_LOW_CH0_M ((RMT_CARRIER_LOW_CH0_V)<<(RMT_CARRIER_LOW_CH0_S)) -#define RMT_CARRIER_LOW_CH0_V 0xFFFF -#define RMT_CARRIER_LOW_CH0_S 0 - -#define RMT_CH1CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00b4) -/* RMT_CARRIER_HIGH_CH1 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ -/*description: This register is used to configure carrier wave's high level value for channel1.*/ -#define RMT_CARRIER_HIGH_CH1 0x0000FFFF -#define RMT_CARRIER_HIGH_CH1_M ((RMT_CARRIER_HIGH_CH1_V)<<(RMT_CARRIER_HIGH_CH1_S)) -#define RMT_CARRIER_HIGH_CH1_V 0xFFFF -#define RMT_CARRIER_HIGH_CH1_S 16 -/* RMT_CARRIER_LOW_CH1 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ -/*description: This register is used to configure carrier wave's low level value for channel1.*/ -#define RMT_CARRIER_LOW_CH1 0x0000FFFF -#define RMT_CARRIER_LOW_CH1_M ((RMT_CARRIER_LOW_CH1_V)<<(RMT_CARRIER_LOW_CH1_S)) -#define RMT_CARRIER_LOW_CH1_V 0xFFFF -#define RMT_CARRIER_LOW_CH1_S 0 - -#define RMT_CH2CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00b8) -/* RMT_CARRIER_HIGH_CH2 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ -/*description: This register is used to configure carrier wave's high level value for channel2.*/ -#define RMT_CARRIER_HIGH_CH2 0x0000FFFF -#define RMT_CARRIER_HIGH_CH2_M ((RMT_CARRIER_HIGH_CH2_V)<<(RMT_CARRIER_HIGH_CH2_S)) -#define RMT_CARRIER_HIGH_CH2_V 0xFFFF -#define RMT_CARRIER_HIGH_CH2_S 16 -/* RMT_CARRIER_LOW_CH2 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ -/*description: This register is used to configure carrier wave's low level value for channel2.*/ -#define RMT_CARRIER_LOW_CH2 0x0000FFFF -#define RMT_CARRIER_LOW_CH2_M ((RMT_CARRIER_LOW_CH2_V)<<(RMT_CARRIER_LOW_CH2_S)) -#define RMT_CARRIER_LOW_CH2_V 0xFFFF -#define RMT_CARRIER_LOW_CH2_S 0 - -#define RMT_CH3CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00bc) -/* RMT_CARRIER_HIGH_CH3 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ -/*description: This register is used to configure carrier wave's high level value for channel3.*/ -#define RMT_CARRIER_HIGH_CH3 0x0000FFFF -#define RMT_CARRIER_HIGH_CH3_M ((RMT_CARRIER_HIGH_CH3_V)<<(RMT_CARRIER_HIGH_CH3_S)) -#define RMT_CARRIER_HIGH_CH3_V 0xFFFF -#define RMT_CARRIER_HIGH_CH3_S 16 -/* RMT_CARRIER_LOW_CH3 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ -/*description: This register is used to configure carrier wave's low level value for channel3.*/ -#define RMT_CARRIER_LOW_CH3 0x0000FFFF -#define RMT_CARRIER_LOW_CH3_M ((RMT_CARRIER_LOW_CH3_V)<<(RMT_CARRIER_LOW_CH3_S)) -#define RMT_CARRIER_LOW_CH3_V 0xFFFF -#define RMT_CARRIER_LOW_CH3_S 0 - -#define RMT_CH4CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00c0) -/* RMT_CARRIER_HIGH_CH4 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ -/*description: This register is used to configure carrier wave's high level value for channel4.*/ -#define RMT_CARRIER_HIGH_CH4 0x0000FFFF -#define RMT_CARRIER_HIGH_CH4_M ((RMT_CARRIER_HIGH_CH4_V)<<(RMT_CARRIER_HIGH_CH4_S)) -#define RMT_CARRIER_HIGH_CH4_V 0xFFFF -#define RMT_CARRIER_HIGH_CH4_S 16 -/* RMT_CARRIER_LOW_CH4 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ -/*description: This register is used to configure carrier wave's low level value for channel4.*/ -#define RMT_CARRIER_LOW_CH4 0x0000FFFF -#define RMT_CARRIER_LOW_CH4_M ((RMT_CARRIER_LOW_CH4_V)<<(RMT_CARRIER_LOW_CH4_S)) -#define RMT_CARRIER_LOW_CH4_V 0xFFFF -#define RMT_CARRIER_LOW_CH4_S 0 - -#define RMT_CH5CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00c4) -/* RMT_CARRIER_HIGH_CH5 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ -/*description: This register is used to configure carrier wave's high level value for channel5.*/ -#define RMT_CARRIER_HIGH_CH5 0x0000FFFF -#define RMT_CARRIER_HIGH_CH5_M ((RMT_CARRIER_HIGH_CH5_V)<<(RMT_CARRIER_HIGH_CH5_S)) -#define RMT_CARRIER_HIGH_CH5_V 0xFFFF -#define RMT_CARRIER_HIGH_CH5_S 16 -/* RMT_CARRIER_LOW_CH5 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ -/*description: This register is used to configure carrier wave's low level value for channel5.*/ -#define RMT_CARRIER_LOW_CH5 0x0000FFFF -#define RMT_CARRIER_LOW_CH5_M ((RMT_CARRIER_LOW_CH5_V)<<(RMT_CARRIER_LOW_CH5_S)) -#define RMT_CARRIER_LOW_CH5_V 0xFFFF -#define RMT_CARRIER_LOW_CH5_S 0 - -#define RMT_CH6CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00c8) -/* RMT_CARRIER_HIGH_CH6 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ -/*description: This register is used to configure carrier wave's high level value for channel6.*/ -#define RMT_CARRIER_HIGH_CH6 0x0000FFFF -#define RMT_CARRIER_HIGH_CH6_M ((RMT_CARRIER_HIGH_CH6_V)<<(RMT_CARRIER_HIGH_CH6_S)) -#define RMT_CARRIER_HIGH_CH6_V 0xFFFF -#define RMT_CARRIER_HIGH_CH6_S 16 -/* RMT_CARRIER_LOW_CH6 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ -/*description: This register is used to configure carrier wave's low level value for channel6.*/ -#define RMT_CARRIER_LOW_CH6 0x0000FFFF -#define RMT_CARRIER_LOW_CH6_M ((RMT_CARRIER_LOW_CH6_V)<<(RMT_CARRIER_LOW_CH6_S)) -#define RMT_CARRIER_LOW_CH6_V 0xFFFF -#define RMT_CARRIER_LOW_CH6_S 0 - -#define RMT_CH7CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00cc) -/* RMT_CARRIER_HIGH_CH7 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ -/*description: This register is used to configure carrier wave's high level value for channel7.*/ -#define RMT_CARRIER_HIGH_CH7 0x0000FFFF -#define RMT_CARRIER_HIGH_CH7_M ((RMT_CARRIER_HIGH_CH7_V)<<(RMT_CARRIER_HIGH_CH7_S)) -#define RMT_CARRIER_HIGH_CH7_V 0xFFFF -#define RMT_CARRIER_HIGH_CH7_S 16 -/* RMT_CARRIER_LOW_CH7 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ -/*description: This register is used to configure carrier wave's low level value for channel7.*/ -#define RMT_CARRIER_LOW_CH7 0x0000FFFF -#define RMT_CARRIER_LOW_CH7_M ((RMT_CARRIER_LOW_CH7_V)<<(RMT_CARRIER_LOW_CH7_S)) -#define RMT_CARRIER_LOW_CH7_V 0xFFFF -#define RMT_CARRIER_LOW_CH7_S 0 - -#define RMT_CH0_TX_LIM_REG (DR_REG_RMT_BASE + 0x00d0) -/* RMT_TX_LIM_CH0 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: When channel0 sends more than reg_rmt_tx_lim_ch0 datas then channel0 - produce the relative interrupt.*/ -#define RMT_TX_LIM_CH0 0x000001FF -#define RMT_TX_LIM_CH0_M ((RMT_TX_LIM_CH0_V)<<(RMT_TX_LIM_CH0_S)) -#define RMT_TX_LIM_CH0_V 0x1FF -#define RMT_TX_LIM_CH0_S 0 - -#define RMT_CH1_TX_LIM_REG (DR_REG_RMT_BASE + 0x00d4) -/* RMT_TX_LIM_CH1 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: When channel1 sends more than reg_rmt_tx_lim_ch1 datas then channel1 - produce the relative interrupt.*/ -#define RMT_TX_LIM_CH1 0x000001FF -#define RMT_TX_LIM_CH1_M ((RMT_TX_LIM_CH1_V)<<(RMT_TX_LIM_CH1_S)) -#define RMT_TX_LIM_CH1_V 0x1FF -#define RMT_TX_LIM_CH1_S 0 - -#define RMT_CH2_TX_LIM_REG (DR_REG_RMT_BASE + 0x00d8) -/* RMT_TX_LIM_CH2 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: When channel2 sends more than reg_rmt_tx_lim_ch2 datas then channel2 - produce the relative interrupt.*/ -#define RMT_TX_LIM_CH2 0x000001FF -#define RMT_TX_LIM_CH2_M ((RMT_TX_LIM_CH2_V)<<(RMT_TX_LIM_CH2_S)) -#define RMT_TX_LIM_CH2_V 0x1FF -#define RMT_TX_LIM_CH2_S 0 - -#define RMT_CH3_TX_LIM_REG (DR_REG_RMT_BASE + 0x00dc) -/* RMT_TX_LIM_CH3 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: When channel3 sends more than reg_rmt_tx_lim_ch3 datas then channel3 - produce the relative interrupt.*/ -#define RMT_TX_LIM_CH3 0x000001FF -#define RMT_TX_LIM_CH3_M ((RMT_TX_LIM_CH3_V)<<(RMT_TX_LIM_CH3_S)) -#define RMT_TX_LIM_CH3_V 0x1FF -#define RMT_TX_LIM_CH3_S 0 - -#define RMT_CH4_TX_LIM_REG (DR_REG_RMT_BASE + 0x00e0) -/* RMT_TX_LIM_CH4 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: When channel4 sends more than reg_rmt_tx_lim_ch4 datas then channel4 - produce the relative interrupt.*/ -#define RMT_TX_LIM_CH4 0x000001FF -#define RMT_TX_LIM_CH4_M ((RMT_TX_LIM_CH4_V)<<(RMT_TX_LIM_CH4_S)) -#define RMT_TX_LIM_CH4_V 0x1FF -#define RMT_TX_LIM_CH4_S 0 - -#define RMT_CH5_TX_LIM_REG (DR_REG_RMT_BASE + 0x00e4) -/* RMT_TX_LIM_CH5 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: When channel5 sends more than reg_rmt_tx_lim_ch5 datas then channel5 - produce the relative interrupt.*/ -#define RMT_TX_LIM_CH5 0x000001FF -#define RMT_TX_LIM_CH5_M ((RMT_TX_LIM_CH5_V)<<(RMT_TX_LIM_CH5_S)) -#define RMT_TX_LIM_CH5_V 0x1FF -#define RMT_TX_LIM_CH5_S 0 - -#define RMT_CH6_TX_LIM_REG (DR_REG_RMT_BASE + 0x00e8) -/* RMT_TX_LIM_CH6 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: When channel6 sends more than reg_rmt_tx_lim_ch6 datas then channel6 - produce the relative interrupt.*/ -#define RMT_TX_LIM_CH6 0x000001FF -#define RMT_TX_LIM_CH6_M ((RMT_TX_LIM_CH6_V)<<(RMT_TX_LIM_CH6_S)) -#define RMT_TX_LIM_CH6_V 0x1FF -#define RMT_TX_LIM_CH6_S 0 - -#define RMT_CH7_TX_LIM_REG (DR_REG_RMT_BASE + 0x00ec) -/* RMT_TX_LIM_CH7 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: When channel7 sends more than reg_rmt_tx_lim_ch7 datas then channel7 - produce the relative interrupt.*/ -#define RMT_TX_LIM_CH7 0x000001FF -#define RMT_TX_LIM_CH7_M ((RMT_TX_LIM_CH7_V)<<(RMT_TX_LIM_CH7_S)) -#define RMT_TX_LIM_CH7_V 0x1FF -#define RMT_TX_LIM_CH7_S 0 - -#define RMT_APB_CONF_REG (DR_REG_RMT_BASE + 0x00f0) -/* RMT_MEM_TX_WRAP_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: when datas need to be send is more than channel's mem can store - then set this bit to enable reusage of mem this bit is used together with reg_rmt_tx_lim_chn.*/ -#define RMT_MEM_TX_WRAP_EN (BIT(1)) -#define RMT_MEM_TX_WRAP_EN_M (BIT(1)) -#define RMT_MEM_TX_WRAP_EN_V 0x1 -#define RMT_MEM_TX_WRAP_EN_S 1 -/* RMT_APB_FIFO_MASK : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: Set this bit to disable apb fifo access*/ -#define RMT_APB_FIFO_MASK (BIT(0)) -#define RMT_APB_FIFO_MASK_M (BIT(0)) -#define RMT_APB_FIFO_MASK_V 0x1 -#define RMT_APB_FIFO_MASK_S 0 - -#define RMT_DATE_REG (DR_REG_RMT_BASE + 0x00fc) -/* RMT_DATE : R/W ;bitpos:[31:0] ;default: 32'h16022600 ; */ -/*description: This is the version register.*/ -#define RMT_DATE 0xFFFFFFFF -#define RMT_DATE_M ((RMT_DATE_V)<<(RMT_DATE_S)) -#define RMT_DATE_V 0xFFFFFFFF -#define RMT_DATE_S 0 - -/* RMT memory block address */ -#define RMT_CHANNEL_MEM(i) (DR_REG_RMT_BASE + 0x800 + 64 * 4 * (i)) - - -#endif /*_SOC_RMT_REG_H_ */ - - +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_RMT_REG_H_ +#define _SOC_RMT_REG_H_ + +#include "soc.h" +#define RMT_CH0DATA_REG (DR_REG_RMT_BASE + 0x0000) + +#define RMT_CH1DATA_REG (DR_REG_RMT_BASE + 0x0004) + +#define RMT_CH2DATA_REG (DR_REG_RMT_BASE + 0x0008) + +#define RMT_CH3DATA_REG (DR_REG_RMT_BASE + 0x000c) + +#define RMT_CH4DATA_REG (DR_REG_RMT_BASE + 0x0010) + +#define RMT_CH5DATA_REG (DR_REG_RMT_BASE + 0x0014) + +#define RMT_CH6DATA_REG (DR_REG_RMT_BASE + 0x0018) + +#define RMT_CH7DATA_REG (DR_REG_RMT_BASE + 0x001c) + +#define RMT_CH0CONF0_REG (DR_REG_RMT_BASE + 0x0020) +/* RMT_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: This bit is used to control clock.when software config RMT + internal registers it controls the register clock.*/ +#define RMT_CLK_EN (BIT(31)) +#define RMT_CLK_EN_M (BIT(31)) +#define RMT_CLK_EN_V 0x1 +#define RMT_CLK_EN_S 31 +/* RMT_MEM_PD : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: This bit is used to reduce power consumed by mem. 1:mem is in low power state.*/ +#define RMT_MEM_PD (BIT(30)) +#define RMT_MEM_PD_M (BIT(30)) +#define RMT_MEM_PD_V 0x1 +#define RMT_MEM_PD_S 30 +/* RMT_CARRIER_OUT_LV_CH0 : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: This bit is used to configure the way carrier wave is modulated + for channel0.1'b1:transmit on low output level 1'b0:transmit on high output level.*/ +#define RMT_CARRIER_OUT_LV_CH0 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH0_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH0_V 0x1 +#define RMT_CARRIER_OUT_LV_CH0_S 29 +/* RMT_CARRIER_EN_CH0 : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: This is the carrier modulation enable control bit for channel0.*/ +#define RMT_CARRIER_EN_CH0 (BIT(28)) +#define RMT_CARRIER_EN_CH0_M (BIT(28)) +#define RMT_CARRIER_EN_CH0_V 0x1 +#define RMT_CARRIER_EN_CH0_S 28 +/* RMT_MEM_SIZE_CH0 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ +/*description: This register is used to configure the the amount of memory blocks + allocated to channel0.*/ +#define RMT_MEM_SIZE_CH0 0x0000000F +#define RMT_MEM_SIZE_CH0_M ((RMT_MEM_SIZE_CH0_V)<<(RMT_MEM_SIZE_CH0_S)) +#define RMT_MEM_SIZE_CH0_V 0xF +#define RMT_MEM_SIZE_CH0_S 24 +/* RMT_IDLE_THRES_CH0 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ +/*description: In receive mode when no edge is detected on the input signal + for longer than reg_idle_thres_ch0 then the receive process is done.*/ +#define RMT_IDLE_THRES_CH0 0x0000FFFF +#define RMT_IDLE_THRES_CH0_M ((RMT_IDLE_THRES_CH0_V)<<(RMT_IDLE_THRES_CH0_S)) +#define RMT_IDLE_THRES_CH0_V 0xFFFF +#define RMT_IDLE_THRES_CH0_S 8 +/* RMT_DIV_CNT_CH0 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ +/*description: This register is used to configure the frequency divider's factor in channel0.*/ +#define RMT_DIV_CNT_CH0 0x000000FF +#define RMT_DIV_CNT_CH0_M ((RMT_DIV_CNT_CH0_V)<<(RMT_DIV_CNT_CH0_S)) +#define RMT_DIV_CNT_CH0_V 0xFF +#define RMT_DIV_CNT_CH0_S 0 + +#define RMT_CH0CONF1_REG (DR_REG_RMT_BASE + 0x0024) +/* RMT_IDLE_OUT_EN_CH0 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for channel0 in IDLE state.*/ +#define RMT_IDLE_OUT_EN_CH0 (BIT(19)) +#define RMT_IDLE_OUT_EN_CH0_M (BIT(19)) +#define RMT_IDLE_OUT_EN_CH0_V 0x1 +#define RMT_IDLE_OUT_EN_CH0_S 19 +/* RMT_IDLE_OUT_LV_CH0 : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This bit configures the output signal's level for channel0 in IDLE state.*/ +#define RMT_IDLE_OUT_LV_CH0 (BIT(18)) +#define RMT_IDLE_OUT_LV_CH0_M (BIT(18)) +#define RMT_IDLE_OUT_LV_CH0_V 0x1 +#define RMT_IDLE_OUT_LV_CH0_S 18 +/* RMT_REF_ALWAYS_ON_CH0 : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ +#define RMT_REF_ALWAYS_ON_CH0 (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH0_M (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH0_V 0x1 +#define RMT_REF_ALWAYS_ON_CH0_S 17 +/* RMT_REF_CNT_RST_CH0 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This bit is used to reset divider in channel0.*/ +#define RMT_REF_CNT_RST_CH0 (BIT(16)) +#define RMT_REF_CNT_RST_CH0_M (BIT(16)) +#define RMT_REF_CNT_RST_CH0_V 0x1 +#define RMT_REF_CNT_RST_CH0_S 16 +/* RMT_RX_FILTER_THRES_CH0 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ +/*description: in receive mode channel0 ignore input pulse when the pulse width + is smaller then this value.*/ +#define RMT_RX_FILTER_THRES_CH0 0x000000FF +#define RMT_RX_FILTER_THRES_CH0_M ((RMT_RX_FILTER_THRES_CH0_V)<<(RMT_RX_FILTER_THRES_CH0_S)) +#define RMT_RX_FILTER_THRES_CH0_V 0xFF +#define RMT_RX_FILTER_THRES_CH0_S 8 +/* RMT_RX_FILTER_EN_CH0 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the receive filter enable bit for channel0.*/ +#define RMT_RX_FILTER_EN_CH0 (BIT(7)) +#define RMT_RX_FILTER_EN_CH0_M (BIT(7)) +#define RMT_RX_FILTER_EN_CH0_V 0x1 +#define RMT_RX_FILTER_EN_CH0_S 7 +/* RMT_TX_CONTI_MODE_CH0 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to continue sending from the first data to the + last data in channel0 again and again.*/ +#define RMT_TX_CONTI_MODE_CH0 (BIT(6)) +#define RMT_TX_CONTI_MODE_CH0_M (BIT(6)) +#define RMT_TX_CONTI_MODE_CH0_V 0x1 +#define RMT_TX_CONTI_MODE_CH0_S 6 +/* RMT_MEM_OWNER_CH0 : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: This is the mark of channel0's ram usage right.1'b1：receiver + uses the ram 0：transmitter uses the ram*/ +#define RMT_MEM_OWNER_CH0 (BIT(5)) +#define RMT_MEM_OWNER_CH0_M (BIT(5)) +#define RMT_MEM_OWNER_CH0_V 0x1 +#define RMT_MEM_OWNER_CH0_S 5 +/* RMT_APB_MEM_RST_CH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to reset W/R ram address for channel0 by apb fifo access*/ +#define RMT_APB_MEM_RST_CH0 (BIT(4)) +#define RMT_APB_MEM_RST_CH0_M (BIT(4)) +#define RMT_APB_MEM_RST_CH0_V 0x1 +#define RMT_APB_MEM_RST_CH0_S 4 +/* RMT_MEM_RD_RST_CH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to reset read ram address for channel0 by transmitter access.*/ +#define RMT_MEM_RD_RST_CH0 (BIT(3)) +#define RMT_MEM_RD_RST_CH0_M (BIT(3)) +#define RMT_MEM_RD_RST_CH0_V 0x1 +#define RMT_MEM_RD_RST_CH0_S 3 +/* RMT_MEM_WR_RST_CH0 : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Set this bit to reset write ram address for channel0 by receiver access.*/ +#define RMT_MEM_WR_RST_CH0 (BIT(2)) +#define RMT_MEM_WR_RST_CH0_M (BIT(2)) +#define RMT_MEM_WR_RST_CH0_V 0x1 +#define RMT_MEM_WR_RST_CH0_S 2 +/* RMT_RX_EN_CH0 : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Set this bit to enbale receving data for channel0.*/ +#define RMT_RX_EN_CH0 (BIT(1)) +#define RMT_RX_EN_CH0_M (BIT(1)) +#define RMT_RX_EN_CH0_V 0x1 +#define RMT_RX_EN_CH0_S 1 +/* RMT_TX_START_CH0 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to start sending data for channel0.*/ +#define RMT_TX_START_CH0 (BIT(0)) +#define RMT_TX_START_CH0_M (BIT(0)) +#define RMT_TX_START_CH0_V 0x1 +#define RMT_TX_START_CH0_S 0 + +#define RMT_CH1CONF0_REG (DR_REG_RMT_BASE + 0x0028) +/* RMT_CARRIER_OUT_LV_CH1 : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: This bit is used to configure the way carrier wave is modulated + for channel1.1'b1:transmit on low output level 1'b0:transmit on high output level.*/ +#define RMT_CARRIER_OUT_LV_CH1 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH1_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH1_V 0x1 +#define RMT_CARRIER_OUT_LV_CH1_S 29 +/* RMT_CARRIER_EN_CH1 : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: This is the carrier modulation enable control bit for channel1.*/ +#define RMT_CARRIER_EN_CH1 (BIT(28)) +#define RMT_CARRIER_EN_CH1_M (BIT(28)) +#define RMT_CARRIER_EN_CH1_V 0x1 +#define RMT_CARRIER_EN_CH1_S 28 +/* RMT_MEM_SIZE_CH1 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ +/*description: This register is used to configure the the amount of memory blocks + allocated to channel1.*/ +#define RMT_MEM_SIZE_CH1 0x0000000F +#define RMT_MEM_SIZE_CH1_M ((RMT_MEM_SIZE_CH1_V)<<(RMT_MEM_SIZE_CH1_S)) +#define RMT_MEM_SIZE_CH1_V 0xF +#define RMT_MEM_SIZE_CH1_S 24 +/* RMT_IDLE_THRES_CH1 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ +/*description: This register is used to configure the the amount of memory blocks + allocated to channel1.*/ +#define RMT_IDLE_THRES_CH1 0x0000FFFF +#define RMT_IDLE_THRES_CH1_M ((RMT_IDLE_THRES_CH1_V)<<(RMT_IDLE_THRES_CH1_S)) +#define RMT_IDLE_THRES_CH1_V 0xFFFF +#define RMT_IDLE_THRES_CH1_S 8 +/* RMT_DIV_CNT_CH1 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ +/*description: This register is used to configure the frequency divider's factor in channel1.*/ +#define RMT_DIV_CNT_CH1 0x000000FF +#define RMT_DIV_CNT_CH1_M ((RMT_DIV_CNT_CH1_V)<<(RMT_DIV_CNT_CH1_S)) +#define RMT_DIV_CNT_CH1_V 0xFF +#define RMT_DIV_CNT_CH1_S 0 + +#define RMT_CH1CONF1_REG (DR_REG_RMT_BASE + 0x002c) +/* RMT_IDLE_OUT_EN_CH1 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for channel1 in IDLE state.*/ +#define RMT_IDLE_OUT_EN_CH1 (BIT(19)) +#define RMT_IDLE_OUT_EN_CH1_M (BIT(19)) +#define RMT_IDLE_OUT_EN_CH1_V 0x1 +#define RMT_IDLE_OUT_EN_CH1_S 19 +/* RMT_IDLE_OUT_LV_CH1 : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This bit configures the output signal's level for channel1 in IDLE state.*/ +#define RMT_IDLE_OUT_LV_CH1 (BIT(18)) +#define RMT_IDLE_OUT_LV_CH1_M (BIT(18)) +#define RMT_IDLE_OUT_LV_CH1_V 0x1 +#define RMT_IDLE_OUT_LV_CH1_S 18 +/* RMT_REF_ALWAYS_ON_CH1 : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ +#define RMT_REF_ALWAYS_ON_CH1 (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH1_M (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH1_V 0x1 +#define RMT_REF_ALWAYS_ON_CH1_S 17 +/* RMT_REF_CNT_RST_CH1 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This bit is used to reset divider in channel1.*/ +#define RMT_REF_CNT_RST_CH1 (BIT(16)) +#define RMT_REF_CNT_RST_CH1_M (BIT(16)) +#define RMT_REF_CNT_RST_CH1_V 0x1 +#define RMT_REF_CNT_RST_CH1_S 16 +/* RMT_RX_FILTER_THRES_CH1 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ +/*description: in receive mode channel1 ignore input pulse when the pulse width + is smaller then this value.*/ +#define RMT_RX_FILTER_THRES_CH1 0x000000FF +#define RMT_RX_FILTER_THRES_CH1_M ((RMT_RX_FILTER_THRES_CH1_V)<<(RMT_RX_FILTER_THRES_CH1_S)) +#define RMT_RX_FILTER_THRES_CH1_V 0xFF +#define RMT_RX_FILTER_THRES_CH1_S 8 +/* RMT_RX_FILTER_EN_CH1 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the receive filter enable bit for channel1.*/ +#define RMT_RX_FILTER_EN_CH1 (BIT(7)) +#define RMT_RX_FILTER_EN_CH1_M (BIT(7)) +#define RMT_RX_FILTER_EN_CH1_V 0x1 +#define RMT_RX_FILTER_EN_CH1_S 7 +/* RMT_TX_CONTI_MODE_CH1 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to continue sending from the first data to the + last data in channel1 again and again.*/ +#define RMT_TX_CONTI_MODE_CH1 (BIT(6)) +#define RMT_TX_CONTI_MODE_CH1_M (BIT(6)) +#define RMT_TX_CONTI_MODE_CH1_V 0x1 +#define RMT_TX_CONTI_MODE_CH1_S 6 +/* RMT_MEM_OWNER_CH1 : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: This is the mark of channel1's ram usage right.1'b1：receiver + uses the ram 0：transmitter uses the ram*/ +#define RMT_MEM_OWNER_CH1 (BIT(5)) +#define RMT_MEM_OWNER_CH1_M (BIT(5)) +#define RMT_MEM_OWNER_CH1_V 0x1 +#define RMT_MEM_OWNER_CH1_S 5 +/* RMT_APB_MEM_RST_CH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to reset W/R ram address for channel1 by apb fifo access*/ +#define RMT_APB_MEM_RST_CH1 (BIT(4)) +#define RMT_APB_MEM_RST_CH1_M (BIT(4)) +#define RMT_APB_MEM_RST_CH1_V 0x1 +#define RMT_APB_MEM_RST_CH1_S 4 +/* RMT_MEM_RD_RST_CH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to reset read ram address for channel1 by transmitter access.*/ +#define RMT_MEM_RD_RST_CH1 (BIT(3)) +#define RMT_MEM_RD_RST_CH1_M (BIT(3)) +#define RMT_MEM_RD_RST_CH1_V 0x1 +#define RMT_MEM_RD_RST_CH1_S 3 +/* RMT_MEM_WR_RST_CH1 : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Set this bit to reset write ram address for channel1 by receiver access.*/ +#define RMT_MEM_WR_RST_CH1 (BIT(2)) +#define RMT_MEM_WR_RST_CH1_M (BIT(2)) +#define RMT_MEM_WR_RST_CH1_V 0x1 +#define RMT_MEM_WR_RST_CH1_S 2 +/* RMT_RX_EN_CH1 : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Set this bit to enbale receving data for channel1.*/ +#define RMT_RX_EN_CH1 (BIT(1)) +#define RMT_RX_EN_CH1_M (BIT(1)) +#define RMT_RX_EN_CH1_V 0x1 +#define RMT_RX_EN_CH1_S 1 +/* RMT_TX_START_CH1 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to start sending data for channel1.*/ +#define RMT_TX_START_CH1 (BIT(0)) +#define RMT_TX_START_CH1_M (BIT(0)) +#define RMT_TX_START_CH1_V 0x1 +#define RMT_TX_START_CH1_S 0 + +#define RMT_CH2CONF0_REG (DR_REG_RMT_BASE + 0x0030) +/* RMT_CARRIER_OUT_LV_CH2 : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: This bit is used to configure carrier wave's position for channel2.1'b1:add + on low level 1'b0:add on high level.*/ +#define RMT_CARRIER_OUT_LV_CH2 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH2_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH2_V 0x1 +#define RMT_CARRIER_OUT_LV_CH2_S 29 +/* RMT_CARRIER_EN_CH2 : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: This is the carrier modulation enable control bit for channel2.*/ +#define RMT_CARRIER_EN_CH2 (BIT(28)) +#define RMT_CARRIER_EN_CH2_M (BIT(28)) +#define RMT_CARRIER_EN_CH2_V 0x1 +#define RMT_CARRIER_EN_CH2_S 28 +/* RMT_MEM_SIZE_CH2 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ +/*description: This register is used to configure the the amount of memory blocks + allocated to channel2.*/ +#define RMT_MEM_SIZE_CH2 0x0000000F +#define RMT_MEM_SIZE_CH2_M ((RMT_MEM_SIZE_CH2_V)<<(RMT_MEM_SIZE_CH2_S)) +#define RMT_MEM_SIZE_CH2_V 0xF +#define RMT_MEM_SIZE_CH2_S 24 +/* RMT_IDLE_THRES_CH2 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ +/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch2 + then the receive process is done.*/ +#define RMT_IDLE_THRES_CH2 0x0000FFFF +#define RMT_IDLE_THRES_CH2_M ((RMT_IDLE_THRES_CH2_V)<<(RMT_IDLE_THRES_CH2_S)) +#define RMT_IDLE_THRES_CH2_V 0xFFFF +#define RMT_IDLE_THRES_CH2_S 8 +/* RMT_DIV_CNT_CH2 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ +/*description: This register is used to configure the frequency divider's factor in channel2.*/ +#define RMT_DIV_CNT_CH2 0x000000FF +#define RMT_DIV_CNT_CH2_M ((RMT_DIV_CNT_CH2_V)<<(RMT_DIV_CNT_CH2_S)) +#define RMT_DIV_CNT_CH2_V 0xFF +#define RMT_DIV_CNT_CH2_S 0 + +#define RMT_CH2CONF1_REG (DR_REG_RMT_BASE + 0x0034) +/* RMT_IDLE_OUT_EN_CH2 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for channel2 in IDLE state.*/ +#define RMT_IDLE_OUT_EN_CH2 (BIT(19)) +#define RMT_IDLE_OUT_EN_CH2_M (BIT(19)) +#define RMT_IDLE_OUT_EN_CH2_V 0x1 +#define RMT_IDLE_OUT_EN_CH2_S 19 +/* RMT_IDLE_OUT_LV_CH2 : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This bit configures the output signal's level for channel2 in IDLE state.*/ +#define RMT_IDLE_OUT_LV_CH2 (BIT(18)) +#define RMT_IDLE_OUT_LV_CH2_M (BIT(18)) +#define RMT_IDLE_OUT_LV_CH2_V 0x1 +#define RMT_IDLE_OUT_LV_CH2_S 18 +/* RMT_REF_ALWAYS_ON_CH2 : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ +#define RMT_REF_ALWAYS_ON_CH2 (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH2_M (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH2_V 0x1 +#define RMT_REF_ALWAYS_ON_CH2_S 17 +/* RMT_REF_CNT_RST_CH2 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This bit is used to reset divider in channel2.*/ +#define RMT_REF_CNT_RST_CH2 (BIT(16)) +#define RMT_REF_CNT_RST_CH2_M (BIT(16)) +#define RMT_REF_CNT_RST_CH2_V 0x1 +#define RMT_REF_CNT_RST_CH2_S 16 +/* RMT_RX_FILTER_THRES_CH2 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ +/*description: in receive mode channel2 ignore input pulse when the pulse width + is smaller then this value.*/ +#define RMT_RX_FILTER_THRES_CH2 0x000000FF +#define RMT_RX_FILTER_THRES_CH2_M ((RMT_RX_FILTER_THRES_CH2_V)<<(RMT_RX_FILTER_THRES_CH2_S)) +#define RMT_RX_FILTER_THRES_CH2_V 0xFF +#define RMT_RX_FILTER_THRES_CH2_S 8 +/* RMT_RX_FILTER_EN_CH2 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the receive filter enable bit for channel2.*/ +#define RMT_RX_FILTER_EN_CH2 (BIT(7)) +#define RMT_RX_FILTER_EN_CH2_M (BIT(7)) +#define RMT_RX_FILTER_EN_CH2_V 0x1 +#define RMT_RX_FILTER_EN_CH2_S 7 +/* RMT_TX_CONTI_MODE_CH2 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to continue sending from the first data to the + last data in channel2.*/ +#define RMT_TX_CONTI_MODE_CH2 (BIT(6)) +#define RMT_TX_CONTI_MODE_CH2_M (BIT(6)) +#define RMT_TX_CONTI_MODE_CH2_V 0x1 +#define RMT_TX_CONTI_MODE_CH2_S 6 +/* RMT_MEM_OWNER_CH2 : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: This is the mark of channel2's ram usage right.1'b1：receiver + uses the ram 0：transmitter uses the ram*/ +#define RMT_MEM_OWNER_CH2 (BIT(5)) +#define RMT_MEM_OWNER_CH2_M (BIT(5)) +#define RMT_MEM_OWNER_CH2_V 0x1 +#define RMT_MEM_OWNER_CH2_S 5 +/* RMT_APB_MEM_RST_CH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to reset W/R ram address for channel2 by apb fifo access*/ +#define RMT_APB_MEM_RST_CH2 (BIT(4)) +#define RMT_APB_MEM_RST_CH2_M (BIT(4)) +#define RMT_APB_MEM_RST_CH2_V 0x1 +#define RMT_APB_MEM_RST_CH2_S 4 +/* RMT_MEM_RD_RST_CH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to reset read ram address for channel2 by transmitter access.*/ +#define RMT_MEM_RD_RST_CH2 (BIT(3)) +#define RMT_MEM_RD_RST_CH2_M (BIT(3)) +#define RMT_MEM_RD_RST_CH2_V 0x1 +#define RMT_MEM_RD_RST_CH2_S 3 +/* RMT_MEM_WR_RST_CH2 : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Set this bit to reset write ram address for channel2 by receiver access.*/ +#define RMT_MEM_WR_RST_CH2 (BIT(2)) +#define RMT_MEM_WR_RST_CH2_M (BIT(2)) +#define RMT_MEM_WR_RST_CH2_V 0x1 +#define RMT_MEM_WR_RST_CH2_S 2 +/* RMT_RX_EN_CH2 : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Set this bit to enbale receving data for channel2.*/ +#define RMT_RX_EN_CH2 (BIT(1)) +#define RMT_RX_EN_CH2_M (BIT(1)) +#define RMT_RX_EN_CH2_V 0x1 +#define RMT_RX_EN_CH2_S 1 +/* RMT_TX_START_CH2 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to start sending data for channel2.*/ +#define RMT_TX_START_CH2 (BIT(0)) +#define RMT_TX_START_CH2_M (BIT(0)) +#define RMT_TX_START_CH2_V 0x1 +#define RMT_TX_START_CH2_S 0 + +#define RMT_CH3CONF0_REG (DR_REG_RMT_BASE + 0x0038) +/* RMT_CARRIER_OUT_LV_CH3 : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: This bit is used to configure carrier wave's position for channel3.1'b1:add + on low level 1'b0:add on high level.*/ +#define RMT_CARRIER_OUT_LV_CH3 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH3_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH3_V 0x1 +#define RMT_CARRIER_OUT_LV_CH3_S 29 +/* RMT_CARRIER_EN_CH3 : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: This is the carrier modulation enable control bit for channel3.*/ +#define RMT_CARRIER_EN_CH3 (BIT(28)) +#define RMT_CARRIER_EN_CH3_M (BIT(28)) +#define RMT_CARRIER_EN_CH3_V 0x1 +#define RMT_CARRIER_EN_CH3_S 28 +/* RMT_MEM_SIZE_CH3 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ +/*description: This register is used to configure the the amount of memory blocks + allocated to channel3.*/ +#define RMT_MEM_SIZE_CH3 0x0000000F +#define RMT_MEM_SIZE_CH3_M ((RMT_MEM_SIZE_CH3_V)<<(RMT_MEM_SIZE_CH3_S)) +#define RMT_MEM_SIZE_CH3_V 0xF +#define RMT_MEM_SIZE_CH3_S 24 +/* RMT_IDLE_THRES_CH3 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ +/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch3 + then the receive process is done.*/ +#define RMT_IDLE_THRES_CH3 0x0000FFFF +#define RMT_IDLE_THRES_CH3_M ((RMT_IDLE_THRES_CH3_V)<<(RMT_IDLE_THRES_CH3_S)) +#define RMT_IDLE_THRES_CH3_V 0xFFFF +#define RMT_IDLE_THRES_CH3_S 8 +/* RMT_DIV_CNT_CH3 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ +/*description: This register is used to configure the frequency divider's factor in channel3.*/ +#define RMT_DIV_CNT_CH3 0x000000FF +#define RMT_DIV_CNT_CH3_M ((RMT_DIV_CNT_CH3_V)<<(RMT_DIV_CNT_CH3_S)) +#define RMT_DIV_CNT_CH3_V 0xFF +#define RMT_DIV_CNT_CH3_S 0 + +#define RMT_CH3CONF1_REG (DR_REG_RMT_BASE + 0x003c) +/* RMT_IDLE_OUT_EN_CH3 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for channel3 in IDLE state.*/ +#define RMT_IDLE_OUT_EN_CH3 (BIT(19)) +#define RMT_IDLE_OUT_EN_CH3_M (BIT(19)) +#define RMT_IDLE_OUT_EN_CH3_V 0x1 +#define RMT_IDLE_OUT_EN_CH3_S 19 +/* RMT_IDLE_OUT_LV_CH3 : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This bit configures the output signal's level for channel3 in IDLE state.*/ +#define RMT_IDLE_OUT_LV_CH3 (BIT(18)) +#define RMT_IDLE_OUT_LV_CH3_M (BIT(18)) +#define RMT_IDLE_OUT_LV_CH3_V 0x1 +#define RMT_IDLE_OUT_LV_CH3_S 18 +/* RMT_REF_ALWAYS_ON_CH3 : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ +#define RMT_REF_ALWAYS_ON_CH3 (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH3_M (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH3_V 0x1 +#define RMT_REF_ALWAYS_ON_CH3_S 17 +/* RMT_REF_CNT_RST_CH3 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This bit is used to reset divider in channel3.*/ +#define RMT_REF_CNT_RST_CH3 (BIT(16)) +#define RMT_REF_CNT_RST_CH3_M (BIT(16)) +#define RMT_REF_CNT_RST_CH3_V 0x1 +#define RMT_REF_CNT_RST_CH3_S 16 +/* RMT_RX_FILTER_THRES_CH3 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ +/*description: in receive mode channel3 ignore input pulse when the pulse width + is smaller then this value.*/ +#define RMT_RX_FILTER_THRES_CH3 0x000000FF +#define RMT_RX_FILTER_THRES_CH3_M ((RMT_RX_FILTER_THRES_CH3_V)<<(RMT_RX_FILTER_THRES_CH3_S)) +#define RMT_RX_FILTER_THRES_CH3_V 0xFF +#define RMT_RX_FILTER_THRES_CH3_S 8 +/* RMT_RX_FILTER_EN_CH3 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the receive filter enable bit for channel3.*/ +#define RMT_RX_FILTER_EN_CH3 (BIT(7)) +#define RMT_RX_FILTER_EN_CH3_M (BIT(7)) +#define RMT_RX_FILTER_EN_CH3_V 0x1 +#define RMT_RX_FILTER_EN_CH3_S 7 +/* RMT_TX_CONTI_MODE_CH3 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to continue sending from the first data to the + last data in channel3.*/ +#define RMT_TX_CONTI_MODE_CH3 (BIT(6)) +#define RMT_TX_CONTI_MODE_CH3_M (BIT(6)) +#define RMT_TX_CONTI_MODE_CH3_V 0x1 +#define RMT_TX_CONTI_MODE_CH3_S 6 +/* RMT_MEM_OWNER_CH3 : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: This is the mark of channel3's ram usage right.1'b1：receiver + uses the ram 0：transmitter uses the ram*/ +#define RMT_MEM_OWNER_CH3 (BIT(5)) +#define RMT_MEM_OWNER_CH3_M (BIT(5)) +#define RMT_MEM_OWNER_CH3_V 0x1 +#define RMT_MEM_OWNER_CH3_S 5 +/* RMT_APB_MEM_RST_CH3 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to reset W/R ram address for channel3 by apb fifo access*/ +#define RMT_APB_MEM_RST_CH3 (BIT(4)) +#define RMT_APB_MEM_RST_CH3_M (BIT(4)) +#define RMT_APB_MEM_RST_CH3_V 0x1 +#define RMT_APB_MEM_RST_CH3_S 4 +/* RMT_MEM_RD_RST_CH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to reset read ram address for channel3 by transmitter access.*/ +#define RMT_MEM_RD_RST_CH3 (BIT(3)) +#define RMT_MEM_RD_RST_CH3_M (BIT(3)) +#define RMT_MEM_RD_RST_CH3_V 0x1 +#define RMT_MEM_RD_RST_CH3_S 3 +/* RMT_MEM_WR_RST_CH3 : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Set this bit to reset write ram address for channel3 by receiver access.*/ +#define RMT_MEM_WR_RST_CH3 (BIT(2)) +#define RMT_MEM_WR_RST_CH3_M (BIT(2)) +#define RMT_MEM_WR_RST_CH3_V 0x1 +#define RMT_MEM_WR_RST_CH3_S 2 +/* RMT_RX_EN_CH3 : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Set this bit to enbale receving data for channel3.*/ +#define RMT_RX_EN_CH3 (BIT(1)) +#define RMT_RX_EN_CH3_M (BIT(1)) +#define RMT_RX_EN_CH3_V 0x1 +#define RMT_RX_EN_CH3_S 1 +/* RMT_TX_START_CH3 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to start sending data for channel3.*/ +#define RMT_TX_START_CH3 (BIT(0)) +#define RMT_TX_START_CH3_M (BIT(0)) +#define RMT_TX_START_CH3_V 0x1 +#define RMT_TX_START_CH3_S 0 + +#define RMT_CH4CONF0_REG (DR_REG_RMT_BASE + 0x0040) +/* RMT_CARRIER_OUT_LV_CH4 : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: This bit is used to configure carrier wave's position for channel4.1'b1:add + on low level 1'b0:add on high level.*/ +#define RMT_CARRIER_OUT_LV_CH4 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH4_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH4_V 0x1 +#define RMT_CARRIER_OUT_LV_CH4_S 29 +/* RMT_CARRIER_EN_CH4 : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: This is the carrier modulation enable control bit for channel4.*/ +#define RMT_CARRIER_EN_CH4 (BIT(28)) +#define RMT_CARRIER_EN_CH4_M (BIT(28)) +#define RMT_CARRIER_EN_CH4_V 0x1 +#define RMT_CARRIER_EN_CH4_S 28 +/* RMT_MEM_SIZE_CH4 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ +/*description: This register is used to configure the the amount of memory blocks + allocated to channel4.*/ +#define RMT_MEM_SIZE_CH4 0x0000000F +#define RMT_MEM_SIZE_CH4_M ((RMT_MEM_SIZE_CH4_V)<<(RMT_MEM_SIZE_CH4_S)) +#define RMT_MEM_SIZE_CH4_V 0xF +#define RMT_MEM_SIZE_CH4_S 24 +/* RMT_IDLE_THRES_CH4 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ +/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch4 + then the receive process is done.*/ +#define RMT_IDLE_THRES_CH4 0x0000FFFF +#define RMT_IDLE_THRES_CH4_M ((RMT_IDLE_THRES_CH4_V)<<(RMT_IDLE_THRES_CH4_S)) +#define RMT_IDLE_THRES_CH4_V 0xFFFF +#define RMT_IDLE_THRES_CH4_S 8 +/* RMT_DIV_CNT_CH4 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ +/*description: This register is used to configure the frequency divider's factor in channel4.*/ +#define RMT_DIV_CNT_CH4 0x000000FF +#define RMT_DIV_CNT_CH4_M ((RMT_DIV_CNT_CH4_V)<<(RMT_DIV_CNT_CH4_S)) +#define RMT_DIV_CNT_CH4_V 0xFF +#define RMT_DIV_CNT_CH4_S 0 + +#define RMT_CH4CONF1_REG (DR_REG_RMT_BASE + 0x0044) +/* RMT_IDLE_OUT_EN_CH4 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for channel4 in IDLE state.*/ +#define RMT_IDLE_OUT_EN_CH4 (BIT(19)) +#define RMT_IDLE_OUT_EN_CH4_M (BIT(19)) +#define RMT_IDLE_OUT_EN_CH4_V 0x1 +#define RMT_IDLE_OUT_EN_CH4_S 19 +/* RMT_IDLE_OUT_LV_CH4 : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This bit configures the output signal's level for channel4 in IDLE state.*/ +#define RMT_IDLE_OUT_LV_CH4 (BIT(18)) +#define RMT_IDLE_OUT_LV_CH4_M (BIT(18)) +#define RMT_IDLE_OUT_LV_CH4_V 0x1 +#define RMT_IDLE_OUT_LV_CH4_S 18 +/* RMT_REF_ALWAYS_ON_CH4 : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ +#define RMT_REF_ALWAYS_ON_CH4 (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH4_M (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH4_V 0x1 +#define RMT_REF_ALWAYS_ON_CH4_S 17 +/* RMT_REF_CNT_RST_CH4 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This bit is used to reset divider in channel4.*/ +#define RMT_REF_CNT_RST_CH4 (BIT(16)) +#define RMT_REF_CNT_RST_CH4_M (BIT(16)) +#define RMT_REF_CNT_RST_CH4_V 0x1 +#define RMT_REF_CNT_RST_CH4_S 16 +/* RMT_RX_FILTER_THRES_CH4 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ +/*description: in receive mode channel4 ignore input pulse when the pulse width + is smaller then this value.*/ +#define RMT_RX_FILTER_THRES_CH4 0x000000FF +#define RMT_RX_FILTER_THRES_CH4_M ((RMT_RX_FILTER_THRES_CH4_V)<<(RMT_RX_FILTER_THRES_CH4_S)) +#define RMT_RX_FILTER_THRES_CH4_V 0xFF +#define RMT_RX_FILTER_THRES_CH4_S 8 +/* RMT_RX_FILTER_EN_CH4 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the receive filter enable bit for channel4.*/ +#define RMT_RX_FILTER_EN_CH4 (BIT(7)) +#define RMT_RX_FILTER_EN_CH4_M (BIT(7)) +#define RMT_RX_FILTER_EN_CH4_V 0x1 +#define RMT_RX_FILTER_EN_CH4_S 7 +/* RMT_TX_CONTI_MODE_CH4 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to continue sending from the first data to the + last data in channel4.*/ +#define RMT_TX_CONTI_MODE_CH4 (BIT(6)) +#define RMT_TX_CONTI_MODE_CH4_M (BIT(6)) +#define RMT_TX_CONTI_MODE_CH4_V 0x1 +#define RMT_TX_CONTI_MODE_CH4_S 6 +/* RMT_MEM_OWNER_CH4 : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: This is the mark of channel4's ram usage right.1'b1：receiver + uses the ram 0：transmitter uses the ram*/ +#define RMT_MEM_OWNER_CH4 (BIT(5)) +#define RMT_MEM_OWNER_CH4_M (BIT(5)) +#define RMT_MEM_OWNER_CH4_V 0x1 +#define RMT_MEM_OWNER_CH4_S 5 +/* RMT_APB_MEM_RST_CH4 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to reset W/R ram address for channel4 by apb fifo access*/ +#define RMT_APB_MEM_RST_CH4 (BIT(4)) +#define RMT_APB_MEM_RST_CH4_M (BIT(4)) +#define RMT_APB_MEM_RST_CH4_V 0x1 +#define RMT_APB_MEM_RST_CH4_S 4 +/* RMT_MEM_RD_RST_CH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to reset read ram address for channel4 by transmitter access.*/ +#define RMT_MEM_RD_RST_CH4 (BIT(3)) +#define RMT_MEM_RD_RST_CH4_M (BIT(3)) +#define RMT_MEM_RD_RST_CH4_V 0x1 +#define RMT_MEM_RD_RST_CH4_S 3 +/* RMT_MEM_WR_RST_CH4 : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Set this bit to reset write ram address for channel4 by receiver access.*/ +#define RMT_MEM_WR_RST_CH4 (BIT(2)) +#define RMT_MEM_WR_RST_CH4_M (BIT(2)) +#define RMT_MEM_WR_RST_CH4_V 0x1 +#define RMT_MEM_WR_RST_CH4_S 2 +/* RMT_RX_EN_CH4 : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Set this bit to enbale receving data for channel4.*/ +#define RMT_RX_EN_CH4 (BIT(1)) +#define RMT_RX_EN_CH4_M (BIT(1)) +#define RMT_RX_EN_CH4_V 0x1 +#define RMT_RX_EN_CH4_S 1 +/* RMT_TX_START_CH4 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to start sending data for channel4.*/ +#define RMT_TX_START_CH4 (BIT(0)) +#define RMT_TX_START_CH4_M (BIT(0)) +#define RMT_TX_START_CH4_V 0x1 +#define RMT_TX_START_CH4_S 0 + +#define RMT_CH5CONF0_REG (DR_REG_RMT_BASE + 0x0048) +/* RMT_CARRIER_OUT_LV_CH5 : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: This bit is used to configure carrier wave's position for channel5.1'b1:add + on low level 1'b0:add on high level.*/ +#define RMT_CARRIER_OUT_LV_CH5 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH5_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH5_V 0x1 +#define RMT_CARRIER_OUT_LV_CH5_S 29 +/* RMT_CARRIER_EN_CH5 : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: This is the carrier modulation enable control bit for channel5.*/ +#define RMT_CARRIER_EN_CH5 (BIT(28)) +#define RMT_CARRIER_EN_CH5_M (BIT(28)) +#define RMT_CARRIER_EN_CH5_V 0x1 +#define RMT_CARRIER_EN_CH5_S 28 +/* RMT_MEM_SIZE_CH5 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ +/*description: This register is used to configure the the amount of memory blocks + allocated to channel5.*/ +#define RMT_MEM_SIZE_CH5 0x0000000F +#define RMT_MEM_SIZE_CH5_M ((RMT_MEM_SIZE_CH5_V)<<(RMT_MEM_SIZE_CH5_S)) +#define RMT_MEM_SIZE_CH5_V 0xF +#define RMT_MEM_SIZE_CH5_S 24 +/* RMT_IDLE_THRES_CH5 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ +/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch5 + then the receive process is done.*/ +#define RMT_IDLE_THRES_CH5 0x0000FFFF +#define RMT_IDLE_THRES_CH5_M ((RMT_IDLE_THRES_CH5_V)<<(RMT_IDLE_THRES_CH5_S)) +#define RMT_IDLE_THRES_CH5_V 0xFFFF +#define RMT_IDLE_THRES_CH5_S 8 +/* RMT_DIV_CNT_CH5 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ +/*description: This register is used to configure the frequency divider's factor in channel5.*/ +#define RMT_DIV_CNT_CH5 0x000000FF +#define RMT_DIV_CNT_CH5_M ((RMT_DIV_CNT_CH5_V)<<(RMT_DIV_CNT_CH5_S)) +#define RMT_DIV_CNT_CH5_V 0xFF +#define RMT_DIV_CNT_CH5_S 0 + +#define RMT_CH5CONF1_REG (DR_REG_RMT_BASE + 0x004c) +/* RMT_IDLE_OUT_EN_CH5 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for channel5 in IDLE state.*/ +#define RMT_IDLE_OUT_EN_CH5 (BIT(19)) +#define RMT_IDLE_OUT_EN_CH5_M (BIT(19)) +#define RMT_IDLE_OUT_EN_CH5_V 0x1 +#define RMT_IDLE_OUT_EN_CH5_S 19 +/* RMT_IDLE_OUT_LV_CH5 : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This bit configures the output signal's level for channel5 in IDLE state.*/ +#define RMT_IDLE_OUT_LV_CH5 (BIT(18)) +#define RMT_IDLE_OUT_LV_CH5_M (BIT(18)) +#define RMT_IDLE_OUT_LV_CH5_V 0x1 +#define RMT_IDLE_OUT_LV_CH5_S 18 +/* RMT_REF_ALWAYS_ON_CH5 : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ +#define RMT_REF_ALWAYS_ON_CH5 (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH5_M (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH5_V 0x1 +#define RMT_REF_ALWAYS_ON_CH5_S 17 +/* RMT_REF_CNT_RST_CH5 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This bit is used to reset divider in channel5.*/ +#define RMT_REF_CNT_RST_CH5 (BIT(16)) +#define RMT_REF_CNT_RST_CH5_M (BIT(16)) +#define RMT_REF_CNT_RST_CH5_V 0x1 +#define RMT_REF_CNT_RST_CH5_S 16 +/* RMT_RX_FILTER_THRES_CH5 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ +/*description: in receive mode channel5 ignore input pulse when the pulse width + is smaller then this value.*/ +#define RMT_RX_FILTER_THRES_CH5 0x000000FF +#define RMT_RX_FILTER_THRES_CH5_M ((RMT_RX_FILTER_THRES_CH5_V)<<(RMT_RX_FILTER_THRES_CH5_S)) +#define RMT_RX_FILTER_THRES_CH5_V 0xFF +#define RMT_RX_FILTER_THRES_CH5_S 8 +/* RMT_RX_FILTER_EN_CH5 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the receive filter enable bit for channel5.*/ +#define RMT_RX_FILTER_EN_CH5 (BIT(7)) +#define RMT_RX_FILTER_EN_CH5_M (BIT(7)) +#define RMT_RX_FILTER_EN_CH5_V 0x1 +#define RMT_RX_FILTER_EN_CH5_S 7 +/* RMT_TX_CONTI_MODE_CH5 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to continue sending from the first data to the + last data in channel5.*/ +#define RMT_TX_CONTI_MODE_CH5 (BIT(6)) +#define RMT_TX_CONTI_MODE_CH5_M (BIT(6)) +#define RMT_TX_CONTI_MODE_CH5_V 0x1 +#define RMT_TX_CONTI_MODE_CH5_S 6 +/* RMT_MEM_OWNER_CH5 : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: This is the mark of channel5's ram usage right.1'b1：receiver + uses the ram 0：transmitter uses the ram*/ +#define RMT_MEM_OWNER_CH5 (BIT(5)) +#define RMT_MEM_OWNER_CH5_M (BIT(5)) +#define RMT_MEM_OWNER_CH5_V 0x1 +#define RMT_MEM_OWNER_CH5_S 5 +/* RMT_APB_MEM_RST_CH5 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to reset W/R ram address for channel5 by apb fifo access*/ +#define RMT_APB_MEM_RST_CH5 (BIT(4)) +#define RMT_APB_MEM_RST_CH5_M (BIT(4)) +#define RMT_APB_MEM_RST_CH5_V 0x1 +#define RMT_APB_MEM_RST_CH5_S 4 +/* RMT_MEM_RD_RST_CH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to reset read ram address for channel5 by transmitter access.*/ +#define RMT_MEM_RD_RST_CH5 (BIT(3)) +#define RMT_MEM_RD_RST_CH5_M (BIT(3)) +#define RMT_MEM_RD_RST_CH5_V 0x1 +#define RMT_MEM_RD_RST_CH5_S 3 +/* RMT_MEM_WR_RST_CH5 : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Set this bit to reset write ram address for channel5 by receiver access.*/ +#define RMT_MEM_WR_RST_CH5 (BIT(2)) +#define RMT_MEM_WR_RST_CH5_M (BIT(2)) +#define RMT_MEM_WR_RST_CH5_V 0x1 +#define RMT_MEM_WR_RST_CH5_S 2 +/* RMT_RX_EN_CH5 : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Set this bit to enbale receving data for channel5.*/ +#define RMT_RX_EN_CH5 (BIT(1)) +#define RMT_RX_EN_CH5_M (BIT(1)) +#define RMT_RX_EN_CH5_V 0x1 +#define RMT_RX_EN_CH5_S 1 +/* RMT_TX_START_CH5 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to start sending data for channel5.*/ +#define RMT_TX_START_CH5 (BIT(0)) +#define RMT_TX_START_CH5_M (BIT(0)) +#define RMT_TX_START_CH5_V 0x1 +#define RMT_TX_START_CH5_S 0 + +#define RMT_CH6CONF0_REG (DR_REG_RMT_BASE + 0x0050) +/* RMT_CARRIER_OUT_LV_CH6 : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: This bit is used to configure carrier wave's position for channel6.1'b1:add + on low level 1'b0:add on high level.*/ +#define RMT_CARRIER_OUT_LV_CH6 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH6_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH6_V 0x1 +#define RMT_CARRIER_OUT_LV_CH6_S 29 +/* RMT_CARRIER_EN_CH6 : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: This is the carrier modulation enable control bit for channel6.*/ +#define RMT_CARRIER_EN_CH6 (BIT(28)) +#define RMT_CARRIER_EN_CH6_M (BIT(28)) +#define RMT_CARRIER_EN_CH6_V 0x1 +#define RMT_CARRIER_EN_CH6_S 28 +/* RMT_MEM_SIZE_CH6 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ +/*description: This register is used to configure the the amount of memory blocks + allocated to channel6.*/ +#define RMT_MEM_SIZE_CH6 0x0000000F +#define RMT_MEM_SIZE_CH6_M ((RMT_MEM_SIZE_CH6_V)<<(RMT_MEM_SIZE_CH6_S)) +#define RMT_MEM_SIZE_CH6_V 0xF +#define RMT_MEM_SIZE_CH6_S 24 +/* RMT_IDLE_THRES_CH6 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ +/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch6 + then the receive process is done.*/ +#define RMT_IDLE_THRES_CH6 0x0000FFFF +#define RMT_IDLE_THRES_CH6_M ((RMT_IDLE_THRES_CH6_V)<<(RMT_IDLE_THRES_CH6_S)) +#define RMT_IDLE_THRES_CH6_V 0xFFFF +#define RMT_IDLE_THRES_CH6_S 8 +/* RMT_DIV_CNT_CH6 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ +/*description: This register is used to configure the frequency divider's factor in channel6.*/ +#define RMT_DIV_CNT_CH6 0x000000FF +#define RMT_DIV_CNT_CH6_M ((RMT_DIV_CNT_CH6_V)<<(RMT_DIV_CNT_CH6_S)) +#define RMT_DIV_CNT_CH6_V 0xFF +#define RMT_DIV_CNT_CH6_S 0 + +#define RMT_CH6CONF1_REG (DR_REG_RMT_BASE + 0x0054) +/* RMT_IDLE_OUT_EN_CH6 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for channel6 in IDLE state.*/ +#define RMT_IDLE_OUT_EN_CH6 (BIT(19)) +#define RMT_IDLE_OUT_EN_CH6_M (BIT(19)) +#define RMT_IDLE_OUT_EN_CH6_V 0x1 +#define RMT_IDLE_OUT_EN_CH6_S 19 +/* RMT_IDLE_OUT_LV_CH6 : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This bit configures the output signal's level for channel6 in IDLE state.*/ +#define RMT_IDLE_OUT_LV_CH6 (BIT(18)) +#define RMT_IDLE_OUT_LV_CH6_M (BIT(18)) +#define RMT_IDLE_OUT_LV_CH6_V 0x1 +#define RMT_IDLE_OUT_LV_CH6_S 18 +/* RMT_REF_ALWAYS_ON_CH6 : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ +#define RMT_REF_ALWAYS_ON_CH6 (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH6_M (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH6_V 0x1 +#define RMT_REF_ALWAYS_ON_CH6_S 17 +/* RMT_REF_CNT_RST_CH6 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This bit is used to reset divider in channel6.*/ +#define RMT_REF_CNT_RST_CH6 (BIT(16)) +#define RMT_REF_CNT_RST_CH6_M (BIT(16)) +#define RMT_REF_CNT_RST_CH6_V 0x1 +#define RMT_REF_CNT_RST_CH6_S 16 +/* RMT_RX_FILTER_THRES_CH6 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ +/*description: in receive mode channel6 ignore input pulse when the pulse width + is smaller then this value.*/ +#define RMT_RX_FILTER_THRES_CH6 0x000000FF +#define RMT_RX_FILTER_THRES_CH6_M ((RMT_RX_FILTER_THRES_CH6_V)<<(RMT_RX_FILTER_THRES_CH6_S)) +#define RMT_RX_FILTER_THRES_CH6_V 0xFF +#define RMT_RX_FILTER_THRES_CH6_S 8 +/* RMT_RX_FILTER_EN_CH6 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the receive filter enable bit for channel6.*/ +#define RMT_RX_FILTER_EN_CH6 (BIT(7)) +#define RMT_RX_FILTER_EN_CH6_M (BIT(7)) +#define RMT_RX_FILTER_EN_CH6_V 0x1 +#define RMT_RX_FILTER_EN_CH6_S 7 +/* RMT_TX_CONTI_MODE_CH6 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to continue sending from the first data to the + last data in channel6.*/ +#define RMT_TX_CONTI_MODE_CH6 (BIT(6)) +#define RMT_TX_CONTI_MODE_CH6_M (BIT(6)) +#define RMT_TX_CONTI_MODE_CH6_V 0x1 +#define RMT_TX_CONTI_MODE_CH6_S 6 +/* RMT_MEM_OWNER_CH6 : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: This is the mark of channel6's ram usage right.1'b1：receiver + uses the ram 0：transmitter uses the ram*/ +#define RMT_MEM_OWNER_CH6 (BIT(5)) +#define RMT_MEM_OWNER_CH6_M (BIT(5)) +#define RMT_MEM_OWNER_CH6_V 0x1 +#define RMT_MEM_OWNER_CH6_S 5 +/* RMT_APB_MEM_RST_CH6 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to reset W/R ram address for channel6 by apb fifo access*/ +#define RMT_APB_MEM_RST_CH6 (BIT(4)) +#define RMT_APB_MEM_RST_CH6_M (BIT(4)) +#define RMT_APB_MEM_RST_CH6_V 0x1 +#define RMT_APB_MEM_RST_CH6_S 4 +/* RMT_MEM_RD_RST_CH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to reset read ram address for channel6 by transmitter access.*/ +#define RMT_MEM_RD_RST_CH6 (BIT(3)) +#define RMT_MEM_RD_RST_CH6_M (BIT(3)) +#define RMT_MEM_RD_RST_CH6_V 0x1 +#define RMT_MEM_RD_RST_CH6_S 3 +/* RMT_MEM_WR_RST_CH6 : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Set this bit to reset write ram address for channel6 by receiver access.*/ +#define RMT_MEM_WR_RST_CH6 (BIT(2)) +#define RMT_MEM_WR_RST_CH6_M (BIT(2)) +#define RMT_MEM_WR_RST_CH6_V 0x1 +#define RMT_MEM_WR_RST_CH6_S 2 +/* RMT_RX_EN_CH6 : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Set this bit to enbale receving data for channel6.*/ +#define RMT_RX_EN_CH6 (BIT(1)) +#define RMT_RX_EN_CH6_M (BIT(1)) +#define RMT_RX_EN_CH6_V 0x1 +#define RMT_RX_EN_CH6_S 1 +/* RMT_TX_START_CH6 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to start sending data for channel6.*/ +#define RMT_TX_START_CH6 (BIT(0)) +#define RMT_TX_START_CH6_M (BIT(0)) +#define RMT_TX_START_CH6_V 0x1 +#define RMT_TX_START_CH6_S 0 + +#define RMT_CH7CONF0_REG (DR_REG_RMT_BASE + 0x0058) +/* RMT_CARRIER_OUT_LV_CH7 : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: This bit is used to configure carrier wave's position for channel7.1'b1:add + on low level 1'b0:add on high level.*/ +#define RMT_CARRIER_OUT_LV_CH7 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH7_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH7_V 0x1 +#define RMT_CARRIER_OUT_LV_CH7_S 29 +/* RMT_CARRIER_EN_CH7 : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: This is the carrier modulation enable control bit for channel7.*/ +#define RMT_CARRIER_EN_CH7 (BIT(28)) +#define RMT_CARRIER_EN_CH7_M (BIT(28)) +#define RMT_CARRIER_EN_CH7_V 0x1 +#define RMT_CARRIER_EN_CH7_S 28 +/* RMT_MEM_SIZE_CH7 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ +/*description: This register is used to configure the the amount of memory blocks + allocated to channel7.*/ +#define RMT_MEM_SIZE_CH7 0x0000000F +#define RMT_MEM_SIZE_CH7_M ((RMT_MEM_SIZE_CH7_V)<<(RMT_MEM_SIZE_CH7_S)) +#define RMT_MEM_SIZE_CH7_V 0xF +#define RMT_MEM_SIZE_CH7_S 24 +/* RMT_IDLE_THRES_CH7 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */ +/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch7 + then the receive process is done.*/ +#define RMT_IDLE_THRES_CH7 0x0000FFFF +#define RMT_IDLE_THRES_CH7_M ((RMT_IDLE_THRES_CH7_V)<<(RMT_IDLE_THRES_CH7_S)) +#define RMT_IDLE_THRES_CH7_V 0xFFFF +#define RMT_IDLE_THRES_CH7_S 8 +/* RMT_DIV_CNT_CH7 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ +/*description: This register is used to configure the frequency divider's factor in channel7.*/ +#define RMT_DIV_CNT_CH7 0x000000FF +#define RMT_DIV_CNT_CH7_M ((RMT_DIV_CNT_CH7_V)<<(RMT_DIV_CNT_CH7_S)) +#define RMT_DIV_CNT_CH7_V 0xFF +#define RMT_DIV_CNT_CH7_S 0 + +#define RMT_CH7CONF1_REG (DR_REG_RMT_BASE + 0x005c) +/* RMT_IDLE_OUT_EN_CH7 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: This is the output enable control bit for channel6 in IDLE state.*/ +#define RMT_IDLE_OUT_EN_CH7 (BIT(19)) +#define RMT_IDLE_OUT_EN_CH7_M (BIT(19)) +#define RMT_IDLE_OUT_EN_CH7_V 0x1 +#define RMT_IDLE_OUT_EN_CH7_S 19 +/* RMT_IDLE_OUT_LV_CH7 : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This bit configures the output signal's level for channel7 in IDLE state.*/ +#define RMT_IDLE_OUT_LV_CH7 (BIT(18)) +#define RMT_IDLE_OUT_LV_CH7_M (BIT(18)) +#define RMT_IDLE_OUT_LV_CH7_V 0x1 +#define RMT_IDLE_OUT_LV_CH7_S 18 +/* RMT_REF_ALWAYS_ON_CH7 : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ +#define RMT_REF_ALWAYS_ON_CH7 (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH7_M (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH7_V 0x1 +#define RMT_REF_ALWAYS_ON_CH7_S 17 +/* RMT_REF_CNT_RST_CH7 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This bit is used to reset divider in channel7.*/ +#define RMT_REF_CNT_RST_CH7 (BIT(16)) +#define RMT_REF_CNT_RST_CH7_M (BIT(16)) +#define RMT_REF_CNT_RST_CH7_V 0x1 +#define RMT_REF_CNT_RST_CH7_S 16 +/* RMT_RX_FILTER_THRES_CH7 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ +/*description: in receive mode channel7 ignore input pulse when the pulse width + is smaller then this value.*/ +#define RMT_RX_FILTER_THRES_CH7 0x000000FF +#define RMT_RX_FILTER_THRES_CH7_M ((RMT_RX_FILTER_THRES_CH7_V)<<(RMT_RX_FILTER_THRES_CH7_S)) +#define RMT_RX_FILTER_THRES_CH7_V 0xFF +#define RMT_RX_FILTER_THRES_CH7_S 8 +/* RMT_RX_FILTER_EN_CH7 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the receive filter enable bit for channel7.*/ +#define RMT_RX_FILTER_EN_CH7 (BIT(7)) +#define RMT_RX_FILTER_EN_CH7_M (BIT(7)) +#define RMT_RX_FILTER_EN_CH7_V 0x1 +#define RMT_RX_FILTER_EN_CH7_S 7 +/* RMT_TX_CONTI_MODE_CH7 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to continue sending from the first data to the + last data in channel7.*/ +#define RMT_TX_CONTI_MODE_CH7 (BIT(6)) +#define RMT_TX_CONTI_MODE_CH7_M (BIT(6)) +#define RMT_TX_CONTI_MODE_CH7_V 0x1 +#define RMT_TX_CONTI_MODE_CH7_S 6 +/* RMT_MEM_OWNER_CH7 : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: This is the mark of channel7's ram usage right.1'b1：receiver + uses the ram 0：transmitter uses the ram*/ +#define RMT_MEM_OWNER_CH7 (BIT(5)) +#define RMT_MEM_OWNER_CH7_M (BIT(5)) +#define RMT_MEM_OWNER_CH7_V 0x1 +#define RMT_MEM_OWNER_CH7_S 5 +/* RMT_APB_MEM_RST_CH7 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to reset W/R ram address for channel7 by apb fifo access*/ +#define RMT_APB_MEM_RST_CH7 (BIT(4)) +#define RMT_APB_MEM_RST_CH7_M (BIT(4)) +#define RMT_APB_MEM_RST_CH7_V 0x1 +#define RMT_APB_MEM_RST_CH7_S 4 +/* RMT_MEM_RD_RST_CH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to reset read ram address for channel7 by transmitter access.*/ +#define RMT_MEM_RD_RST_CH7 (BIT(3)) +#define RMT_MEM_RD_RST_CH7_M (BIT(3)) +#define RMT_MEM_RD_RST_CH7_V 0x1 +#define RMT_MEM_RD_RST_CH7_S 3 +/* RMT_MEM_WR_RST_CH7 : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Set this bit to reset write ram address for channel7 by receiver access.*/ +#define RMT_MEM_WR_RST_CH7 (BIT(2)) +#define RMT_MEM_WR_RST_CH7_M (BIT(2)) +#define RMT_MEM_WR_RST_CH7_V 0x1 +#define RMT_MEM_WR_RST_CH7_S 2 +/* RMT_RX_EN_CH7 : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Set this bit to enbale receving data for channel7.*/ +#define RMT_RX_EN_CH7 (BIT(1)) +#define RMT_RX_EN_CH7_M (BIT(1)) +#define RMT_RX_EN_CH7_V 0x1 +#define RMT_RX_EN_CH7_S 1 +/* RMT_TX_START_CH7 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to start sending data for channel7.*/ +#define RMT_TX_START_CH7 (BIT(0)) +#define RMT_TX_START_CH7_M (BIT(0)) +#define RMT_TX_START_CH7_V 0x1 +#define RMT_TX_START_CH7_S 0 + +#define RMT_CH0STATUS_REG (DR_REG_RMT_BASE + 0x0060) +/* RMT_STATUS_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The status for channel0*/ +#define RMT_STATUS_CH0 0xFFFFFFFF +#define RMT_STATUS_CH0_M ((RMT_STATUS_CH0_V)<<(RMT_STATUS_CH0_S)) +#define RMT_STATUS_CH0_V 0xFFFFFFFF +#define RMT_STATUS_CH0_S 0 + +#define RMT_CH1STATUS_REG (DR_REG_RMT_BASE + 0x0064) +/* RMT_STATUS_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The status for channel1*/ +#define RMT_STATUS_CH1 0xFFFFFFFF +#define RMT_STATUS_CH1_M ((RMT_STATUS_CH1_V)<<(RMT_STATUS_CH1_S)) +#define RMT_STATUS_CH1_V 0xFFFFFFFF +#define RMT_STATUS_CH1_S 0 + +#define RMT_CH2STATUS_REG (DR_REG_RMT_BASE + 0x0068) +/* RMT_STATUS_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The status for channel2*/ +#define RMT_STATUS_CH2 0xFFFFFFFF +#define RMT_STATUS_CH2_M ((RMT_STATUS_CH2_V)<<(RMT_STATUS_CH2_S)) +#define RMT_STATUS_CH2_V 0xFFFFFFFF +#define RMT_STATUS_CH2_S 0 + +#define RMT_CH3STATUS_REG (DR_REG_RMT_BASE + 0x006c) +/* RMT_STATUS_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The status for channel3*/ +#define RMT_STATUS_CH3 0xFFFFFFFF +#define RMT_STATUS_CH3_M ((RMT_STATUS_CH3_V)<<(RMT_STATUS_CH3_S)) +#define RMT_STATUS_CH3_V 0xFFFFFFFF +#define RMT_STATUS_CH3_S 0 + +#define RMT_CH4STATUS_REG (DR_REG_RMT_BASE + 0x0070) +/* RMT_STATUS_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The status for channel4*/ +#define RMT_STATUS_CH4 0xFFFFFFFF +#define RMT_STATUS_CH4_M ((RMT_STATUS_CH4_V)<<(RMT_STATUS_CH4_S)) +#define RMT_STATUS_CH4_V 0xFFFFFFFF +#define RMT_STATUS_CH4_S 0 + +#define RMT_CH5STATUS_REG (DR_REG_RMT_BASE + 0x0074) +/* RMT_STATUS_CH5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The status for channel5*/ +#define RMT_STATUS_CH5 0xFFFFFFFF +#define RMT_STATUS_CH5_M ((RMT_STATUS_CH5_V)<<(RMT_STATUS_CH5_S)) +#define RMT_STATUS_CH5_V 0xFFFFFFFF +#define RMT_STATUS_CH5_S 0 + +#define RMT_CH6STATUS_REG (DR_REG_RMT_BASE + 0x0078) +/* RMT_STATUS_CH6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The status for channel6*/ +#define RMT_STATUS_CH6 0xFFFFFFFF +#define RMT_STATUS_CH6_M ((RMT_STATUS_CH6_V)<<(RMT_STATUS_CH6_S)) +#define RMT_STATUS_CH6_V 0xFFFFFFFF +#define RMT_STATUS_CH6_S 0 + +#define RMT_CH7STATUS_REG (DR_REG_RMT_BASE + 0x007c) +/* RMT_STATUS_CH7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The status for channel7*/ +#define RMT_STATUS_CH7 0xFFFFFFFF +#define RMT_STATUS_CH7_M ((RMT_STATUS_CH7_V)<<(RMT_STATUS_CH7_S)) +#define RMT_STATUS_CH7_V 0xFFFFFFFF +#define RMT_STATUS_CH7_S 0 + +#define RMT_CH0ADDR_REG (DR_REG_RMT_BASE + 0x0080) +/* RMT_APB_MEM_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The ram relative address in channel0 by apb fifo access*/ +#define RMT_APB_MEM_ADDR_CH0 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH0_M ((RMT_APB_MEM_ADDR_CH0_V)<<(RMT_APB_MEM_ADDR_CH0_S)) +#define RMT_APB_MEM_ADDR_CH0_V 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH0_S 0 + +#define RMT_CH1ADDR_REG (DR_REG_RMT_BASE + 0x0084) +/* RMT_APB_MEM_ADDR_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The ram relative address in channel1 by apb fifo access*/ +#define RMT_APB_MEM_ADDR_CH1 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH1_M ((RMT_APB_MEM_ADDR_CH1_V)<<(RMT_APB_MEM_ADDR_CH1_S)) +#define RMT_APB_MEM_ADDR_CH1_V 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH1_S 0 + +#define RMT_CH2ADDR_REG (DR_REG_RMT_BASE + 0x0088) +/* RMT_APB_MEM_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The ram relative address in channel2 by apb fifo access*/ +#define RMT_APB_MEM_ADDR_CH2 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH2_M ((RMT_APB_MEM_ADDR_CH2_V)<<(RMT_APB_MEM_ADDR_CH2_S)) +#define RMT_APB_MEM_ADDR_CH2_V 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH2_S 0 + +#define RMT_CH3ADDR_REG (DR_REG_RMT_BASE + 0x008c) +/* RMT_APB_MEM_ADDR_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The ram relative address in channel3 by apb fifo access*/ +#define RMT_APB_MEM_ADDR_CH3 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH3_M ((RMT_APB_MEM_ADDR_CH3_V)<<(RMT_APB_MEM_ADDR_CH3_S)) +#define RMT_APB_MEM_ADDR_CH3_V 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH3_S 0 + +#define RMT_CH4ADDR_REG (DR_REG_RMT_BASE + 0x0090) +/* RMT_APB_MEM_ADDR_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The ram relative address in channel4 by apb fifo access*/ +#define RMT_APB_MEM_ADDR_CH4 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH4_M ((RMT_APB_MEM_ADDR_CH4_V)<<(RMT_APB_MEM_ADDR_CH4_S)) +#define RMT_APB_MEM_ADDR_CH4_V 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH4_S 0 + +#define RMT_CH5ADDR_REG (DR_REG_RMT_BASE + 0x0094) +/* RMT_APB_MEM_ADDR_CH5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The ram relative address in channel5 by apb fifo access*/ +#define RMT_APB_MEM_ADDR_CH5 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH5_M ((RMT_APB_MEM_ADDR_CH5_V)<<(RMT_APB_MEM_ADDR_CH5_S)) +#define RMT_APB_MEM_ADDR_CH5_V 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH5_S 0 + +#define RMT_CH6ADDR_REG (DR_REG_RMT_BASE + 0x0098) +/* RMT_APB_MEM_ADDR_CH6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The ram relative address in channel6 by apb fifo access*/ +#define RMT_APB_MEM_ADDR_CH6 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH6_M ((RMT_APB_MEM_ADDR_CH6_V)<<(RMT_APB_MEM_ADDR_CH6_S)) +#define RMT_APB_MEM_ADDR_CH6_V 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH6_S 0 + +#define RMT_CH7ADDR_REG (DR_REG_RMT_BASE + 0x009c) +/* RMT_APB_MEM_ADDR_CH7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The ram relative address in channel7 by apb fifo access*/ +#define RMT_APB_MEM_ADDR_CH7 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH7_M ((RMT_APB_MEM_ADDR_CH7_V)<<(RMT_APB_MEM_ADDR_CH7_S)) +#define RMT_APB_MEM_ADDR_CH7_V 0xFFFFFFFF +#define RMT_APB_MEM_ADDR_CH7_S 0 + +#define RMT_INT_RAW_REG (DR_REG_RMT_BASE + 0x00a0) +/* RMT_CH7_TX_THR_EVENT_INT_RAW : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 7 turns to high level when + transmitter in channle7 have send datas more than reg_rmt_tx_lim_ch7 after detecting this interrupt software can updata the old datas with new datas.*/ +#define RMT_CH7_TX_THR_EVENT_INT_RAW (BIT(31)) +#define RMT_CH7_TX_THR_EVENT_INT_RAW_M (BIT(31)) +#define RMT_CH7_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH7_TX_THR_EVENT_INT_RAW_S 31 +/* RMT_CH6_TX_THR_EVENT_INT_RAW : RO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 6 turns to high level when + transmitter in channle6 have send datas more than reg_rmt_tx_lim_ch6 after detecting this interrupt software can updata the old datas with new datas.*/ +#define RMT_CH6_TX_THR_EVENT_INT_RAW (BIT(30)) +#define RMT_CH6_TX_THR_EVENT_INT_RAW_M (BIT(30)) +#define RMT_CH6_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH6_TX_THR_EVENT_INT_RAW_S 30 +/* RMT_CH5_TX_THR_EVENT_INT_RAW : RO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 5 turns to high level when + transmitter in channle5 have send datas more than reg_rmt_tx_lim_ch5 after detecting this interrupt software can updata the old datas with new datas.*/ +#define RMT_CH5_TX_THR_EVENT_INT_RAW (BIT(29)) +#define RMT_CH5_TX_THR_EVENT_INT_RAW_M (BIT(29)) +#define RMT_CH5_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH5_TX_THR_EVENT_INT_RAW_S 29 +/* RMT_CH4_TX_THR_EVENT_INT_RAW : RO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 4 turns to high level when + transmitter in channle4 have send datas more than reg_rmt_tx_lim_ch4 after detecting this interrupt software can updata the old datas with new datas.*/ +#define RMT_CH4_TX_THR_EVENT_INT_RAW (BIT(28)) +#define RMT_CH4_TX_THR_EVENT_INT_RAW_M (BIT(28)) +#define RMT_CH4_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH4_TX_THR_EVENT_INT_RAW_S 28 +/* RMT_CH3_TX_THR_EVENT_INT_RAW : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 3 turns to high level when + transmitter in channle3 have send datas more than reg_rmt_tx_lim_ch3 after detecting this interrupt software can updata the old datas with new datas.*/ +#define RMT_CH3_TX_THR_EVENT_INT_RAW (BIT(27)) +#define RMT_CH3_TX_THR_EVENT_INT_RAW_M (BIT(27)) +#define RMT_CH3_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH3_TX_THR_EVENT_INT_RAW_S 27 +/* RMT_CH2_TX_THR_EVENT_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 2 turns to high level when + transmitter in channle2 have send datas more than reg_rmt_tx_lim_ch2 after detecting this interrupt software can updata the old datas with new datas.*/ +#define RMT_CH2_TX_THR_EVENT_INT_RAW (BIT(26)) +#define RMT_CH2_TX_THR_EVENT_INT_RAW_M (BIT(26)) +#define RMT_CH2_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH2_TX_THR_EVENT_INT_RAW_S 26 +/* RMT_CH1_TX_THR_EVENT_INT_RAW : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 1 turns to high level when + transmitter in channle1 have send datas more than reg_rmt_tx_lim_ch1 after detecting this interrupt software can updata the old datas with new datas.*/ +#define RMT_CH1_TX_THR_EVENT_INT_RAW (BIT(25)) +#define RMT_CH1_TX_THR_EVENT_INT_RAW_M (BIT(25)) +#define RMT_CH1_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH1_TX_THR_EVENT_INT_RAW_S 25 +/* RMT_CH0_TX_THR_EVENT_INT_RAW : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 0 turns to high level when + transmitter in channle0 have send datas more than reg_rmt_tx_lim_ch0 after detecting this interrupt software can updata the old datas with new datas.*/ +#define RMT_CH0_TX_THR_EVENT_INT_RAW (BIT(24)) +#define RMT_CH0_TX_THR_EVENT_INT_RAW_M (BIT(24)) +#define RMT_CH0_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH0_TX_THR_EVENT_INT_RAW_S 24 +/* RMT_CH7_ERR_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 7 turns to high level when + channle 7 detects some errors.*/ +#define RMT_CH7_ERR_INT_RAW (BIT(23)) +#define RMT_CH7_ERR_INT_RAW_M (BIT(23)) +#define RMT_CH7_ERR_INT_RAW_V 0x1 +#define RMT_CH7_ERR_INT_RAW_S 23 +/* RMT_CH7_RX_END_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 7 turns to high level when + the receive process is done.*/ +#define RMT_CH7_RX_END_INT_RAW (BIT(22)) +#define RMT_CH7_RX_END_INT_RAW_M (BIT(22)) +#define RMT_CH7_RX_END_INT_RAW_V 0x1 +#define RMT_CH7_RX_END_INT_RAW_S 22 +/* RMT_CH7_TX_END_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 7 turns to high level when + the transmit process is done.*/ +#define RMT_CH7_TX_END_INT_RAW (BIT(21)) +#define RMT_CH7_TX_END_INT_RAW_M (BIT(21)) +#define RMT_CH7_TX_END_INT_RAW_V 0x1 +#define RMT_CH7_TX_END_INT_RAW_S 21 +/* RMT_CH6_ERR_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 6 turns to high level when + channle 6 detects some errors.*/ +#define RMT_CH6_ERR_INT_RAW (BIT(20)) +#define RMT_CH6_ERR_INT_RAW_M (BIT(20)) +#define RMT_CH6_ERR_INT_RAW_V 0x1 +#define RMT_CH6_ERR_INT_RAW_S 20 +/* RMT_CH6_RX_END_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 6 turns to high level when + the receive process is done.*/ +#define RMT_CH6_RX_END_INT_RAW (BIT(19)) +#define RMT_CH6_RX_END_INT_RAW_M (BIT(19)) +#define RMT_CH6_RX_END_INT_RAW_V 0x1 +#define RMT_CH6_RX_END_INT_RAW_S 19 +/* RMT_CH6_TX_END_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 6 turns to high level when + the transmit process is done.*/ +#define RMT_CH6_TX_END_INT_RAW (BIT(18)) +#define RMT_CH6_TX_END_INT_RAW_M (BIT(18)) +#define RMT_CH6_TX_END_INT_RAW_V 0x1 +#define RMT_CH6_TX_END_INT_RAW_S 18 +/* RMT_CH5_ERR_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 5 turns to high level when + channle 5 detects some errors.*/ +#define RMT_CH5_ERR_INT_RAW (BIT(17)) +#define RMT_CH5_ERR_INT_RAW_M (BIT(17)) +#define RMT_CH5_ERR_INT_RAW_V 0x1 +#define RMT_CH5_ERR_INT_RAW_S 17 +/* RMT_CH5_RX_END_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 5 turns to high level when + the receive process is done.*/ +#define RMT_CH5_RX_END_INT_RAW (BIT(16)) +#define RMT_CH5_RX_END_INT_RAW_M (BIT(16)) +#define RMT_CH5_RX_END_INT_RAW_V 0x1 +#define RMT_CH5_RX_END_INT_RAW_S 16 +/* RMT_CH5_TX_END_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 5 turns to high level when + the transmit process is done.*/ +#define RMT_CH5_TX_END_INT_RAW (BIT(15)) +#define RMT_CH5_TX_END_INT_RAW_M (BIT(15)) +#define RMT_CH5_TX_END_INT_RAW_V 0x1 +#define RMT_CH5_TX_END_INT_RAW_S 15 +/* RMT_CH4_ERR_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 4 turns to high level when + channle 4 detects some errors.*/ +#define RMT_CH4_ERR_INT_RAW (BIT(14)) +#define RMT_CH4_ERR_INT_RAW_M (BIT(14)) +#define RMT_CH4_ERR_INT_RAW_V 0x1 +#define RMT_CH4_ERR_INT_RAW_S 14 +/* RMT_CH4_RX_END_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 4 turns to high level when + the receive process is done.*/ +#define RMT_CH4_RX_END_INT_RAW (BIT(13)) +#define RMT_CH4_RX_END_INT_RAW_M (BIT(13)) +#define RMT_CH4_RX_END_INT_RAW_V 0x1 +#define RMT_CH4_RX_END_INT_RAW_S 13 +/* RMT_CH4_TX_END_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 4 turns to high level when + the transmit process is done.*/ +#define RMT_CH4_TX_END_INT_RAW (BIT(12)) +#define RMT_CH4_TX_END_INT_RAW_M (BIT(12)) +#define RMT_CH4_TX_END_INT_RAW_V 0x1 +#define RMT_CH4_TX_END_INT_RAW_S 12 +/* RMT_CH3_ERR_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 3 turns to high level when + channle 3 detects some errors.*/ +#define RMT_CH3_ERR_INT_RAW (BIT(11)) +#define RMT_CH3_ERR_INT_RAW_M (BIT(11)) +#define RMT_CH3_ERR_INT_RAW_V 0x1 +#define RMT_CH3_ERR_INT_RAW_S 11 +/* RMT_CH3_RX_END_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 3 turns to high level when + the receive process is done.*/ +#define RMT_CH3_RX_END_INT_RAW (BIT(10)) +#define RMT_CH3_RX_END_INT_RAW_M (BIT(10)) +#define RMT_CH3_RX_END_INT_RAW_V 0x1 +#define RMT_CH3_RX_END_INT_RAW_S 10 +/* RMT_CH3_TX_END_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 3 turns to high level when + the transmit process is done.*/ +#define RMT_CH3_TX_END_INT_RAW (BIT(9)) +#define RMT_CH3_TX_END_INT_RAW_M (BIT(9)) +#define RMT_CH3_TX_END_INT_RAW_V 0x1 +#define RMT_CH3_TX_END_INT_RAW_S 9 +/* RMT_CH2_ERR_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 2 turns to high level when + channle 2 detects some errors.*/ +#define RMT_CH2_ERR_INT_RAW (BIT(8)) +#define RMT_CH2_ERR_INT_RAW_M (BIT(8)) +#define RMT_CH2_ERR_INT_RAW_V 0x1 +#define RMT_CH2_ERR_INT_RAW_S 8 +/* RMT_CH2_RX_END_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 2 turns to high level when + the receive process is done.*/ +#define RMT_CH2_RX_END_INT_RAW (BIT(7)) +#define RMT_CH2_RX_END_INT_RAW_M (BIT(7)) +#define RMT_CH2_RX_END_INT_RAW_V 0x1 +#define RMT_CH2_RX_END_INT_RAW_S 7 +/* RMT_CH2_TX_END_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 2 turns to high level when + the transmit process is done.*/ +#define RMT_CH2_TX_END_INT_RAW (BIT(6)) +#define RMT_CH2_TX_END_INT_RAW_M (BIT(6)) +#define RMT_CH2_TX_END_INT_RAW_V 0x1 +#define RMT_CH2_TX_END_INT_RAW_S 6 +/* RMT_CH1_ERR_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 1 turns to high level when + channle 1 detects some errors.*/ +#define RMT_CH1_ERR_INT_RAW (BIT(5)) +#define RMT_CH1_ERR_INT_RAW_M (BIT(5)) +#define RMT_CH1_ERR_INT_RAW_V 0x1 +#define RMT_CH1_ERR_INT_RAW_S 5 +/* RMT_CH1_RX_END_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 1 turns to high level when + the receive process is done.*/ +#define RMT_CH1_RX_END_INT_RAW (BIT(4)) +#define RMT_CH1_RX_END_INT_RAW_M (BIT(4)) +#define RMT_CH1_RX_END_INT_RAW_V 0x1 +#define RMT_CH1_RX_END_INT_RAW_S 4 +/* RMT_CH1_TX_END_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 1 turns to high level when + the transmit process is done.*/ +#define RMT_CH1_TX_END_INT_RAW (BIT(3)) +#define RMT_CH1_TX_END_INT_RAW_M (BIT(3)) +#define RMT_CH1_TX_END_INT_RAW_V 0x1 +#define RMT_CH1_TX_END_INT_RAW_S 3 +/* RMT_CH0_ERR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 0 turns to high level when + channle 0 detects some errors.*/ +#define RMT_CH0_ERR_INT_RAW (BIT(2)) +#define RMT_CH0_ERR_INT_RAW_M (BIT(2)) +#define RMT_CH0_ERR_INT_RAW_V 0x1 +#define RMT_CH0_ERR_INT_RAW_S 2 +/* RMT_CH0_RX_END_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 0 turns to high level when + the receive process is done.*/ +#define RMT_CH0_RX_END_INT_RAW (BIT(1)) +#define RMT_CH0_RX_END_INT_RAW_M (BIT(1)) +#define RMT_CH0_RX_END_INT_RAW_V 0x1 +#define RMT_CH0_RX_END_INT_RAW_S 1 +/* RMT_CH0_TX_END_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for channel 0 turns to high level when + the transmit process is done.*/ +#define RMT_CH0_TX_END_INT_RAW (BIT(0)) +#define RMT_CH0_TX_END_INT_RAW_M (BIT(0)) +#define RMT_CH0_TX_END_INT_RAW_V 0x1 +#define RMT_CH0_TX_END_INT_RAW_S 0 + +#define RMT_INT_ST_REG (DR_REG_RMT_BASE + 0x00a4) +/* RMT_CH7_TX_THR_EVENT_INT_ST : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 7's rmt_ch7_tx_thr_event_int_raw + when mt_ch7_tx_thr_event_int_ena is set to 1.*/ +#define RMT_CH7_TX_THR_EVENT_INT_ST (BIT(31)) +#define RMT_CH7_TX_THR_EVENT_INT_ST_M (BIT(31)) +#define RMT_CH7_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH7_TX_THR_EVENT_INT_ST_S 31 +/* RMT_CH6_TX_THR_EVENT_INT_ST : RO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 6's rmt_ch6_tx_thr_event_int_raw + when mt_ch6_tx_thr_event_int_ena is set to 1.*/ +#define RMT_CH6_TX_THR_EVENT_INT_ST (BIT(30)) +#define RMT_CH6_TX_THR_EVENT_INT_ST_M (BIT(30)) +#define RMT_CH6_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH6_TX_THR_EVENT_INT_ST_S 30 +/* RMT_CH5_TX_THR_EVENT_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 5's rmt_ch5_tx_thr_event_int_raw + when mt_ch5_tx_thr_event_int_ena is set to 1.*/ +#define RMT_CH5_TX_THR_EVENT_INT_ST (BIT(29)) +#define RMT_CH5_TX_THR_EVENT_INT_ST_M (BIT(29)) +#define RMT_CH5_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH5_TX_THR_EVENT_INT_ST_S 29 +/* RMT_CH4_TX_THR_EVENT_INT_ST : RO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 4's rmt_ch4_tx_thr_event_int_raw + when mt_ch4_tx_thr_event_int_ena is set to 1.*/ +#define RMT_CH4_TX_THR_EVENT_INT_ST (BIT(28)) +#define RMT_CH4_TX_THR_EVENT_INT_ST_M (BIT(28)) +#define RMT_CH4_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH4_TX_THR_EVENT_INT_ST_S 28 +/* RMT_CH3_TX_THR_EVENT_INT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 3's rmt_ch3_tx_thr_event_int_raw + when mt_ch3_tx_thr_event_int_ena is set to 1.*/ +#define RMT_CH3_TX_THR_EVENT_INT_ST (BIT(27)) +#define RMT_CH3_TX_THR_EVENT_INT_ST_M (BIT(27)) +#define RMT_CH3_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH3_TX_THR_EVENT_INT_ST_S 27 +/* RMT_CH2_TX_THR_EVENT_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 2's rmt_ch2_tx_thr_event_int_raw + when mt_ch2_tx_thr_event_int_ena is set to 1.*/ +#define RMT_CH2_TX_THR_EVENT_INT_ST (BIT(26)) +#define RMT_CH2_TX_THR_EVENT_INT_ST_M (BIT(26)) +#define RMT_CH2_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH2_TX_THR_EVENT_INT_ST_S 26 +/* RMT_CH1_TX_THR_EVENT_INT_ST : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 1's rmt_ch1_tx_thr_event_int_raw + when mt_ch1_tx_thr_event_int_ena is set to 1.*/ +#define RMT_CH1_TX_THR_EVENT_INT_ST (BIT(25)) +#define RMT_CH1_TX_THR_EVENT_INT_ST_M (BIT(25)) +#define RMT_CH1_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH1_TX_THR_EVENT_INT_ST_S 25 +/* RMT_CH0_TX_THR_EVENT_INT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 0's rmt_ch0_tx_thr_event_int_raw + when mt_ch0_tx_thr_event_int_ena is set to 1.*/ +#define RMT_CH0_TX_THR_EVENT_INT_ST (BIT(24)) +#define RMT_CH0_TX_THR_EVENT_INT_ST_M (BIT(24)) +#define RMT_CH0_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH0_TX_THR_EVENT_INT_ST_S 24 +/* RMT_CH7_ERR_INT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 7's rmt_ch7_err_int_raw + when rmt_ch7_err_int_ena is set to 1.*/ +#define RMT_CH7_ERR_INT_ST (BIT(23)) +#define RMT_CH7_ERR_INT_ST_M (BIT(23)) +#define RMT_CH7_ERR_INT_ST_V 0x1 +#define RMT_CH7_ERR_INT_ST_S 23 +/* RMT_CH7_RX_END_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 7's rmt_ch7_rx_end_int_raw + when rmt_ch7_rx_end_int_ena is set to 1.*/ +#define RMT_CH7_RX_END_INT_ST (BIT(22)) +#define RMT_CH7_RX_END_INT_ST_M (BIT(22)) +#define RMT_CH7_RX_END_INT_ST_V 0x1 +#define RMT_CH7_RX_END_INT_ST_S 22 +/* RMT_CH7_TX_END_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 7's mt_ch7_tx_end_int_raw + when mt_ch7_tx_end_int_ena is set to 1.*/ +#define RMT_CH7_TX_END_INT_ST (BIT(21)) +#define RMT_CH7_TX_END_INT_ST_M (BIT(21)) +#define RMT_CH7_TX_END_INT_ST_V 0x1 +#define RMT_CH7_TX_END_INT_ST_S 21 +/* RMT_CH6_ERR_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 6's rmt_ch6_err_int_raw + when rmt_ch6_err_int_ena is set to 1.*/ +#define RMT_CH6_ERR_INT_ST (BIT(20)) +#define RMT_CH6_ERR_INT_ST_M (BIT(20)) +#define RMT_CH6_ERR_INT_ST_V 0x1 +#define RMT_CH6_ERR_INT_ST_S 20 +/* RMT_CH6_RX_END_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 6's rmt_ch6_rx_end_int_raw + when rmt_ch6_rx_end_int_ena is set to 1.*/ +#define RMT_CH6_RX_END_INT_ST (BIT(19)) +#define RMT_CH6_RX_END_INT_ST_M (BIT(19)) +#define RMT_CH6_RX_END_INT_ST_V 0x1 +#define RMT_CH6_RX_END_INT_ST_S 19 +/* RMT_CH6_TX_END_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 6's mt_ch6_tx_end_int_raw + when mt_ch6_tx_end_int_ena is set to 1.*/ +#define RMT_CH6_TX_END_INT_ST (BIT(18)) +#define RMT_CH6_TX_END_INT_ST_M (BIT(18)) +#define RMT_CH6_TX_END_INT_ST_V 0x1 +#define RMT_CH6_TX_END_INT_ST_S 18 +/* RMT_CH5_ERR_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 5's rmt_ch5_err_int_raw + when rmt_ch5_err_int_ena is set to 1.*/ +#define RMT_CH5_ERR_INT_ST (BIT(17)) +#define RMT_CH5_ERR_INT_ST_M (BIT(17)) +#define RMT_CH5_ERR_INT_ST_V 0x1 +#define RMT_CH5_ERR_INT_ST_S 17 +/* RMT_CH5_RX_END_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 5's rmt_ch5_rx_end_int_raw + when rmt_ch5_rx_end_int_ena is set to 1.*/ +#define RMT_CH5_RX_END_INT_ST (BIT(16)) +#define RMT_CH5_RX_END_INT_ST_M (BIT(16)) +#define RMT_CH5_RX_END_INT_ST_V 0x1 +#define RMT_CH5_RX_END_INT_ST_S 16 +/* RMT_CH5_TX_END_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 5's mt_ch5_tx_end_int_raw + when mt_ch5_tx_end_int_ena is set to 1.*/ +#define RMT_CH5_TX_END_INT_ST (BIT(15)) +#define RMT_CH5_TX_END_INT_ST_M (BIT(15)) +#define RMT_CH5_TX_END_INT_ST_V 0x1 +#define RMT_CH5_TX_END_INT_ST_S 15 +/* RMT_CH4_ERR_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 4's rmt_ch4_err_int_raw + when rmt_ch4_err_int_ena is set to 1.*/ +#define RMT_CH4_ERR_INT_ST (BIT(14)) +#define RMT_CH4_ERR_INT_ST_M (BIT(14)) +#define RMT_CH4_ERR_INT_ST_V 0x1 +#define RMT_CH4_ERR_INT_ST_S 14 +/* RMT_CH4_RX_END_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 4's rmt_ch4_rx_end_int_raw + when rmt_ch4_rx_end_int_ena is set to 1.*/ +#define RMT_CH4_RX_END_INT_ST (BIT(13)) +#define RMT_CH4_RX_END_INT_ST_M (BIT(13)) +#define RMT_CH4_RX_END_INT_ST_V 0x1 +#define RMT_CH4_RX_END_INT_ST_S 13 +/* RMT_CH4_TX_END_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 4's mt_ch4_tx_end_int_raw + when mt_ch4_tx_end_int_ena is set to 1.*/ +#define RMT_CH4_TX_END_INT_ST (BIT(12)) +#define RMT_CH4_TX_END_INT_ST_M (BIT(12)) +#define RMT_CH4_TX_END_INT_ST_V 0x1 +#define RMT_CH4_TX_END_INT_ST_S 12 +/* RMT_CH3_ERR_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 3's rmt_ch3_err_int_raw + when rmt_ch3_err_int_ena is set to 1.*/ +#define RMT_CH3_ERR_INT_ST (BIT(11)) +#define RMT_CH3_ERR_INT_ST_M (BIT(11)) +#define RMT_CH3_ERR_INT_ST_V 0x1 +#define RMT_CH3_ERR_INT_ST_S 11 +/* RMT_CH3_RX_END_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 3's rmt_ch3_rx_end_int_raw + when rmt_ch3_rx_end_int_ena is set to 1.*/ +#define RMT_CH3_RX_END_INT_ST (BIT(10)) +#define RMT_CH3_RX_END_INT_ST_M (BIT(10)) +#define RMT_CH3_RX_END_INT_ST_V 0x1 +#define RMT_CH3_RX_END_INT_ST_S 10 +/* RMT_CH3_TX_END_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 3's mt_ch3_tx_end_int_raw + when mt_ch3_tx_end_int_ena is set to 1.*/ +#define RMT_CH3_TX_END_INT_ST (BIT(9)) +#define RMT_CH3_TX_END_INT_ST_M (BIT(9)) +#define RMT_CH3_TX_END_INT_ST_V 0x1 +#define RMT_CH3_TX_END_INT_ST_S 9 +/* RMT_CH2_ERR_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 2's rmt_ch2_err_int_raw + when rmt_ch2_err_int_ena is set to 1.*/ +#define RMT_CH2_ERR_INT_ST (BIT(8)) +#define RMT_CH2_ERR_INT_ST_M (BIT(8)) +#define RMT_CH2_ERR_INT_ST_V 0x1 +#define RMT_CH2_ERR_INT_ST_S 8 +/* RMT_CH2_RX_END_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 2's rmt_ch2_rx_end_int_raw + when rmt_ch2_rx_end_int_ena is set to 1.*/ +#define RMT_CH2_RX_END_INT_ST (BIT(7)) +#define RMT_CH2_RX_END_INT_ST_M (BIT(7)) +#define RMT_CH2_RX_END_INT_ST_V 0x1 +#define RMT_CH2_RX_END_INT_ST_S 7 +/* RMT_CH2_TX_END_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 2's mt_ch2_tx_end_int_raw + when mt_ch2_tx_end_int_ena is set to 1.*/ +#define RMT_CH2_TX_END_INT_ST (BIT(6)) +#define RMT_CH2_TX_END_INT_ST_M (BIT(6)) +#define RMT_CH2_TX_END_INT_ST_V 0x1 +#define RMT_CH2_TX_END_INT_ST_S 6 +/* RMT_CH1_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 1's rmt_ch1_err_int_raw + when rmt_ch1_err_int_ena is set to 1.*/ +#define RMT_CH1_ERR_INT_ST (BIT(5)) +#define RMT_CH1_ERR_INT_ST_M (BIT(5)) +#define RMT_CH1_ERR_INT_ST_V 0x1 +#define RMT_CH1_ERR_INT_ST_S 5 +/* RMT_CH1_RX_END_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 1's rmt_ch1_rx_end_int_raw + when rmt_ch1_rx_end_int_ena is set to 1.*/ +#define RMT_CH1_RX_END_INT_ST (BIT(4)) +#define RMT_CH1_RX_END_INT_ST_M (BIT(4)) +#define RMT_CH1_RX_END_INT_ST_V 0x1 +#define RMT_CH1_RX_END_INT_ST_S 4 +/* RMT_CH1_TX_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 1's mt_ch1_tx_end_int_raw + when mt_ch1_tx_end_int_ena is set to 1.*/ +#define RMT_CH1_TX_END_INT_ST (BIT(3)) +#define RMT_CH1_TX_END_INT_ST_M (BIT(3)) +#define RMT_CH1_TX_END_INT_ST_V 0x1 +#define RMT_CH1_TX_END_INT_ST_S 3 +/* RMT_CH0_ERR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 0's rmt_ch0_err_int_raw + when rmt_ch0_err_int_ena is set to 0.*/ +#define RMT_CH0_ERR_INT_ST (BIT(2)) +#define RMT_CH0_ERR_INT_ST_M (BIT(2)) +#define RMT_CH0_ERR_INT_ST_V 0x1 +#define RMT_CH0_ERR_INT_ST_S 2 +/* RMT_CH0_RX_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 0's rmt_ch0_rx_end_int_raw + when rmt_ch0_rx_end_int_ena is set to 0.*/ +#define RMT_CH0_RX_END_INT_ST (BIT(1)) +#define RMT_CH0_RX_END_INT_ST_M (BIT(1)) +#define RMT_CH0_RX_END_INT_ST_V 0x1 +#define RMT_CH0_RX_END_INT_ST_S 1 +/* RMT_CH0_TX_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt state bit for channel 0's mt_ch0_tx_end_int_raw + when mt_ch0_tx_end_int_ena is set to 0.*/ +#define RMT_CH0_TX_END_INT_ST (BIT(0)) +#define RMT_CH0_TX_END_INT_ST_M (BIT(0)) +#define RMT_CH0_TX_END_INT_ST_V 0x1 +#define RMT_CH0_TX_END_INT_ST_S 0 + +#define RMT_INT_ENA_REG (DR_REG_RMT_BASE + 0x00a8) +/* RMT_CH7_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch7_tx_thr_event_int_st.*/ +#define RMT_CH7_TX_THR_EVENT_INT_ENA (BIT(31)) +#define RMT_CH7_TX_THR_EVENT_INT_ENA_M (BIT(31)) +#define RMT_CH7_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH7_TX_THR_EVENT_INT_ENA_S 31 +/* RMT_CH6_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch6_tx_thr_event_int_st.*/ +#define RMT_CH6_TX_THR_EVENT_INT_ENA (BIT(30)) +#define RMT_CH6_TX_THR_EVENT_INT_ENA_M (BIT(30)) +#define RMT_CH6_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH6_TX_THR_EVENT_INT_ENA_S 30 +/* RMT_CH5_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch5_tx_thr_event_int_st.*/ +#define RMT_CH5_TX_THR_EVENT_INT_ENA (BIT(29)) +#define RMT_CH5_TX_THR_EVENT_INT_ENA_M (BIT(29)) +#define RMT_CH5_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH5_TX_THR_EVENT_INT_ENA_S 29 +/* RMT_CH4_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch4_tx_thr_event_int_st.*/ +#define RMT_CH4_TX_THR_EVENT_INT_ENA (BIT(28)) +#define RMT_CH4_TX_THR_EVENT_INT_ENA_M (BIT(28)) +#define RMT_CH4_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH4_TX_THR_EVENT_INT_ENA_S 28 +/* RMT_CH3_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch3_tx_thr_event_int_st.*/ +#define RMT_CH3_TX_THR_EVENT_INT_ENA (BIT(27)) +#define RMT_CH3_TX_THR_EVENT_INT_ENA_M (BIT(27)) +#define RMT_CH3_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH3_TX_THR_EVENT_INT_ENA_S 27 +/* RMT_CH2_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch2_tx_thr_event_int_st.*/ +#define RMT_CH2_TX_THR_EVENT_INT_ENA (BIT(26)) +#define RMT_CH2_TX_THR_EVENT_INT_ENA_M (BIT(26)) +#define RMT_CH2_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH2_TX_THR_EVENT_INT_ENA_S 26 +/* RMT_CH1_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch1_tx_thr_event_int_st.*/ +#define RMT_CH1_TX_THR_EVENT_INT_ENA (BIT(25)) +#define RMT_CH1_TX_THR_EVENT_INT_ENA_M (BIT(25)) +#define RMT_CH1_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH1_TX_THR_EVENT_INT_ENA_S 25 +/* RMT_CH0_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch0_tx_thr_event_int_st.*/ +#define RMT_CH0_TX_THR_EVENT_INT_ENA (BIT(24)) +#define RMT_CH0_TX_THR_EVENT_INT_ENA_M (BIT(24)) +#define RMT_CH0_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH0_TX_THR_EVENT_INT_ENA_S 24 +/* RMT_CH7_ERR_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch7_err_int_st.*/ +#define RMT_CH7_ERR_INT_ENA (BIT(23)) +#define RMT_CH7_ERR_INT_ENA_M (BIT(23)) +#define RMT_CH7_ERR_INT_ENA_V 0x1 +#define RMT_CH7_ERR_INT_ENA_S 23 +/* RMT_CH7_RX_END_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch7_rx_end_int_st.*/ +#define RMT_CH7_RX_END_INT_ENA (BIT(22)) +#define RMT_CH7_RX_END_INT_ENA_M (BIT(22)) +#define RMT_CH7_RX_END_INT_ENA_V 0x1 +#define RMT_CH7_RX_END_INT_ENA_S 22 +/* RMT_CH7_TX_END_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch7_tx_end_int_st.*/ +#define RMT_CH7_TX_END_INT_ENA (BIT(21)) +#define RMT_CH7_TX_END_INT_ENA_M (BIT(21)) +#define RMT_CH7_TX_END_INT_ENA_V 0x1 +#define RMT_CH7_TX_END_INT_ENA_S 21 +/* RMT_CH6_ERR_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch6_err_int_st.*/ +#define RMT_CH6_ERR_INT_ENA (BIT(20)) +#define RMT_CH6_ERR_INT_ENA_M (BIT(20)) +#define RMT_CH6_ERR_INT_ENA_V 0x1 +#define RMT_CH6_ERR_INT_ENA_S 20 +/* RMT_CH6_RX_END_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch6_rx_end_int_st.*/ +#define RMT_CH6_RX_END_INT_ENA (BIT(19)) +#define RMT_CH6_RX_END_INT_ENA_M (BIT(19)) +#define RMT_CH6_RX_END_INT_ENA_V 0x1 +#define RMT_CH6_RX_END_INT_ENA_S 19 +/* RMT_CH6_TX_END_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch6_tx_end_int_st.*/ +#define RMT_CH6_TX_END_INT_ENA (BIT(18)) +#define RMT_CH6_TX_END_INT_ENA_M (BIT(18)) +#define RMT_CH6_TX_END_INT_ENA_V 0x1 +#define RMT_CH6_TX_END_INT_ENA_S 18 +/* RMT_CH5_ERR_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch5_err_int_st.*/ +#define RMT_CH5_ERR_INT_ENA (BIT(17)) +#define RMT_CH5_ERR_INT_ENA_M (BIT(17)) +#define RMT_CH5_ERR_INT_ENA_V 0x1 +#define RMT_CH5_ERR_INT_ENA_S 17 +/* RMT_CH5_RX_END_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch5_rx_end_int_st.*/ +#define RMT_CH5_RX_END_INT_ENA (BIT(16)) +#define RMT_CH5_RX_END_INT_ENA_M (BIT(16)) +#define RMT_CH5_RX_END_INT_ENA_V 0x1 +#define RMT_CH5_RX_END_INT_ENA_S 16 +/* RMT_CH5_TX_END_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch5_tx_end_int_st.*/ +#define RMT_CH5_TX_END_INT_ENA (BIT(15)) +#define RMT_CH5_TX_END_INT_ENA_M (BIT(15)) +#define RMT_CH5_TX_END_INT_ENA_V 0x1 +#define RMT_CH5_TX_END_INT_ENA_S 15 +/* RMT_CH4_ERR_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch4_err_int_st.*/ +#define RMT_CH4_ERR_INT_ENA (BIT(14)) +#define RMT_CH4_ERR_INT_ENA_M (BIT(14)) +#define RMT_CH4_ERR_INT_ENA_V 0x1 +#define RMT_CH4_ERR_INT_ENA_S 14 +/* RMT_CH4_RX_END_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch4_rx_end_int_st.*/ +#define RMT_CH4_RX_END_INT_ENA (BIT(13)) +#define RMT_CH4_RX_END_INT_ENA_M (BIT(13)) +#define RMT_CH4_RX_END_INT_ENA_V 0x1 +#define RMT_CH4_RX_END_INT_ENA_S 13 +/* RMT_CH4_TX_END_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch4_tx_end_int_st.*/ +#define RMT_CH4_TX_END_INT_ENA (BIT(12)) +#define RMT_CH4_TX_END_INT_ENA_M (BIT(12)) +#define RMT_CH4_TX_END_INT_ENA_V 0x1 +#define RMT_CH4_TX_END_INT_ENA_S 12 +/* RMT_CH3_ERR_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch3_err_int_st.*/ +#define RMT_CH3_ERR_INT_ENA (BIT(11)) +#define RMT_CH3_ERR_INT_ENA_M (BIT(11)) +#define RMT_CH3_ERR_INT_ENA_V 0x1 +#define RMT_CH3_ERR_INT_ENA_S 11 +/* RMT_CH3_RX_END_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch3_rx_end_int_st.*/ +#define RMT_CH3_RX_END_INT_ENA (BIT(10)) +#define RMT_CH3_RX_END_INT_ENA_M (BIT(10)) +#define RMT_CH3_RX_END_INT_ENA_V 0x1 +#define RMT_CH3_RX_END_INT_ENA_S 10 +/* RMT_CH3_TX_END_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch3_tx_end_int_st.*/ +#define RMT_CH3_TX_END_INT_ENA (BIT(9)) +#define RMT_CH3_TX_END_INT_ENA_M (BIT(9)) +#define RMT_CH3_TX_END_INT_ENA_V 0x1 +#define RMT_CH3_TX_END_INT_ENA_S 9 +/* RMT_CH2_ERR_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch2_err_int_st.*/ +#define RMT_CH2_ERR_INT_ENA (BIT(8)) +#define RMT_CH2_ERR_INT_ENA_M (BIT(8)) +#define RMT_CH2_ERR_INT_ENA_V 0x1 +#define RMT_CH2_ERR_INT_ENA_S 8 +/* RMT_CH2_RX_END_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch2_rx_end_int_st.*/ +#define RMT_CH2_RX_END_INT_ENA (BIT(7)) +#define RMT_CH2_RX_END_INT_ENA_M (BIT(7)) +#define RMT_CH2_RX_END_INT_ENA_V 0x1 +#define RMT_CH2_RX_END_INT_ENA_S 7 +/* RMT_CH2_TX_END_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch2_tx_end_int_st.*/ +#define RMT_CH2_TX_END_INT_ENA (BIT(6)) +#define RMT_CH2_TX_END_INT_ENA_M (BIT(6)) +#define RMT_CH2_TX_END_INT_ENA_V 0x1 +#define RMT_CH2_TX_END_INT_ENA_S 6 +/* RMT_CH1_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch1_err_int_st.*/ +#define RMT_CH1_ERR_INT_ENA (BIT(5)) +#define RMT_CH1_ERR_INT_ENA_M (BIT(5)) +#define RMT_CH1_ERR_INT_ENA_V 0x1 +#define RMT_CH1_ERR_INT_ENA_S 5 +/* RMT_CH1_RX_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch1_rx_end_int_st.*/ +#define RMT_CH1_RX_END_INT_ENA (BIT(4)) +#define RMT_CH1_RX_END_INT_ENA_M (BIT(4)) +#define RMT_CH1_RX_END_INT_ENA_V 0x1 +#define RMT_CH1_RX_END_INT_ENA_S 4 +/* RMT_CH1_TX_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch1_tx_end_int_st.*/ +#define RMT_CH1_TX_END_INT_ENA (BIT(3)) +#define RMT_CH1_TX_END_INT_ENA_M (BIT(3)) +#define RMT_CH1_TX_END_INT_ENA_V 0x1 +#define RMT_CH1_TX_END_INT_ENA_S 3 +/* RMT_CH0_ERR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch0_err_int_st.*/ +#define RMT_CH0_ERR_INT_ENA (BIT(2)) +#define RMT_CH0_ERR_INT_ENA_M (BIT(2)) +#define RMT_CH0_ERR_INT_ENA_V 0x1 +#define RMT_CH0_ERR_INT_ENA_S 2 +/* RMT_CH0_RX_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch0_rx_end_int_st.*/ +#define RMT_CH0_RX_END_INT_ENA (BIT(1)) +#define RMT_CH0_RX_END_INT_ENA_M (BIT(1)) +#define RMT_CH0_RX_END_INT_ENA_V 0x1 +#define RMT_CH0_RX_END_INT_ENA_S 1 +/* RMT_CH0_TX_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to enable rmt_ch0_tx_end_int_st.*/ +#define RMT_CH0_TX_END_INT_ENA (BIT(0)) +#define RMT_CH0_TX_END_INT_ENA_M (BIT(0)) +#define RMT_CH0_TX_END_INT_ENA_V 0x1 +#define RMT_CH0_TX_END_INT_ENA_S 0 + +#define RMT_INT_CLR_REG (DR_REG_RMT_BASE + 0x00ac) +/* RMT_CH7_TX_THR_EVENT_INT_CLR : WO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch7_tx_thr_event_int_raw interrupt.*/ +#define RMT_CH7_TX_THR_EVENT_INT_CLR (BIT(31)) +#define RMT_CH7_TX_THR_EVENT_INT_CLR_M (BIT(31)) +#define RMT_CH7_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH7_TX_THR_EVENT_INT_CLR_S 31 +/* RMT_CH6_TX_THR_EVENT_INT_CLR : WO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch6_tx_thr_event_int_raw interrupt.*/ +#define RMT_CH6_TX_THR_EVENT_INT_CLR (BIT(30)) +#define RMT_CH6_TX_THR_EVENT_INT_CLR_M (BIT(30)) +#define RMT_CH6_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH6_TX_THR_EVENT_INT_CLR_S 30 +/* RMT_CH5_TX_THR_EVENT_INT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch5_tx_thr_event_int_raw interrupt.*/ +#define RMT_CH5_TX_THR_EVENT_INT_CLR (BIT(29)) +#define RMT_CH5_TX_THR_EVENT_INT_CLR_M (BIT(29)) +#define RMT_CH5_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH5_TX_THR_EVENT_INT_CLR_S 29 +/* RMT_CH4_TX_THR_EVENT_INT_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch4_tx_thr_event_int_raw interrupt.*/ +#define RMT_CH4_TX_THR_EVENT_INT_CLR (BIT(28)) +#define RMT_CH4_TX_THR_EVENT_INT_CLR_M (BIT(28)) +#define RMT_CH4_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH4_TX_THR_EVENT_INT_CLR_S 28 +/* RMT_CH3_TX_THR_EVENT_INT_CLR : WO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch3_tx_thr_event_int_raw interrupt.*/ +#define RMT_CH3_TX_THR_EVENT_INT_CLR (BIT(27)) +#define RMT_CH3_TX_THR_EVENT_INT_CLR_M (BIT(27)) +#define RMT_CH3_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH3_TX_THR_EVENT_INT_CLR_S 27 +/* RMT_CH2_TX_THR_EVENT_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch2_tx_thr_event_int_raw interrupt.*/ +#define RMT_CH2_TX_THR_EVENT_INT_CLR (BIT(26)) +#define RMT_CH2_TX_THR_EVENT_INT_CLR_M (BIT(26)) +#define RMT_CH2_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH2_TX_THR_EVENT_INT_CLR_S 26 +/* RMT_CH1_TX_THR_EVENT_INT_CLR : WO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch1_tx_thr_event_int_raw interrupt.*/ +#define RMT_CH1_TX_THR_EVENT_INT_CLR (BIT(25)) +#define RMT_CH1_TX_THR_EVENT_INT_CLR_M (BIT(25)) +#define RMT_CH1_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH1_TX_THR_EVENT_INT_CLR_S 25 +/* RMT_CH0_TX_THR_EVENT_INT_CLR : WO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch0_tx_thr_event_int_raw interrupt.*/ +#define RMT_CH0_TX_THR_EVENT_INT_CLR (BIT(24)) +#define RMT_CH0_TX_THR_EVENT_INT_CLR_M (BIT(24)) +#define RMT_CH0_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH0_TX_THR_EVENT_INT_CLR_S 24 +/* RMT_CH7_ERR_INT_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch7_err_int_raw.*/ +#define RMT_CH7_ERR_INT_CLR (BIT(23)) +#define RMT_CH7_ERR_INT_CLR_M (BIT(23)) +#define RMT_CH7_ERR_INT_CLR_V 0x1 +#define RMT_CH7_ERR_INT_CLR_S 23 +/* RMT_CH7_RX_END_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch7_tx_end_int_raw.*/ +#define RMT_CH7_RX_END_INT_CLR (BIT(22)) +#define RMT_CH7_RX_END_INT_CLR_M (BIT(22)) +#define RMT_CH7_RX_END_INT_CLR_V 0x1 +#define RMT_CH7_RX_END_INT_CLR_S 22 +/* RMT_CH7_TX_END_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch7_rx_end_int_raw..*/ +#define RMT_CH7_TX_END_INT_CLR (BIT(21)) +#define RMT_CH7_TX_END_INT_CLR_M (BIT(21)) +#define RMT_CH7_TX_END_INT_CLR_V 0x1 +#define RMT_CH7_TX_END_INT_CLR_S 21 +/* RMT_CH6_ERR_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch6_err_int_raw.*/ +#define RMT_CH6_ERR_INT_CLR (BIT(20)) +#define RMT_CH6_ERR_INT_CLR_M (BIT(20)) +#define RMT_CH6_ERR_INT_CLR_V 0x1 +#define RMT_CH6_ERR_INT_CLR_S 20 +/* RMT_CH6_RX_END_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch6_tx_end_int_raw.*/ +#define RMT_CH6_RX_END_INT_CLR (BIT(19)) +#define RMT_CH6_RX_END_INT_CLR_M (BIT(19)) +#define RMT_CH6_RX_END_INT_CLR_V 0x1 +#define RMT_CH6_RX_END_INT_CLR_S 19 +/* RMT_CH6_TX_END_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch6_rx_end_int_raw..*/ +#define RMT_CH6_TX_END_INT_CLR (BIT(18)) +#define RMT_CH6_TX_END_INT_CLR_M (BIT(18)) +#define RMT_CH6_TX_END_INT_CLR_V 0x1 +#define RMT_CH6_TX_END_INT_CLR_S 18 +/* RMT_CH5_ERR_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch5_err_int_raw.*/ +#define RMT_CH5_ERR_INT_CLR (BIT(17)) +#define RMT_CH5_ERR_INT_CLR_M (BIT(17)) +#define RMT_CH5_ERR_INT_CLR_V 0x1 +#define RMT_CH5_ERR_INT_CLR_S 17 +/* RMT_CH5_RX_END_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch5_tx_end_int_raw.*/ +#define RMT_CH5_RX_END_INT_CLR (BIT(16)) +#define RMT_CH5_RX_END_INT_CLR_M (BIT(16)) +#define RMT_CH5_RX_END_INT_CLR_V 0x1 +#define RMT_CH5_RX_END_INT_CLR_S 16 +/* RMT_CH5_TX_END_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch5_rx_end_int_raw..*/ +#define RMT_CH5_TX_END_INT_CLR (BIT(15)) +#define RMT_CH5_TX_END_INT_CLR_M (BIT(15)) +#define RMT_CH5_TX_END_INT_CLR_V 0x1 +#define RMT_CH5_TX_END_INT_CLR_S 15 +/* RMT_CH4_ERR_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch4_err_int_raw.*/ +#define RMT_CH4_ERR_INT_CLR (BIT(14)) +#define RMT_CH4_ERR_INT_CLR_M (BIT(14)) +#define RMT_CH4_ERR_INT_CLR_V 0x1 +#define RMT_CH4_ERR_INT_CLR_S 14 +/* RMT_CH4_RX_END_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch4_tx_end_int_raw.*/ +#define RMT_CH4_RX_END_INT_CLR (BIT(13)) +#define RMT_CH4_RX_END_INT_CLR_M (BIT(13)) +#define RMT_CH4_RX_END_INT_CLR_V 0x1 +#define RMT_CH4_RX_END_INT_CLR_S 13 +/* RMT_CH4_TX_END_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch4_rx_end_int_raw..*/ +#define RMT_CH4_TX_END_INT_CLR (BIT(12)) +#define RMT_CH4_TX_END_INT_CLR_M (BIT(12)) +#define RMT_CH4_TX_END_INT_CLR_V 0x1 +#define RMT_CH4_TX_END_INT_CLR_S 12 +/* RMT_CH3_ERR_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch3_err_int_raw.*/ +#define RMT_CH3_ERR_INT_CLR (BIT(11)) +#define RMT_CH3_ERR_INT_CLR_M (BIT(11)) +#define RMT_CH3_ERR_INT_CLR_V 0x1 +#define RMT_CH3_ERR_INT_CLR_S 11 +/* RMT_CH3_RX_END_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch3_tx_end_int_raw.*/ +#define RMT_CH3_RX_END_INT_CLR (BIT(10)) +#define RMT_CH3_RX_END_INT_CLR_M (BIT(10)) +#define RMT_CH3_RX_END_INT_CLR_V 0x1 +#define RMT_CH3_RX_END_INT_CLR_S 10 +/* RMT_CH3_TX_END_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch3_rx_end_int_raw..*/ +#define RMT_CH3_TX_END_INT_CLR (BIT(9)) +#define RMT_CH3_TX_END_INT_CLR_M (BIT(9)) +#define RMT_CH3_TX_END_INT_CLR_V 0x1 +#define RMT_CH3_TX_END_INT_CLR_S 9 +/* RMT_CH2_ERR_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch2_err_int_raw.*/ +#define RMT_CH2_ERR_INT_CLR (BIT(8)) +#define RMT_CH2_ERR_INT_CLR_M (BIT(8)) +#define RMT_CH2_ERR_INT_CLR_V 0x1 +#define RMT_CH2_ERR_INT_CLR_S 8 +/* RMT_CH2_RX_END_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch2_tx_end_int_raw.*/ +#define RMT_CH2_RX_END_INT_CLR (BIT(7)) +#define RMT_CH2_RX_END_INT_CLR_M (BIT(7)) +#define RMT_CH2_RX_END_INT_CLR_V 0x1 +#define RMT_CH2_RX_END_INT_CLR_S 7 +/* RMT_CH2_TX_END_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch2_rx_end_int_raw..*/ +#define RMT_CH2_TX_END_INT_CLR (BIT(6)) +#define RMT_CH2_TX_END_INT_CLR_M (BIT(6)) +#define RMT_CH2_TX_END_INT_CLR_V 0x1 +#define RMT_CH2_TX_END_INT_CLR_S 6 +/* RMT_CH1_ERR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch1_err_int_raw.*/ +#define RMT_CH1_ERR_INT_CLR (BIT(5)) +#define RMT_CH1_ERR_INT_CLR_M (BIT(5)) +#define RMT_CH1_ERR_INT_CLR_V 0x1 +#define RMT_CH1_ERR_INT_CLR_S 5 +/* RMT_CH1_RX_END_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch1_tx_end_int_raw.*/ +#define RMT_CH1_RX_END_INT_CLR (BIT(4)) +#define RMT_CH1_RX_END_INT_CLR_M (BIT(4)) +#define RMT_CH1_RX_END_INT_CLR_V 0x1 +#define RMT_CH1_RX_END_INT_CLR_S 4 +/* RMT_CH1_TX_END_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch1_rx_end_int_raw..*/ +#define RMT_CH1_TX_END_INT_CLR (BIT(3)) +#define RMT_CH1_TX_END_INT_CLR_M (BIT(3)) +#define RMT_CH1_TX_END_INT_CLR_V 0x1 +#define RMT_CH1_TX_END_INT_CLR_S 3 +/* RMT_CH0_ERR_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch0_err_int_raw.*/ +#define RMT_CH0_ERR_INT_CLR (BIT(2)) +#define RMT_CH0_ERR_INT_CLR_M (BIT(2)) +#define RMT_CH0_ERR_INT_CLR_V 0x1 +#define RMT_CH0_ERR_INT_CLR_S 2 +/* RMT_CH0_RX_END_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch0_tx_end_int_raw.*/ +#define RMT_CH0_RX_END_INT_CLR (BIT(1)) +#define RMT_CH0_RX_END_INT_CLR_M (BIT(1)) +#define RMT_CH0_RX_END_INT_CLR_V 0x1 +#define RMT_CH0_RX_END_INT_CLR_S 1 +/* RMT_CH0_TX_END_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rmt_ch0_rx_end_int_raw..*/ +#define RMT_CH0_TX_END_INT_CLR (BIT(0)) +#define RMT_CH0_TX_END_INT_CLR_M (BIT(0)) +#define RMT_CH0_TX_END_INT_CLR_V 0x1 +#define RMT_CH0_TX_END_INT_CLR_S 0 + +#define RMT_CH0CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00b0) +/* RMT_CARRIER_HIGH_CH0 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's high level value for channel0.*/ +#define RMT_CARRIER_HIGH_CH0 0x0000FFFF +#define RMT_CARRIER_HIGH_CH0_M ((RMT_CARRIER_HIGH_CH0_V)<<(RMT_CARRIER_HIGH_CH0_S)) +#define RMT_CARRIER_HIGH_CH0_V 0xFFFF +#define RMT_CARRIER_HIGH_CH0_S 16 +/* RMT_CARRIER_LOW_CH0 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's low level value for channel0.*/ +#define RMT_CARRIER_LOW_CH0 0x0000FFFF +#define RMT_CARRIER_LOW_CH0_M ((RMT_CARRIER_LOW_CH0_V)<<(RMT_CARRIER_LOW_CH0_S)) +#define RMT_CARRIER_LOW_CH0_V 0xFFFF +#define RMT_CARRIER_LOW_CH0_S 0 + +#define RMT_CH1CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00b4) +/* RMT_CARRIER_HIGH_CH1 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's high level value for channel1.*/ +#define RMT_CARRIER_HIGH_CH1 0x0000FFFF +#define RMT_CARRIER_HIGH_CH1_M ((RMT_CARRIER_HIGH_CH1_V)<<(RMT_CARRIER_HIGH_CH1_S)) +#define RMT_CARRIER_HIGH_CH1_V 0xFFFF +#define RMT_CARRIER_HIGH_CH1_S 16 +/* RMT_CARRIER_LOW_CH1 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's low level value for channel1.*/ +#define RMT_CARRIER_LOW_CH1 0x0000FFFF +#define RMT_CARRIER_LOW_CH1_M ((RMT_CARRIER_LOW_CH1_V)<<(RMT_CARRIER_LOW_CH1_S)) +#define RMT_CARRIER_LOW_CH1_V 0xFFFF +#define RMT_CARRIER_LOW_CH1_S 0 + +#define RMT_CH2CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00b8) +/* RMT_CARRIER_HIGH_CH2 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's high level value for channel2.*/ +#define RMT_CARRIER_HIGH_CH2 0x0000FFFF +#define RMT_CARRIER_HIGH_CH2_M ((RMT_CARRIER_HIGH_CH2_V)<<(RMT_CARRIER_HIGH_CH2_S)) +#define RMT_CARRIER_HIGH_CH2_V 0xFFFF +#define RMT_CARRIER_HIGH_CH2_S 16 +/* RMT_CARRIER_LOW_CH2 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's low level value for channel2.*/ +#define RMT_CARRIER_LOW_CH2 0x0000FFFF +#define RMT_CARRIER_LOW_CH2_M ((RMT_CARRIER_LOW_CH2_V)<<(RMT_CARRIER_LOW_CH2_S)) +#define RMT_CARRIER_LOW_CH2_V 0xFFFF +#define RMT_CARRIER_LOW_CH2_S 0 + +#define RMT_CH3CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00bc) +/* RMT_CARRIER_HIGH_CH3 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's high level value for channel3.*/ +#define RMT_CARRIER_HIGH_CH3 0x0000FFFF +#define RMT_CARRIER_HIGH_CH3_M ((RMT_CARRIER_HIGH_CH3_V)<<(RMT_CARRIER_HIGH_CH3_S)) +#define RMT_CARRIER_HIGH_CH3_V 0xFFFF +#define RMT_CARRIER_HIGH_CH3_S 16 +/* RMT_CARRIER_LOW_CH3 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's low level value for channel3.*/ +#define RMT_CARRIER_LOW_CH3 0x0000FFFF +#define RMT_CARRIER_LOW_CH3_M ((RMT_CARRIER_LOW_CH3_V)<<(RMT_CARRIER_LOW_CH3_S)) +#define RMT_CARRIER_LOW_CH3_V 0xFFFF +#define RMT_CARRIER_LOW_CH3_S 0 + +#define RMT_CH4CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00c0) +/* RMT_CARRIER_HIGH_CH4 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's high level value for channel4.*/ +#define RMT_CARRIER_HIGH_CH4 0x0000FFFF +#define RMT_CARRIER_HIGH_CH4_M ((RMT_CARRIER_HIGH_CH4_V)<<(RMT_CARRIER_HIGH_CH4_S)) +#define RMT_CARRIER_HIGH_CH4_V 0xFFFF +#define RMT_CARRIER_HIGH_CH4_S 16 +/* RMT_CARRIER_LOW_CH4 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's low level value for channel4.*/ +#define RMT_CARRIER_LOW_CH4 0x0000FFFF +#define RMT_CARRIER_LOW_CH4_M ((RMT_CARRIER_LOW_CH4_V)<<(RMT_CARRIER_LOW_CH4_S)) +#define RMT_CARRIER_LOW_CH4_V 0xFFFF +#define RMT_CARRIER_LOW_CH4_S 0 + +#define RMT_CH5CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00c4) +/* RMT_CARRIER_HIGH_CH5 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's high level value for channel5.*/ +#define RMT_CARRIER_HIGH_CH5 0x0000FFFF +#define RMT_CARRIER_HIGH_CH5_M ((RMT_CARRIER_HIGH_CH5_V)<<(RMT_CARRIER_HIGH_CH5_S)) +#define RMT_CARRIER_HIGH_CH5_V 0xFFFF +#define RMT_CARRIER_HIGH_CH5_S 16 +/* RMT_CARRIER_LOW_CH5 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's low level value for channel5.*/ +#define RMT_CARRIER_LOW_CH5 0x0000FFFF +#define RMT_CARRIER_LOW_CH5_M ((RMT_CARRIER_LOW_CH5_V)<<(RMT_CARRIER_LOW_CH5_S)) +#define RMT_CARRIER_LOW_CH5_V 0xFFFF +#define RMT_CARRIER_LOW_CH5_S 0 + +#define RMT_CH6CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00c8) +/* RMT_CARRIER_HIGH_CH6 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's high level value for channel6.*/ +#define RMT_CARRIER_HIGH_CH6 0x0000FFFF +#define RMT_CARRIER_HIGH_CH6_M ((RMT_CARRIER_HIGH_CH6_V)<<(RMT_CARRIER_HIGH_CH6_S)) +#define RMT_CARRIER_HIGH_CH6_V 0xFFFF +#define RMT_CARRIER_HIGH_CH6_S 16 +/* RMT_CARRIER_LOW_CH6 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's low level value for channel6.*/ +#define RMT_CARRIER_LOW_CH6 0x0000FFFF +#define RMT_CARRIER_LOW_CH6_M ((RMT_CARRIER_LOW_CH6_V)<<(RMT_CARRIER_LOW_CH6_S)) +#define RMT_CARRIER_LOW_CH6_V 0xFFFF +#define RMT_CARRIER_LOW_CH6_S 0 + +#define RMT_CH7CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00cc) +/* RMT_CARRIER_HIGH_CH7 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's high level value for channel7.*/ +#define RMT_CARRIER_HIGH_CH7 0x0000FFFF +#define RMT_CARRIER_HIGH_CH7_M ((RMT_CARRIER_HIGH_CH7_V)<<(RMT_CARRIER_HIGH_CH7_S)) +#define RMT_CARRIER_HIGH_CH7_V 0xFFFF +#define RMT_CARRIER_HIGH_CH7_S 16 +/* RMT_CARRIER_LOW_CH7 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ +/*description: This register is used to configure carrier wave's low level value for channel7.*/ +#define RMT_CARRIER_LOW_CH7 0x0000FFFF +#define RMT_CARRIER_LOW_CH7_M ((RMT_CARRIER_LOW_CH7_V)<<(RMT_CARRIER_LOW_CH7_S)) +#define RMT_CARRIER_LOW_CH7_V 0xFFFF +#define RMT_CARRIER_LOW_CH7_S 0 + +#define RMT_CH0_TX_LIM_REG (DR_REG_RMT_BASE + 0x00d0) +/* RMT_TX_LIM_CH0 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: When channel0 sends more than reg_rmt_tx_lim_ch0 datas then channel0 + produce the relative interrupt.*/ +#define RMT_TX_LIM_CH0 0x000001FF +#define RMT_TX_LIM_CH0_M ((RMT_TX_LIM_CH0_V)<<(RMT_TX_LIM_CH0_S)) +#define RMT_TX_LIM_CH0_V 0x1FF +#define RMT_TX_LIM_CH0_S 0 + +#define RMT_CH1_TX_LIM_REG (DR_REG_RMT_BASE + 0x00d4) +/* RMT_TX_LIM_CH1 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: When channel1 sends more than reg_rmt_tx_lim_ch1 datas then channel1 + produce the relative interrupt.*/ +#define RMT_TX_LIM_CH1 0x000001FF +#define RMT_TX_LIM_CH1_M ((RMT_TX_LIM_CH1_V)<<(RMT_TX_LIM_CH1_S)) +#define RMT_TX_LIM_CH1_V 0x1FF +#define RMT_TX_LIM_CH1_S 0 + +#define RMT_CH2_TX_LIM_REG (DR_REG_RMT_BASE + 0x00d8) +/* RMT_TX_LIM_CH2 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: When channel2 sends more than reg_rmt_tx_lim_ch2 datas then channel2 + produce the relative interrupt.*/ +#define RMT_TX_LIM_CH2 0x000001FF +#define RMT_TX_LIM_CH2_M ((RMT_TX_LIM_CH2_V)<<(RMT_TX_LIM_CH2_S)) +#define RMT_TX_LIM_CH2_V 0x1FF +#define RMT_TX_LIM_CH2_S 0 + +#define RMT_CH3_TX_LIM_REG (DR_REG_RMT_BASE + 0x00dc) +/* RMT_TX_LIM_CH3 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: When channel3 sends more than reg_rmt_tx_lim_ch3 datas then channel3 + produce the relative interrupt.*/ +#define RMT_TX_LIM_CH3 0x000001FF +#define RMT_TX_LIM_CH3_M ((RMT_TX_LIM_CH3_V)<<(RMT_TX_LIM_CH3_S)) +#define RMT_TX_LIM_CH3_V 0x1FF +#define RMT_TX_LIM_CH3_S 0 + +#define RMT_CH4_TX_LIM_REG (DR_REG_RMT_BASE + 0x00e0) +/* RMT_TX_LIM_CH4 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: When channel4 sends more than reg_rmt_tx_lim_ch4 datas then channel4 + produce the relative interrupt.*/ +#define RMT_TX_LIM_CH4 0x000001FF +#define RMT_TX_LIM_CH4_M ((RMT_TX_LIM_CH4_V)<<(RMT_TX_LIM_CH4_S)) +#define RMT_TX_LIM_CH4_V 0x1FF +#define RMT_TX_LIM_CH4_S 0 + +#define RMT_CH5_TX_LIM_REG (DR_REG_RMT_BASE + 0x00e4) +/* RMT_TX_LIM_CH5 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: When channel5 sends more than reg_rmt_tx_lim_ch5 datas then channel5 + produce the relative interrupt.*/ +#define RMT_TX_LIM_CH5 0x000001FF +#define RMT_TX_LIM_CH5_M ((RMT_TX_LIM_CH5_V)<<(RMT_TX_LIM_CH5_S)) +#define RMT_TX_LIM_CH5_V 0x1FF +#define RMT_TX_LIM_CH5_S 0 + +#define RMT_CH6_TX_LIM_REG (DR_REG_RMT_BASE + 0x00e8) +/* RMT_TX_LIM_CH6 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: When channel6 sends more than reg_rmt_tx_lim_ch6 datas then channel6 + produce the relative interrupt.*/ +#define RMT_TX_LIM_CH6 0x000001FF +#define RMT_TX_LIM_CH6_M ((RMT_TX_LIM_CH6_V)<<(RMT_TX_LIM_CH6_S)) +#define RMT_TX_LIM_CH6_V 0x1FF +#define RMT_TX_LIM_CH6_S 0 + +#define RMT_CH7_TX_LIM_REG (DR_REG_RMT_BASE + 0x00ec) +/* RMT_TX_LIM_CH7 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: When channel7 sends more than reg_rmt_tx_lim_ch7 datas then channel7 + produce the relative interrupt.*/ +#define RMT_TX_LIM_CH7 0x000001FF +#define RMT_TX_LIM_CH7_M ((RMT_TX_LIM_CH7_V)<<(RMT_TX_LIM_CH7_S)) +#define RMT_TX_LIM_CH7_V 0x1FF +#define RMT_TX_LIM_CH7_S 0 + +#define RMT_APB_CONF_REG (DR_REG_RMT_BASE + 0x00f0) +/* RMT_MEM_TX_WRAP_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: when datas need to be send is more than channel's mem can store + then set this bit to enable reusage of mem this bit is used together with reg_rmt_tx_lim_chn.*/ +#define RMT_MEM_TX_WRAP_EN (BIT(1)) +#define RMT_MEM_TX_WRAP_EN_M (BIT(1)) +#define RMT_MEM_TX_WRAP_EN_V 0x1 +#define RMT_MEM_TX_WRAP_EN_S 1 +/* RMT_APB_FIFO_MASK : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to disable apb fifo access*/ +#define RMT_APB_FIFO_MASK (BIT(0)) +#define RMT_APB_FIFO_MASK_M (BIT(0)) +#define RMT_APB_FIFO_MASK_V 0x1 +#define RMT_APB_FIFO_MASK_S 0 + +#define RMT_DATE_REG (DR_REG_RMT_BASE + 0x00fc) +/* RMT_DATE : R/W ;bitpos:[31:0] ;default: 32'h16022600 ; */ +/*description: This is the version register.*/ +#define RMT_DATE 0xFFFFFFFF +#define RMT_DATE_M ((RMT_DATE_V)<<(RMT_DATE_S)) +#define RMT_DATE_V 0xFFFFFFFF +#define RMT_DATE_S 0 + +/* RMT memory block address */ +#define RMT_CHANNEL_MEM(i) (DR_REG_RMT_BASE + 0x800 + 64 * 4 * (i)) + + +#endif /*_SOC_RMT_REG_H_ */ + + diff --git a/components/soc/esp32/include/soc/rtc_io_reg.h b/components/soc/esp32/include/soc/rtc_io_reg.h index 345bb8045..086e8b767 100644 --- a/components/soc/esp32/include/soc/rtc_io_reg.h +++ b/components/soc/esp32/include/soc/rtc_io_reg.h @@ -1,1951 +1,1951 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_RTC_IO_REG_H_ -#define _SOC_RTC_IO_REG_H_ - - -#include "soc.h" -#define RTC_GPIO_OUT_REG (DR_REG_RTCIO_BASE + 0x0) -/* RTC_GPIO_OUT_DATA : R/W ;bitpos:[31:14] ;default: 0 ; */ -/*description: GPIO0~17 output value*/ -#define RTC_GPIO_OUT_DATA 0x0003FFFF -#define RTC_GPIO_OUT_DATA_M ((RTC_GPIO_OUT_DATA_V)<<(RTC_GPIO_OUT_DATA_S)) -#define RTC_GPIO_OUT_DATA_V 0x3FFFF -#define RTC_GPIO_OUT_DATA_S 14 - -#define RTC_GPIO_OUT_W1TS_REG (DR_REG_RTCIO_BASE + 0x4) -/* RTC_GPIO_OUT_DATA_W1TS : WO ;bitpos:[31:14] ;default: 0 ; */ -/*description: GPIO0~17 output value write 1 to set*/ -#define RTC_GPIO_OUT_DATA_W1TS 0x0003FFFF -#define RTC_GPIO_OUT_DATA_W1TS_M ((RTC_GPIO_OUT_DATA_W1TS_V)<<(RTC_GPIO_OUT_DATA_W1TS_S)) -#define RTC_GPIO_OUT_DATA_W1TS_V 0x3FFFF -#define RTC_GPIO_OUT_DATA_W1TS_S 14 - -#define RTC_GPIO_OUT_W1TC_REG (DR_REG_RTCIO_BASE + 0x8) -/* RTC_GPIO_OUT_DATA_W1TC : WO ;bitpos:[31:14] ;default: 0 ; */ -/*description: GPIO0~17 output value write 1 to clear*/ -#define RTC_GPIO_OUT_DATA_W1TC 0x0003FFFF -#define RTC_GPIO_OUT_DATA_W1TC_M ((RTC_GPIO_OUT_DATA_W1TC_V)<<(RTC_GPIO_OUT_DATA_W1TC_S)) -#define RTC_GPIO_OUT_DATA_W1TC_V 0x3FFFF -#define RTC_GPIO_OUT_DATA_W1TC_S 14 - -#define RTC_GPIO_ENABLE_REG (DR_REG_RTCIO_BASE + 0xc) -/* RTC_GPIO_ENABLE : R/W ;bitpos:[31:14] ;default: 0 ; */ -/*description: GPIO0~17 output enable*/ -#define RTC_GPIO_ENABLE 0x0003FFFF -#define RTC_GPIO_ENABLE_M ((RTC_GPIO_ENABLE_V)<<(RTC_GPIO_ENABLE_S)) -#define RTC_GPIO_ENABLE_V 0x3FFFF -#define RTC_GPIO_ENABLE_S 14 - -#define RTC_GPIO_ENABLE_W1TS_REG (DR_REG_RTCIO_BASE + 0x10) -/* RTC_GPIO_ENABLE_W1TS : WO ;bitpos:[31:14] ;default: 0 ; */ -/*description: GPIO0~17 output enable write 1 to set*/ -#define RTC_GPIO_ENABLE_W1TS 0x0003FFFF -#define RTC_GPIO_ENABLE_W1TS_M ((RTC_GPIO_ENABLE_W1TS_V)<<(RTC_GPIO_ENABLE_W1TS_S)) -#define RTC_GPIO_ENABLE_W1TS_V 0x3FFFF -#define RTC_GPIO_ENABLE_W1TS_S 14 - -#define RTC_GPIO_ENABLE_W1TC_REG (DR_REG_RTCIO_BASE + 0x14) -/* RTC_GPIO_ENABLE_W1TC : WO ;bitpos:[31:14] ;default: 0 ; */ -/*description: GPIO0~17 output enable write 1 to clear*/ -#define RTC_GPIO_ENABLE_W1TC 0x0003FFFF -#define RTC_GPIO_ENABLE_W1TC_M ((RTC_GPIO_ENABLE_W1TC_V)<<(RTC_GPIO_ENABLE_W1TC_S)) -#define RTC_GPIO_ENABLE_W1TC_V 0x3FFFF -#define RTC_GPIO_ENABLE_W1TC_S 14 - -#define RTC_GPIO_STATUS_REG (DR_REG_RTCIO_BASE + 0x18) -/* RTC_GPIO_STATUS_INT : R/W ;bitpos:[31:14] ;default: 0 ; */ -/*description: GPIO0~17 interrupt status*/ -#define RTC_GPIO_STATUS_INT 0x0003FFFF -#define RTC_GPIO_STATUS_INT_M ((RTC_GPIO_STATUS_INT_V)<<(RTC_GPIO_STATUS_INT_S)) -#define RTC_GPIO_STATUS_INT_V 0x3FFFF -#define RTC_GPIO_STATUS_INT_S 14 - -#define RTC_GPIO_STATUS_W1TS_REG (DR_REG_RTCIO_BASE + 0x1c) -/* RTC_GPIO_STATUS_INT_W1TS : WO ;bitpos:[31:14] ;default: 0 ; */ -/*description: GPIO0~17 interrupt status write 1 to set*/ -#define RTC_GPIO_STATUS_INT_W1TS 0x0003FFFF -#define RTC_GPIO_STATUS_INT_W1TS_M ((RTC_GPIO_STATUS_INT_W1TS_V)<<(RTC_GPIO_STATUS_INT_W1TS_S)) -#define RTC_GPIO_STATUS_INT_W1TS_V 0x3FFFF -#define RTC_GPIO_STATUS_INT_W1TS_S 14 - -#define RTC_GPIO_STATUS_W1TC_REG (DR_REG_RTCIO_BASE + 0x20) -/* RTC_GPIO_STATUS_INT_W1TC : WO ;bitpos:[31:14] ;default: 0 ; */ -/*description: GPIO0~17 interrupt status write 1 to clear*/ -#define RTC_GPIO_STATUS_INT_W1TC 0x0003FFFF -#define RTC_GPIO_STATUS_INT_W1TC_M ((RTC_GPIO_STATUS_INT_W1TC_V)<<(RTC_GPIO_STATUS_INT_W1TC_S)) -#define RTC_GPIO_STATUS_INT_W1TC_V 0x3FFFF -#define RTC_GPIO_STATUS_INT_W1TC_S 14 - -#define RTC_GPIO_IN_REG (DR_REG_RTCIO_BASE + 0x24) -/* RTC_GPIO_IN_NEXT : RO ;bitpos:[31:14] ;default: ; */ -/*description: GPIO0~17 input value*/ -#define RTC_GPIO_IN_NEXT 0x0003FFFF -#define RTC_GPIO_IN_NEXT_M ((RTC_GPIO_IN_NEXT_V)<<(RTC_GPIO_IN_NEXT_S)) -#define RTC_GPIO_IN_NEXT_V 0x3FFFF -#define RTC_GPIO_IN_NEXT_S 14 - -#define RTC_GPIO_PIN0_REG (DR_REG_RTCIO_BASE + 0x28) -/* RTC_GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: GPIO wake up enable only available in light sleep*/ -#define RTC_GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN0_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN0_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN0_WAKEUP_ENABLE_S 10 -/* RTC_GPIO_PIN0_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN0_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN0_INT_TYPE_M ((RTC_GPIO_PIN0_INT_TYPE_V)<<(RTC_GPIO_PIN0_INT_TYPE_S)) -#define RTC_GPIO_PIN0_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN0_INT_TYPE_S 7 -/* RTC_GPIO_PIN0_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN0_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN0_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN0_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN0_PAD_DRIVER_S 2 - -#define RTC_GPIO_PIN1_REG (DR_REG_RTCIO_BASE + 0x2c) -/* RTC_GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: GPIO wake up enable only available in light sleep*/ -#define RTC_GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN1_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN1_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN1_WAKEUP_ENABLE_S 10 -/* RTC_GPIO_PIN1_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN1_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN1_INT_TYPE_M ((RTC_GPIO_PIN1_INT_TYPE_V)<<(RTC_GPIO_PIN1_INT_TYPE_S)) -#define RTC_GPIO_PIN1_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN1_INT_TYPE_S 7 -/* RTC_GPIO_PIN1_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN1_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN1_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN1_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN1_PAD_DRIVER_S 2 - -#define RTC_GPIO_PIN2_REG (DR_REG_RTCIO_BASE + 0x30) -/* RTC_GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: GPIO wake up enable only available in light sleep*/ -#define RTC_GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN2_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN2_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN2_WAKEUP_ENABLE_S 10 -/* RTC_GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN2_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN2_INT_TYPE_M ((RTC_GPIO_PIN2_INT_TYPE_V)<<(RTC_GPIO_PIN2_INT_TYPE_S)) -#define RTC_GPIO_PIN2_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN2_INT_TYPE_S 7 -/* RTC_GPIO_PIN2_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN2_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN2_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN2_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN2_PAD_DRIVER_S 2 - -#define RTC_GPIO_PIN3_REG (DR_REG_RTCIO_BASE + 0x34) -/* RTC_GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: GPIO wake up enable only available in light sleep*/ -#define RTC_GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN3_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN3_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN3_WAKEUP_ENABLE_S 10 -/* RTC_GPIO_PIN3_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN3_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN3_INT_TYPE_M ((RTC_GPIO_PIN3_INT_TYPE_V)<<(RTC_GPIO_PIN3_INT_TYPE_S)) -#define RTC_GPIO_PIN3_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN3_INT_TYPE_S 7 -/* RTC_GPIO_PIN3_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN3_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN3_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN3_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN3_PAD_DRIVER_S 2 - -#define RTC_GPIO_PIN4_REG (DR_REG_RTCIO_BASE + 0x38) -/* RTC_GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: GPIO wake up enable only available in light sleep*/ -#define RTC_GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN4_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN4_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN4_WAKEUP_ENABLE_S 10 -/* RTC_GPIO_PIN4_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN4_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN4_INT_TYPE_M ((RTC_GPIO_PIN4_INT_TYPE_V)<<(RTC_GPIO_PIN4_INT_TYPE_S)) -#define RTC_GPIO_PIN4_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN4_INT_TYPE_S 7 -/* RTC_GPIO_PIN4_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN4_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN4_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN4_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN4_PAD_DRIVER_S 2 - -#define RTC_GPIO_PIN5_REG (DR_REG_RTCIO_BASE + 0x3c) -/* RTC_GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: GPIO wake up enable only available in light sleep*/ -#define RTC_GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN5_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN5_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN5_WAKEUP_ENABLE_S 10 -/* RTC_GPIO_PIN5_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN5_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN5_INT_TYPE_M ((RTC_GPIO_PIN5_INT_TYPE_V)<<(RTC_GPIO_PIN5_INT_TYPE_S)) -#define RTC_GPIO_PIN5_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN5_INT_TYPE_S 7 -/* RTC_GPIO_PIN5_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN5_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN5_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN5_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN5_PAD_DRIVER_S 2 - -#define RTC_GPIO_PIN6_REG (DR_REG_RTCIO_BASE + 0x40) -/* RTC_GPIO_PIN6_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: GPIO wake up enable only available in light sleep*/ -#define RTC_GPIO_PIN6_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN6_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN6_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN6_WAKEUP_ENABLE_S 10 -/* RTC_GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN6_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN6_INT_TYPE_M ((RTC_GPIO_PIN6_INT_TYPE_V)<<(RTC_GPIO_PIN6_INT_TYPE_S)) -#define RTC_GPIO_PIN6_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN6_INT_TYPE_S 7 -/* RTC_GPIO_PIN6_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN6_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN6_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN6_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN6_PAD_DRIVER_S 2 - -#define RTC_GPIO_PIN7_REG (DR_REG_RTCIO_BASE + 0x44) -/* RTC_GPIO_PIN7_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: GPIO wake up enable only available in light sleep*/ -#define RTC_GPIO_PIN7_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN7_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN7_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN7_WAKEUP_ENABLE_S 10 -/* RTC_GPIO_PIN7_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN7_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN7_INT_TYPE_M ((RTC_GPIO_PIN7_INT_TYPE_V)<<(RTC_GPIO_PIN7_INT_TYPE_S)) -#define RTC_GPIO_PIN7_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN7_INT_TYPE_S 7 -/* RTC_GPIO_PIN7_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN7_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN7_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN7_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN7_PAD_DRIVER_S 2 - -#define RTC_GPIO_PIN8_REG (DR_REG_RTCIO_BASE + 0x48) -/* RTC_GPIO_PIN8_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: GPIO wake up enable only available in light sleep*/ -#define RTC_GPIO_PIN8_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN8_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN8_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN8_WAKEUP_ENABLE_S 10 -/* RTC_GPIO_PIN8_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN8_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN8_INT_TYPE_M ((RTC_GPIO_PIN8_INT_TYPE_V)<<(RTC_GPIO_PIN8_INT_TYPE_S)) -#define RTC_GPIO_PIN8_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN8_INT_TYPE_S 7 -/* RTC_GPIO_PIN8_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN8_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN8_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN8_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN8_PAD_DRIVER_S 2 - -#define RTC_GPIO_PIN9_REG (DR_REG_RTCIO_BASE + 0x4c) -/* RTC_GPIO_PIN9_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: GPIO wake up enable only available in light sleep*/ -#define RTC_GPIO_PIN9_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN9_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN9_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN9_WAKEUP_ENABLE_S 10 -/* RTC_GPIO_PIN9_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN9_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN9_INT_TYPE_M ((RTC_GPIO_PIN9_INT_TYPE_V)<<(RTC_GPIO_PIN9_INT_TYPE_S)) -#define RTC_GPIO_PIN9_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN9_INT_TYPE_S 7 -/* RTC_GPIO_PIN9_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN9_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN9_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN9_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN9_PAD_DRIVER_S 2 - -#define RTC_GPIO_PIN10_REG (DR_REG_RTCIO_BASE + 0x50) -/* RTC_GPIO_PIN10_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: GPIO wake up enable only available in light sleep*/ -#define RTC_GPIO_PIN10_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN10_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN10_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN10_WAKEUP_ENABLE_S 10 -/* RTC_GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN10_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN10_INT_TYPE_M ((RTC_GPIO_PIN10_INT_TYPE_V)<<(RTC_GPIO_PIN10_INT_TYPE_S)) -#define RTC_GPIO_PIN10_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN10_INT_TYPE_S 7 -/* RTC_GPIO_PIN10_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN10_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN10_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN10_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN10_PAD_DRIVER_S 2 - -#define RTC_GPIO_PIN11_REG (DR_REG_RTCIO_BASE + 0x54) -/* RTC_GPIO_PIN11_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: GPIO wake up enable only available in light sleep*/ -#define RTC_GPIO_PIN11_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN11_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN11_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN11_WAKEUP_ENABLE_S 10 -/* RTC_GPIO_PIN11_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN11_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN11_INT_TYPE_M ((RTC_GPIO_PIN11_INT_TYPE_V)<<(RTC_GPIO_PIN11_INT_TYPE_S)) -#define RTC_GPIO_PIN11_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN11_INT_TYPE_S 7 -/* RTC_GPIO_PIN11_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN11_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN11_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN11_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN11_PAD_DRIVER_S 2 - -#define RTC_GPIO_PIN12_REG (DR_REG_RTCIO_BASE + 0x58) -/* RTC_GPIO_PIN12_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: GPIO wake up enable only available in light sleep*/ -#define RTC_GPIO_PIN12_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN12_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN12_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN12_WAKEUP_ENABLE_S 10 -/* RTC_GPIO_PIN12_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN12_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN12_INT_TYPE_M ((RTC_GPIO_PIN12_INT_TYPE_V)<<(RTC_GPIO_PIN12_INT_TYPE_S)) -#define RTC_GPIO_PIN12_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN12_INT_TYPE_S 7 -/* RTC_GPIO_PIN12_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN12_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN12_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN12_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN12_PAD_DRIVER_S 2 - -#define RTC_GPIO_PIN13_REG (DR_REG_RTCIO_BASE + 0x5c) -/* RTC_GPIO_PIN13_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: GPIO wake up enable only available in light sleep*/ -#define RTC_GPIO_PIN13_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN13_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN13_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN13_WAKEUP_ENABLE_S 10 -/* RTC_GPIO_PIN13_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN13_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN13_INT_TYPE_M ((RTC_GPIO_PIN13_INT_TYPE_V)<<(RTC_GPIO_PIN13_INT_TYPE_S)) -#define RTC_GPIO_PIN13_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN13_INT_TYPE_S 7 -/* RTC_GPIO_PIN13_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN13_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN13_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN13_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN13_PAD_DRIVER_S 2 - -#define RTC_GPIO_PIN14_REG (DR_REG_RTCIO_BASE + 0x60) -/* RTC_GPIO_PIN14_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: GPIO wake up enable only available in light sleep*/ -#define RTC_GPIO_PIN14_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN14_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN14_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN14_WAKEUP_ENABLE_S 10 -/* RTC_GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN14_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN14_INT_TYPE_M ((RTC_GPIO_PIN14_INT_TYPE_V)<<(RTC_GPIO_PIN14_INT_TYPE_S)) -#define RTC_GPIO_PIN14_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN14_INT_TYPE_S 7 -/* RTC_GPIO_PIN14_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN14_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN14_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN14_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN14_PAD_DRIVER_S 2 - -#define RTC_GPIO_PIN15_REG (DR_REG_RTCIO_BASE + 0x64) -/* RTC_GPIO_PIN15_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: GPIO wake up enable only available in light sleep*/ -#define RTC_GPIO_PIN15_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN15_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN15_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN15_WAKEUP_ENABLE_S 10 -/* RTC_GPIO_PIN15_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN15_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN15_INT_TYPE_M ((RTC_GPIO_PIN15_INT_TYPE_V)<<(RTC_GPIO_PIN15_INT_TYPE_S)) -#define RTC_GPIO_PIN15_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN15_INT_TYPE_S 7 -/* RTC_GPIO_PIN15_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN15_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN15_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN15_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN15_PAD_DRIVER_S 2 - -#define RTC_GPIO_PIN16_REG (DR_REG_RTCIO_BASE + 0x68) -/* RTC_GPIO_PIN16_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: GPIO wake up enable only available in light sleep*/ -#define RTC_GPIO_PIN16_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN16_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN16_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN16_WAKEUP_ENABLE_S 10 -/* RTC_GPIO_PIN16_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN16_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN16_INT_TYPE_M ((RTC_GPIO_PIN16_INT_TYPE_V)<<(RTC_GPIO_PIN16_INT_TYPE_S)) -#define RTC_GPIO_PIN16_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN16_INT_TYPE_S 7 -/* RTC_GPIO_PIN16_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN16_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN16_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN16_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN16_PAD_DRIVER_S 2 - -#define RTC_GPIO_PIN17_REG (DR_REG_RTCIO_BASE + 0x6c) -/* RTC_GPIO_PIN17_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ -/*description: GPIO wake up enable only available in light sleep*/ -#define RTC_GPIO_PIN17_WAKEUP_ENABLE (BIT(10)) -#define RTC_GPIO_PIN17_WAKEUP_ENABLE_M (BIT(10)) -#define RTC_GPIO_PIN17_WAKEUP_ENABLE_V 0x1 -#define RTC_GPIO_PIN17_WAKEUP_ENABLE_S 10 -/* RTC_GPIO_PIN17_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ -/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ -#define RTC_GPIO_PIN17_INT_TYPE 0x00000007 -#define RTC_GPIO_PIN17_INT_TYPE_M ((RTC_GPIO_PIN17_INT_TYPE_V)<<(RTC_GPIO_PIN17_INT_TYPE_S)) -#define RTC_GPIO_PIN17_INT_TYPE_V 0x7 -#define RTC_GPIO_PIN17_INT_TYPE_S 7 -/* RTC_GPIO_PIN17_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ -/*description: if set to 0: normal output if set to 1: open drain*/ -#define RTC_GPIO_PIN17_PAD_DRIVER (BIT(2)) -#define RTC_GPIO_PIN17_PAD_DRIVER_M (BIT(2)) -#define RTC_GPIO_PIN17_PAD_DRIVER_V 0x1 -#define RTC_GPIO_PIN17_PAD_DRIVER_S 2 - -#define RTC_IO_RTC_DEBUG_SEL_REG (DR_REG_RTCIO_BASE + 0x70) -/* RTC_IO_DEBUG_12M_NO_GATING : R/W ;bitpos:[25] ;default: 1'd0 ; */ -/*description: */ -#define RTC_IO_DEBUG_12M_NO_GATING (BIT(25)) -#define RTC_IO_DEBUG_12M_NO_GATING_M (BIT(25)) -#define RTC_IO_DEBUG_12M_NO_GATING_V 0x1 -#define RTC_IO_DEBUG_12M_NO_GATING_S 25 -/* RTC_IO_DEBUG_SEL4 : R/W ;bitpos:[24:20] ;default: 5'd0 ; */ -/*description: */ -#define RTC_IO_DEBUG_SEL4 0x0000001F -#define RTC_IO_DEBUG_SEL4_M ((RTC_IO_DEBUG_SEL4_V)<<(RTC_IO_DEBUG_SEL4_S)) -#define RTC_IO_DEBUG_SEL4_V 0x1F -#define RTC_IO_DEBUG_SEL4_S 20 -/* RTC_IO_DEBUG_SEL3 : R/W ;bitpos:[19:15] ;default: 5'd0 ; */ -/*description: */ -#define RTC_IO_DEBUG_SEL3 0x0000001F -#define RTC_IO_DEBUG_SEL3_M ((RTC_IO_DEBUG_SEL3_V)<<(RTC_IO_DEBUG_SEL3_S)) -#define RTC_IO_DEBUG_SEL3_V 0x1F -#define RTC_IO_DEBUG_SEL3_S 15 -/* RTC_IO_DEBUG_SEL2 : R/W ;bitpos:[14:10] ;default: 5'd0 ; */ -/*description: */ -#define RTC_IO_DEBUG_SEL2 0x0000001F -#define RTC_IO_DEBUG_SEL2_M ((RTC_IO_DEBUG_SEL2_V)<<(RTC_IO_DEBUG_SEL2_S)) -#define RTC_IO_DEBUG_SEL2_V 0x1F -#define RTC_IO_DEBUG_SEL2_S 10 -/* RTC_IO_DEBUG_SEL1 : R/W ;bitpos:[9:5] ;default: 5'd0 ; */ -/*description: */ -#define RTC_IO_DEBUG_SEL1 0x0000001F -#define RTC_IO_DEBUG_SEL1_M ((RTC_IO_DEBUG_SEL1_V)<<(RTC_IO_DEBUG_SEL1_S)) -#define RTC_IO_DEBUG_SEL1_V 0x1F -#define RTC_IO_DEBUG_SEL1_S 5 -/* RTC_IO_DEBUG_SEL0 : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ -/*description: */ -#define RTC_IO_DEBUG_SEL0 0x0000001F -#define RTC_IO_DEBUG_SEL0_M ((RTC_IO_DEBUG_SEL0_V)<<(RTC_IO_DEBUG_SEL0_S)) -#define RTC_IO_DEBUG_SEL0_V 0x1F -#define RTC_IO_DEBUG_SEL0_S 0 - -#define RTC_IO_DIG_PAD_HOLD_REG (DR_REG_RTCIO_BASE + 0x74) -/* RTC_IO_DIG_PAD_HOLD : R/W ;bitpos:[31:0] ;default: 1'd0 ; */ -/*description: select the digital pad hold value.*/ -#define RTC_IO_DIG_PAD_HOLD 0xFFFFFFFF -#define RTC_IO_DIG_PAD_HOLD_M ((RTC_IO_DIG_PAD_HOLD_V)<<(RTC_IO_DIG_PAD_HOLD_S)) -#define RTC_IO_DIG_PAD_HOLD_V 0xFFFFFFFF -#define RTC_IO_DIG_PAD_HOLD_S 0 - -#define RTC_IO_HALL_SENS_REG (DR_REG_RTCIO_BASE + 0x78) -/* RTC_IO_XPD_HALL : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: Power on hall sensor and connect to VP and VN*/ -#define RTC_IO_XPD_HALL (BIT(31)) -#define RTC_IO_XPD_HALL_M (BIT(31)) -#define RTC_IO_XPD_HALL_V 0x1 -#define RTC_IO_XPD_HALL_S 31 -/* RTC_IO_HALL_PHASE : R/W ;bitpos:[30] ;default: 1'd0 ; */ -/*description: Reverse phase of hall sensor*/ -#define RTC_IO_HALL_PHASE (BIT(30)) -#define RTC_IO_HALL_PHASE_M (BIT(30)) -#define RTC_IO_HALL_PHASE_V 0x1 -#define RTC_IO_HALL_PHASE_S 30 - -#define RTC_IO_SENSOR_PADS_REG (DR_REG_RTCIO_BASE + 0x7c) -/* RTC_IO_SENSE1_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: hold the current value of the output when setting the hold to Ò1Ó*/ -#define RTC_IO_SENSE1_HOLD (BIT(31)) -#define RTC_IO_SENSE1_HOLD_M (BIT(31)) -#define RTC_IO_SENSE1_HOLD_V 0x1 -#define RTC_IO_SENSE1_HOLD_S 31 -/* RTC_IO_SENSE2_HOLD : R/W ;bitpos:[30] ;default: 1'd0 ; */ -/*description: hold the current value of the output when setting the hold to Ò1Ó*/ -#define RTC_IO_SENSE2_HOLD (BIT(30)) -#define RTC_IO_SENSE2_HOLD_M (BIT(30)) -#define RTC_IO_SENSE2_HOLD_V 0x1 -#define RTC_IO_SENSE2_HOLD_S 30 -/* RTC_IO_SENSE3_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */ -/*description: hold the current value of the output when setting the hold to Ò1Ó*/ -#define RTC_IO_SENSE3_HOLD (BIT(29)) -#define RTC_IO_SENSE3_HOLD_M (BIT(29)) -#define RTC_IO_SENSE3_HOLD_V 0x1 -#define RTC_IO_SENSE3_HOLD_S 29 -/* RTC_IO_SENSE4_HOLD : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: hold the current value of the output when setting the hold to Ò1Ó*/ -#define RTC_IO_SENSE4_HOLD (BIT(28)) -#define RTC_IO_SENSE4_HOLD_M (BIT(28)) -#define RTC_IO_SENSE4_HOLD_V 0x1 -#define RTC_IO_SENSE4_HOLD_S 28 -/* RTC_IO_SENSE1_MUX_SEL : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ -#define RTC_IO_SENSE1_MUX_SEL (BIT(27)) -#define RTC_IO_SENSE1_MUX_SEL_M (BIT(27)) -#define RTC_IO_SENSE1_MUX_SEL_V 0x1 -#define RTC_IO_SENSE1_MUX_SEL_S 27 -/* RTC_IO_SENSE2_MUX_SEL : R/W ;bitpos:[26] ;default: 1'd0 ; */ -/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ -#define RTC_IO_SENSE2_MUX_SEL (BIT(26)) -#define RTC_IO_SENSE2_MUX_SEL_M (BIT(26)) -#define RTC_IO_SENSE2_MUX_SEL_V 0x1 -#define RTC_IO_SENSE2_MUX_SEL_S 26 -/* RTC_IO_SENSE3_MUX_SEL : R/W ;bitpos:[25] ;default: 1'd0 ; */ -/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ -#define RTC_IO_SENSE3_MUX_SEL (BIT(25)) -#define RTC_IO_SENSE3_MUX_SEL_M (BIT(25)) -#define RTC_IO_SENSE3_MUX_SEL_V 0x1 -#define RTC_IO_SENSE3_MUX_SEL_S 25 -/* RTC_IO_SENSE4_MUX_SEL : R/W ;bitpos:[24] ;default: 1'd0 ; */ -/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ -#define RTC_IO_SENSE4_MUX_SEL (BIT(24)) -#define RTC_IO_SENSE4_MUX_SEL_M (BIT(24)) -#define RTC_IO_SENSE4_MUX_SEL_V 0x1 -#define RTC_IO_SENSE4_MUX_SEL_S 24 -/* RTC_IO_SENSE1_FUN_SEL : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: the functional selection signal of the pad*/ -#define RTC_IO_SENSE1_FUN_SEL 0x00000003 -#define RTC_IO_SENSE1_FUN_SEL_M ((RTC_IO_SENSE1_FUN_SEL_V)<<(RTC_IO_SENSE1_FUN_SEL_S)) -#define RTC_IO_SENSE1_FUN_SEL_V 0x3 -#define RTC_IO_SENSE1_FUN_SEL_S 22 -/* RTC_IO_SENSE1_SLP_SEL : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: the sleep status selection signal of the pad*/ -#define RTC_IO_SENSE1_SLP_SEL (BIT(21)) -#define RTC_IO_SENSE1_SLP_SEL_M (BIT(21)) -#define RTC_IO_SENSE1_SLP_SEL_V 0x1 -#define RTC_IO_SENSE1_SLP_SEL_S 21 -/* RTC_IO_SENSE1_SLP_IE : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: the input enable of the pad in sleep status*/ -#define RTC_IO_SENSE1_SLP_IE (BIT(20)) -#define RTC_IO_SENSE1_SLP_IE_M (BIT(20)) -#define RTC_IO_SENSE1_SLP_IE_V 0x1 -#define RTC_IO_SENSE1_SLP_IE_S 20 -/* RTC_IO_SENSE1_FUN_IE : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: the input enable of the pad*/ -#define RTC_IO_SENSE1_FUN_IE (BIT(19)) -#define RTC_IO_SENSE1_FUN_IE_M (BIT(19)) -#define RTC_IO_SENSE1_FUN_IE_V 0x1 -#define RTC_IO_SENSE1_FUN_IE_S 19 -/* RTC_IO_SENSE2_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ -/*description: the functional selection signal of the pad*/ -#define RTC_IO_SENSE2_FUN_SEL 0x00000003 -#define RTC_IO_SENSE2_FUN_SEL_M ((RTC_IO_SENSE2_FUN_SEL_V)<<(RTC_IO_SENSE2_FUN_SEL_S)) -#define RTC_IO_SENSE2_FUN_SEL_V 0x3 -#define RTC_IO_SENSE2_FUN_SEL_S 17 -/* RTC_IO_SENSE2_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: the sleep status selection signal of the pad*/ -#define RTC_IO_SENSE2_SLP_SEL (BIT(16)) -#define RTC_IO_SENSE2_SLP_SEL_M (BIT(16)) -#define RTC_IO_SENSE2_SLP_SEL_V 0x1 -#define RTC_IO_SENSE2_SLP_SEL_S 16 -/* RTC_IO_SENSE2_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: the input enable of the pad in sleep status*/ -#define RTC_IO_SENSE2_SLP_IE (BIT(15)) -#define RTC_IO_SENSE2_SLP_IE_M (BIT(15)) -#define RTC_IO_SENSE2_SLP_IE_V 0x1 -#define RTC_IO_SENSE2_SLP_IE_S 15 -/* RTC_IO_SENSE2_FUN_IE : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: the input enable of the pad*/ -#define RTC_IO_SENSE2_FUN_IE (BIT(14)) -#define RTC_IO_SENSE2_FUN_IE_M (BIT(14)) -#define RTC_IO_SENSE2_FUN_IE_V 0x1 -#define RTC_IO_SENSE2_FUN_IE_S 14 -/* RTC_IO_SENSE3_FUN_SEL : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ -/*description: the functional selection signal of the pad*/ -#define RTC_IO_SENSE3_FUN_SEL 0x00000003 -#define RTC_IO_SENSE3_FUN_SEL_M ((RTC_IO_SENSE3_FUN_SEL_V)<<(RTC_IO_SENSE3_FUN_SEL_S)) -#define RTC_IO_SENSE3_FUN_SEL_V 0x3 -#define RTC_IO_SENSE3_FUN_SEL_S 12 -/* RTC_IO_SENSE3_SLP_SEL : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: the sleep status selection signal of the pad*/ -#define RTC_IO_SENSE3_SLP_SEL (BIT(11)) -#define RTC_IO_SENSE3_SLP_SEL_M (BIT(11)) -#define RTC_IO_SENSE3_SLP_SEL_V 0x1 -#define RTC_IO_SENSE3_SLP_SEL_S 11 -/* RTC_IO_SENSE3_SLP_IE : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: the input enable of the pad in sleep status*/ -#define RTC_IO_SENSE3_SLP_IE (BIT(10)) -#define RTC_IO_SENSE3_SLP_IE_M (BIT(10)) -#define RTC_IO_SENSE3_SLP_IE_V 0x1 -#define RTC_IO_SENSE3_SLP_IE_S 10 -/* RTC_IO_SENSE3_FUN_IE : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: the input enable of the pad*/ -#define RTC_IO_SENSE3_FUN_IE (BIT(9)) -#define RTC_IO_SENSE3_FUN_IE_M (BIT(9)) -#define RTC_IO_SENSE3_FUN_IE_V 0x1 -#define RTC_IO_SENSE3_FUN_IE_S 9 -/* RTC_IO_SENSE4_FUN_SEL : R/W ;bitpos:[8:7] ;default: 2'd0 ; */ -/*description: the functional selection signal of the pad*/ -#define RTC_IO_SENSE4_FUN_SEL 0x00000003 -#define RTC_IO_SENSE4_FUN_SEL_M ((RTC_IO_SENSE4_FUN_SEL_V)<<(RTC_IO_SENSE4_FUN_SEL_S)) -#define RTC_IO_SENSE4_FUN_SEL_V 0x3 -#define RTC_IO_SENSE4_FUN_SEL_S 7 -/* RTC_IO_SENSE4_SLP_SEL : R/W ;bitpos:[6] ;default: 1'd0 ; */ -/*description: the sleep status selection signal of the pad*/ -#define RTC_IO_SENSE4_SLP_SEL (BIT(6)) -#define RTC_IO_SENSE4_SLP_SEL_M (BIT(6)) -#define RTC_IO_SENSE4_SLP_SEL_V 0x1 -#define RTC_IO_SENSE4_SLP_SEL_S 6 -/* RTC_IO_SENSE4_SLP_IE : R/W ;bitpos:[5] ;default: 1'd0 ; */ -/*description: the input enable of the pad in sleep status*/ -#define RTC_IO_SENSE4_SLP_IE (BIT(5)) -#define RTC_IO_SENSE4_SLP_IE_M (BIT(5)) -#define RTC_IO_SENSE4_SLP_IE_V 0x1 -#define RTC_IO_SENSE4_SLP_IE_S 5 -/* RTC_IO_SENSE4_FUN_IE : R/W ;bitpos:[4] ;default: 1'd0 ; */ -/*description: the input enable of the pad*/ -#define RTC_IO_SENSE4_FUN_IE (BIT(4)) -#define RTC_IO_SENSE4_FUN_IE_M (BIT(4)) -#define RTC_IO_SENSE4_FUN_IE_V 0x1 -#define RTC_IO_SENSE4_FUN_IE_S 4 - -#define RTC_IO_ADC_PAD_REG (DR_REG_RTCIO_BASE + 0x80) -/* RTC_IO_ADC1_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: hold the current value of the output when setting the hold to Ò1Ó*/ -#define RTC_IO_ADC1_HOLD (BIT(31)) -#define RTC_IO_ADC1_HOLD_M (BIT(31)) -#define RTC_IO_ADC1_HOLD_V 0x1 -#define RTC_IO_ADC1_HOLD_S 31 -/* RTC_IO_ADC2_HOLD : R/W ;bitpos:[30] ;default: 1'd0 ; */ -/*description: hold the current value of the output when setting the hold to Ò1Ó*/ -#define RTC_IO_ADC2_HOLD (BIT(30)) -#define RTC_IO_ADC2_HOLD_M (BIT(30)) -#define RTC_IO_ADC2_HOLD_V 0x1 -#define RTC_IO_ADC2_HOLD_S 30 -/* RTC_IO_ADC1_MUX_SEL : R/W ;bitpos:[29] ;default: 1'd0 ; */ -/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ -#define RTC_IO_ADC1_MUX_SEL (BIT(29)) -#define RTC_IO_ADC1_MUX_SEL_M (BIT(29)) -#define RTC_IO_ADC1_MUX_SEL_V 0x1 -#define RTC_IO_ADC1_MUX_SEL_S 29 -/* RTC_IO_ADC2_MUX_SEL : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ -#define RTC_IO_ADC2_MUX_SEL (BIT(28)) -#define RTC_IO_ADC2_MUX_SEL_M (BIT(28)) -#define RTC_IO_ADC2_MUX_SEL_V 0x1 -#define RTC_IO_ADC2_MUX_SEL_S 28 -/* RTC_IO_ADC1_FUN_SEL : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ -/*description: the functional selection signal of the pad*/ -#define RTC_IO_ADC1_FUN_SEL 0x00000003 -#define RTC_IO_ADC1_FUN_SEL_M ((RTC_IO_ADC1_FUN_SEL_V)<<(RTC_IO_ADC1_FUN_SEL_S)) -#define RTC_IO_ADC1_FUN_SEL_V 0x3 -#define RTC_IO_ADC1_FUN_SEL_S 26 -/* RTC_IO_ADC1_SLP_SEL : R/W ;bitpos:[25] ;default: 1'd0 ; */ -/*description: the sleep status selection signal of the pad*/ -#define RTC_IO_ADC1_SLP_SEL (BIT(25)) -#define RTC_IO_ADC1_SLP_SEL_M (BIT(25)) -#define RTC_IO_ADC1_SLP_SEL_V 0x1 -#define RTC_IO_ADC1_SLP_SEL_S 25 -/* RTC_IO_ADC1_SLP_IE : R/W ;bitpos:[24] ;default: 1'd0 ; */ -/*description: the input enable of the pad in sleep status*/ -#define RTC_IO_ADC1_SLP_IE (BIT(24)) -#define RTC_IO_ADC1_SLP_IE_M (BIT(24)) -#define RTC_IO_ADC1_SLP_IE_V 0x1 -#define RTC_IO_ADC1_SLP_IE_S 24 -/* RTC_IO_ADC1_FUN_IE : R/W ;bitpos:[23] ;default: 1'd0 ; */ -/*description: the input enable of the pad*/ -#define RTC_IO_ADC1_FUN_IE (BIT(23)) -#define RTC_IO_ADC1_FUN_IE_M (BIT(23)) -#define RTC_IO_ADC1_FUN_IE_V 0x1 -#define RTC_IO_ADC1_FUN_IE_S 23 -/* RTC_IO_ADC2_FUN_SEL : R/W ;bitpos:[22:21] ;default: 2'd0 ; */ -/*description: the functional selection signal of the pad*/ -#define RTC_IO_ADC2_FUN_SEL 0x00000003 -#define RTC_IO_ADC2_FUN_SEL_M ((RTC_IO_ADC2_FUN_SEL_V)<<(RTC_IO_ADC2_FUN_SEL_S)) -#define RTC_IO_ADC2_FUN_SEL_V 0x3 -#define RTC_IO_ADC2_FUN_SEL_S 21 -/* RTC_IO_ADC2_SLP_SEL : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: the sleep status selection signal of the pad*/ -#define RTC_IO_ADC2_SLP_SEL (BIT(20)) -#define RTC_IO_ADC2_SLP_SEL_M (BIT(20)) -#define RTC_IO_ADC2_SLP_SEL_V 0x1 -#define RTC_IO_ADC2_SLP_SEL_S 20 -/* RTC_IO_ADC2_SLP_IE : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: the input enable of the pad in sleep status*/ -#define RTC_IO_ADC2_SLP_IE (BIT(19)) -#define RTC_IO_ADC2_SLP_IE_M (BIT(19)) -#define RTC_IO_ADC2_SLP_IE_V 0x1 -#define RTC_IO_ADC2_SLP_IE_S 19 -/* RTC_IO_ADC2_FUN_IE : R/W ;bitpos:[18] ;default: 1'd0 ; */ -/*description: the input enable of the pad*/ -#define RTC_IO_ADC2_FUN_IE (BIT(18)) -#define RTC_IO_ADC2_FUN_IE_M (BIT(18)) -#define RTC_IO_ADC2_FUN_IE_V 0x1 -#define RTC_IO_ADC2_FUN_IE_S 18 - -#define RTC_IO_PAD_DAC1_REG (DR_REG_RTCIO_BASE + 0x84) -/* RTC_IO_PDAC1_DRV : R/W ;bitpos:[31:30] ;default: 2'd2 ; */ -/*description: the driver strength of the pad*/ -#define RTC_IO_PDAC1_DRV 0x00000003 -#define RTC_IO_PDAC1_DRV_M ((RTC_IO_PDAC1_DRV_V)<<(RTC_IO_PDAC1_DRV_S)) -#define RTC_IO_PDAC1_DRV_V 0x3 -#define RTC_IO_PDAC1_DRV_S 30 -/* RTC_IO_PDAC1_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */ -/*description: hold the current value of the output when setting the hold to Ò1Ó*/ -#define RTC_IO_PDAC1_HOLD (BIT(29)) -#define RTC_IO_PDAC1_HOLD_M (BIT(29)) -#define RTC_IO_PDAC1_HOLD_V 0x1 -#define RTC_IO_PDAC1_HOLD_S 29 -/* RTC_IO_PDAC1_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: the pull down enable of the pad*/ -#define RTC_IO_PDAC1_RDE (BIT(28)) -#define RTC_IO_PDAC1_RDE_M (BIT(28)) -#define RTC_IO_PDAC1_RDE_V 0x1 -#define RTC_IO_PDAC1_RDE_S 28 -/* RTC_IO_PDAC1_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: the pull up enable of the pad*/ -#define RTC_IO_PDAC1_RUE (BIT(27)) -#define RTC_IO_PDAC1_RUE_M (BIT(27)) -#define RTC_IO_PDAC1_RUE_V 0x1 -#define RTC_IO_PDAC1_RUE_S 27 -/* RTC_IO_PDAC1_DAC : R/W ;bitpos:[26:19] ;default: 8'd0 ; */ -/*description: PAD DAC1 control code.*/ -#define RTC_IO_PDAC1_DAC 0x000000FF -#define RTC_IO_PDAC1_DAC_M ((RTC_IO_PDAC1_DAC_V)<<(RTC_IO_PDAC1_DAC_S)) -#define RTC_IO_PDAC1_DAC_V 0xFF -#define RTC_IO_PDAC1_DAC_S 19 -/* RTC_IO_PDAC1_XPD_DAC : R/W ;bitpos:[18] ;default: 1'd0 ; */ -/*description: Power on DAC1. Usually we need to tristate PDAC1 if we power - on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/ -#define RTC_IO_PDAC1_XPD_DAC (BIT(18)) -#define RTC_IO_PDAC1_XPD_DAC_M (BIT(18)) -#define RTC_IO_PDAC1_XPD_DAC_V 0x1 -#define RTC_IO_PDAC1_XPD_DAC_S 18 -/* RTC_IO_PDAC1_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ -/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ -#define RTC_IO_PDAC1_MUX_SEL (BIT(17)) -#define RTC_IO_PDAC1_MUX_SEL_M (BIT(17)) -#define RTC_IO_PDAC1_MUX_SEL_V 0x1 -#define RTC_IO_PDAC1_MUX_SEL_S 17 -/* RTC_IO_PDAC1_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */ -/*description: the functional selection signal of the pad*/ -#define RTC_IO_PDAC1_FUN_SEL 0x00000003 -#define RTC_IO_PDAC1_FUN_SEL_M ((RTC_IO_PDAC1_FUN_SEL_V)<<(RTC_IO_PDAC1_FUN_SEL_S)) -#define RTC_IO_PDAC1_FUN_SEL_V 0x3 -#define RTC_IO_PDAC1_FUN_SEL_S 15 -/* RTC_IO_PDAC1_SLP_SEL : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: the sleep status selection signal of the pad*/ -#define RTC_IO_PDAC1_SLP_SEL (BIT(14)) -#define RTC_IO_PDAC1_SLP_SEL_M (BIT(14)) -#define RTC_IO_PDAC1_SLP_SEL_V 0x1 -#define RTC_IO_PDAC1_SLP_SEL_S 14 -/* RTC_IO_PDAC1_SLP_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: the input enable of the pad in sleep status*/ -#define RTC_IO_PDAC1_SLP_IE (BIT(13)) -#define RTC_IO_PDAC1_SLP_IE_M (BIT(13)) -#define RTC_IO_PDAC1_SLP_IE_V 0x1 -#define RTC_IO_PDAC1_SLP_IE_S 13 -/* RTC_IO_PDAC1_SLP_OE : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: the output enable of the pad in sleep status*/ -#define RTC_IO_PDAC1_SLP_OE (BIT(12)) -#define RTC_IO_PDAC1_SLP_OE_M (BIT(12)) -#define RTC_IO_PDAC1_SLP_OE_V 0x1 -#define RTC_IO_PDAC1_SLP_OE_S 12 -/* RTC_IO_PDAC1_FUN_IE : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: the input enable of the pad*/ -#define RTC_IO_PDAC1_FUN_IE (BIT(11)) -#define RTC_IO_PDAC1_FUN_IE_M (BIT(11)) -#define RTC_IO_PDAC1_FUN_IE_V 0x1 -#define RTC_IO_PDAC1_FUN_IE_S 11 -/* RTC_IO_PDAC1_DAC_XPD_FORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: Power on DAC1. Usually we need to tristate PDAC1 if we power - on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/ -#define RTC_IO_PDAC1_DAC_XPD_FORCE (BIT(10)) -#define RTC_IO_PDAC1_DAC_XPD_FORCE_M (BIT(10)) -#define RTC_IO_PDAC1_DAC_XPD_FORCE_V 0x1 -#define RTC_IO_PDAC1_DAC_XPD_FORCE_S 10 - -#define RTC_IO_PAD_DAC2_REG (DR_REG_RTCIO_BASE + 0x88) -/* RTC_IO_PDAC2_DRV : R/W ;bitpos:[31:30] ;default: 2'd2 ; */ -/*description: the driver strength of the pad*/ -#define RTC_IO_PDAC2_DRV 0x00000003 -#define RTC_IO_PDAC2_DRV_M ((RTC_IO_PDAC2_DRV_V)<<(RTC_IO_PDAC2_DRV_S)) -#define RTC_IO_PDAC2_DRV_V 0x3 -#define RTC_IO_PDAC2_DRV_S 30 -/* RTC_IO_PDAC2_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */ -/*description: hold the current value of the output when setting the hold to Ò1Ó*/ -#define RTC_IO_PDAC2_HOLD (BIT(29)) -#define RTC_IO_PDAC2_HOLD_M (BIT(29)) -#define RTC_IO_PDAC2_HOLD_V 0x1 -#define RTC_IO_PDAC2_HOLD_S 29 -/* RTC_IO_PDAC2_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: the pull down enable of the pad*/ -#define RTC_IO_PDAC2_RDE (BIT(28)) -#define RTC_IO_PDAC2_RDE_M (BIT(28)) -#define RTC_IO_PDAC2_RDE_V 0x1 -#define RTC_IO_PDAC2_RDE_S 28 -/* RTC_IO_PDAC2_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: the pull up enable of the pad*/ -#define RTC_IO_PDAC2_RUE (BIT(27)) -#define RTC_IO_PDAC2_RUE_M (BIT(27)) -#define RTC_IO_PDAC2_RUE_V 0x1 -#define RTC_IO_PDAC2_RUE_S 27 -/* RTC_IO_PDAC2_DAC : R/W ;bitpos:[26:19] ;default: 8'd0 ; */ -/*description: PAD DAC2 control code.*/ -#define RTC_IO_PDAC2_DAC 0x000000FF -#define RTC_IO_PDAC2_DAC_M ((RTC_IO_PDAC2_DAC_V)<<(RTC_IO_PDAC2_DAC_S)) -#define RTC_IO_PDAC2_DAC_V 0xFF -#define RTC_IO_PDAC2_DAC_S 19 -/* RTC_IO_PDAC2_XPD_DAC : R/W ;bitpos:[18] ;default: 1'd0 ; */ -/*description: Power on DAC2. Usually we need to tristate PDAC1 if we power - on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/ -#define RTC_IO_PDAC2_XPD_DAC (BIT(18)) -#define RTC_IO_PDAC2_XPD_DAC_M (BIT(18)) -#define RTC_IO_PDAC2_XPD_DAC_V 0x1 -#define RTC_IO_PDAC2_XPD_DAC_S 18 -/* RTC_IO_PDAC2_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ -/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ -#define RTC_IO_PDAC2_MUX_SEL (BIT(17)) -#define RTC_IO_PDAC2_MUX_SEL_M (BIT(17)) -#define RTC_IO_PDAC2_MUX_SEL_V 0x1 -#define RTC_IO_PDAC2_MUX_SEL_S 17 -/* RTC_IO_PDAC2_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */ -/*description: the functional selection signal of the pad*/ -#define RTC_IO_PDAC2_FUN_SEL 0x00000003 -#define RTC_IO_PDAC2_FUN_SEL_M ((RTC_IO_PDAC2_FUN_SEL_V)<<(RTC_IO_PDAC2_FUN_SEL_S)) -#define RTC_IO_PDAC2_FUN_SEL_V 0x3 -#define RTC_IO_PDAC2_FUN_SEL_S 15 -/* RTC_IO_PDAC2_SLP_SEL : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: the sleep status selection signal of the pad*/ -#define RTC_IO_PDAC2_SLP_SEL (BIT(14)) -#define RTC_IO_PDAC2_SLP_SEL_M (BIT(14)) -#define RTC_IO_PDAC2_SLP_SEL_V 0x1 -#define RTC_IO_PDAC2_SLP_SEL_S 14 -/* RTC_IO_PDAC2_SLP_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: the input enable of the pad in sleep status*/ -#define RTC_IO_PDAC2_SLP_IE (BIT(13)) -#define RTC_IO_PDAC2_SLP_IE_M (BIT(13)) -#define RTC_IO_PDAC2_SLP_IE_V 0x1 -#define RTC_IO_PDAC2_SLP_IE_S 13 -/* RTC_IO_PDAC2_SLP_OE : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: the output enable of the pad in sleep status*/ -#define RTC_IO_PDAC2_SLP_OE (BIT(12)) -#define RTC_IO_PDAC2_SLP_OE_M (BIT(12)) -#define RTC_IO_PDAC2_SLP_OE_V 0x1 -#define RTC_IO_PDAC2_SLP_OE_S 12 -/* RTC_IO_PDAC2_FUN_IE : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: the input enable of the pad*/ -#define RTC_IO_PDAC2_FUN_IE (BIT(11)) -#define RTC_IO_PDAC2_FUN_IE_M (BIT(11)) -#define RTC_IO_PDAC2_FUN_IE_V 0x1 -#define RTC_IO_PDAC2_FUN_IE_S 11 -/* RTC_IO_PDAC2_DAC_XPD_FORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: Power on DAC2. Usually we need to tristate PDAC2 if we power - on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/ -#define RTC_IO_PDAC2_DAC_XPD_FORCE (BIT(10)) -#define RTC_IO_PDAC2_DAC_XPD_FORCE_M (BIT(10)) -#define RTC_IO_PDAC2_DAC_XPD_FORCE_V 0x1 -#define RTC_IO_PDAC2_DAC_XPD_FORCE_S 10 - -#define RTC_IO_XTAL_32K_PAD_REG (DR_REG_RTCIO_BASE + 0x8c) -/* RTC_IO_X32N_DRV : R/W ;bitpos:[31:30] ;default: 2'd2 ; */ -/*description: the driver strength of the pad*/ -#define RTC_IO_X32N_DRV 0x00000003 -#define RTC_IO_X32N_DRV_M ((RTC_IO_X32N_DRV_V)<<(RTC_IO_X32N_DRV_S)) -#define RTC_IO_X32N_DRV_V 0x3 -#define RTC_IO_X32N_DRV_S 30 -/* RTC_IO_X32N_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */ -/*description: hold the current value of the output when setting the hold to Ò1Ó*/ -#define RTC_IO_X32N_HOLD (BIT(29)) -#define RTC_IO_X32N_HOLD_M (BIT(29)) -#define RTC_IO_X32N_HOLD_V 0x1 -#define RTC_IO_X32N_HOLD_S 29 -/* RTC_IO_X32N_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: the pull down enable of the pad*/ -#define RTC_IO_X32N_RDE (BIT(28)) -#define RTC_IO_X32N_RDE_M (BIT(28)) -#define RTC_IO_X32N_RDE_V 0x1 -#define RTC_IO_X32N_RDE_S 28 -/* RTC_IO_X32N_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: the pull up enable of the pad*/ -#define RTC_IO_X32N_RUE (BIT(27)) -#define RTC_IO_X32N_RUE_M (BIT(27)) -#define RTC_IO_X32N_RUE_V 0x1 -#define RTC_IO_X32N_RUE_S 27 -/* RTC_IO_X32P_DRV : R/W ;bitpos:[26:25] ;default: 2'd2 ; */ -/*description: the driver strength of the pad*/ -#define RTC_IO_X32P_DRV 0x00000003 -#define RTC_IO_X32P_DRV_M ((RTC_IO_X32P_DRV_V)<<(RTC_IO_X32P_DRV_S)) -#define RTC_IO_X32P_DRV_V 0x3 -#define RTC_IO_X32P_DRV_S 25 -/* RTC_IO_X32P_HOLD : R/W ;bitpos:[24] ;default: 1'd0 ; */ -/*description: hold the current value of the output when setting the hold to Ò1Ó*/ -#define RTC_IO_X32P_HOLD (BIT(24)) -#define RTC_IO_X32P_HOLD_M (BIT(24)) -#define RTC_IO_X32P_HOLD_V 0x1 -#define RTC_IO_X32P_HOLD_S 24 -/* RTC_IO_X32P_RDE : R/W ;bitpos:[23] ;default: 1'd0 ; */ -/*description: the pull down enable of the pad*/ -#define RTC_IO_X32P_RDE (BIT(23)) -#define RTC_IO_X32P_RDE_M (BIT(23)) -#define RTC_IO_X32P_RDE_V 0x1 -#define RTC_IO_X32P_RDE_S 23 -/* RTC_IO_X32P_RUE : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: the pull up enable of the pad*/ -#define RTC_IO_X32P_RUE (BIT(22)) -#define RTC_IO_X32P_RUE_M (BIT(22)) -#define RTC_IO_X32P_RUE_V 0x1 -#define RTC_IO_X32P_RUE_S 22 -/* RTC_IO_DAC_XTAL_32K : R/W ;bitpos:[21:20] ;default: 2'b01 ; */ -/*description: 32K XTAL bias current DAC.*/ -#define RTC_IO_DAC_XTAL_32K 0x00000003 -#define RTC_IO_DAC_XTAL_32K_M ((RTC_IO_DAC_XTAL_32K_V)<<(RTC_IO_DAC_XTAL_32K_S)) -#define RTC_IO_DAC_XTAL_32K_V 0x3 -#define RTC_IO_DAC_XTAL_32K_S 20 -/* RTC_IO_XPD_XTAL_32K : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: Power up 32kHz crystal oscillator*/ -#define RTC_IO_XPD_XTAL_32K (BIT(19)) -#define RTC_IO_XPD_XTAL_32K_M (BIT(19)) -#define RTC_IO_XPD_XTAL_32K_V 0x1 -#define RTC_IO_XPD_XTAL_32K_S 19 -/* RTC_IO_X32N_MUX_SEL : R/W ;bitpos:[18] ;default: 1'd0 ; */ -/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ -#define RTC_IO_X32N_MUX_SEL (BIT(18)) -#define RTC_IO_X32N_MUX_SEL_M (BIT(18)) -#define RTC_IO_X32N_MUX_SEL_V 0x1 -#define RTC_IO_X32N_MUX_SEL_S 18 -/* RTC_IO_X32P_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ -/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ -#define RTC_IO_X32P_MUX_SEL (BIT(17)) -#define RTC_IO_X32P_MUX_SEL_M (BIT(17)) -#define RTC_IO_X32P_MUX_SEL_V 0x1 -#define RTC_IO_X32P_MUX_SEL_S 17 -/* RTC_IO_X32N_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */ -/*description: the functional selection signal of the pad*/ -#define RTC_IO_X32N_FUN_SEL 0x00000003 -#define RTC_IO_X32N_FUN_SEL_M ((RTC_IO_X32N_FUN_SEL_V)<<(RTC_IO_X32N_FUN_SEL_S)) -#define RTC_IO_X32N_FUN_SEL_V 0x3 -#define RTC_IO_X32N_FUN_SEL_S 15 -/* RTC_IO_X32N_SLP_SEL : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: the sleep status selection signal of the pad*/ -#define RTC_IO_X32N_SLP_SEL (BIT(14)) -#define RTC_IO_X32N_SLP_SEL_M (BIT(14)) -#define RTC_IO_X32N_SLP_SEL_V 0x1 -#define RTC_IO_X32N_SLP_SEL_S 14 -/* RTC_IO_X32N_SLP_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: the input enable of the pad in sleep status*/ -#define RTC_IO_X32N_SLP_IE (BIT(13)) -#define RTC_IO_X32N_SLP_IE_M (BIT(13)) -#define RTC_IO_X32N_SLP_IE_V 0x1 -#define RTC_IO_X32N_SLP_IE_S 13 -/* RTC_IO_X32N_SLP_OE : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: the output enable of the pad in sleep status*/ -#define RTC_IO_X32N_SLP_OE (BIT(12)) -#define RTC_IO_X32N_SLP_OE_M (BIT(12)) -#define RTC_IO_X32N_SLP_OE_V 0x1 -#define RTC_IO_X32N_SLP_OE_S 12 -/* RTC_IO_X32N_FUN_IE : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: the input enable of the pad*/ -#define RTC_IO_X32N_FUN_IE (BIT(11)) -#define RTC_IO_X32N_FUN_IE_M (BIT(11)) -#define RTC_IO_X32N_FUN_IE_V 0x1 -#define RTC_IO_X32N_FUN_IE_S 11 -/* RTC_IO_X32P_FUN_SEL : R/W ;bitpos:[10:9] ;default: 2'd0 ; */ -/*description: the functional selection signal of the pad*/ -#define RTC_IO_X32P_FUN_SEL 0x00000003 -#define RTC_IO_X32P_FUN_SEL_M ((RTC_IO_X32P_FUN_SEL_V)<<(RTC_IO_X32P_FUN_SEL_S)) -#define RTC_IO_X32P_FUN_SEL_V 0x3 -#define RTC_IO_X32P_FUN_SEL_S 9 -/* RTC_IO_X32P_SLP_SEL : R/W ;bitpos:[8] ;default: 1'd0 ; */ -/*description: the sleep status selection signal of the pad*/ -#define RTC_IO_X32P_SLP_SEL (BIT(8)) -#define RTC_IO_X32P_SLP_SEL_M (BIT(8)) -#define RTC_IO_X32P_SLP_SEL_V 0x1 -#define RTC_IO_X32P_SLP_SEL_S 8 -/* RTC_IO_X32P_SLP_IE : R/W ;bitpos:[7] ;default: 1'd0 ; */ -/*description: the input enable of the pad in sleep status*/ -#define RTC_IO_X32P_SLP_IE (BIT(7)) -#define RTC_IO_X32P_SLP_IE_M (BIT(7)) -#define RTC_IO_X32P_SLP_IE_V 0x1 -#define RTC_IO_X32P_SLP_IE_S 7 -/* RTC_IO_X32P_SLP_OE : R/W ;bitpos:[6] ;default: 1'd0 ; */ -/*description: the output enable of the pad in sleep status*/ -#define RTC_IO_X32P_SLP_OE (BIT(6)) -#define RTC_IO_X32P_SLP_OE_M (BIT(6)) -#define RTC_IO_X32P_SLP_OE_V 0x1 -#define RTC_IO_X32P_SLP_OE_S 6 -/* RTC_IO_X32P_FUN_IE : R/W ;bitpos:[5] ;default: 1'd0 ; */ -/*description: the input enable of the pad*/ -#define RTC_IO_X32P_FUN_IE (BIT(5)) -#define RTC_IO_X32P_FUN_IE_M (BIT(5)) -#define RTC_IO_X32P_FUN_IE_V 0x1 -#define RTC_IO_X32P_FUN_IE_S 5 -/* RTC_IO_DRES_XTAL_32K : R/W ;bitpos:[4:3] ;default: 2'b10 ; */ -/*description: 32K XTAL resistor bias control.*/ -#define RTC_IO_DRES_XTAL_32K 0x00000003 -#define RTC_IO_DRES_XTAL_32K_M ((RTC_IO_DRES_XTAL_32K_V)<<(RTC_IO_DRES_XTAL_32K_S)) -#define RTC_IO_DRES_XTAL_32K_V 0x3 -#define RTC_IO_DRES_XTAL_32K_S 3 -/* RTC_IO_DBIAS_XTAL_32K : R/W ;bitpos:[2:1] ;default: 2'b00 ; */ -/*description: 32K XTAL self-bias reference control.*/ -#define RTC_IO_DBIAS_XTAL_32K 0x00000003 -#define RTC_IO_DBIAS_XTAL_32K_M ((RTC_IO_DBIAS_XTAL_32K_V)<<(RTC_IO_DBIAS_XTAL_32K_S)) -#define RTC_IO_DBIAS_XTAL_32K_V 0x3 -#define RTC_IO_DBIAS_XTAL_32K_S 1 - -#define RTC_IO_TOUCH_CFG_REG (DR_REG_RTCIO_BASE + 0x90) -/* RTC_IO_TOUCH_XPD_BIAS : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: touch sensor bias power on.*/ -#define RTC_IO_TOUCH_XPD_BIAS (BIT(31)) -#define RTC_IO_TOUCH_XPD_BIAS_M (BIT(31)) -#define RTC_IO_TOUCH_XPD_BIAS_V 0x1 -#define RTC_IO_TOUCH_XPD_BIAS_S 31 -/* RTC_IO_TOUCH_DREFH : R/W ;bitpos:[30:29] ;default: 2'b11 ; */ -/*description: touch sensor saw wave top voltage.*/ -#define RTC_IO_TOUCH_DREFH 0x00000003 -#define RTC_IO_TOUCH_DREFH_M ((RTC_IO_TOUCH_DREFH_V)<<(RTC_IO_TOUCH_DREFH_S)) -#define RTC_IO_TOUCH_DREFH_V 0x3 -#define RTC_IO_TOUCH_DREFH_S 29 -/* RTC_IO_TOUCH_DREFL : R/W ;bitpos:[28:27] ;default: 2'b00 ; */ -/*description: touch sensor saw wave bottom voltage.*/ -#define RTC_IO_TOUCH_DREFL 0x00000003 -#define RTC_IO_TOUCH_DREFL_M ((RTC_IO_TOUCH_DREFL_V)<<(RTC_IO_TOUCH_DREFL_S)) -#define RTC_IO_TOUCH_DREFL_V 0x3 -#define RTC_IO_TOUCH_DREFL_S 27 -/* RTC_IO_TOUCH_DRANGE : R/W ;bitpos:[26:25] ;default: 2'b11 ; */ -/*description: touch sensor saw wave voltage range.*/ -#define RTC_IO_TOUCH_DRANGE 0x00000003 -#define RTC_IO_TOUCH_DRANGE_M ((RTC_IO_TOUCH_DRANGE_V)<<(RTC_IO_TOUCH_DRANGE_S)) -#define RTC_IO_TOUCH_DRANGE_V 0x3 -#define RTC_IO_TOUCH_DRANGE_S 25 -/* RTC_IO_TOUCH_DCUR : R/W ;bitpos:[24:23] ;default: 2'b00 ; */ -/*description: touch sensor bias current. Should have option to tie with BIAS_SLEEP(When - BIAS_SLEEP this setting is available*/ -#define RTC_IO_TOUCH_DCUR 0x00000003 -#define RTC_IO_TOUCH_DCUR_M ((RTC_IO_TOUCH_DCUR_V)<<(RTC_IO_TOUCH_DCUR_S)) -#define RTC_IO_TOUCH_DCUR_V 0x3 -#define RTC_IO_TOUCH_DCUR_S 23 - -#define RTC_IO_TOUCH_PAD0_REG (DR_REG_RTCIO_BASE + 0x94) -/* RTC_IO_TOUCH_PAD0_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: hold the current value of the output when setting the hold to Ò1Ó*/ -#define RTC_IO_TOUCH_PAD0_HOLD (BIT(31)) -#define RTC_IO_TOUCH_PAD0_HOLD_M (BIT(31)) -#define RTC_IO_TOUCH_PAD0_HOLD_V 0x1 -#define RTC_IO_TOUCH_PAD0_HOLD_S 31 -/* RTC_IO_TOUCH_PAD0_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ -/*description: the driver strength of the pad*/ -#define RTC_IO_TOUCH_PAD0_DRV 0x00000003 -#define RTC_IO_TOUCH_PAD0_DRV_M ((RTC_IO_TOUCH_PAD0_DRV_V)<<(RTC_IO_TOUCH_PAD0_DRV_S)) -#define RTC_IO_TOUCH_PAD0_DRV_V 0x3 -#define RTC_IO_TOUCH_PAD0_DRV_S 29 -/* RTC_IO_TOUCH_PAD0_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */ -/*description: the pull down enable of the pad*/ -#define RTC_IO_TOUCH_PAD0_RDE (BIT(28)) -#define RTC_IO_TOUCH_PAD0_RDE_M (BIT(28)) -#define RTC_IO_TOUCH_PAD0_RDE_V 0x1 -#define RTC_IO_TOUCH_PAD0_RDE_S 28 -/* RTC_IO_TOUCH_PAD0_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: the pull up enable of the pad*/ -#define RTC_IO_TOUCH_PAD0_RUE (BIT(27)) -#define RTC_IO_TOUCH_PAD0_RUE_M (BIT(27)) -#define RTC_IO_TOUCH_PAD0_RUE_V 0x1 -#define RTC_IO_TOUCH_PAD0_RUE_S 27 -/* RTC_IO_TOUCH_PAD0_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ -/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ -#define RTC_IO_TOUCH_PAD0_DAC 0x00000007 -#define RTC_IO_TOUCH_PAD0_DAC_M ((RTC_IO_TOUCH_PAD0_DAC_V)<<(RTC_IO_TOUCH_PAD0_DAC_S)) -#define RTC_IO_TOUCH_PAD0_DAC_V 0x7 -#define RTC_IO_TOUCH_PAD0_DAC_S 23 -/* RTC_IO_TOUCH_PAD0_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: start touch sensor.*/ -#define RTC_IO_TOUCH_PAD0_START (BIT(22)) -#define RTC_IO_TOUCH_PAD0_START_M (BIT(22)) -#define RTC_IO_TOUCH_PAD0_START_V 0x1 -#define RTC_IO_TOUCH_PAD0_START_S 22 -/* RTC_IO_TOUCH_PAD0_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ -#define RTC_IO_TOUCH_PAD0_TIE_OPT (BIT(21)) -#define RTC_IO_TOUCH_PAD0_TIE_OPT_M (BIT(21)) -#define RTC_IO_TOUCH_PAD0_TIE_OPT_V 0x1 -#define RTC_IO_TOUCH_PAD0_TIE_OPT_S 21 -/* RTC_IO_TOUCH_PAD0_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: touch sensor power on.*/ -#define RTC_IO_TOUCH_PAD0_XPD (BIT(20)) -#define RTC_IO_TOUCH_PAD0_XPD_M (BIT(20)) -#define RTC_IO_TOUCH_PAD0_XPD_V 0x1 -#define RTC_IO_TOUCH_PAD0_XPD_S 20 -/* RTC_IO_TOUCH_PAD0_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ -#define RTC_IO_TOUCH_PAD0_MUX_SEL (BIT(19)) -#define RTC_IO_TOUCH_PAD0_MUX_SEL_M (BIT(19)) -#define RTC_IO_TOUCH_PAD0_MUX_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD0_MUX_SEL_S 19 -/* RTC_IO_TOUCH_PAD0_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ -/*description: the functional selection signal of the pad*/ -#define RTC_IO_TOUCH_PAD0_FUN_SEL 0x00000003 -#define RTC_IO_TOUCH_PAD0_FUN_SEL_M ((RTC_IO_TOUCH_PAD0_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD0_FUN_SEL_S)) -#define RTC_IO_TOUCH_PAD0_FUN_SEL_V 0x3 -#define RTC_IO_TOUCH_PAD0_FUN_SEL_S 17 -/* RTC_IO_TOUCH_PAD0_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: the sleep status selection signal of the pad*/ -#define RTC_IO_TOUCH_PAD0_SLP_SEL (BIT(16)) -#define RTC_IO_TOUCH_PAD0_SLP_SEL_M (BIT(16)) -#define RTC_IO_TOUCH_PAD0_SLP_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD0_SLP_SEL_S 16 -/* RTC_IO_TOUCH_PAD0_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: the input enable of the pad in sleep status*/ -#define RTC_IO_TOUCH_PAD0_SLP_IE (BIT(15)) -#define RTC_IO_TOUCH_PAD0_SLP_IE_M (BIT(15)) -#define RTC_IO_TOUCH_PAD0_SLP_IE_V 0x1 -#define RTC_IO_TOUCH_PAD0_SLP_IE_S 15 -/* RTC_IO_TOUCH_PAD0_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: the output enable of the pad in sleep status*/ -#define RTC_IO_TOUCH_PAD0_SLP_OE (BIT(14)) -#define RTC_IO_TOUCH_PAD0_SLP_OE_M (BIT(14)) -#define RTC_IO_TOUCH_PAD0_SLP_OE_V 0x1 -#define RTC_IO_TOUCH_PAD0_SLP_OE_S 14 -/* RTC_IO_TOUCH_PAD0_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: the input enable of the pad*/ -#define RTC_IO_TOUCH_PAD0_FUN_IE (BIT(13)) -#define RTC_IO_TOUCH_PAD0_FUN_IE_M (BIT(13)) -#define RTC_IO_TOUCH_PAD0_FUN_IE_V 0x1 -#define RTC_IO_TOUCH_PAD0_FUN_IE_S 13 -/* RTC_IO_TOUCH_PAD0_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale GPIO4*/ -#define RTC_IO_TOUCH_PAD0_TO_GPIO (BIT(12)) -#define RTC_IO_TOUCH_PAD0_TO_GPIO_M (BIT(12)) -#define RTC_IO_TOUCH_PAD0_TO_GPIO_V 0x1 -#define RTC_IO_TOUCH_PAD0_TO_GPIO_S 12 - -#define RTC_IO_TOUCH_PAD1_REG (DR_REG_RTCIO_BASE + 0x98) -/* RTC_IO_TOUCH_PAD1_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: */ -#define RTC_IO_TOUCH_PAD1_HOLD (BIT(31)) -#define RTC_IO_TOUCH_PAD1_HOLD_M (BIT(31)) -#define RTC_IO_TOUCH_PAD1_HOLD_V 0x1 -#define RTC_IO_TOUCH_PAD1_HOLD_S 31 -/* RTC_IO_TOUCH_PAD1_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ -/*description: the driver strength of the pad*/ -#define RTC_IO_TOUCH_PAD1_DRV 0x00000003 -#define RTC_IO_TOUCH_PAD1_DRV_M ((RTC_IO_TOUCH_PAD1_DRV_V)<<(RTC_IO_TOUCH_PAD1_DRV_S)) -#define RTC_IO_TOUCH_PAD1_DRV_V 0x3 -#define RTC_IO_TOUCH_PAD1_DRV_S 29 -/* RTC_IO_TOUCH_PAD1_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: the pull down enable of the pad*/ -#define RTC_IO_TOUCH_PAD1_RDE (BIT(28)) -#define RTC_IO_TOUCH_PAD1_RDE_M (BIT(28)) -#define RTC_IO_TOUCH_PAD1_RDE_V 0x1 -#define RTC_IO_TOUCH_PAD1_RDE_S 28 -/* RTC_IO_TOUCH_PAD1_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */ -/*description: the pull up enable of the pad*/ -#define RTC_IO_TOUCH_PAD1_RUE (BIT(27)) -#define RTC_IO_TOUCH_PAD1_RUE_M (BIT(27)) -#define RTC_IO_TOUCH_PAD1_RUE_V 0x1 -#define RTC_IO_TOUCH_PAD1_RUE_S 27 -/* RTC_IO_TOUCH_PAD1_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ -/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ -#define RTC_IO_TOUCH_PAD1_DAC 0x00000007 -#define RTC_IO_TOUCH_PAD1_DAC_M ((RTC_IO_TOUCH_PAD1_DAC_V)<<(RTC_IO_TOUCH_PAD1_DAC_S)) -#define RTC_IO_TOUCH_PAD1_DAC_V 0x7 -#define RTC_IO_TOUCH_PAD1_DAC_S 23 -/* RTC_IO_TOUCH_PAD1_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: start touch sensor.*/ -#define RTC_IO_TOUCH_PAD1_START (BIT(22)) -#define RTC_IO_TOUCH_PAD1_START_M (BIT(22)) -#define RTC_IO_TOUCH_PAD1_START_V 0x1 -#define RTC_IO_TOUCH_PAD1_START_S 22 -/* RTC_IO_TOUCH_PAD1_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ -#define RTC_IO_TOUCH_PAD1_TIE_OPT (BIT(21)) -#define RTC_IO_TOUCH_PAD1_TIE_OPT_M (BIT(21)) -#define RTC_IO_TOUCH_PAD1_TIE_OPT_V 0x1 -#define RTC_IO_TOUCH_PAD1_TIE_OPT_S 21 -/* RTC_IO_TOUCH_PAD1_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: touch sensor power on.*/ -#define RTC_IO_TOUCH_PAD1_XPD (BIT(20)) -#define RTC_IO_TOUCH_PAD1_XPD_M (BIT(20)) -#define RTC_IO_TOUCH_PAD1_XPD_V 0x1 -#define RTC_IO_TOUCH_PAD1_XPD_S 20 -/* RTC_IO_TOUCH_PAD1_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ -#define RTC_IO_TOUCH_PAD1_MUX_SEL (BIT(19)) -#define RTC_IO_TOUCH_PAD1_MUX_SEL_M (BIT(19)) -#define RTC_IO_TOUCH_PAD1_MUX_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD1_MUX_SEL_S 19 -/* RTC_IO_TOUCH_PAD1_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ -/*description: the functional selection signal of the pad*/ -#define RTC_IO_TOUCH_PAD1_FUN_SEL 0x00000003 -#define RTC_IO_TOUCH_PAD1_FUN_SEL_M ((RTC_IO_TOUCH_PAD1_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD1_FUN_SEL_S)) -#define RTC_IO_TOUCH_PAD1_FUN_SEL_V 0x3 -#define RTC_IO_TOUCH_PAD1_FUN_SEL_S 17 -/* RTC_IO_TOUCH_PAD1_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: the sleep status selection signal of the pad*/ -#define RTC_IO_TOUCH_PAD1_SLP_SEL (BIT(16)) -#define RTC_IO_TOUCH_PAD1_SLP_SEL_M (BIT(16)) -#define RTC_IO_TOUCH_PAD1_SLP_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD1_SLP_SEL_S 16 -/* RTC_IO_TOUCH_PAD1_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: the input enable of the pad in sleep status*/ -#define RTC_IO_TOUCH_PAD1_SLP_IE (BIT(15)) -#define RTC_IO_TOUCH_PAD1_SLP_IE_M (BIT(15)) -#define RTC_IO_TOUCH_PAD1_SLP_IE_V 0x1 -#define RTC_IO_TOUCH_PAD1_SLP_IE_S 15 -/* RTC_IO_TOUCH_PAD1_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: the output enable of the pad in sleep status*/ -#define RTC_IO_TOUCH_PAD1_SLP_OE (BIT(14)) -#define RTC_IO_TOUCH_PAD1_SLP_OE_M (BIT(14)) -#define RTC_IO_TOUCH_PAD1_SLP_OE_V 0x1 -#define RTC_IO_TOUCH_PAD1_SLP_OE_S 14 -/* RTC_IO_TOUCH_PAD1_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: the input enable of the pad*/ -#define RTC_IO_TOUCH_PAD1_FUN_IE (BIT(13)) -#define RTC_IO_TOUCH_PAD1_FUN_IE_M (BIT(13)) -#define RTC_IO_TOUCH_PAD1_FUN_IE_V 0x1 -#define RTC_IO_TOUCH_PAD1_FUN_IE_S 13 -/* RTC_IO_TOUCH_PAD1_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO0*/ -#define RTC_IO_TOUCH_PAD1_TO_GPIO (BIT(12)) -#define RTC_IO_TOUCH_PAD1_TO_GPIO_M (BIT(12)) -#define RTC_IO_TOUCH_PAD1_TO_GPIO_V 0x1 -#define RTC_IO_TOUCH_PAD1_TO_GPIO_S 12 - -#define RTC_IO_TOUCH_PAD2_REG (DR_REG_RTCIO_BASE + 0x9c) -/* RTC_IO_TOUCH_PAD2_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: hold the current value of the output when setting the hold to Ò1Ó*/ -#define RTC_IO_TOUCH_PAD2_HOLD (BIT(31)) -#define RTC_IO_TOUCH_PAD2_HOLD_M (BIT(31)) -#define RTC_IO_TOUCH_PAD2_HOLD_V 0x1 -#define RTC_IO_TOUCH_PAD2_HOLD_S 31 -/* RTC_IO_TOUCH_PAD2_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ -/*description: the driver strength of the pad*/ -#define RTC_IO_TOUCH_PAD2_DRV 0x00000003 -#define RTC_IO_TOUCH_PAD2_DRV_M ((RTC_IO_TOUCH_PAD2_DRV_V)<<(RTC_IO_TOUCH_PAD2_DRV_S)) -#define RTC_IO_TOUCH_PAD2_DRV_V 0x3 -#define RTC_IO_TOUCH_PAD2_DRV_S 29 -/* RTC_IO_TOUCH_PAD2_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */ -/*description: the pull down enable of the pad*/ -#define RTC_IO_TOUCH_PAD2_RDE (BIT(28)) -#define RTC_IO_TOUCH_PAD2_RDE_M (BIT(28)) -#define RTC_IO_TOUCH_PAD2_RDE_V 0x1 -#define RTC_IO_TOUCH_PAD2_RDE_S 28 -/* RTC_IO_TOUCH_PAD2_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: the pull up enable of the pad*/ -#define RTC_IO_TOUCH_PAD2_RUE (BIT(27)) -#define RTC_IO_TOUCH_PAD2_RUE_M (BIT(27)) -#define RTC_IO_TOUCH_PAD2_RUE_V 0x1 -#define RTC_IO_TOUCH_PAD2_RUE_S 27 -/* RTC_IO_TOUCH_PAD2_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ -/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ -#define RTC_IO_TOUCH_PAD2_DAC 0x00000007 -#define RTC_IO_TOUCH_PAD2_DAC_M ((RTC_IO_TOUCH_PAD2_DAC_V)<<(RTC_IO_TOUCH_PAD2_DAC_S)) -#define RTC_IO_TOUCH_PAD2_DAC_V 0x7 -#define RTC_IO_TOUCH_PAD2_DAC_S 23 -/* RTC_IO_TOUCH_PAD2_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: start touch sensor.*/ -#define RTC_IO_TOUCH_PAD2_START (BIT(22)) -#define RTC_IO_TOUCH_PAD2_START_M (BIT(22)) -#define RTC_IO_TOUCH_PAD2_START_V 0x1 -#define RTC_IO_TOUCH_PAD2_START_S 22 -/* RTC_IO_TOUCH_PAD2_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ -#define RTC_IO_TOUCH_PAD2_TIE_OPT (BIT(21)) -#define RTC_IO_TOUCH_PAD2_TIE_OPT_M (BIT(21)) -#define RTC_IO_TOUCH_PAD2_TIE_OPT_V 0x1 -#define RTC_IO_TOUCH_PAD2_TIE_OPT_S 21 -/* RTC_IO_TOUCH_PAD2_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: touch sensor power on.*/ -#define RTC_IO_TOUCH_PAD2_XPD (BIT(20)) -#define RTC_IO_TOUCH_PAD2_XPD_M (BIT(20)) -#define RTC_IO_TOUCH_PAD2_XPD_V 0x1 -#define RTC_IO_TOUCH_PAD2_XPD_S 20 -/* RTC_IO_TOUCH_PAD2_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ -#define RTC_IO_TOUCH_PAD2_MUX_SEL (BIT(19)) -#define RTC_IO_TOUCH_PAD2_MUX_SEL_M (BIT(19)) -#define RTC_IO_TOUCH_PAD2_MUX_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD2_MUX_SEL_S 19 -/* RTC_IO_TOUCH_PAD2_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ -/*description: the functional selection signal of the pad*/ -#define RTC_IO_TOUCH_PAD2_FUN_SEL 0x00000003 -#define RTC_IO_TOUCH_PAD2_FUN_SEL_M ((RTC_IO_TOUCH_PAD2_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD2_FUN_SEL_S)) -#define RTC_IO_TOUCH_PAD2_FUN_SEL_V 0x3 -#define RTC_IO_TOUCH_PAD2_FUN_SEL_S 17 -/* RTC_IO_TOUCH_PAD2_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: the sleep status selection signal of the pad*/ -#define RTC_IO_TOUCH_PAD2_SLP_SEL (BIT(16)) -#define RTC_IO_TOUCH_PAD2_SLP_SEL_M (BIT(16)) -#define RTC_IO_TOUCH_PAD2_SLP_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD2_SLP_SEL_S 16 -/* RTC_IO_TOUCH_PAD2_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: the input enable of the pad in sleep status*/ -#define RTC_IO_TOUCH_PAD2_SLP_IE (BIT(15)) -#define RTC_IO_TOUCH_PAD2_SLP_IE_M (BIT(15)) -#define RTC_IO_TOUCH_PAD2_SLP_IE_V 0x1 -#define RTC_IO_TOUCH_PAD2_SLP_IE_S 15 -/* RTC_IO_TOUCH_PAD2_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: the output enable of the pad in sleep status*/ -#define RTC_IO_TOUCH_PAD2_SLP_OE (BIT(14)) -#define RTC_IO_TOUCH_PAD2_SLP_OE_M (BIT(14)) -#define RTC_IO_TOUCH_PAD2_SLP_OE_V 0x1 -#define RTC_IO_TOUCH_PAD2_SLP_OE_S 14 -/* RTC_IO_TOUCH_PAD2_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: the input enable of the pad*/ -#define RTC_IO_TOUCH_PAD2_FUN_IE (BIT(13)) -#define RTC_IO_TOUCH_PAD2_FUN_IE_M (BIT(13)) -#define RTC_IO_TOUCH_PAD2_FUN_IE_V 0x1 -#define RTC_IO_TOUCH_PAD2_FUN_IE_S 13 -/* RTC_IO_TOUCH_PAD2_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO2*/ -#define RTC_IO_TOUCH_PAD2_TO_GPIO (BIT(12)) -#define RTC_IO_TOUCH_PAD2_TO_GPIO_M (BIT(12)) -#define RTC_IO_TOUCH_PAD2_TO_GPIO_V 0x1 -#define RTC_IO_TOUCH_PAD2_TO_GPIO_S 12 - -#define RTC_IO_TOUCH_PAD3_REG (DR_REG_RTCIO_BASE + 0xa0) -/* RTC_IO_TOUCH_PAD3_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: hold the current value of the output when setting the hold to Ò1Ó*/ -#define RTC_IO_TOUCH_PAD3_HOLD (BIT(31)) -#define RTC_IO_TOUCH_PAD3_HOLD_M (BIT(31)) -#define RTC_IO_TOUCH_PAD3_HOLD_V 0x1 -#define RTC_IO_TOUCH_PAD3_HOLD_S 31 -/* RTC_IO_TOUCH_PAD3_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ -/*description: the driver strength of the pad*/ -#define RTC_IO_TOUCH_PAD3_DRV 0x00000003 -#define RTC_IO_TOUCH_PAD3_DRV_M ((RTC_IO_TOUCH_PAD3_DRV_V)<<(RTC_IO_TOUCH_PAD3_DRV_S)) -#define RTC_IO_TOUCH_PAD3_DRV_V 0x3 -#define RTC_IO_TOUCH_PAD3_DRV_S 29 -/* RTC_IO_TOUCH_PAD3_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: the pull down enable of the pad*/ -#define RTC_IO_TOUCH_PAD3_RDE (BIT(28)) -#define RTC_IO_TOUCH_PAD3_RDE_M (BIT(28)) -#define RTC_IO_TOUCH_PAD3_RDE_V 0x1 -#define RTC_IO_TOUCH_PAD3_RDE_S 28 -/* RTC_IO_TOUCH_PAD3_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */ -/*description: the pull up enable of the pad*/ -#define RTC_IO_TOUCH_PAD3_RUE (BIT(27)) -#define RTC_IO_TOUCH_PAD3_RUE_M (BIT(27)) -#define RTC_IO_TOUCH_PAD3_RUE_V 0x1 -#define RTC_IO_TOUCH_PAD3_RUE_S 27 -/* RTC_IO_TOUCH_PAD3_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ -/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ -#define RTC_IO_TOUCH_PAD3_DAC 0x00000007 -#define RTC_IO_TOUCH_PAD3_DAC_M ((RTC_IO_TOUCH_PAD3_DAC_V)<<(RTC_IO_TOUCH_PAD3_DAC_S)) -#define RTC_IO_TOUCH_PAD3_DAC_V 0x7 -#define RTC_IO_TOUCH_PAD3_DAC_S 23 -/* RTC_IO_TOUCH_PAD3_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: start touch sensor.*/ -#define RTC_IO_TOUCH_PAD3_START (BIT(22)) -#define RTC_IO_TOUCH_PAD3_START_M (BIT(22)) -#define RTC_IO_TOUCH_PAD3_START_V 0x1 -#define RTC_IO_TOUCH_PAD3_START_S 22 -/* RTC_IO_TOUCH_PAD3_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ -#define RTC_IO_TOUCH_PAD3_TIE_OPT (BIT(21)) -#define RTC_IO_TOUCH_PAD3_TIE_OPT_M (BIT(21)) -#define RTC_IO_TOUCH_PAD3_TIE_OPT_V 0x1 -#define RTC_IO_TOUCH_PAD3_TIE_OPT_S 21 -/* RTC_IO_TOUCH_PAD3_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: touch sensor power on.*/ -#define RTC_IO_TOUCH_PAD3_XPD (BIT(20)) -#define RTC_IO_TOUCH_PAD3_XPD_M (BIT(20)) -#define RTC_IO_TOUCH_PAD3_XPD_V 0x1 -#define RTC_IO_TOUCH_PAD3_XPD_S 20 -/* RTC_IO_TOUCH_PAD3_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ -#define RTC_IO_TOUCH_PAD3_MUX_SEL (BIT(19)) -#define RTC_IO_TOUCH_PAD3_MUX_SEL_M (BIT(19)) -#define RTC_IO_TOUCH_PAD3_MUX_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD3_MUX_SEL_S 19 -/* RTC_IO_TOUCH_PAD3_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ -/*description: the functional selection signal of the pad*/ -#define RTC_IO_TOUCH_PAD3_FUN_SEL 0x00000003 -#define RTC_IO_TOUCH_PAD3_FUN_SEL_M ((RTC_IO_TOUCH_PAD3_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD3_FUN_SEL_S)) -#define RTC_IO_TOUCH_PAD3_FUN_SEL_V 0x3 -#define RTC_IO_TOUCH_PAD3_FUN_SEL_S 17 -/* RTC_IO_TOUCH_PAD3_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: the sleep status selection signal of the pad*/ -#define RTC_IO_TOUCH_PAD3_SLP_SEL (BIT(16)) -#define RTC_IO_TOUCH_PAD3_SLP_SEL_M (BIT(16)) -#define RTC_IO_TOUCH_PAD3_SLP_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD3_SLP_SEL_S 16 -/* RTC_IO_TOUCH_PAD3_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: the input enable of the pad in sleep status*/ -#define RTC_IO_TOUCH_PAD3_SLP_IE (BIT(15)) -#define RTC_IO_TOUCH_PAD3_SLP_IE_M (BIT(15)) -#define RTC_IO_TOUCH_PAD3_SLP_IE_V 0x1 -#define RTC_IO_TOUCH_PAD3_SLP_IE_S 15 -/* RTC_IO_TOUCH_PAD3_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: the output enable of the pad in sleep status*/ -#define RTC_IO_TOUCH_PAD3_SLP_OE (BIT(14)) -#define RTC_IO_TOUCH_PAD3_SLP_OE_M (BIT(14)) -#define RTC_IO_TOUCH_PAD3_SLP_OE_V 0x1 -#define RTC_IO_TOUCH_PAD3_SLP_OE_S 14 -/* RTC_IO_TOUCH_PAD3_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: the input enable of the pad*/ -#define RTC_IO_TOUCH_PAD3_FUN_IE (BIT(13)) -#define RTC_IO_TOUCH_PAD3_FUN_IE_M (BIT(13)) -#define RTC_IO_TOUCH_PAD3_FUN_IE_V 0x1 -#define RTC_IO_TOUCH_PAD3_FUN_IE_S 13 -/* RTC_IO_TOUCH_PAD3_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTDO*/ -#define RTC_IO_TOUCH_PAD3_TO_GPIO (BIT(12)) -#define RTC_IO_TOUCH_PAD3_TO_GPIO_M (BIT(12)) -#define RTC_IO_TOUCH_PAD3_TO_GPIO_V 0x1 -#define RTC_IO_TOUCH_PAD3_TO_GPIO_S 12 - -#define RTC_IO_TOUCH_PAD4_REG (DR_REG_RTCIO_BASE + 0xa4) -/* RTC_IO_TOUCH_PAD4_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: hold the current value of the output when setting the hold to Ò1Ó*/ -#define RTC_IO_TOUCH_PAD4_HOLD (BIT(31)) -#define RTC_IO_TOUCH_PAD4_HOLD_M (BIT(31)) -#define RTC_IO_TOUCH_PAD4_HOLD_V 0x1 -#define RTC_IO_TOUCH_PAD4_HOLD_S 31 -/* RTC_IO_TOUCH_PAD4_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ -/*description: the driver strength of the pad*/ -#define RTC_IO_TOUCH_PAD4_DRV 0x00000003 -#define RTC_IO_TOUCH_PAD4_DRV_M ((RTC_IO_TOUCH_PAD4_DRV_V)<<(RTC_IO_TOUCH_PAD4_DRV_S)) -#define RTC_IO_TOUCH_PAD4_DRV_V 0x3 -#define RTC_IO_TOUCH_PAD4_DRV_S 29 -/* RTC_IO_TOUCH_PAD4_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */ -/*description: the pull down enable of the pad*/ -#define RTC_IO_TOUCH_PAD4_RDE (BIT(28)) -#define RTC_IO_TOUCH_PAD4_RDE_M (BIT(28)) -#define RTC_IO_TOUCH_PAD4_RDE_V 0x1 -#define RTC_IO_TOUCH_PAD4_RDE_S 28 -/* RTC_IO_TOUCH_PAD4_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: the pull up enable of the pad*/ -#define RTC_IO_TOUCH_PAD4_RUE (BIT(27)) -#define RTC_IO_TOUCH_PAD4_RUE_M (BIT(27)) -#define RTC_IO_TOUCH_PAD4_RUE_V 0x1 -#define RTC_IO_TOUCH_PAD4_RUE_S 27 -/* RTC_IO_TOUCH_PAD4_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ -/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ -#define RTC_IO_TOUCH_PAD4_DAC 0x00000007 -#define RTC_IO_TOUCH_PAD4_DAC_M ((RTC_IO_TOUCH_PAD4_DAC_V)<<(RTC_IO_TOUCH_PAD4_DAC_S)) -#define RTC_IO_TOUCH_PAD4_DAC_V 0x7 -#define RTC_IO_TOUCH_PAD4_DAC_S 23 -/* RTC_IO_TOUCH_PAD4_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: start touch sensor.*/ -#define RTC_IO_TOUCH_PAD4_START (BIT(22)) -#define RTC_IO_TOUCH_PAD4_START_M (BIT(22)) -#define RTC_IO_TOUCH_PAD4_START_V 0x1 -#define RTC_IO_TOUCH_PAD4_START_S 22 -/* RTC_IO_TOUCH_PAD4_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ -#define RTC_IO_TOUCH_PAD4_TIE_OPT (BIT(21)) -#define RTC_IO_TOUCH_PAD4_TIE_OPT_M (BIT(21)) -#define RTC_IO_TOUCH_PAD4_TIE_OPT_V 0x1 -#define RTC_IO_TOUCH_PAD4_TIE_OPT_S 21 -/* RTC_IO_TOUCH_PAD4_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: touch sensor power on.*/ -#define RTC_IO_TOUCH_PAD4_XPD (BIT(20)) -#define RTC_IO_TOUCH_PAD4_XPD_M (BIT(20)) -#define RTC_IO_TOUCH_PAD4_XPD_V 0x1 -#define RTC_IO_TOUCH_PAD4_XPD_S 20 -/* RTC_IO_TOUCH_PAD4_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ -#define RTC_IO_TOUCH_PAD4_MUX_SEL (BIT(19)) -#define RTC_IO_TOUCH_PAD4_MUX_SEL_M (BIT(19)) -#define RTC_IO_TOUCH_PAD4_MUX_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD4_MUX_SEL_S 19 -/* RTC_IO_TOUCH_PAD4_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ -/*description: the functional selection signal of the pad*/ -#define RTC_IO_TOUCH_PAD4_FUN_SEL 0x00000003 -#define RTC_IO_TOUCH_PAD4_FUN_SEL_M ((RTC_IO_TOUCH_PAD4_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD4_FUN_SEL_S)) -#define RTC_IO_TOUCH_PAD4_FUN_SEL_V 0x3 -#define RTC_IO_TOUCH_PAD4_FUN_SEL_S 17 -/* RTC_IO_TOUCH_PAD4_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: the sleep status selection signal of the pad*/ -#define RTC_IO_TOUCH_PAD4_SLP_SEL (BIT(16)) -#define RTC_IO_TOUCH_PAD4_SLP_SEL_M (BIT(16)) -#define RTC_IO_TOUCH_PAD4_SLP_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD4_SLP_SEL_S 16 -/* RTC_IO_TOUCH_PAD4_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: the input enable of the pad in sleep status*/ -#define RTC_IO_TOUCH_PAD4_SLP_IE (BIT(15)) -#define RTC_IO_TOUCH_PAD4_SLP_IE_M (BIT(15)) -#define RTC_IO_TOUCH_PAD4_SLP_IE_V 0x1 -#define RTC_IO_TOUCH_PAD4_SLP_IE_S 15 -/* RTC_IO_TOUCH_PAD4_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: the output enable of the pad in sleep status*/ -#define RTC_IO_TOUCH_PAD4_SLP_OE (BIT(14)) -#define RTC_IO_TOUCH_PAD4_SLP_OE_M (BIT(14)) -#define RTC_IO_TOUCH_PAD4_SLP_OE_V 0x1 -#define RTC_IO_TOUCH_PAD4_SLP_OE_S 14 -/* RTC_IO_TOUCH_PAD4_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: the input enable of the pad*/ -#define RTC_IO_TOUCH_PAD4_FUN_IE (BIT(13)) -#define RTC_IO_TOUCH_PAD4_FUN_IE_M (BIT(13)) -#define RTC_IO_TOUCH_PAD4_FUN_IE_V 0x1 -#define RTC_IO_TOUCH_PAD4_FUN_IE_S 13 -/* RTC_IO_TOUCH_PAD4_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTCK*/ -#define RTC_IO_TOUCH_PAD4_TO_GPIO (BIT(12)) -#define RTC_IO_TOUCH_PAD4_TO_GPIO_M (BIT(12)) -#define RTC_IO_TOUCH_PAD4_TO_GPIO_V 0x1 -#define RTC_IO_TOUCH_PAD4_TO_GPIO_S 12 - -#define RTC_IO_TOUCH_PAD5_REG (DR_REG_RTCIO_BASE + 0xa8) -/* RTC_IO_TOUCH_PAD5_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: hold the current value of the output when setting the hold to Ò1Ó*/ -#define RTC_IO_TOUCH_PAD5_HOLD (BIT(31)) -#define RTC_IO_TOUCH_PAD5_HOLD_M (BIT(31)) -#define RTC_IO_TOUCH_PAD5_HOLD_V 0x1 -#define RTC_IO_TOUCH_PAD5_HOLD_S 31 -/* RTC_IO_TOUCH_PAD5_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ -/*description: the driver strength of the pad*/ -#define RTC_IO_TOUCH_PAD5_DRV 0x00000003 -#define RTC_IO_TOUCH_PAD5_DRV_M ((RTC_IO_TOUCH_PAD5_DRV_V)<<(RTC_IO_TOUCH_PAD5_DRV_S)) -#define RTC_IO_TOUCH_PAD5_DRV_V 0x3 -#define RTC_IO_TOUCH_PAD5_DRV_S 29 -/* RTC_IO_TOUCH_PAD5_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */ -/*description: the pull down enable of the pad*/ -#define RTC_IO_TOUCH_PAD5_RDE (BIT(28)) -#define RTC_IO_TOUCH_PAD5_RDE_M (BIT(28)) -#define RTC_IO_TOUCH_PAD5_RDE_V 0x1 -#define RTC_IO_TOUCH_PAD5_RDE_S 28 -/* RTC_IO_TOUCH_PAD5_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: the pull up enable of the pad*/ -#define RTC_IO_TOUCH_PAD5_RUE (BIT(27)) -#define RTC_IO_TOUCH_PAD5_RUE_M (BIT(27)) -#define RTC_IO_TOUCH_PAD5_RUE_V 0x1 -#define RTC_IO_TOUCH_PAD5_RUE_S 27 -/* RTC_IO_TOUCH_PAD5_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ -/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ -#define RTC_IO_TOUCH_PAD5_DAC 0x00000007 -#define RTC_IO_TOUCH_PAD5_DAC_M ((RTC_IO_TOUCH_PAD5_DAC_V)<<(RTC_IO_TOUCH_PAD5_DAC_S)) -#define RTC_IO_TOUCH_PAD5_DAC_V 0x7 -#define RTC_IO_TOUCH_PAD5_DAC_S 23 -/* RTC_IO_TOUCH_PAD5_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: start touch sensor.*/ -#define RTC_IO_TOUCH_PAD5_START (BIT(22)) -#define RTC_IO_TOUCH_PAD5_START_M (BIT(22)) -#define RTC_IO_TOUCH_PAD5_START_V 0x1 -#define RTC_IO_TOUCH_PAD5_START_S 22 -/* RTC_IO_TOUCH_PAD5_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ -#define RTC_IO_TOUCH_PAD5_TIE_OPT (BIT(21)) -#define RTC_IO_TOUCH_PAD5_TIE_OPT_M (BIT(21)) -#define RTC_IO_TOUCH_PAD5_TIE_OPT_V 0x1 -#define RTC_IO_TOUCH_PAD5_TIE_OPT_S 21 -/* RTC_IO_TOUCH_PAD5_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: touch sensor power on.*/ -#define RTC_IO_TOUCH_PAD5_XPD (BIT(20)) -#define RTC_IO_TOUCH_PAD5_XPD_M (BIT(20)) -#define RTC_IO_TOUCH_PAD5_XPD_V 0x1 -#define RTC_IO_TOUCH_PAD5_XPD_S 20 -/* RTC_IO_TOUCH_PAD5_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ -#define RTC_IO_TOUCH_PAD5_MUX_SEL (BIT(19)) -#define RTC_IO_TOUCH_PAD5_MUX_SEL_M (BIT(19)) -#define RTC_IO_TOUCH_PAD5_MUX_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD5_MUX_SEL_S 19 -/* RTC_IO_TOUCH_PAD5_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ -/*description: the functional selection signal of the pad*/ -#define RTC_IO_TOUCH_PAD5_FUN_SEL 0x00000003 -#define RTC_IO_TOUCH_PAD5_FUN_SEL_M ((RTC_IO_TOUCH_PAD5_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD5_FUN_SEL_S)) -#define RTC_IO_TOUCH_PAD5_FUN_SEL_V 0x3 -#define RTC_IO_TOUCH_PAD5_FUN_SEL_S 17 -/* RTC_IO_TOUCH_PAD5_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: the sleep status selection signal of the pad*/ -#define RTC_IO_TOUCH_PAD5_SLP_SEL (BIT(16)) -#define RTC_IO_TOUCH_PAD5_SLP_SEL_M (BIT(16)) -#define RTC_IO_TOUCH_PAD5_SLP_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD5_SLP_SEL_S 16 -/* RTC_IO_TOUCH_PAD5_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: the input enable of the pad in sleep status*/ -#define RTC_IO_TOUCH_PAD5_SLP_IE (BIT(15)) -#define RTC_IO_TOUCH_PAD5_SLP_IE_M (BIT(15)) -#define RTC_IO_TOUCH_PAD5_SLP_IE_V 0x1 -#define RTC_IO_TOUCH_PAD5_SLP_IE_S 15 -/* RTC_IO_TOUCH_PAD5_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: the output enable of the pad in sleep status*/ -#define RTC_IO_TOUCH_PAD5_SLP_OE (BIT(14)) -#define RTC_IO_TOUCH_PAD5_SLP_OE_M (BIT(14)) -#define RTC_IO_TOUCH_PAD5_SLP_OE_V 0x1 -#define RTC_IO_TOUCH_PAD5_SLP_OE_S 14 -/* RTC_IO_TOUCH_PAD5_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: the input enable of the pad*/ -#define RTC_IO_TOUCH_PAD5_FUN_IE (BIT(13)) -#define RTC_IO_TOUCH_PAD5_FUN_IE_M (BIT(13)) -#define RTC_IO_TOUCH_PAD5_FUN_IE_V 0x1 -#define RTC_IO_TOUCH_PAD5_FUN_IE_S 13 -/* RTC_IO_TOUCH_PAD5_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTDI*/ -#define RTC_IO_TOUCH_PAD5_TO_GPIO (BIT(12)) -#define RTC_IO_TOUCH_PAD5_TO_GPIO_M (BIT(12)) -#define RTC_IO_TOUCH_PAD5_TO_GPIO_V 0x1 -#define RTC_IO_TOUCH_PAD5_TO_GPIO_S 12 - -#define RTC_IO_TOUCH_PAD6_REG (DR_REG_RTCIO_BASE + 0xac) -/* RTC_IO_TOUCH_PAD6_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: hold the current value of the output when setting the hold to Ò1Ó*/ -#define RTC_IO_TOUCH_PAD6_HOLD (BIT(31)) -#define RTC_IO_TOUCH_PAD6_HOLD_M (BIT(31)) -#define RTC_IO_TOUCH_PAD6_HOLD_V 0x1 -#define RTC_IO_TOUCH_PAD6_HOLD_S 31 -/* RTC_IO_TOUCH_PAD6_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ -/*description: the driver strength of the pad*/ -#define RTC_IO_TOUCH_PAD6_DRV 0x00000003 -#define RTC_IO_TOUCH_PAD6_DRV_M ((RTC_IO_TOUCH_PAD6_DRV_V)<<(RTC_IO_TOUCH_PAD6_DRV_S)) -#define RTC_IO_TOUCH_PAD6_DRV_V 0x3 -#define RTC_IO_TOUCH_PAD6_DRV_S 29 -/* RTC_IO_TOUCH_PAD6_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: the pull down enable of the pad*/ -#define RTC_IO_TOUCH_PAD6_RDE (BIT(28)) -#define RTC_IO_TOUCH_PAD6_RDE_M (BIT(28)) -#define RTC_IO_TOUCH_PAD6_RDE_V 0x1 -#define RTC_IO_TOUCH_PAD6_RDE_S 28 -/* RTC_IO_TOUCH_PAD6_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */ -/*description: the pull up enable of the pad*/ -#define RTC_IO_TOUCH_PAD6_RUE (BIT(27)) -#define RTC_IO_TOUCH_PAD6_RUE_M (BIT(27)) -#define RTC_IO_TOUCH_PAD6_RUE_V 0x1 -#define RTC_IO_TOUCH_PAD6_RUE_S 27 -/* RTC_IO_TOUCH_PAD6_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ -/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ -#define RTC_IO_TOUCH_PAD6_DAC 0x00000007 -#define RTC_IO_TOUCH_PAD6_DAC_M ((RTC_IO_TOUCH_PAD6_DAC_V)<<(RTC_IO_TOUCH_PAD6_DAC_S)) -#define RTC_IO_TOUCH_PAD6_DAC_V 0x7 -#define RTC_IO_TOUCH_PAD6_DAC_S 23 -/* RTC_IO_TOUCH_PAD6_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: start touch sensor.*/ -#define RTC_IO_TOUCH_PAD6_START (BIT(22)) -#define RTC_IO_TOUCH_PAD6_START_M (BIT(22)) -#define RTC_IO_TOUCH_PAD6_START_V 0x1 -#define RTC_IO_TOUCH_PAD6_START_S 22 -/* RTC_IO_TOUCH_PAD6_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ -#define RTC_IO_TOUCH_PAD6_TIE_OPT (BIT(21)) -#define RTC_IO_TOUCH_PAD6_TIE_OPT_M (BIT(21)) -#define RTC_IO_TOUCH_PAD6_TIE_OPT_V 0x1 -#define RTC_IO_TOUCH_PAD6_TIE_OPT_S 21 -/* RTC_IO_TOUCH_PAD6_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: touch sensor power on.*/ -#define RTC_IO_TOUCH_PAD6_XPD (BIT(20)) -#define RTC_IO_TOUCH_PAD6_XPD_M (BIT(20)) -#define RTC_IO_TOUCH_PAD6_XPD_V 0x1 -#define RTC_IO_TOUCH_PAD6_XPD_S 20 -/* RTC_IO_TOUCH_PAD6_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ -#define RTC_IO_TOUCH_PAD6_MUX_SEL (BIT(19)) -#define RTC_IO_TOUCH_PAD6_MUX_SEL_M (BIT(19)) -#define RTC_IO_TOUCH_PAD6_MUX_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD6_MUX_SEL_S 19 -/* RTC_IO_TOUCH_PAD6_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ -/*description: the functional selection signal of the pad*/ -#define RTC_IO_TOUCH_PAD6_FUN_SEL 0x00000003 -#define RTC_IO_TOUCH_PAD6_FUN_SEL_M ((RTC_IO_TOUCH_PAD6_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD6_FUN_SEL_S)) -#define RTC_IO_TOUCH_PAD6_FUN_SEL_V 0x3 -#define RTC_IO_TOUCH_PAD6_FUN_SEL_S 17 -/* RTC_IO_TOUCH_PAD6_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: the sleep status selection signal of the pad*/ -#define RTC_IO_TOUCH_PAD6_SLP_SEL (BIT(16)) -#define RTC_IO_TOUCH_PAD6_SLP_SEL_M (BIT(16)) -#define RTC_IO_TOUCH_PAD6_SLP_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD6_SLP_SEL_S 16 -/* RTC_IO_TOUCH_PAD6_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: the input enable of the pad in sleep status*/ -#define RTC_IO_TOUCH_PAD6_SLP_IE (BIT(15)) -#define RTC_IO_TOUCH_PAD6_SLP_IE_M (BIT(15)) -#define RTC_IO_TOUCH_PAD6_SLP_IE_V 0x1 -#define RTC_IO_TOUCH_PAD6_SLP_IE_S 15 -/* RTC_IO_TOUCH_PAD6_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: the output enable of the pad in sleep status*/ -#define RTC_IO_TOUCH_PAD6_SLP_OE (BIT(14)) -#define RTC_IO_TOUCH_PAD6_SLP_OE_M (BIT(14)) -#define RTC_IO_TOUCH_PAD6_SLP_OE_V 0x1 -#define RTC_IO_TOUCH_PAD6_SLP_OE_S 14 -/* RTC_IO_TOUCH_PAD6_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: the input enable of the pad*/ -#define RTC_IO_TOUCH_PAD6_FUN_IE (BIT(13)) -#define RTC_IO_TOUCH_PAD6_FUN_IE_M (BIT(13)) -#define RTC_IO_TOUCH_PAD6_FUN_IE_V 0x1 -#define RTC_IO_TOUCH_PAD6_FUN_IE_S 13 -/* RTC_IO_TOUCH_PAD6_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTMS*/ -#define RTC_IO_TOUCH_PAD6_TO_GPIO (BIT(12)) -#define RTC_IO_TOUCH_PAD6_TO_GPIO_M (BIT(12)) -#define RTC_IO_TOUCH_PAD6_TO_GPIO_V 0x1 -#define RTC_IO_TOUCH_PAD6_TO_GPIO_S 12 - -#define RTC_IO_TOUCH_PAD7_REG (DR_REG_RTCIO_BASE + 0xb0) -/* RTC_IO_TOUCH_PAD7_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: hold the current value of the output when setting the hold to Ò1Ó*/ -#define RTC_IO_TOUCH_PAD7_HOLD (BIT(31)) -#define RTC_IO_TOUCH_PAD7_HOLD_M (BIT(31)) -#define RTC_IO_TOUCH_PAD7_HOLD_V 0x1 -#define RTC_IO_TOUCH_PAD7_HOLD_S 31 -/* RTC_IO_TOUCH_PAD7_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ -/*description: the driver strength of the pad*/ -#define RTC_IO_TOUCH_PAD7_DRV 0x00000003 -#define RTC_IO_TOUCH_PAD7_DRV_M ((RTC_IO_TOUCH_PAD7_DRV_V)<<(RTC_IO_TOUCH_PAD7_DRV_S)) -#define RTC_IO_TOUCH_PAD7_DRV_V 0x3 -#define RTC_IO_TOUCH_PAD7_DRV_S 29 -/* RTC_IO_TOUCH_PAD7_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: the pull down enable of the pad*/ -#define RTC_IO_TOUCH_PAD7_RDE (BIT(28)) -#define RTC_IO_TOUCH_PAD7_RDE_M (BIT(28)) -#define RTC_IO_TOUCH_PAD7_RDE_V 0x1 -#define RTC_IO_TOUCH_PAD7_RDE_S 28 -/* RTC_IO_TOUCH_PAD7_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: the pull up enable of the pad*/ -#define RTC_IO_TOUCH_PAD7_RUE (BIT(27)) -#define RTC_IO_TOUCH_PAD7_RUE_M (BIT(27)) -#define RTC_IO_TOUCH_PAD7_RUE_V 0x1 -#define RTC_IO_TOUCH_PAD7_RUE_S 27 -/* RTC_IO_TOUCH_PAD7_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ -/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ -#define RTC_IO_TOUCH_PAD7_DAC 0x00000007 -#define RTC_IO_TOUCH_PAD7_DAC_M ((RTC_IO_TOUCH_PAD7_DAC_V)<<(RTC_IO_TOUCH_PAD7_DAC_S)) -#define RTC_IO_TOUCH_PAD7_DAC_V 0x7 -#define RTC_IO_TOUCH_PAD7_DAC_S 23 -/* RTC_IO_TOUCH_PAD7_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: start touch sensor.*/ -#define RTC_IO_TOUCH_PAD7_START (BIT(22)) -#define RTC_IO_TOUCH_PAD7_START_M (BIT(22)) -#define RTC_IO_TOUCH_PAD7_START_V 0x1 -#define RTC_IO_TOUCH_PAD7_START_S 22 -/* RTC_IO_TOUCH_PAD7_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ -#define RTC_IO_TOUCH_PAD7_TIE_OPT (BIT(21)) -#define RTC_IO_TOUCH_PAD7_TIE_OPT_M (BIT(21)) -#define RTC_IO_TOUCH_PAD7_TIE_OPT_V 0x1 -#define RTC_IO_TOUCH_PAD7_TIE_OPT_S 21 -/* RTC_IO_TOUCH_PAD7_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: touch sensor power on.*/ -#define RTC_IO_TOUCH_PAD7_XPD (BIT(20)) -#define RTC_IO_TOUCH_PAD7_XPD_M (BIT(20)) -#define RTC_IO_TOUCH_PAD7_XPD_V 0x1 -#define RTC_IO_TOUCH_PAD7_XPD_S 20 -/* RTC_IO_TOUCH_PAD7_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ -#define RTC_IO_TOUCH_PAD7_MUX_SEL (BIT(19)) -#define RTC_IO_TOUCH_PAD7_MUX_SEL_M (BIT(19)) -#define RTC_IO_TOUCH_PAD7_MUX_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD7_MUX_SEL_S 19 -/* RTC_IO_TOUCH_PAD7_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ -/*description: the functional selection signal of the pad*/ -#define RTC_IO_TOUCH_PAD7_FUN_SEL 0x00000003 -#define RTC_IO_TOUCH_PAD7_FUN_SEL_M ((RTC_IO_TOUCH_PAD7_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD7_FUN_SEL_S)) -#define RTC_IO_TOUCH_PAD7_FUN_SEL_V 0x3 -#define RTC_IO_TOUCH_PAD7_FUN_SEL_S 17 -/* RTC_IO_TOUCH_PAD7_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: the sleep status selection signal of the pad*/ -#define RTC_IO_TOUCH_PAD7_SLP_SEL (BIT(16)) -#define RTC_IO_TOUCH_PAD7_SLP_SEL_M (BIT(16)) -#define RTC_IO_TOUCH_PAD7_SLP_SEL_V 0x1 -#define RTC_IO_TOUCH_PAD7_SLP_SEL_S 16 -/* RTC_IO_TOUCH_PAD7_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: the input enable of the pad in sleep status*/ -#define RTC_IO_TOUCH_PAD7_SLP_IE (BIT(15)) -#define RTC_IO_TOUCH_PAD7_SLP_IE_M (BIT(15)) -#define RTC_IO_TOUCH_PAD7_SLP_IE_V 0x1 -#define RTC_IO_TOUCH_PAD7_SLP_IE_S 15 -/* RTC_IO_TOUCH_PAD7_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: the output enable of the pad in sleep status*/ -#define RTC_IO_TOUCH_PAD7_SLP_OE (BIT(14)) -#define RTC_IO_TOUCH_PAD7_SLP_OE_M (BIT(14)) -#define RTC_IO_TOUCH_PAD7_SLP_OE_V 0x1 -#define RTC_IO_TOUCH_PAD7_SLP_OE_S 14 -/* RTC_IO_TOUCH_PAD7_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: the input enable of the pad*/ -#define RTC_IO_TOUCH_PAD7_FUN_IE (BIT(13)) -#define RTC_IO_TOUCH_PAD7_FUN_IE_M (BIT(13)) -#define RTC_IO_TOUCH_PAD7_FUN_IE_V 0x1 -#define RTC_IO_TOUCH_PAD7_FUN_IE_S 13 -/* RTC_IO_TOUCH_PAD7_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO27*/ -#define RTC_IO_TOUCH_PAD7_TO_GPIO (BIT(12)) -#define RTC_IO_TOUCH_PAD7_TO_GPIO_M (BIT(12)) -#define RTC_IO_TOUCH_PAD7_TO_GPIO_V 0x1 -#define RTC_IO_TOUCH_PAD7_TO_GPIO_S 12 - -#define RTC_IO_TOUCH_PAD8_REG (DR_REG_RTCIO_BASE + 0xb4) -/* RTC_IO_TOUCH_PAD8_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ -/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ -#define RTC_IO_TOUCH_PAD8_DAC 0x00000007 -#define RTC_IO_TOUCH_PAD8_DAC_M ((RTC_IO_TOUCH_PAD8_DAC_V)<<(RTC_IO_TOUCH_PAD8_DAC_S)) -#define RTC_IO_TOUCH_PAD8_DAC_V 0x7 -#define RTC_IO_TOUCH_PAD8_DAC_S 23 -/* RTC_IO_TOUCH_PAD8_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: start touch sensor.*/ -#define RTC_IO_TOUCH_PAD8_START (BIT(22)) -#define RTC_IO_TOUCH_PAD8_START_M (BIT(22)) -#define RTC_IO_TOUCH_PAD8_START_V 0x1 -#define RTC_IO_TOUCH_PAD8_START_S 22 -/* RTC_IO_TOUCH_PAD8_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ -#define RTC_IO_TOUCH_PAD8_TIE_OPT (BIT(21)) -#define RTC_IO_TOUCH_PAD8_TIE_OPT_M (BIT(21)) -#define RTC_IO_TOUCH_PAD8_TIE_OPT_V 0x1 -#define RTC_IO_TOUCH_PAD8_TIE_OPT_S 21 -/* RTC_IO_TOUCH_PAD8_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: touch sensor power on.*/ -#define RTC_IO_TOUCH_PAD8_XPD (BIT(20)) -#define RTC_IO_TOUCH_PAD8_XPD_M (BIT(20)) -#define RTC_IO_TOUCH_PAD8_XPD_V 0x1 -#define RTC_IO_TOUCH_PAD8_XPD_S 20 -/* RTC_IO_TOUCH_PAD8_TO_GPIO : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale*/ -#define RTC_IO_TOUCH_PAD8_TO_GPIO (BIT(19)) -#define RTC_IO_TOUCH_PAD8_TO_GPIO_M (BIT(19)) -#define RTC_IO_TOUCH_PAD8_TO_GPIO_V 0x1 -#define RTC_IO_TOUCH_PAD8_TO_GPIO_S 19 - -#define RTC_IO_TOUCH_PAD9_REG (DR_REG_RTCIO_BASE + 0xb8) -/* RTC_IO_TOUCH_PAD9_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ -/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ -#define RTC_IO_TOUCH_PAD9_DAC 0x00000007 -#define RTC_IO_TOUCH_PAD9_DAC_M ((RTC_IO_TOUCH_PAD9_DAC_V)<<(RTC_IO_TOUCH_PAD9_DAC_S)) -#define RTC_IO_TOUCH_PAD9_DAC_V 0x7 -#define RTC_IO_TOUCH_PAD9_DAC_S 23 -/* RTC_IO_TOUCH_PAD9_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: start touch sensor.*/ -#define RTC_IO_TOUCH_PAD9_START (BIT(22)) -#define RTC_IO_TOUCH_PAD9_START_M (BIT(22)) -#define RTC_IO_TOUCH_PAD9_START_V 0x1 -#define RTC_IO_TOUCH_PAD9_START_S 22 -/* RTC_IO_TOUCH_PAD9_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ -#define RTC_IO_TOUCH_PAD9_TIE_OPT (BIT(21)) -#define RTC_IO_TOUCH_PAD9_TIE_OPT_M (BIT(21)) -#define RTC_IO_TOUCH_PAD9_TIE_OPT_V 0x1 -#define RTC_IO_TOUCH_PAD9_TIE_OPT_S 21 -/* RTC_IO_TOUCH_PAD9_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: touch sensor power on.*/ -#define RTC_IO_TOUCH_PAD9_XPD (BIT(20)) -#define RTC_IO_TOUCH_PAD9_XPD_M (BIT(20)) -#define RTC_IO_TOUCH_PAD9_XPD_V 0x1 -#define RTC_IO_TOUCH_PAD9_XPD_S 20 -/* RTC_IO_TOUCH_PAD9_TO_GPIO : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale*/ -#define RTC_IO_TOUCH_PAD9_TO_GPIO (BIT(19)) -#define RTC_IO_TOUCH_PAD9_TO_GPIO_M (BIT(19)) -#define RTC_IO_TOUCH_PAD9_TO_GPIO_V 0x1 -#define RTC_IO_TOUCH_PAD9_TO_GPIO_S 19 - -#define RTC_IO_EXT_WAKEUP0_REG (DR_REG_RTCIO_BASE + 0xbc) -/* RTC_IO_EXT_WAKEUP0_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */ -/*description: select the wakeup source Ó0Ó select GPIO0 Ó1Ó select GPIO2 ...Ò17Ó select GPIO17*/ -#define RTC_IO_EXT_WAKEUP0_SEL 0x0000001F -#define RTC_IO_EXT_WAKEUP0_SEL_M ((RTC_IO_EXT_WAKEUP0_SEL_V)<<(RTC_IO_EXT_WAKEUP0_SEL_S)) -#define RTC_IO_EXT_WAKEUP0_SEL_V 0x1F -#define RTC_IO_EXT_WAKEUP0_SEL_S 27 - -#define RTC_IO_XTL_EXT_CTR_REG (DR_REG_RTCIO_BASE + 0xc0) -/* RTC_IO_XTL_EXT_CTR_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */ -/*description: select the external xtl power source Ó0Ó select GPIO0 Ó1Ó select - GPIO2 ...Ò17Ó select GPIO17*/ -#define RTC_IO_XTL_EXT_CTR_SEL 0x0000001F -#define RTC_IO_XTL_EXT_CTR_SEL_M ((RTC_IO_XTL_EXT_CTR_SEL_V)<<(RTC_IO_XTL_EXT_CTR_SEL_S)) -#define RTC_IO_XTL_EXT_CTR_SEL_V 0x1F -#define RTC_IO_XTL_EXT_CTR_SEL_S 27 - -#define RTC_IO_SAR_I2C_IO_REG (DR_REG_RTCIO_BASE + 0xc4) -/* RTC_IO_SAR_I2C_SDA_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ -/*description: Ò0Ó using TOUCH_PAD[1] as i2c sda Ò1Ó using TOUCH_PAD[3] as i2c sda*/ -#define RTC_IO_SAR_I2C_SDA_SEL 0x00000003 -#define RTC_IO_SAR_I2C_SDA_SEL_M ((RTC_IO_SAR_I2C_SDA_SEL_V)<<(RTC_IO_SAR_I2C_SDA_SEL_S)) -#define RTC_IO_SAR_I2C_SDA_SEL_V 0x3 -#define RTC_IO_SAR_I2C_SDA_SEL_S 30 -/* RTC_IO_SAR_I2C_SCL_SEL : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ -/*description: Ò0Ó using TOUCH_PAD[0] as i2c clk Ò1Ó using TOUCH_PAD[2] as i2c clk*/ -#define RTC_IO_SAR_I2C_SCL_SEL 0x00000003 -#define RTC_IO_SAR_I2C_SCL_SEL_M ((RTC_IO_SAR_I2C_SCL_SEL_V)<<(RTC_IO_SAR_I2C_SCL_SEL_S)) -#define RTC_IO_SAR_I2C_SCL_SEL_V 0x3 -#define RTC_IO_SAR_I2C_SCL_SEL_S 28 -/* RTC_IO_SAR_DEBUG_BIT_SEL : R/W ;bitpos:[27:23] ;default: 5'h0 ; */ -/*description: */ -#define RTC_IO_SAR_DEBUG_BIT_SEL 0x0000001F -#define RTC_IO_SAR_DEBUG_BIT_SEL_M ((RTC_IO_SAR_DEBUG_BIT_SEL_V)<<(RTC_IO_SAR_DEBUG_BIT_SEL_S)) -#define RTC_IO_SAR_DEBUG_BIT_SEL_V 0x1F -#define RTC_IO_SAR_DEBUG_BIT_SEL_S 23 - -#define RTC_IO_DATE_REG (DR_REG_RTCIO_BASE + 0xc8) -/* RTC_IO_IO_DATE : R/W ;bitpos:[27:0] ;default: 28'h1603160 ; */ -/*description: date*/ -#define RTC_IO_IO_DATE 0x0FFFFFFF -#define RTC_IO_IO_DATE_M ((RTC_IO_IO_DATE_V)<<(RTC_IO_IO_DATE_S)) -#define RTC_IO_IO_DATE_V 0xFFFFFFF -#define RTC_IO_IO_DATE_S 0 -#define RTC_IO_RTC_IO_DATE_VERSION 0x1703160 - - - - -#endif /*_SOC_RTC_IO_REG_H_ */ - - +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_RTC_IO_REG_H_ +#define _SOC_RTC_IO_REG_H_ + + +#include "soc.h" +#define RTC_GPIO_OUT_REG (DR_REG_RTCIO_BASE + 0x0) +/* RTC_GPIO_OUT_DATA : R/W ;bitpos:[31:14] ;default: 0 ; */ +/*description: GPIO0~17 output value*/ +#define RTC_GPIO_OUT_DATA 0x0003FFFF +#define RTC_GPIO_OUT_DATA_M ((RTC_GPIO_OUT_DATA_V)<<(RTC_GPIO_OUT_DATA_S)) +#define RTC_GPIO_OUT_DATA_V 0x3FFFF +#define RTC_GPIO_OUT_DATA_S 14 + +#define RTC_GPIO_OUT_W1TS_REG (DR_REG_RTCIO_BASE + 0x4) +/* RTC_GPIO_OUT_DATA_W1TS : WO ;bitpos:[31:14] ;default: 0 ; */ +/*description: GPIO0~17 output value write 1 to set*/ +#define RTC_GPIO_OUT_DATA_W1TS 0x0003FFFF +#define RTC_GPIO_OUT_DATA_W1TS_M ((RTC_GPIO_OUT_DATA_W1TS_V)<<(RTC_GPIO_OUT_DATA_W1TS_S)) +#define RTC_GPIO_OUT_DATA_W1TS_V 0x3FFFF +#define RTC_GPIO_OUT_DATA_W1TS_S 14 + +#define RTC_GPIO_OUT_W1TC_REG (DR_REG_RTCIO_BASE + 0x8) +/* RTC_GPIO_OUT_DATA_W1TC : WO ;bitpos:[31:14] ;default: 0 ; */ +/*description: GPIO0~17 output value write 1 to clear*/ +#define RTC_GPIO_OUT_DATA_W1TC 0x0003FFFF +#define RTC_GPIO_OUT_DATA_W1TC_M ((RTC_GPIO_OUT_DATA_W1TC_V)<<(RTC_GPIO_OUT_DATA_W1TC_S)) +#define RTC_GPIO_OUT_DATA_W1TC_V 0x3FFFF +#define RTC_GPIO_OUT_DATA_W1TC_S 14 + +#define RTC_GPIO_ENABLE_REG (DR_REG_RTCIO_BASE + 0xc) +/* RTC_GPIO_ENABLE : R/W ;bitpos:[31:14] ;default: 0 ; */ +/*description: GPIO0~17 output enable*/ +#define RTC_GPIO_ENABLE 0x0003FFFF +#define RTC_GPIO_ENABLE_M ((RTC_GPIO_ENABLE_V)<<(RTC_GPIO_ENABLE_S)) +#define RTC_GPIO_ENABLE_V 0x3FFFF +#define RTC_GPIO_ENABLE_S 14 + +#define RTC_GPIO_ENABLE_W1TS_REG (DR_REG_RTCIO_BASE + 0x10) +/* RTC_GPIO_ENABLE_W1TS : WO ;bitpos:[31:14] ;default: 0 ; */ +/*description: GPIO0~17 output enable write 1 to set*/ +#define RTC_GPIO_ENABLE_W1TS 0x0003FFFF +#define RTC_GPIO_ENABLE_W1TS_M ((RTC_GPIO_ENABLE_W1TS_V)<<(RTC_GPIO_ENABLE_W1TS_S)) +#define RTC_GPIO_ENABLE_W1TS_V 0x3FFFF +#define RTC_GPIO_ENABLE_W1TS_S 14 + +#define RTC_GPIO_ENABLE_W1TC_REG (DR_REG_RTCIO_BASE + 0x14) +/* RTC_GPIO_ENABLE_W1TC : WO ;bitpos:[31:14] ;default: 0 ; */ +/*description: GPIO0~17 output enable write 1 to clear*/ +#define RTC_GPIO_ENABLE_W1TC 0x0003FFFF +#define RTC_GPIO_ENABLE_W1TC_M ((RTC_GPIO_ENABLE_W1TC_V)<<(RTC_GPIO_ENABLE_W1TC_S)) +#define RTC_GPIO_ENABLE_W1TC_V 0x3FFFF +#define RTC_GPIO_ENABLE_W1TC_S 14 + +#define RTC_GPIO_STATUS_REG (DR_REG_RTCIO_BASE + 0x18) +/* RTC_GPIO_STATUS_INT : R/W ;bitpos:[31:14] ;default: 0 ; */ +/*description: GPIO0~17 interrupt status*/ +#define RTC_GPIO_STATUS_INT 0x0003FFFF +#define RTC_GPIO_STATUS_INT_M ((RTC_GPIO_STATUS_INT_V)<<(RTC_GPIO_STATUS_INT_S)) +#define RTC_GPIO_STATUS_INT_V 0x3FFFF +#define RTC_GPIO_STATUS_INT_S 14 + +#define RTC_GPIO_STATUS_W1TS_REG (DR_REG_RTCIO_BASE + 0x1c) +/* RTC_GPIO_STATUS_INT_W1TS : WO ;bitpos:[31:14] ;default: 0 ; */ +/*description: GPIO0~17 interrupt status write 1 to set*/ +#define RTC_GPIO_STATUS_INT_W1TS 0x0003FFFF +#define RTC_GPIO_STATUS_INT_W1TS_M ((RTC_GPIO_STATUS_INT_W1TS_V)<<(RTC_GPIO_STATUS_INT_W1TS_S)) +#define RTC_GPIO_STATUS_INT_W1TS_V 0x3FFFF +#define RTC_GPIO_STATUS_INT_W1TS_S 14 + +#define RTC_GPIO_STATUS_W1TC_REG (DR_REG_RTCIO_BASE + 0x20) +/* RTC_GPIO_STATUS_INT_W1TC : WO ;bitpos:[31:14] ;default: 0 ; */ +/*description: GPIO0~17 interrupt status write 1 to clear*/ +#define RTC_GPIO_STATUS_INT_W1TC 0x0003FFFF +#define RTC_GPIO_STATUS_INT_W1TC_M ((RTC_GPIO_STATUS_INT_W1TC_V)<<(RTC_GPIO_STATUS_INT_W1TC_S)) +#define RTC_GPIO_STATUS_INT_W1TC_V 0x3FFFF +#define RTC_GPIO_STATUS_INT_W1TC_S 14 + +#define RTC_GPIO_IN_REG (DR_REG_RTCIO_BASE + 0x24) +/* RTC_GPIO_IN_NEXT : RO ;bitpos:[31:14] ;default: ; */ +/*description: GPIO0~17 input value*/ +#define RTC_GPIO_IN_NEXT 0x0003FFFF +#define RTC_GPIO_IN_NEXT_M ((RTC_GPIO_IN_NEXT_V)<<(RTC_GPIO_IN_NEXT_S)) +#define RTC_GPIO_IN_NEXT_V 0x3FFFF +#define RTC_GPIO_IN_NEXT_S 14 + +#define RTC_GPIO_PIN0_REG (DR_REG_RTCIO_BASE + 0x28) +/* RTC_GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN0_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN0_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN0_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN0_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN0_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN0_INT_TYPE_M ((RTC_GPIO_PIN0_INT_TYPE_V)<<(RTC_GPIO_PIN0_INT_TYPE_S)) +#define RTC_GPIO_PIN0_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN0_INT_TYPE_S 7 +/* RTC_GPIO_PIN0_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN0_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN0_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN0_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN0_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN1_REG (DR_REG_RTCIO_BASE + 0x2c) +/* RTC_GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN1_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN1_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN1_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN1_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN1_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN1_INT_TYPE_M ((RTC_GPIO_PIN1_INT_TYPE_V)<<(RTC_GPIO_PIN1_INT_TYPE_S)) +#define RTC_GPIO_PIN1_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN1_INT_TYPE_S 7 +/* RTC_GPIO_PIN1_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN1_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN1_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN1_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN1_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN2_REG (DR_REG_RTCIO_BASE + 0x30) +/* RTC_GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN2_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN2_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN2_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN2_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN2_INT_TYPE_M ((RTC_GPIO_PIN2_INT_TYPE_V)<<(RTC_GPIO_PIN2_INT_TYPE_S)) +#define RTC_GPIO_PIN2_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN2_INT_TYPE_S 7 +/* RTC_GPIO_PIN2_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN2_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN2_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN2_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN2_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN3_REG (DR_REG_RTCIO_BASE + 0x34) +/* RTC_GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN3_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN3_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN3_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN3_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN3_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN3_INT_TYPE_M ((RTC_GPIO_PIN3_INT_TYPE_V)<<(RTC_GPIO_PIN3_INT_TYPE_S)) +#define RTC_GPIO_PIN3_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN3_INT_TYPE_S 7 +/* RTC_GPIO_PIN3_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN3_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN3_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN3_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN3_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN4_REG (DR_REG_RTCIO_BASE + 0x38) +/* RTC_GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN4_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN4_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN4_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN4_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN4_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN4_INT_TYPE_M ((RTC_GPIO_PIN4_INT_TYPE_V)<<(RTC_GPIO_PIN4_INT_TYPE_S)) +#define RTC_GPIO_PIN4_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN4_INT_TYPE_S 7 +/* RTC_GPIO_PIN4_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN4_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN4_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN4_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN4_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN5_REG (DR_REG_RTCIO_BASE + 0x3c) +/* RTC_GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN5_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN5_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN5_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN5_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN5_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN5_INT_TYPE_M ((RTC_GPIO_PIN5_INT_TYPE_V)<<(RTC_GPIO_PIN5_INT_TYPE_S)) +#define RTC_GPIO_PIN5_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN5_INT_TYPE_S 7 +/* RTC_GPIO_PIN5_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN5_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN5_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN5_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN5_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN6_REG (DR_REG_RTCIO_BASE + 0x40) +/* RTC_GPIO_PIN6_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN6_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN6_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN6_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN6_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN6_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN6_INT_TYPE_M ((RTC_GPIO_PIN6_INT_TYPE_V)<<(RTC_GPIO_PIN6_INT_TYPE_S)) +#define RTC_GPIO_PIN6_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN6_INT_TYPE_S 7 +/* RTC_GPIO_PIN6_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN6_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN6_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN6_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN6_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN7_REG (DR_REG_RTCIO_BASE + 0x44) +/* RTC_GPIO_PIN7_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN7_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN7_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN7_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN7_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN7_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN7_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN7_INT_TYPE_M ((RTC_GPIO_PIN7_INT_TYPE_V)<<(RTC_GPIO_PIN7_INT_TYPE_S)) +#define RTC_GPIO_PIN7_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN7_INT_TYPE_S 7 +/* RTC_GPIO_PIN7_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN7_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN7_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN7_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN7_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN8_REG (DR_REG_RTCIO_BASE + 0x48) +/* RTC_GPIO_PIN8_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN8_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN8_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN8_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN8_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN8_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN8_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN8_INT_TYPE_M ((RTC_GPIO_PIN8_INT_TYPE_V)<<(RTC_GPIO_PIN8_INT_TYPE_S)) +#define RTC_GPIO_PIN8_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN8_INT_TYPE_S 7 +/* RTC_GPIO_PIN8_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN8_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN8_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN8_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN8_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN9_REG (DR_REG_RTCIO_BASE + 0x4c) +/* RTC_GPIO_PIN9_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN9_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN9_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN9_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN9_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN9_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN9_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN9_INT_TYPE_M ((RTC_GPIO_PIN9_INT_TYPE_V)<<(RTC_GPIO_PIN9_INT_TYPE_S)) +#define RTC_GPIO_PIN9_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN9_INT_TYPE_S 7 +/* RTC_GPIO_PIN9_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN9_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN9_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN9_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN9_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN10_REG (DR_REG_RTCIO_BASE + 0x50) +/* RTC_GPIO_PIN10_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN10_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN10_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN10_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN10_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN10_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN10_INT_TYPE_M ((RTC_GPIO_PIN10_INT_TYPE_V)<<(RTC_GPIO_PIN10_INT_TYPE_S)) +#define RTC_GPIO_PIN10_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN10_INT_TYPE_S 7 +/* RTC_GPIO_PIN10_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN10_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN10_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN10_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN10_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN11_REG (DR_REG_RTCIO_BASE + 0x54) +/* RTC_GPIO_PIN11_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN11_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN11_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN11_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN11_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN11_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN11_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN11_INT_TYPE_M ((RTC_GPIO_PIN11_INT_TYPE_V)<<(RTC_GPIO_PIN11_INT_TYPE_S)) +#define RTC_GPIO_PIN11_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN11_INT_TYPE_S 7 +/* RTC_GPIO_PIN11_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN11_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN11_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN11_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN11_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN12_REG (DR_REG_RTCIO_BASE + 0x58) +/* RTC_GPIO_PIN12_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN12_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN12_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN12_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN12_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN12_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN12_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN12_INT_TYPE_M ((RTC_GPIO_PIN12_INT_TYPE_V)<<(RTC_GPIO_PIN12_INT_TYPE_S)) +#define RTC_GPIO_PIN12_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN12_INT_TYPE_S 7 +/* RTC_GPIO_PIN12_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN12_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN12_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN12_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN12_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN13_REG (DR_REG_RTCIO_BASE + 0x5c) +/* RTC_GPIO_PIN13_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN13_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN13_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN13_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN13_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN13_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN13_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN13_INT_TYPE_M ((RTC_GPIO_PIN13_INT_TYPE_V)<<(RTC_GPIO_PIN13_INT_TYPE_S)) +#define RTC_GPIO_PIN13_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN13_INT_TYPE_S 7 +/* RTC_GPIO_PIN13_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN13_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN13_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN13_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN13_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN14_REG (DR_REG_RTCIO_BASE + 0x60) +/* RTC_GPIO_PIN14_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN14_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN14_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN14_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN14_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN14_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN14_INT_TYPE_M ((RTC_GPIO_PIN14_INT_TYPE_V)<<(RTC_GPIO_PIN14_INT_TYPE_S)) +#define RTC_GPIO_PIN14_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN14_INT_TYPE_S 7 +/* RTC_GPIO_PIN14_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN14_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN14_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN14_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN14_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN15_REG (DR_REG_RTCIO_BASE + 0x64) +/* RTC_GPIO_PIN15_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN15_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN15_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN15_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN15_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN15_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN15_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN15_INT_TYPE_M ((RTC_GPIO_PIN15_INT_TYPE_V)<<(RTC_GPIO_PIN15_INT_TYPE_S)) +#define RTC_GPIO_PIN15_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN15_INT_TYPE_S 7 +/* RTC_GPIO_PIN15_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN15_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN15_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN15_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN15_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN16_REG (DR_REG_RTCIO_BASE + 0x68) +/* RTC_GPIO_PIN16_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN16_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN16_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN16_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN16_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN16_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN16_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN16_INT_TYPE_M ((RTC_GPIO_PIN16_INT_TYPE_V)<<(RTC_GPIO_PIN16_INT_TYPE_S)) +#define RTC_GPIO_PIN16_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN16_INT_TYPE_S 7 +/* RTC_GPIO_PIN16_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN16_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN16_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN16_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN16_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN17_REG (DR_REG_RTCIO_BASE + 0x6c) +/* RTC_GPIO_PIN17_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: GPIO wake up enable only available in light sleep*/ +#define RTC_GPIO_PIN17_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN17_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN17_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN17_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN17_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN17_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN17_INT_TYPE_M ((RTC_GPIO_PIN17_INT_TYPE_V)<<(RTC_GPIO_PIN17_INT_TYPE_S)) +#define RTC_GPIO_PIN17_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN17_INT_TYPE_S 7 +/* RTC_GPIO_PIN17_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN17_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN17_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN17_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN17_PAD_DRIVER_S 2 + +#define RTC_IO_RTC_DEBUG_SEL_REG (DR_REG_RTCIO_BASE + 0x70) +/* RTC_IO_DEBUG_12M_NO_GATING : R/W ;bitpos:[25] ;default: 1'd0 ; */ +/*description: */ +#define RTC_IO_DEBUG_12M_NO_GATING (BIT(25)) +#define RTC_IO_DEBUG_12M_NO_GATING_M (BIT(25)) +#define RTC_IO_DEBUG_12M_NO_GATING_V 0x1 +#define RTC_IO_DEBUG_12M_NO_GATING_S 25 +/* RTC_IO_DEBUG_SEL4 : R/W ;bitpos:[24:20] ;default: 5'd0 ; */ +/*description: */ +#define RTC_IO_DEBUG_SEL4 0x0000001F +#define RTC_IO_DEBUG_SEL4_M ((RTC_IO_DEBUG_SEL4_V)<<(RTC_IO_DEBUG_SEL4_S)) +#define RTC_IO_DEBUG_SEL4_V 0x1F +#define RTC_IO_DEBUG_SEL4_S 20 +/* RTC_IO_DEBUG_SEL3 : R/W ;bitpos:[19:15] ;default: 5'd0 ; */ +/*description: */ +#define RTC_IO_DEBUG_SEL3 0x0000001F +#define RTC_IO_DEBUG_SEL3_M ((RTC_IO_DEBUG_SEL3_V)<<(RTC_IO_DEBUG_SEL3_S)) +#define RTC_IO_DEBUG_SEL3_V 0x1F +#define RTC_IO_DEBUG_SEL3_S 15 +/* RTC_IO_DEBUG_SEL2 : R/W ;bitpos:[14:10] ;default: 5'd0 ; */ +/*description: */ +#define RTC_IO_DEBUG_SEL2 0x0000001F +#define RTC_IO_DEBUG_SEL2_M ((RTC_IO_DEBUG_SEL2_V)<<(RTC_IO_DEBUG_SEL2_S)) +#define RTC_IO_DEBUG_SEL2_V 0x1F +#define RTC_IO_DEBUG_SEL2_S 10 +/* RTC_IO_DEBUG_SEL1 : R/W ;bitpos:[9:5] ;default: 5'd0 ; */ +/*description: */ +#define RTC_IO_DEBUG_SEL1 0x0000001F +#define RTC_IO_DEBUG_SEL1_M ((RTC_IO_DEBUG_SEL1_V)<<(RTC_IO_DEBUG_SEL1_S)) +#define RTC_IO_DEBUG_SEL1_V 0x1F +#define RTC_IO_DEBUG_SEL1_S 5 +/* RTC_IO_DEBUG_SEL0 : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define RTC_IO_DEBUG_SEL0 0x0000001F +#define RTC_IO_DEBUG_SEL0_M ((RTC_IO_DEBUG_SEL0_V)<<(RTC_IO_DEBUG_SEL0_S)) +#define RTC_IO_DEBUG_SEL0_V 0x1F +#define RTC_IO_DEBUG_SEL0_S 0 + +#define RTC_IO_DIG_PAD_HOLD_REG (DR_REG_RTCIO_BASE + 0x74) +/* RTC_IO_DIG_PAD_HOLD : R/W ;bitpos:[31:0] ;default: 1'd0 ; */ +/*description: select the digital pad hold value.*/ +#define RTC_IO_DIG_PAD_HOLD 0xFFFFFFFF +#define RTC_IO_DIG_PAD_HOLD_M ((RTC_IO_DIG_PAD_HOLD_V)<<(RTC_IO_DIG_PAD_HOLD_S)) +#define RTC_IO_DIG_PAD_HOLD_V 0xFFFFFFFF +#define RTC_IO_DIG_PAD_HOLD_S 0 + +#define RTC_IO_HALL_SENS_REG (DR_REG_RTCIO_BASE + 0x78) +/* RTC_IO_XPD_HALL : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: Power on hall sensor and connect to VP and VN*/ +#define RTC_IO_XPD_HALL (BIT(31)) +#define RTC_IO_XPD_HALL_M (BIT(31)) +#define RTC_IO_XPD_HALL_V 0x1 +#define RTC_IO_XPD_HALL_S 31 +/* RTC_IO_HALL_PHASE : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: Reverse phase of hall sensor*/ +#define RTC_IO_HALL_PHASE (BIT(30)) +#define RTC_IO_HALL_PHASE_M (BIT(30)) +#define RTC_IO_HALL_PHASE_V 0x1 +#define RTC_IO_HALL_PHASE_S 30 + +#define RTC_IO_SENSOR_PADS_REG (DR_REG_RTCIO_BASE + 0x7c) +/* RTC_IO_SENSE1_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_SENSE1_HOLD (BIT(31)) +#define RTC_IO_SENSE1_HOLD_M (BIT(31)) +#define RTC_IO_SENSE1_HOLD_V 0x1 +#define RTC_IO_SENSE1_HOLD_S 31 +/* RTC_IO_SENSE2_HOLD : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_SENSE2_HOLD (BIT(30)) +#define RTC_IO_SENSE2_HOLD_M (BIT(30)) +#define RTC_IO_SENSE2_HOLD_V 0x1 +#define RTC_IO_SENSE2_HOLD_S 30 +/* RTC_IO_SENSE3_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_SENSE3_HOLD (BIT(29)) +#define RTC_IO_SENSE3_HOLD_M (BIT(29)) +#define RTC_IO_SENSE3_HOLD_V 0x1 +#define RTC_IO_SENSE3_HOLD_S 29 +/* RTC_IO_SENSE4_HOLD : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_SENSE4_HOLD (BIT(28)) +#define RTC_IO_SENSE4_HOLD_M (BIT(28)) +#define RTC_IO_SENSE4_HOLD_V 0x1 +#define RTC_IO_SENSE4_HOLD_S 28 +/* RTC_IO_SENSE1_MUX_SEL : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_SENSE1_MUX_SEL (BIT(27)) +#define RTC_IO_SENSE1_MUX_SEL_M (BIT(27)) +#define RTC_IO_SENSE1_MUX_SEL_V 0x1 +#define RTC_IO_SENSE1_MUX_SEL_S 27 +/* RTC_IO_SENSE2_MUX_SEL : R/W ;bitpos:[26] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_SENSE2_MUX_SEL (BIT(26)) +#define RTC_IO_SENSE2_MUX_SEL_M (BIT(26)) +#define RTC_IO_SENSE2_MUX_SEL_V 0x1 +#define RTC_IO_SENSE2_MUX_SEL_S 26 +/* RTC_IO_SENSE3_MUX_SEL : R/W ;bitpos:[25] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_SENSE3_MUX_SEL (BIT(25)) +#define RTC_IO_SENSE3_MUX_SEL_M (BIT(25)) +#define RTC_IO_SENSE3_MUX_SEL_V 0x1 +#define RTC_IO_SENSE3_MUX_SEL_S 25 +/* RTC_IO_SENSE4_MUX_SEL : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_SENSE4_MUX_SEL (BIT(24)) +#define RTC_IO_SENSE4_MUX_SEL_M (BIT(24)) +#define RTC_IO_SENSE4_MUX_SEL_V 0x1 +#define RTC_IO_SENSE4_MUX_SEL_S 24 +/* RTC_IO_SENSE1_FUN_SEL : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_SENSE1_FUN_SEL 0x00000003 +#define RTC_IO_SENSE1_FUN_SEL_M ((RTC_IO_SENSE1_FUN_SEL_V)<<(RTC_IO_SENSE1_FUN_SEL_S)) +#define RTC_IO_SENSE1_FUN_SEL_V 0x3 +#define RTC_IO_SENSE1_FUN_SEL_S 22 +/* RTC_IO_SENSE1_SLP_SEL : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_SENSE1_SLP_SEL (BIT(21)) +#define RTC_IO_SENSE1_SLP_SEL_M (BIT(21)) +#define RTC_IO_SENSE1_SLP_SEL_V 0x1 +#define RTC_IO_SENSE1_SLP_SEL_S 21 +/* RTC_IO_SENSE1_SLP_IE : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_SENSE1_SLP_IE (BIT(20)) +#define RTC_IO_SENSE1_SLP_IE_M (BIT(20)) +#define RTC_IO_SENSE1_SLP_IE_V 0x1 +#define RTC_IO_SENSE1_SLP_IE_S 20 +/* RTC_IO_SENSE1_FUN_IE : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_SENSE1_FUN_IE (BIT(19)) +#define RTC_IO_SENSE1_FUN_IE_M (BIT(19)) +#define RTC_IO_SENSE1_FUN_IE_V 0x1 +#define RTC_IO_SENSE1_FUN_IE_S 19 +/* RTC_IO_SENSE2_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_SENSE2_FUN_SEL 0x00000003 +#define RTC_IO_SENSE2_FUN_SEL_M ((RTC_IO_SENSE2_FUN_SEL_V)<<(RTC_IO_SENSE2_FUN_SEL_S)) +#define RTC_IO_SENSE2_FUN_SEL_V 0x3 +#define RTC_IO_SENSE2_FUN_SEL_S 17 +/* RTC_IO_SENSE2_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_SENSE2_SLP_SEL (BIT(16)) +#define RTC_IO_SENSE2_SLP_SEL_M (BIT(16)) +#define RTC_IO_SENSE2_SLP_SEL_V 0x1 +#define RTC_IO_SENSE2_SLP_SEL_S 16 +/* RTC_IO_SENSE2_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_SENSE2_SLP_IE (BIT(15)) +#define RTC_IO_SENSE2_SLP_IE_M (BIT(15)) +#define RTC_IO_SENSE2_SLP_IE_V 0x1 +#define RTC_IO_SENSE2_SLP_IE_S 15 +/* RTC_IO_SENSE2_FUN_IE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_SENSE2_FUN_IE (BIT(14)) +#define RTC_IO_SENSE2_FUN_IE_M (BIT(14)) +#define RTC_IO_SENSE2_FUN_IE_V 0x1 +#define RTC_IO_SENSE2_FUN_IE_S 14 +/* RTC_IO_SENSE3_FUN_SEL : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_SENSE3_FUN_SEL 0x00000003 +#define RTC_IO_SENSE3_FUN_SEL_M ((RTC_IO_SENSE3_FUN_SEL_V)<<(RTC_IO_SENSE3_FUN_SEL_S)) +#define RTC_IO_SENSE3_FUN_SEL_V 0x3 +#define RTC_IO_SENSE3_FUN_SEL_S 12 +/* RTC_IO_SENSE3_SLP_SEL : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_SENSE3_SLP_SEL (BIT(11)) +#define RTC_IO_SENSE3_SLP_SEL_M (BIT(11)) +#define RTC_IO_SENSE3_SLP_SEL_V 0x1 +#define RTC_IO_SENSE3_SLP_SEL_S 11 +/* RTC_IO_SENSE3_SLP_IE : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_SENSE3_SLP_IE (BIT(10)) +#define RTC_IO_SENSE3_SLP_IE_M (BIT(10)) +#define RTC_IO_SENSE3_SLP_IE_V 0x1 +#define RTC_IO_SENSE3_SLP_IE_S 10 +/* RTC_IO_SENSE3_FUN_IE : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_SENSE3_FUN_IE (BIT(9)) +#define RTC_IO_SENSE3_FUN_IE_M (BIT(9)) +#define RTC_IO_SENSE3_FUN_IE_V 0x1 +#define RTC_IO_SENSE3_FUN_IE_S 9 +/* RTC_IO_SENSE4_FUN_SEL : R/W ;bitpos:[8:7] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_SENSE4_FUN_SEL 0x00000003 +#define RTC_IO_SENSE4_FUN_SEL_M ((RTC_IO_SENSE4_FUN_SEL_V)<<(RTC_IO_SENSE4_FUN_SEL_S)) +#define RTC_IO_SENSE4_FUN_SEL_V 0x3 +#define RTC_IO_SENSE4_FUN_SEL_S 7 +/* RTC_IO_SENSE4_SLP_SEL : R/W ;bitpos:[6] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_SENSE4_SLP_SEL (BIT(6)) +#define RTC_IO_SENSE4_SLP_SEL_M (BIT(6)) +#define RTC_IO_SENSE4_SLP_SEL_V 0x1 +#define RTC_IO_SENSE4_SLP_SEL_S 6 +/* RTC_IO_SENSE4_SLP_IE : R/W ;bitpos:[5] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_SENSE4_SLP_IE (BIT(5)) +#define RTC_IO_SENSE4_SLP_IE_M (BIT(5)) +#define RTC_IO_SENSE4_SLP_IE_V 0x1 +#define RTC_IO_SENSE4_SLP_IE_S 5 +/* RTC_IO_SENSE4_FUN_IE : R/W ;bitpos:[4] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_SENSE4_FUN_IE (BIT(4)) +#define RTC_IO_SENSE4_FUN_IE_M (BIT(4)) +#define RTC_IO_SENSE4_FUN_IE_V 0x1 +#define RTC_IO_SENSE4_FUN_IE_S 4 + +#define RTC_IO_ADC_PAD_REG (DR_REG_RTCIO_BASE + 0x80) +/* RTC_IO_ADC1_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_ADC1_HOLD (BIT(31)) +#define RTC_IO_ADC1_HOLD_M (BIT(31)) +#define RTC_IO_ADC1_HOLD_V 0x1 +#define RTC_IO_ADC1_HOLD_S 31 +/* RTC_IO_ADC2_HOLD : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_ADC2_HOLD (BIT(30)) +#define RTC_IO_ADC2_HOLD_M (BIT(30)) +#define RTC_IO_ADC2_HOLD_V 0x1 +#define RTC_IO_ADC2_HOLD_S 30 +/* RTC_IO_ADC1_MUX_SEL : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_ADC1_MUX_SEL (BIT(29)) +#define RTC_IO_ADC1_MUX_SEL_M (BIT(29)) +#define RTC_IO_ADC1_MUX_SEL_V 0x1 +#define RTC_IO_ADC1_MUX_SEL_S 29 +/* RTC_IO_ADC2_MUX_SEL : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_ADC2_MUX_SEL (BIT(28)) +#define RTC_IO_ADC2_MUX_SEL_M (BIT(28)) +#define RTC_IO_ADC2_MUX_SEL_V 0x1 +#define RTC_IO_ADC2_MUX_SEL_S 28 +/* RTC_IO_ADC1_FUN_SEL : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_ADC1_FUN_SEL 0x00000003 +#define RTC_IO_ADC1_FUN_SEL_M ((RTC_IO_ADC1_FUN_SEL_V)<<(RTC_IO_ADC1_FUN_SEL_S)) +#define RTC_IO_ADC1_FUN_SEL_V 0x3 +#define RTC_IO_ADC1_FUN_SEL_S 26 +/* RTC_IO_ADC1_SLP_SEL : R/W ;bitpos:[25] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_ADC1_SLP_SEL (BIT(25)) +#define RTC_IO_ADC1_SLP_SEL_M (BIT(25)) +#define RTC_IO_ADC1_SLP_SEL_V 0x1 +#define RTC_IO_ADC1_SLP_SEL_S 25 +/* RTC_IO_ADC1_SLP_IE : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_ADC1_SLP_IE (BIT(24)) +#define RTC_IO_ADC1_SLP_IE_M (BIT(24)) +#define RTC_IO_ADC1_SLP_IE_V 0x1 +#define RTC_IO_ADC1_SLP_IE_S 24 +/* RTC_IO_ADC1_FUN_IE : R/W ;bitpos:[23] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_ADC1_FUN_IE (BIT(23)) +#define RTC_IO_ADC1_FUN_IE_M (BIT(23)) +#define RTC_IO_ADC1_FUN_IE_V 0x1 +#define RTC_IO_ADC1_FUN_IE_S 23 +/* RTC_IO_ADC2_FUN_SEL : R/W ;bitpos:[22:21] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_ADC2_FUN_SEL 0x00000003 +#define RTC_IO_ADC2_FUN_SEL_M ((RTC_IO_ADC2_FUN_SEL_V)<<(RTC_IO_ADC2_FUN_SEL_S)) +#define RTC_IO_ADC2_FUN_SEL_V 0x3 +#define RTC_IO_ADC2_FUN_SEL_S 21 +/* RTC_IO_ADC2_SLP_SEL : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_ADC2_SLP_SEL (BIT(20)) +#define RTC_IO_ADC2_SLP_SEL_M (BIT(20)) +#define RTC_IO_ADC2_SLP_SEL_V 0x1 +#define RTC_IO_ADC2_SLP_SEL_S 20 +/* RTC_IO_ADC2_SLP_IE : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_ADC2_SLP_IE (BIT(19)) +#define RTC_IO_ADC2_SLP_IE_M (BIT(19)) +#define RTC_IO_ADC2_SLP_IE_V 0x1 +#define RTC_IO_ADC2_SLP_IE_S 19 +/* RTC_IO_ADC2_FUN_IE : R/W ;bitpos:[18] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_ADC2_FUN_IE (BIT(18)) +#define RTC_IO_ADC2_FUN_IE_M (BIT(18)) +#define RTC_IO_ADC2_FUN_IE_V 0x1 +#define RTC_IO_ADC2_FUN_IE_S 18 + +#define RTC_IO_PAD_DAC1_REG (DR_REG_RTCIO_BASE + 0x84) +/* RTC_IO_PDAC1_DRV : R/W ;bitpos:[31:30] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_PDAC1_DRV 0x00000003 +#define RTC_IO_PDAC1_DRV_M ((RTC_IO_PDAC1_DRV_V)<<(RTC_IO_PDAC1_DRV_S)) +#define RTC_IO_PDAC1_DRV_V 0x3 +#define RTC_IO_PDAC1_DRV_S 30 +/* RTC_IO_PDAC1_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_PDAC1_HOLD (BIT(29)) +#define RTC_IO_PDAC1_HOLD_M (BIT(29)) +#define RTC_IO_PDAC1_HOLD_V 0x1 +#define RTC_IO_PDAC1_HOLD_S 29 +/* RTC_IO_PDAC1_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_PDAC1_RDE (BIT(28)) +#define RTC_IO_PDAC1_RDE_M (BIT(28)) +#define RTC_IO_PDAC1_RDE_V 0x1 +#define RTC_IO_PDAC1_RDE_S 28 +/* RTC_IO_PDAC1_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_PDAC1_RUE (BIT(27)) +#define RTC_IO_PDAC1_RUE_M (BIT(27)) +#define RTC_IO_PDAC1_RUE_V 0x1 +#define RTC_IO_PDAC1_RUE_S 27 +/* RTC_IO_PDAC1_DAC : R/W ;bitpos:[26:19] ;default: 8'd0 ; */ +/*description: PAD DAC1 control code.*/ +#define RTC_IO_PDAC1_DAC 0x000000FF +#define RTC_IO_PDAC1_DAC_M ((RTC_IO_PDAC1_DAC_V)<<(RTC_IO_PDAC1_DAC_S)) +#define RTC_IO_PDAC1_DAC_V 0xFF +#define RTC_IO_PDAC1_DAC_S 19 +/* RTC_IO_PDAC1_XPD_DAC : R/W ;bitpos:[18] ;default: 1'd0 ; */ +/*description: Power on DAC1. Usually we need to tristate PDAC1 if we power + on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/ +#define RTC_IO_PDAC1_XPD_DAC (BIT(18)) +#define RTC_IO_PDAC1_XPD_DAC_M (BIT(18)) +#define RTC_IO_PDAC1_XPD_DAC_V 0x1 +#define RTC_IO_PDAC1_XPD_DAC_S 18 +/* RTC_IO_PDAC1_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_PDAC1_MUX_SEL (BIT(17)) +#define RTC_IO_PDAC1_MUX_SEL_M (BIT(17)) +#define RTC_IO_PDAC1_MUX_SEL_V 0x1 +#define RTC_IO_PDAC1_MUX_SEL_S 17 +/* RTC_IO_PDAC1_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_PDAC1_FUN_SEL 0x00000003 +#define RTC_IO_PDAC1_FUN_SEL_M ((RTC_IO_PDAC1_FUN_SEL_V)<<(RTC_IO_PDAC1_FUN_SEL_S)) +#define RTC_IO_PDAC1_FUN_SEL_V 0x3 +#define RTC_IO_PDAC1_FUN_SEL_S 15 +/* RTC_IO_PDAC1_SLP_SEL : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_PDAC1_SLP_SEL (BIT(14)) +#define RTC_IO_PDAC1_SLP_SEL_M (BIT(14)) +#define RTC_IO_PDAC1_SLP_SEL_V 0x1 +#define RTC_IO_PDAC1_SLP_SEL_S 14 +/* RTC_IO_PDAC1_SLP_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_PDAC1_SLP_IE (BIT(13)) +#define RTC_IO_PDAC1_SLP_IE_M (BIT(13)) +#define RTC_IO_PDAC1_SLP_IE_V 0x1 +#define RTC_IO_PDAC1_SLP_IE_S 13 +/* RTC_IO_PDAC1_SLP_OE : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_PDAC1_SLP_OE (BIT(12)) +#define RTC_IO_PDAC1_SLP_OE_M (BIT(12)) +#define RTC_IO_PDAC1_SLP_OE_V 0x1 +#define RTC_IO_PDAC1_SLP_OE_S 12 +/* RTC_IO_PDAC1_FUN_IE : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_PDAC1_FUN_IE (BIT(11)) +#define RTC_IO_PDAC1_FUN_IE_M (BIT(11)) +#define RTC_IO_PDAC1_FUN_IE_V 0x1 +#define RTC_IO_PDAC1_FUN_IE_S 11 +/* RTC_IO_PDAC1_DAC_XPD_FORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: Power on DAC1. Usually we need to tristate PDAC1 if we power + on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/ +#define RTC_IO_PDAC1_DAC_XPD_FORCE (BIT(10)) +#define RTC_IO_PDAC1_DAC_XPD_FORCE_M (BIT(10)) +#define RTC_IO_PDAC1_DAC_XPD_FORCE_V 0x1 +#define RTC_IO_PDAC1_DAC_XPD_FORCE_S 10 + +#define RTC_IO_PAD_DAC2_REG (DR_REG_RTCIO_BASE + 0x88) +/* RTC_IO_PDAC2_DRV : R/W ;bitpos:[31:30] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_PDAC2_DRV 0x00000003 +#define RTC_IO_PDAC2_DRV_M ((RTC_IO_PDAC2_DRV_V)<<(RTC_IO_PDAC2_DRV_S)) +#define RTC_IO_PDAC2_DRV_V 0x3 +#define RTC_IO_PDAC2_DRV_S 30 +/* RTC_IO_PDAC2_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_PDAC2_HOLD (BIT(29)) +#define RTC_IO_PDAC2_HOLD_M (BIT(29)) +#define RTC_IO_PDAC2_HOLD_V 0x1 +#define RTC_IO_PDAC2_HOLD_S 29 +/* RTC_IO_PDAC2_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_PDAC2_RDE (BIT(28)) +#define RTC_IO_PDAC2_RDE_M (BIT(28)) +#define RTC_IO_PDAC2_RDE_V 0x1 +#define RTC_IO_PDAC2_RDE_S 28 +/* RTC_IO_PDAC2_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_PDAC2_RUE (BIT(27)) +#define RTC_IO_PDAC2_RUE_M (BIT(27)) +#define RTC_IO_PDAC2_RUE_V 0x1 +#define RTC_IO_PDAC2_RUE_S 27 +/* RTC_IO_PDAC2_DAC : R/W ;bitpos:[26:19] ;default: 8'd0 ; */ +/*description: PAD DAC2 control code.*/ +#define RTC_IO_PDAC2_DAC 0x000000FF +#define RTC_IO_PDAC2_DAC_M ((RTC_IO_PDAC2_DAC_V)<<(RTC_IO_PDAC2_DAC_S)) +#define RTC_IO_PDAC2_DAC_V 0xFF +#define RTC_IO_PDAC2_DAC_S 19 +/* RTC_IO_PDAC2_XPD_DAC : R/W ;bitpos:[18] ;default: 1'd0 ; */ +/*description: Power on DAC2. Usually we need to tristate PDAC1 if we power + on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/ +#define RTC_IO_PDAC2_XPD_DAC (BIT(18)) +#define RTC_IO_PDAC2_XPD_DAC_M (BIT(18)) +#define RTC_IO_PDAC2_XPD_DAC_V 0x1 +#define RTC_IO_PDAC2_XPD_DAC_S 18 +/* RTC_IO_PDAC2_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_PDAC2_MUX_SEL (BIT(17)) +#define RTC_IO_PDAC2_MUX_SEL_M (BIT(17)) +#define RTC_IO_PDAC2_MUX_SEL_V 0x1 +#define RTC_IO_PDAC2_MUX_SEL_S 17 +/* RTC_IO_PDAC2_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_PDAC2_FUN_SEL 0x00000003 +#define RTC_IO_PDAC2_FUN_SEL_M ((RTC_IO_PDAC2_FUN_SEL_V)<<(RTC_IO_PDAC2_FUN_SEL_S)) +#define RTC_IO_PDAC2_FUN_SEL_V 0x3 +#define RTC_IO_PDAC2_FUN_SEL_S 15 +/* RTC_IO_PDAC2_SLP_SEL : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_PDAC2_SLP_SEL (BIT(14)) +#define RTC_IO_PDAC2_SLP_SEL_M (BIT(14)) +#define RTC_IO_PDAC2_SLP_SEL_V 0x1 +#define RTC_IO_PDAC2_SLP_SEL_S 14 +/* RTC_IO_PDAC2_SLP_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_PDAC2_SLP_IE (BIT(13)) +#define RTC_IO_PDAC2_SLP_IE_M (BIT(13)) +#define RTC_IO_PDAC2_SLP_IE_V 0x1 +#define RTC_IO_PDAC2_SLP_IE_S 13 +/* RTC_IO_PDAC2_SLP_OE : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_PDAC2_SLP_OE (BIT(12)) +#define RTC_IO_PDAC2_SLP_OE_M (BIT(12)) +#define RTC_IO_PDAC2_SLP_OE_V 0x1 +#define RTC_IO_PDAC2_SLP_OE_S 12 +/* RTC_IO_PDAC2_FUN_IE : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_PDAC2_FUN_IE (BIT(11)) +#define RTC_IO_PDAC2_FUN_IE_M (BIT(11)) +#define RTC_IO_PDAC2_FUN_IE_V 0x1 +#define RTC_IO_PDAC2_FUN_IE_S 11 +/* RTC_IO_PDAC2_DAC_XPD_FORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: Power on DAC2. Usually we need to tristate PDAC2 if we power + on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/ +#define RTC_IO_PDAC2_DAC_XPD_FORCE (BIT(10)) +#define RTC_IO_PDAC2_DAC_XPD_FORCE_M (BIT(10)) +#define RTC_IO_PDAC2_DAC_XPD_FORCE_V 0x1 +#define RTC_IO_PDAC2_DAC_XPD_FORCE_S 10 + +#define RTC_IO_XTAL_32K_PAD_REG (DR_REG_RTCIO_BASE + 0x8c) +/* RTC_IO_X32N_DRV : R/W ;bitpos:[31:30] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_X32N_DRV 0x00000003 +#define RTC_IO_X32N_DRV_M ((RTC_IO_X32N_DRV_V)<<(RTC_IO_X32N_DRV_S)) +#define RTC_IO_X32N_DRV_V 0x3 +#define RTC_IO_X32N_DRV_S 30 +/* RTC_IO_X32N_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_X32N_HOLD (BIT(29)) +#define RTC_IO_X32N_HOLD_M (BIT(29)) +#define RTC_IO_X32N_HOLD_V 0x1 +#define RTC_IO_X32N_HOLD_S 29 +/* RTC_IO_X32N_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_X32N_RDE (BIT(28)) +#define RTC_IO_X32N_RDE_M (BIT(28)) +#define RTC_IO_X32N_RDE_V 0x1 +#define RTC_IO_X32N_RDE_S 28 +/* RTC_IO_X32N_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_X32N_RUE (BIT(27)) +#define RTC_IO_X32N_RUE_M (BIT(27)) +#define RTC_IO_X32N_RUE_V 0x1 +#define RTC_IO_X32N_RUE_S 27 +/* RTC_IO_X32P_DRV : R/W ;bitpos:[26:25] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_X32P_DRV 0x00000003 +#define RTC_IO_X32P_DRV_M ((RTC_IO_X32P_DRV_V)<<(RTC_IO_X32P_DRV_S)) +#define RTC_IO_X32P_DRV_V 0x3 +#define RTC_IO_X32P_DRV_S 25 +/* RTC_IO_X32P_HOLD : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_X32P_HOLD (BIT(24)) +#define RTC_IO_X32P_HOLD_M (BIT(24)) +#define RTC_IO_X32P_HOLD_V 0x1 +#define RTC_IO_X32P_HOLD_S 24 +/* RTC_IO_X32P_RDE : R/W ;bitpos:[23] ;default: 1'd0 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_X32P_RDE (BIT(23)) +#define RTC_IO_X32P_RDE_M (BIT(23)) +#define RTC_IO_X32P_RDE_V 0x1 +#define RTC_IO_X32P_RDE_S 23 +/* RTC_IO_X32P_RUE : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_X32P_RUE (BIT(22)) +#define RTC_IO_X32P_RUE_M (BIT(22)) +#define RTC_IO_X32P_RUE_V 0x1 +#define RTC_IO_X32P_RUE_S 22 +/* RTC_IO_DAC_XTAL_32K : R/W ;bitpos:[21:20] ;default: 2'b01 ; */ +/*description: 32K XTAL bias current DAC.*/ +#define RTC_IO_DAC_XTAL_32K 0x00000003 +#define RTC_IO_DAC_XTAL_32K_M ((RTC_IO_DAC_XTAL_32K_V)<<(RTC_IO_DAC_XTAL_32K_S)) +#define RTC_IO_DAC_XTAL_32K_V 0x3 +#define RTC_IO_DAC_XTAL_32K_S 20 +/* RTC_IO_XPD_XTAL_32K : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: Power up 32kHz crystal oscillator*/ +#define RTC_IO_XPD_XTAL_32K (BIT(19)) +#define RTC_IO_XPD_XTAL_32K_M (BIT(19)) +#define RTC_IO_XPD_XTAL_32K_V 0x1 +#define RTC_IO_XPD_XTAL_32K_S 19 +/* RTC_IO_X32N_MUX_SEL : R/W ;bitpos:[18] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_X32N_MUX_SEL (BIT(18)) +#define RTC_IO_X32N_MUX_SEL_M (BIT(18)) +#define RTC_IO_X32N_MUX_SEL_V 0x1 +#define RTC_IO_X32N_MUX_SEL_S 18 +/* RTC_IO_X32P_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_X32P_MUX_SEL (BIT(17)) +#define RTC_IO_X32P_MUX_SEL_M (BIT(17)) +#define RTC_IO_X32P_MUX_SEL_V 0x1 +#define RTC_IO_X32P_MUX_SEL_S 17 +/* RTC_IO_X32N_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_X32N_FUN_SEL 0x00000003 +#define RTC_IO_X32N_FUN_SEL_M ((RTC_IO_X32N_FUN_SEL_V)<<(RTC_IO_X32N_FUN_SEL_S)) +#define RTC_IO_X32N_FUN_SEL_V 0x3 +#define RTC_IO_X32N_FUN_SEL_S 15 +/* RTC_IO_X32N_SLP_SEL : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_X32N_SLP_SEL (BIT(14)) +#define RTC_IO_X32N_SLP_SEL_M (BIT(14)) +#define RTC_IO_X32N_SLP_SEL_V 0x1 +#define RTC_IO_X32N_SLP_SEL_S 14 +/* RTC_IO_X32N_SLP_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_X32N_SLP_IE (BIT(13)) +#define RTC_IO_X32N_SLP_IE_M (BIT(13)) +#define RTC_IO_X32N_SLP_IE_V 0x1 +#define RTC_IO_X32N_SLP_IE_S 13 +/* RTC_IO_X32N_SLP_OE : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_X32N_SLP_OE (BIT(12)) +#define RTC_IO_X32N_SLP_OE_M (BIT(12)) +#define RTC_IO_X32N_SLP_OE_V 0x1 +#define RTC_IO_X32N_SLP_OE_S 12 +/* RTC_IO_X32N_FUN_IE : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_X32N_FUN_IE (BIT(11)) +#define RTC_IO_X32N_FUN_IE_M (BIT(11)) +#define RTC_IO_X32N_FUN_IE_V 0x1 +#define RTC_IO_X32N_FUN_IE_S 11 +/* RTC_IO_X32P_FUN_SEL : R/W ;bitpos:[10:9] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_X32P_FUN_SEL 0x00000003 +#define RTC_IO_X32P_FUN_SEL_M ((RTC_IO_X32P_FUN_SEL_V)<<(RTC_IO_X32P_FUN_SEL_S)) +#define RTC_IO_X32P_FUN_SEL_V 0x3 +#define RTC_IO_X32P_FUN_SEL_S 9 +/* RTC_IO_X32P_SLP_SEL : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_X32P_SLP_SEL (BIT(8)) +#define RTC_IO_X32P_SLP_SEL_M (BIT(8)) +#define RTC_IO_X32P_SLP_SEL_V 0x1 +#define RTC_IO_X32P_SLP_SEL_S 8 +/* RTC_IO_X32P_SLP_IE : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_X32P_SLP_IE (BIT(7)) +#define RTC_IO_X32P_SLP_IE_M (BIT(7)) +#define RTC_IO_X32P_SLP_IE_V 0x1 +#define RTC_IO_X32P_SLP_IE_S 7 +/* RTC_IO_X32P_SLP_OE : R/W ;bitpos:[6] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_X32P_SLP_OE (BIT(6)) +#define RTC_IO_X32P_SLP_OE_M (BIT(6)) +#define RTC_IO_X32P_SLP_OE_V 0x1 +#define RTC_IO_X32P_SLP_OE_S 6 +/* RTC_IO_X32P_FUN_IE : R/W ;bitpos:[5] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_X32P_FUN_IE (BIT(5)) +#define RTC_IO_X32P_FUN_IE_M (BIT(5)) +#define RTC_IO_X32P_FUN_IE_V 0x1 +#define RTC_IO_X32P_FUN_IE_S 5 +/* RTC_IO_DRES_XTAL_32K : R/W ;bitpos:[4:3] ;default: 2'b10 ; */ +/*description: 32K XTAL resistor bias control.*/ +#define RTC_IO_DRES_XTAL_32K 0x00000003 +#define RTC_IO_DRES_XTAL_32K_M ((RTC_IO_DRES_XTAL_32K_V)<<(RTC_IO_DRES_XTAL_32K_S)) +#define RTC_IO_DRES_XTAL_32K_V 0x3 +#define RTC_IO_DRES_XTAL_32K_S 3 +/* RTC_IO_DBIAS_XTAL_32K : R/W ;bitpos:[2:1] ;default: 2'b00 ; */ +/*description: 32K XTAL self-bias reference control.*/ +#define RTC_IO_DBIAS_XTAL_32K 0x00000003 +#define RTC_IO_DBIAS_XTAL_32K_M ((RTC_IO_DBIAS_XTAL_32K_V)<<(RTC_IO_DBIAS_XTAL_32K_S)) +#define RTC_IO_DBIAS_XTAL_32K_V 0x3 +#define RTC_IO_DBIAS_XTAL_32K_S 1 + +#define RTC_IO_TOUCH_CFG_REG (DR_REG_RTCIO_BASE + 0x90) +/* RTC_IO_TOUCH_XPD_BIAS : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: touch sensor bias power on.*/ +#define RTC_IO_TOUCH_XPD_BIAS (BIT(31)) +#define RTC_IO_TOUCH_XPD_BIAS_M (BIT(31)) +#define RTC_IO_TOUCH_XPD_BIAS_V 0x1 +#define RTC_IO_TOUCH_XPD_BIAS_S 31 +/* RTC_IO_TOUCH_DREFH : R/W ;bitpos:[30:29] ;default: 2'b11 ; */ +/*description: touch sensor saw wave top voltage.*/ +#define RTC_IO_TOUCH_DREFH 0x00000003 +#define RTC_IO_TOUCH_DREFH_M ((RTC_IO_TOUCH_DREFH_V)<<(RTC_IO_TOUCH_DREFH_S)) +#define RTC_IO_TOUCH_DREFH_V 0x3 +#define RTC_IO_TOUCH_DREFH_S 29 +/* RTC_IO_TOUCH_DREFL : R/W ;bitpos:[28:27] ;default: 2'b00 ; */ +/*description: touch sensor saw wave bottom voltage.*/ +#define RTC_IO_TOUCH_DREFL 0x00000003 +#define RTC_IO_TOUCH_DREFL_M ((RTC_IO_TOUCH_DREFL_V)<<(RTC_IO_TOUCH_DREFL_S)) +#define RTC_IO_TOUCH_DREFL_V 0x3 +#define RTC_IO_TOUCH_DREFL_S 27 +/* RTC_IO_TOUCH_DRANGE : R/W ;bitpos:[26:25] ;default: 2'b11 ; */ +/*description: touch sensor saw wave voltage range.*/ +#define RTC_IO_TOUCH_DRANGE 0x00000003 +#define RTC_IO_TOUCH_DRANGE_M ((RTC_IO_TOUCH_DRANGE_V)<<(RTC_IO_TOUCH_DRANGE_S)) +#define RTC_IO_TOUCH_DRANGE_V 0x3 +#define RTC_IO_TOUCH_DRANGE_S 25 +/* RTC_IO_TOUCH_DCUR : R/W ;bitpos:[24:23] ;default: 2'b00 ; */ +/*description: touch sensor bias current. Should have option to tie with BIAS_SLEEP(When + BIAS_SLEEP this setting is available*/ +#define RTC_IO_TOUCH_DCUR 0x00000003 +#define RTC_IO_TOUCH_DCUR_M ((RTC_IO_TOUCH_DCUR_V)<<(RTC_IO_TOUCH_DCUR_S)) +#define RTC_IO_TOUCH_DCUR_V 0x3 +#define RTC_IO_TOUCH_DCUR_S 23 + +#define RTC_IO_TOUCH_PAD0_REG (DR_REG_RTCIO_BASE + 0x94) +/* RTC_IO_TOUCH_PAD0_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_TOUCH_PAD0_HOLD (BIT(31)) +#define RTC_IO_TOUCH_PAD0_HOLD_M (BIT(31)) +#define RTC_IO_TOUCH_PAD0_HOLD_V 0x1 +#define RTC_IO_TOUCH_PAD0_HOLD_S 31 +/* RTC_IO_TOUCH_PAD0_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_TOUCH_PAD0_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD0_DRV_M ((RTC_IO_TOUCH_PAD0_DRV_V)<<(RTC_IO_TOUCH_PAD0_DRV_S)) +#define RTC_IO_TOUCH_PAD0_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD0_DRV_S 29 +/* RTC_IO_TOUCH_PAD0_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_TOUCH_PAD0_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD0_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD0_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD0_RDE_S 28 +/* RTC_IO_TOUCH_PAD0_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_TOUCH_PAD0_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD0_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD0_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD0_RUE_S 27 +/* RTC_IO_TOUCH_PAD0_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ +#define RTC_IO_TOUCH_PAD0_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD0_DAC_M ((RTC_IO_TOUCH_PAD0_DAC_V)<<(RTC_IO_TOUCH_PAD0_DAC_S)) +#define RTC_IO_TOUCH_PAD0_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD0_DAC_S 23 +/* RTC_IO_TOUCH_PAD0_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: start touch sensor.*/ +#define RTC_IO_TOUCH_PAD0_START (BIT(22)) +#define RTC_IO_TOUCH_PAD0_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD0_START_V 0x1 +#define RTC_IO_TOUCH_PAD0_START_S 22 +/* RTC_IO_TOUCH_PAD0_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ +#define RTC_IO_TOUCH_PAD0_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD0_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD0_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD0_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD0_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: touch sensor power on.*/ +#define RTC_IO_TOUCH_PAD0_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD0_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD0_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD0_XPD_S 20 +/* RTC_IO_TOUCH_PAD0_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_TOUCH_PAD0_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD0_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD0_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD0_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD0_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD0_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD0_FUN_SEL_M ((RTC_IO_TOUCH_PAD0_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD0_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD0_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD0_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD0_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD0_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD0_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD0_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD0_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD0_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD0_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD0_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD0_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD0_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD0_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD0_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD0_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD0_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD0_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD0_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_TOUCH_PAD0_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD0_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD0_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD0_FUN_IE_S 13 +/* RTC_IO_TOUCH_PAD0_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale GPIO4*/ +#define RTC_IO_TOUCH_PAD0_TO_GPIO (BIT(12)) +#define RTC_IO_TOUCH_PAD0_TO_GPIO_M (BIT(12)) +#define RTC_IO_TOUCH_PAD0_TO_GPIO_V 0x1 +#define RTC_IO_TOUCH_PAD0_TO_GPIO_S 12 + +#define RTC_IO_TOUCH_PAD1_REG (DR_REG_RTCIO_BASE + 0x98) +/* RTC_IO_TOUCH_PAD1_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: */ +#define RTC_IO_TOUCH_PAD1_HOLD (BIT(31)) +#define RTC_IO_TOUCH_PAD1_HOLD_M (BIT(31)) +#define RTC_IO_TOUCH_PAD1_HOLD_V 0x1 +#define RTC_IO_TOUCH_PAD1_HOLD_S 31 +/* RTC_IO_TOUCH_PAD1_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_TOUCH_PAD1_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD1_DRV_M ((RTC_IO_TOUCH_PAD1_DRV_V)<<(RTC_IO_TOUCH_PAD1_DRV_S)) +#define RTC_IO_TOUCH_PAD1_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD1_DRV_S 29 +/* RTC_IO_TOUCH_PAD1_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_TOUCH_PAD1_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD1_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD1_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD1_RDE_S 28 +/* RTC_IO_TOUCH_PAD1_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_TOUCH_PAD1_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD1_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD1_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD1_RUE_S 27 +/* RTC_IO_TOUCH_PAD1_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ +#define RTC_IO_TOUCH_PAD1_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD1_DAC_M ((RTC_IO_TOUCH_PAD1_DAC_V)<<(RTC_IO_TOUCH_PAD1_DAC_S)) +#define RTC_IO_TOUCH_PAD1_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD1_DAC_S 23 +/* RTC_IO_TOUCH_PAD1_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: start touch sensor.*/ +#define RTC_IO_TOUCH_PAD1_START (BIT(22)) +#define RTC_IO_TOUCH_PAD1_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD1_START_V 0x1 +#define RTC_IO_TOUCH_PAD1_START_S 22 +/* RTC_IO_TOUCH_PAD1_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ +#define RTC_IO_TOUCH_PAD1_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD1_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD1_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD1_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD1_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: touch sensor power on.*/ +#define RTC_IO_TOUCH_PAD1_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD1_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD1_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD1_XPD_S 20 +/* RTC_IO_TOUCH_PAD1_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_TOUCH_PAD1_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD1_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD1_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD1_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD1_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD1_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD1_FUN_SEL_M ((RTC_IO_TOUCH_PAD1_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD1_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD1_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD1_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD1_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD1_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD1_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD1_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD1_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD1_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD1_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD1_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD1_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD1_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD1_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD1_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD1_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD1_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD1_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD1_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_TOUCH_PAD1_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD1_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD1_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD1_FUN_IE_S 13 +/* RTC_IO_TOUCH_PAD1_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO0*/ +#define RTC_IO_TOUCH_PAD1_TO_GPIO (BIT(12)) +#define RTC_IO_TOUCH_PAD1_TO_GPIO_M (BIT(12)) +#define RTC_IO_TOUCH_PAD1_TO_GPIO_V 0x1 +#define RTC_IO_TOUCH_PAD1_TO_GPIO_S 12 + +#define RTC_IO_TOUCH_PAD2_REG (DR_REG_RTCIO_BASE + 0x9c) +/* RTC_IO_TOUCH_PAD2_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_TOUCH_PAD2_HOLD (BIT(31)) +#define RTC_IO_TOUCH_PAD2_HOLD_M (BIT(31)) +#define RTC_IO_TOUCH_PAD2_HOLD_V 0x1 +#define RTC_IO_TOUCH_PAD2_HOLD_S 31 +/* RTC_IO_TOUCH_PAD2_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_TOUCH_PAD2_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD2_DRV_M ((RTC_IO_TOUCH_PAD2_DRV_V)<<(RTC_IO_TOUCH_PAD2_DRV_S)) +#define RTC_IO_TOUCH_PAD2_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD2_DRV_S 29 +/* RTC_IO_TOUCH_PAD2_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_TOUCH_PAD2_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD2_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD2_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD2_RDE_S 28 +/* RTC_IO_TOUCH_PAD2_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_TOUCH_PAD2_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD2_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD2_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD2_RUE_S 27 +/* RTC_IO_TOUCH_PAD2_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ +#define RTC_IO_TOUCH_PAD2_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD2_DAC_M ((RTC_IO_TOUCH_PAD2_DAC_V)<<(RTC_IO_TOUCH_PAD2_DAC_S)) +#define RTC_IO_TOUCH_PAD2_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD2_DAC_S 23 +/* RTC_IO_TOUCH_PAD2_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: start touch sensor.*/ +#define RTC_IO_TOUCH_PAD2_START (BIT(22)) +#define RTC_IO_TOUCH_PAD2_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD2_START_V 0x1 +#define RTC_IO_TOUCH_PAD2_START_S 22 +/* RTC_IO_TOUCH_PAD2_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ +#define RTC_IO_TOUCH_PAD2_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD2_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD2_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD2_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD2_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: touch sensor power on.*/ +#define RTC_IO_TOUCH_PAD2_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD2_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD2_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD2_XPD_S 20 +/* RTC_IO_TOUCH_PAD2_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_TOUCH_PAD2_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD2_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD2_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD2_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD2_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD2_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD2_FUN_SEL_M ((RTC_IO_TOUCH_PAD2_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD2_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD2_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD2_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD2_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD2_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD2_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD2_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD2_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD2_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD2_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD2_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD2_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD2_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD2_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD2_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD2_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD2_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD2_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD2_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_TOUCH_PAD2_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD2_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD2_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD2_FUN_IE_S 13 +/* RTC_IO_TOUCH_PAD2_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO2*/ +#define RTC_IO_TOUCH_PAD2_TO_GPIO (BIT(12)) +#define RTC_IO_TOUCH_PAD2_TO_GPIO_M (BIT(12)) +#define RTC_IO_TOUCH_PAD2_TO_GPIO_V 0x1 +#define RTC_IO_TOUCH_PAD2_TO_GPIO_S 12 + +#define RTC_IO_TOUCH_PAD3_REG (DR_REG_RTCIO_BASE + 0xa0) +/* RTC_IO_TOUCH_PAD3_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_TOUCH_PAD3_HOLD (BIT(31)) +#define RTC_IO_TOUCH_PAD3_HOLD_M (BIT(31)) +#define RTC_IO_TOUCH_PAD3_HOLD_V 0x1 +#define RTC_IO_TOUCH_PAD3_HOLD_S 31 +/* RTC_IO_TOUCH_PAD3_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_TOUCH_PAD3_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD3_DRV_M ((RTC_IO_TOUCH_PAD3_DRV_V)<<(RTC_IO_TOUCH_PAD3_DRV_S)) +#define RTC_IO_TOUCH_PAD3_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD3_DRV_S 29 +/* RTC_IO_TOUCH_PAD3_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_TOUCH_PAD3_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD3_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD3_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD3_RDE_S 28 +/* RTC_IO_TOUCH_PAD3_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_TOUCH_PAD3_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD3_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD3_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD3_RUE_S 27 +/* RTC_IO_TOUCH_PAD3_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ +#define RTC_IO_TOUCH_PAD3_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD3_DAC_M ((RTC_IO_TOUCH_PAD3_DAC_V)<<(RTC_IO_TOUCH_PAD3_DAC_S)) +#define RTC_IO_TOUCH_PAD3_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD3_DAC_S 23 +/* RTC_IO_TOUCH_PAD3_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: start touch sensor.*/ +#define RTC_IO_TOUCH_PAD3_START (BIT(22)) +#define RTC_IO_TOUCH_PAD3_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD3_START_V 0x1 +#define RTC_IO_TOUCH_PAD3_START_S 22 +/* RTC_IO_TOUCH_PAD3_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ +#define RTC_IO_TOUCH_PAD3_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD3_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD3_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD3_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD3_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: touch sensor power on.*/ +#define RTC_IO_TOUCH_PAD3_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD3_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD3_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD3_XPD_S 20 +/* RTC_IO_TOUCH_PAD3_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_TOUCH_PAD3_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD3_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD3_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD3_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD3_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD3_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD3_FUN_SEL_M ((RTC_IO_TOUCH_PAD3_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD3_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD3_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD3_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD3_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD3_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD3_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD3_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD3_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD3_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD3_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD3_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD3_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD3_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD3_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD3_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD3_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD3_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD3_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD3_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_TOUCH_PAD3_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD3_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD3_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD3_FUN_IE_S 13 +/* RTC_IO_TOUCH_PAD3_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTDO*/ +#define RTC_IO_TOUCH_PAD3_TO_GPIO (BIT(12)) +#define RTC_IO_TOUCH_PAD3_TO_GPIO_M (BIT(12)) +#define RTC_IO_TOUCH_PAD3_TO_GPIO_V 0x1 +#define RTC_IO_TOUCH_PAD3_TO_GPIO_S 12 + +#define RTC_IO_TOUCH_PAD4_REG (DR_REG_RTCIO_BASE + 0xa4) +/* RTC_IO_TOUCH_PAD4_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_TOUCH_PAD4_HOLD (BIT(31)) +#define RTC_IO_TOUCH_PAD4_HOLD_M (BIT(31)) +#define RTC_IO_TOUCH_PAD4_HOLD_V 0x1 +#define RTC_IO_TOUCH_PAD4_HOLD_S 31 +/* RTC_IO_TOUCH_PAD4_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_TOUCH_PAD4_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD4_DRV_M ((RTC_IO_TOUCH_PAD4_DRV_V)<<(RTC_IO_TOUCH_PAD4_DRV_S)) +#define RTC_IO_TOUCH_PAD4_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD4_DRV_S 29 +/* RTC_IO_TOUCH_PAD4_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_TOUCH_PAD4_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD4_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD4_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD4_RDE_S 28 +/* RTC_IO_TOUCH_PAD4_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_TOUCH_PAD4_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD4_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD4_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD4_RUE_S 27 +/* RTC_IO_TOUCH_PAD4_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ +#define RTC_IO_TOUCH_PAD4_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD4_DAC_M ((RTC_IO_TOUCH_PAD4_DAC_V)<<(RTC_IO_TOUCH_PAD4_DAC_S)) +#define RTC_IO_TOUCH_PAD4_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD4_DAC_S 23 +/* RTC_IO_TOUCH_PAD4_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: start touch sensor.*/ +#define RTC_IO_TOUCH_PAD4_START (BIT(22)) +#define RTC_IO_TOUCH_PAD4_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD4_START_V 0x1 +#define RTC_IO_TOUCH_PAD4_START_S 22 +/* RTC_IO_TOUCH_PAD4_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ +#define RTC_IO_TOUCH_PAD4_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD4_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD4_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD4_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD4_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: touch sensor power on.*/ +#define RTC_IO_TOUCH_PAD4_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD4_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD4_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD4_XPD_S 20 +/* RTC_IO_TOUCH_PAD4_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_TOUCH_PAD4_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD4_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD4_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD4_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD4_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD4_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD4_FUN_SEL_M ((RTC_IO_TOUCH_PAD4_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD4_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD4_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD4_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD4_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD4_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD4_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD4_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD4_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD4_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD4_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD4_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD4_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD4_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD4_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD4_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD4_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD4_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD4_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD4_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_TOUCH_PAD4_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD4_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD4_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD4_FUN_IE_S 13 +/* RTC_IO_TOUCH_PAD4_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTCK*/ +#define RTC_IO_TOUCH_PAD4_TO_GPIO (BIT(12)) +#define RTC_IO_TOUCH_PAD4_TO_GPIO_M (BIT(12)) +#define RTC_IO_TOUCH_PAD4_TO_GPIO_V 0x1 +#define RTC_IO_TOUCH_PAD4_TO_GPIO_S 12 + +#define RTC_IO_TOUCH_PAD5_REG (DR_REG_RTCIO_BASE + 0xa8) +/* RTC_IO_TOUCH_PAD5_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_TOUCH_PAD5_HOLD (BIT(31)) +#define RTC_IO_TOUCH_PAD5_HOLD_M (BIT(31)) +#define RTC_IO_TOUCH_PAD5_HOLD_V 0x1 +#define RTC_IO_TOUCH_PAD5_HOLD_S 31 +/* RTC_IO_TOUCH_PAD5_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_TOUCH_PAD5_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD5_DRV_M ((RTC_IO_TOUCH_PAD5_DRV_V)<<(RTC_IO_TOUCH_PAD5_DRV_S)) +#define RTC_IO_TOUCH_PAD5_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD5_DRV_S 29 +/* RTC_IO_TOUCH_PAD5_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_TOUCH_PAD5_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD5_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD5_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD5_RDE_S 28 +/* RTC_IO_TOUCH_PAD5_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_TOUCH_PAD5_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD5_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD5_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD5_RUE_S 27 +/* RTC_IO_TOUCH_PAD5_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ +#define RTC_IO_TOUCH_PAD5_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD5_DAC_M ((RTC_IO_TOUCH_PAD5_DAC_V)<<(RTC_IO_TOUCH_PAD5_DAC_S)) +#define RTC_IO_TOUCH_PAD5_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD5_DAC_S 23 +/* RTC_IO_TOUCH_PAD5_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: start touch sensor.*/ +#define RTC_IO_TOUCH_PAD5_START (BIT(22)) +#define RTC_IO_TOUCH_PAD5_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD5_START_V 0x1 +#define RTC_IO_TOUCH_PAD5_START_S 22 +/* RTC_IO_TOUCH_PAD5_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ +#define RTC_IO_TOUCH_PAD5_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD5_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD5_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD5_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD5_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: touch sensor power on.*/ +#define RTC_IO_TOUCH_PAD5_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD5_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD5_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD5_XPD_S 20 +/* RTC_IO_TOUCH_PAD5_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_TOUCH_PAD5_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD5_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD5_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD5_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD5_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD5_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD5_FUN_SEL_M ((RTC_IO_TOUCH_PAD5_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD5_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD5_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD5_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD5_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD5_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD5_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD5_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD5_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD5_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD5_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD5_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD5_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD5_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD5_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD5_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD5_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD5_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD5_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD5_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_TOUCH_PAD5_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD5_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD5_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD5_FUN_IE_S 13 +/* RTC_IO_TOUCH_PAD5_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTDI*/ +#define RTC_IO_TOUCH_PAD5_TO_GPIO (BIT(12)) +#define RTC_IO_TOUCH_PAD5_TO_GPIO_M (BIT(12)) +#define RTC_IO_TOUCH_PAD5_TO_GPIO_V 0x1 +#define RTC_IO_TOUCH_PAD5_TO_GPIO_S 12 + +#define RTC_IO_TOUCH_PAD6_REG (DR_REG_RTCIO_BASE + 0xac) +/* RTC_IO_TOUCH_PAD6_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_TOUCH_PAD6_HOLD (BIT(31)) +#define RTC_IO_TOUCH_PAD6_HOLD_M (BIT(31)) +#define RTC_IO_TOUCH_PAD6_HOLD_V 0x1 +#define RTC_IO_TOUCH_PAD6_HOLD_S 31 +/* RTC_IO_TOUCH_PAD6_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_TOUCH_PAD6_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD6_DRV_M ((RTC_IO_TOUCH_PAD6_DRV_V)<<(RTC_IO_TOUCH_PAD6_DRV_S)) +#define RTC_IO_TOUCH_PAD6_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD6_DRV_S 29 +/* RTC_IO_TOUCH_PAD6_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_TOUCH_PAD6_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD6_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD6_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD6_RDE_S 28 +/* RTC_IO_TOUCH_PAD6_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_TOUCH_PAD6_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD6_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD6_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD6_RUE_S 27 +/* RTC_IO_TOUCH_PAD6_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ +#define RTC_IO_TOUCH_PAD6_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD6_DAC_M ((RTC_IO_TOUCH_PAD6_DAC_V)<<(RTC_IO_TOUCH_PAD6_DAC_S)) +#define RTC_IO_TOUCH_PAD6_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD6_DAC_S 23 +/* RTC_IO_TOUCH_PAD6_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: start touch sensor.*/ +#define RTC_IO_TOUCH_PAD6_START (BIT(22)) +#define RTC_IO_TOUCH_PAD6_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD6_START_V 0x1 +#define RTC_IO_TOUCH_PAD6_START_S 22 +/* RTC_IO_TOUCH_PAD6_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ +#define RTC_IO_TOUCH_PAD6_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD6_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD6_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD6_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD6_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: touch sensor power on.*/ +#define RTC_IO_TOUCH_PAD6_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD6_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD6_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD6_XPD_S 20 +/* RTC_IO_TOUCH_PAD6_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_TOUCH_PAD6_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD6_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD6_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD6_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD6_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD6_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD6_FUN_SEL_M ((RTC_IO_TOUCH_PAD6_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD6_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD6_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD6_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD6_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD6_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD6_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD6_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD6_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD6_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD6_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD6_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD6_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD6_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD6_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD6_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD6_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD6_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD6_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD6_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_TOUCH_PAD6_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD6_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD6_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD6_FUN_IE_S 13 +/* RTC_IO_TOUCH_PAD6_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTMS*/ +#define RTC_IO_TOUCH_PAD6_TO_GPIO (BIT(12)) +#define RTC_IO_TOUCH_PAD6_TO_GPIO_M (BIT(12)) +#define RTC_IO_TOUCH_PAD6_TO_GPIO_V 0x1 +#define RTC_IO_TOUCH_PAD6_TO_GPIO_S 12 + +#define RTC_IO_TOUCH_PAD7_REG (DR_REG_RTCIO_BASE + 0xb0) +/* RTC_IO_TOUCH_PAD7_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: hold the current value of the output when setting the hold to Ò1Ó*/ +#define RTC_IO_TOUCH_PAD7_HOLD (BIT(31)) +#define RTC_IO_TOUCH_PAD7_HOLD_M (BIT(31)) +#define RTC_IO_TOUCH_PAD7_HOLD_V 0x1 +#define RTC_IO_TOUCH_PAD7_HOLD_S 31 +/* RTC_IO_TOUCH_PAD7_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: the driver strength of the pad*/ +#define RTC_IO_TOUCH_PAD7_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD7_DRV_M ((RTC_IO_TOUCH_PAD7_DRV_V)<<(RTC_IO_TOUCH_PAD7_DRV_S)) +#define RTC_IO_TOUCH_PAD7_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD7_DRV_S 29 +/* RTC_IO_TOUCH_PAD7_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: the pull down enable of the pad*/ +#define RTC_IO_TOUCH_PAD7_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD7_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD7_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD7_RDE_S 28 +/* RTC_IO_TOUCH_PAD7_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: the pull up enable of the pad*/ +#define RTC_IO_TOUCH_PAD7_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD7_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD7_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD7_RUE_S 27 +/* RTC_IO_TOUCH_PAD7_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ +#define RTC_IO_TOUCH_PAD7_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD7_DAC_M ((RTC_IO_TOUCH_PAD7_DAC_V)<<(RTC_IO_TOUCH_PAD7_DAC_S)) +#define RTC_IO_TOUCH_PAD7_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD7_DAC_S 23 +/* RTC_IO_TOUCH_PAD7_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: start touch sensor.*/ +#define RTC_IO_TOUCH_PAD7_START (BIT(22)) +#define RTC_IO_TOUCH_PAD7_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD7_START_V 0x1 +#define RTC_IO_TOUCH_PAD7_START_S 22 +/* RTC_IO_TOUCH_PAD7_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ +#define RTC_IO_TOUCH_PAD7_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD7_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD7_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD7_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD7_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: touch sensor power on.*/ +#define RTC_IO_TOUCH_PAD7_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD7_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD7_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD7_XPD_S 20 +/* RTC_IO_TOUCH_PAD7_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ +#define RTC_IO_TOUCH_PAD7_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD7_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD7_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD7_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD7_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: the functional selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD7_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD7_FUN_SEL_M ((RTC_IO_TOUCH_PAD7_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD7_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD7_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD7_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD7_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: the sleep status selection signal of the pad*/ +#define RTC_IO_TOUCH_PAD7_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD7_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD7_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD7_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD7_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: the input enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD7_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD7_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD7_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD7_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD7_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: the output enable of the pad in sleep status*/ +#define RTC_IO_TOUCH_PAD7_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD7_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD7_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD7_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD7_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: the input enable of the pad*/ +#define RTC_IO_TOUCH_PAD7_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD7_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD7_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD7_FUN_IE_S 13 +/* RTC_IO_TOUCH_PAD7_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO27*/ +#define RTC_IO_TOUCH_PAD7_TO_GPIO (BIT(12)) +#define RTC_IO_TOUCH_PAD7_TO_GPIO_M (BIT(12)) +#define RTC_IO_TOUCH_PAD7_TO_GPIO_V 0x1 +#define RTC_IO_TOUCH_PAD7_TO_GPIO_S 12 + +#define RTC_IO_TOUCH_PAD8_REG (DR_REG_RTCIO_BASE + 0xb4) +/* RTC_IO_TOUCH_PAD8_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ +#define RTC_IO_TOUCH_PAD8_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD8_DAC_M ((RTC_IO_TOUCH_PAD8_DAC_V)<<(RTC_IO_TOUCH_PAD8_DAC_S)) +#define RTC_IO_TOUCH_PAD8_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD8_DAC_S 23 +/* RTC_IO_TOUCH_PAD8_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: start touch sensor.*/ +#define RTC_IO_TOUCH_PAD8_START (BIT(22)) +#define RTC_IO_TOUCH_PAD8_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD8_START_V 0x1 +#define RTC_IO_TOUCH_PAD8_START_S 22 +/* RTC_IO_TOUCH_PAD8_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ +#define RTC_IO_TOUCH_PAD8_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD8_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD8_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD8_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD8_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: touch sensor power on.*/ +#define RTC_IO_TOUCH_PAD8_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD8_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD8_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD8_XPD_S 20 +/* RTC_IO_TOUCH_PAD8_TO_GPIO : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale*/ +#define RTC_IO_TOUCH_PAD8_TO_GPIO (BIT(19)) +#define RTC_IO_TOUCH_PAD8_TO_GPIO_M (BIT(19)) +#define RTC_IO_TOUCH_PAD8_TO_GPIO_V 0x1 +#define RTC_IO_TOUCH_PAD8_TO_GPIO_S 19 + +#define RTC_IO_TOUCH_PAD9_REG (DR_REG_RTCIO_BASE + 0xb8) +/* RTC_IO_TOUCH_PAD9_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/ +#define RTC_IO_TOUCH_PAD9_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD9_DAC_M ((RTC_IO_TOUCH_PAD9_DAC_V)<<(RTC_IO_TOUCH_PAD9_DAC_S)) +#define RTC_IO_TOUCH_PAD9_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD9_DAC_S 23 +/* RTC_IO_TOUCH_PAD9_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: start touch sensor.*/ +#define RTC_IO_TOUCH_PAD9_START (BIT(22)) +#define RTC_IO_TOUCH_PAD9_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD9_START_V 0x1 +#define RTC_IO_TOUCH_PAD9_START_S 22 +/* RTC_IO_TOUCH_PAD9_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: default touch sensor tie option. 0: tie low 1: tie high.*/ +#define RTC_IO_TOUCH_PAD9_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD9_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD9_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD9_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD9_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: touch sensor power on.*/ +#define RTC_IO_TOUCH_PAD9_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD9_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD9_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD9_XPD_S 20 +/* RTC_IO_TOUCH_PAD9_TO_GPIO : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale*/ +#define RTC_IO_TOUCH_PAD9_TO_GPIO (BIT(19)) +#define RTC_IO_TOUCH_PAD9_TO_GPIO_M (BIT(19)) +#define RTC_IO_TOUCH_PAD9_TO_GPIO_V 0x1 +#define RTC_IO_TOUCH_PAD9_TO_GPIO_S 19 + +#define RTC_IO_EXT_WAKEUP0_REG (DR_REG_RTCIO_BASE + 0xbc) +/* RTC_IO_EXT_WAKEUP0_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */ +/*description: select the wakeup source Ó0Ó select GPIO0 Ó1Ó select GPIO2 ...Ò17Ó select GPIO17*/ +#define RTC_IO_EXT_WAKEUP0_SEL 0x0000001F +#define RTC_IO_EXT_WAKEUP0_SEL_M ((RTC_IO_EXT_WAKEUP0_SEL_V)<<(RTC_IO_EXT_WAKEUP0_SEL_S)) +#define RTC_IO_EXT_WAKEUP0_SEL_V 0x1F +#define RTC_IO_EXT_WAKEUP0_SEL_S 27 + +#define RTC_IO_XTL_EXT_CTR_REG (DR_REG_RTCIO_BASE + 0xc0) +/* RTC_IO_XTL_EXT_CTR_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */ +/*description: select the external xtl power source Ó0Ó select GPIO0 Ó1Ó select + GPIO2 ...Ò17Ó select GPIO17*/ +#define RTC_IO_XTL_EXT_CTR_SEL 0x0000001F +#define RTC_IO_XTL_EXT_CTR_SEL_M ((RTC_IO_XTL_EXT_CTR_SEL_V)<<(RTC_IO_XTL_EXT_CTR_SEL_S)) +#define RTC_IO_XTL_EXT_CTR_SEL_V 0x1F +#define RTC_IO_XTL_EXT_CTR_SEL_S 27 + +#define RTC_IO_SAR_I2C_IO_REG (DR_REG_RTCIO_BASE + 0xc4) +/* RTC_IO_SAR_I2C_SDA_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: Ò0Ó using TOUCH_PAD[1] as i2c sda Ò1Ó using TOUCH_PAD[3] as i2c sda*/ +#define RTC_IO_SAR_I2C_SDA_SEL 0x00000003 +#define RTC_IO_SAR_I2C_SDA_SEL_M ((RTC_IO_SAR_I2C_SDA_SEL_V)<<(RTC_IO_SAR_I2C_SDA_SEL_S)) +#define RTC_IO_SAR_I2C_SDA_SEL_V 0x3 +#define RTC_IO_SAR_I2C_SDA_SEL_S 30 +/* RTC_IO_SAR_I2C_SCL_SEL : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ +/*description: Ò0Ó using TOUCH_PAD[0] as i2c clk Ò1Ó using TOUCH_PAD[2] as i2c clk*/ +#define RTC_IO_SAR_I2C_SCL_SEL 0x00000003 +#define RTC_IO_SAR_I2C_SCL_SEL_M ((RTC_IO_SAR_I2C_SCL_SEL_V)<<(RTC_IO_SAR_I2C_SCL_SEL_S)) +#define RTC_IO_SAR_I2C_SCL_SEL_V 0x3 +#define RTC_IO_SAR_I2C_SCL_SEL_S 28 +/* RTC_IO_SAR_DEBUG_BIT_SEL : R/W ;bitpos:[27:23] ;default: 5'h0 ; */ +/*description: */ +#define RTC_IO_SAR_DEBUG_BIT_SEL 0x0000001F +#define RTC_IO_SAR_DEBUG_BIT_SEL_M ((RTC_IO_SAR_DEBUG_BIT_SEL_V)<<(RTC_IO_SAR_DEBUG_BIT_SEL_S)) +#define RTC_IO_SAR_DEBUG_BIT_SEL_V 0x1F +#define RTC_IO_SAR_DEBUG_BIT_SEL_S 23 + +#define RTC_IO_DATE_REG (DR_REG_RTCIO_BASE + 0xc8) +/* RTC_IO_IO_DATE : R/W ;bitpos:[27:0] ;default: 28'h1603160 ; */ +/*description: date*/ +#define RTC_IO_IO_DATE 0x0FFFFFFF +#define RTC_IO_IO_DATE_M ((RTC_IO_IO_DATE_V)<<(RTC_IO_IO_DATE_S)) +#define RTC_IO_IO_DATE_V 0xFFFFFFF +#define RTC_IO_IO_DATE_S 0 +#define RTC_IO_RTC_IO_DATE_VERSION 0x1703160 + + + + +#endif /*_SOC_RTC_IO_REG_H_ */ + + diff --git a/components/soc/esp32/include/soc/spi_reg.h b/components/soc/esp32/include/soc/spi_reg.h index 0cc27b899..fac2965c7 100644 --- a/components/soc/esp32/include/soc/spi_reg.h +++ b/components/soc/esp32/include/soc/spi_reg.h @@ -1,1713 +1,1713 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef __SPI_REG_H__ -#define __SPI_REG_H__ - - -#include "soc.h" -#define REG_SPI_BASE(i) (DR_REG_SPI1_BASE + (((i)>1) ? (((i)* 0x1000) + 0x20000) : (((~(i)) & 1)* 0x1000 ))) - -#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0) -/* SPI_FLASH_READ : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: Read flash enable. Read flash operation will be triggered when - the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ -#define SPI_FLASH_READ (BIT(31)) -#define SPI_FLASH_READ_M (BIT(31)) -#define SPI_FLASH_READ_V 0x1 -#define SPI_FLASH_READ_S 31 -/* SPI_FLASH_WREN : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Write flash enable. Write enable command will be sent when the - bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ -#define SPI_FLASH_WREN (BIT(30)) -#define SPI_FLASH_WREN_M (BIT(30)) -#define SPI_FLASH_WREN_V 0x1 -#define SPI_FLASH_WREN_S 30 -/* SPI_FLASH_WRDI : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: Write flash disable. Write disable command will be sent when - the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ -#define SPI_FLASH_WRDI (BIT(29)) -#define SPI_FLASH_WRDI_M (BIT(29)) -#define SPI_FLASH_WRDI_V 0x1 -#define SPI_FLASH_WRDI_S 29 -/* SPI_FLASH_RDID : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: Read JEDEC ID . Read ID command will be sent when the bit is - set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ -#define SPI_FLASH_RDID (BIT(28)) -#define SPI_FLASH_RDID_M (BIT(28)) -#define SPI_FLASH_RDID_V 0x1 -#define SPI_FLASH_RDID_S 28 -/* SPI_FLASH_RDSR : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: Read status register-1. Read status operation will be triggered - when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ -#define SPI_FLASH_RDSR (BIT(27)) -#define SPI_FLASH_RDSR_M (BIT(27)) -#define SPI_FLASH_RDSR_V 0x1 -#define SPI_FLASH_RDSR_S 27 -/* SPI_FLASH_WRSR : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: Write status register enable. Write status operation will - be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ -#define SPI_FLASH_WRSR (BIT(26)) -#define SPI_FLASH_WRSR_M (BIT(26)) -#define SPI_FLASH_WRSR_V 0x1 -#define SPI_FLASH_WRSR_S 26 -/* SPI_FLASH_PP : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: Page program enable(1 byte ~256 bytes data to be programmed). - Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/ -#define SPI_FLASH_PP (BIT(25)) -#define SPI_FLASH_PP_M (BIT(25)) -#define SPI_FLASH_PP_V 0x1 -#define SPI_FLASH_PP_S 25 -/* SPI_FLASH_SE : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: Sector erase enable. A 4KB sector is erased via SPI command 20H. Sector erase operation will be triggered - when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ -#define SPI_FLASH_SE (BIT(24)) -#define SPI_FLASH_SE_M (BIT(24)) -#define SPI_FLASH_SE_V 0x1 -#define SPI_FLASH_SE_S 24 -/* SPI_FLASH_BE : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: Block erase enable. A 64KB block is erased via SPI command D8H. Block erase operation will be triggered - when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ -#define SPI_FLASH_BE (BIT(23)) -#define SPI_FLASH_BE_M (BIT(23)) -#define SPI_FLASH_BE_V 0x1 -#define SPI_FLASH_BE_S 23 -/* SPI_FLASH_CE : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: Chip erase enable. Chip erase operation will be triggered when - the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ -#define SPI_FLASH_CE (BIT(22)) -#define SPI_FLASH_CE_M (BIT(22)) -#define SPI_FLASH_CE_V 0x1 -#define SPI_FLASH_CE_S 22 -/* SPI_FLASH_DP : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Drive Flash into power down. An operation will be triggered - when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ -#define SPI_FLASH_DP (BIT(21)) -#define SPI_FLASH_DP_M (BIT(21)) -#define SPI_FLASH_DP_V 0x1 -#define SPI_FLASH_DP_S 21 -/* SPI_FLASH_RES : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: This bit combined with reg_resandres bit releases Flash from - the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/ -#define SPI_FLASH_RES (BIT(20)) -#define SPI_FLASH_RES_M (BIT(20)) -#define SPI_FLASH_RES_V 0x1 -#define SPI_FLASH_RES_S 20 -/* SPI_FLASH_HPM : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: Drive Flash into high performance mode. The bit will be cleared - once the operation done.1: enable 0: disable.*/ -#define SPI_FLASH_HPM (BIT(19)) -#define SPI_FLASH_HPM_M (BIT(19)) -#define SPI_FLASH_HPM_V 0x1 -#define SPI_FLASH_HPM_S 19 -/* SPI_USR : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: User define command enable. An operation will be triggered when - the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ -#define SPI_USR (BIT(18)) -#define SPI_USR_M (BIT(18)) -#define SPI_USR_V 0x1 -#define SPI_USR_S 18 -/* SPI_FLASH_PES : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: program erase suspend bit program erase suspend operation will - be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ -#define SPI_FLASH_PES (BIT(17)) -#define SPI_FLASH_PES_M (BIT(17)) -#define SPI_FLASH_PES_V 0x1 -#define SPI_FLASH_PES_S 17 -/* SPI_FLASH_PER : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: program erase resume bit program erase suspend operation will - be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ -#define SPI_FLASH_PER (BIT(16)) -#define SPI_FLASH_PER_M (BIT(16)) -#define SPI_FLASH_PER_V 0x1 -#define SPI_FLASH_PER_S 16 - -#define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x4) +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef __SPI_REG_H__ +#define __SPI_REG_H__ + + +#include "soc.h" +#define REG_SPI_BASE(i) (DR_REG_SPI1_BASE + (((i)>1) ? (((i)* 0x1000) + 0x20000) : (((~(i)) & 1)* 0x1000 ))) + +#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0) +/* SPI_FLASH_READ : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Read flash enable. Read flash operation will be triggered when + the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ +#define SPI_FLASH_READ (BIT(31)) +#define SPI_FLASH_READ_M (BIT(31)) +#define SPI_FLASH_READ_V 0x1 +#define SPI_FLASH_READ_S 31 +/* SPI_FLASH_WREN : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Write flash enable. Write enable command will be sent when the + bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ +#define SPI_FLASH_WREN (BIT(30)) +#define SPI_FLASH_WREN_M (BIT(30)) +#define SPI_FLASH_WREN_V 0x1 +#define SPI_FLASH_WREN_S 30 +/* SPI_FLASH_WRDI : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Write flash disable. Write disable command will be sent when + the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ +#define SPI_FLASH_WRDI (BIT(29)) +#define SPI_FLASH_WRDI_M (BIT(29)) +#define SPI_FLASH_WRDI_V 0x1 +#define SPI_FLASH_WRDI_S 29 +/* SPI_FLASH_RDID : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Read JEDEC ID . Read ID command will be sent when the bit is + set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ +#define SPI_FLASH_RDID (BIT(28)) +#define SPI_FLASH_RDID_M (BIT(28)) +#define SPI_FLASH_RDID_V 0x1 +#define SPI_FLASH_RDID_S 28 +/* SPI_FLASH_RDSR : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Read status register-1. Read status operation will be triggered + when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_FLASH_RDSR (BIT(27)) +#define SPI_FLASH_RDSR_M (BIT(27)) +#define SPI_FLASH_RDSR_V 0x1 +#define SPI_FLASH_RDSR_S 27 +/* SPI_FLASH_WRSR : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Write status register enable. Write status operation will + be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_FLASH_WRSR (BIT(26)) +#define SPI_FLASH_WRSR_M (BIT(26)) +#define SPI_FLASH_WRSR_V 0x1 +#define SPI_FLASH_WRSR_S 26 +/* SPI_FLASH_PP : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: Page program enable(1 byte ~256 bytes data to be programmed). + Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/ +#define SPI_FLASH_PP (BIT(25)) +#define SPI_FLASH_PP_M (BIT(25)) +#define SPI_FLASH_PP_V 0x1 +#define SPI_FLASH_PP_S 25 +/* SPI_FLASH_SE : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: Sector erase enable. A 4KB sector is erased via SPI command 20H. Sector erase operation will be triggered + when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_FLASH_SE (BIT(24)) +#define SPI_FLASH_SE_M (BIT(24)) +#define SPI_FLASH_SE_V 0x1 +#define SPI_FLASH_SE_S 24 +/* SPI_FLASH_BE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: Block erase enable. A 64KB block is erased via SPI command D8H. Block erase operation will be triggered + when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_FLASH_BE (BIT(23)) +#define SPI_FLASH_BE_M (BIT(23)) +#define SPI_FLASH_BE_V 0x1 +#define SPI_FLASH_BE_S 23 +/* SPI_FLASH_CE : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Chip erase enable. Chip erase operation will be triggered when + the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_FLASH_CE (BIT(22)) +#define SPI_FLASH_CE_M (BIT(22)) +#define SPI_FLASH_CE_V 0x1 +#define SPI_FLASH_CE_S 22 +/* SPI_FLASH_DP : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Drive Flash into power down. An operation will be triggered + when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_FLASH_DP (BIT(21)) +#define SPI_FLASH_DP_M (BIT(21)) +#define SPI_FLASH_DP_V 0x1 +#define SPI_FLASH_DP_S 21 +/* SPI_FLASH_RES : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: This bit combined with reg_resandres bit releases Flash from + the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_FLASH_RES (BIT(20)) +#define SPI_FLASH_RES_M (BIT(20)) +#define SPI_FLASH_RES_V 0x1 +#define SPI_FLASH_RES_S 20 +/* SPI_FLASH_HPM : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: Drive Flash into high performance mode. The bit will be cleared + once the operation done.1: enable 0: disable.*/ +#define SPI_FLASH_HPM (BIT(19)) +#define SPI_FLASH_HPM_M (BIT(19)) +#define SPI_FLASH_HPM_V 0x1 +#define SPI_FLASH_HPM_S 19 +/* SPI_USR : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: User define command enable. An operation will be triggered when + the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_USR (BIT(18)) +#define SPI_USR_M (BIT(18)) +#define SPI_USR_V 0x1 +#define SPI_USR_S 18 +/* SPI_FLASH_PES : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: program erase suspend bit program erase suspend operation will + be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_FLASH_PES (BIT(17)) +#define SPI_FLASH_PES_M (BIT(17)) +#define SPI_FLASH_PES_V 0x1 +#define SPI_FLASH_PES_S 17 +/* SPI_FLASH_PER : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: program erase resume bit program erase suspend operation will + be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ +#define SPI_FLASH_PER (BIT(16)) +#define SPI_FLASH_PER_M (BIT(16)) +#define SPI_FLASH_PER_V 0x1 +#define SPI_FLASH_PER_S 16 + +#define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x4) //The CSV actually is wrong here. It indicates that the lower 8 bits of this register are reserved. This is not true, //all 32 bits of SPI_ADDR_REG are usable/used. - -#define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8) -/* SPI_WR_BIT_ORDER : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: In command address write-data (MOSI) phases 1: LSB firs 0: MSB first*/ -#define SPI_WR_BIT_ORDER (BIT(26)) -#define SPI_WR_BIT_ORDER_M (BIT(26)) -#define SPI_WR_BIT_ORDER_V 0x1 -#define SPI_WR_BIT_ORDER_S 26 -/* SPI_RD_BIT_ORDER : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: In read-data (MISO) phase 1: LSB first 0: MSB first*/ -#define SPI_RD_BIT_ORDER (BIT(25)) -#define SPI_RD_BIT_ORDER_M (BIT(25)) -#define SPI_RD_BIT_ORDER_V 0x1 -#define SPI_RD_BIT_ORDER_S 25 -/* SPI_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: In the read operations address phase and read-data phase apply - 4 signals. 1: enable 0: disable.*/ -#define SPI_FREAD_QIO (BIT(24)) -#define SPI_FREAD_QIO_M (BIT(24)) -#define SPI_FREAD_QIO_V 0x1 -#define SPI_FREAD_QIO_S 24 -/* SPI_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: In the read operations address phase and read-data phase apply - 2 signals. 1: enable 0: disable.*/ -#define SPI_FREAD_DIO (BIT(23)) -#define SPI_FREAD_DIO_M (BIT(23)) -#define SPI_FREAD_DIO_V 0x1 -#define SPI_FREAD_DIO_S 23 -/* SPI_WRSR_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: two bytes data will be written to status register when it is - set. 1: enable 0: disable.*/ -#define SPI_WRSR_2B (BIT(22)) -#define SPI_WRSR_2B_M (BIT(22)) -#define SPI_WRSR_2B_V 0x1 -#define SPI_WRSR_2B_S 22 -/* SPI_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */ -/*description: Write protect signal output when SPI is idle. 1: output high 0: output low.*/ -#define SPI_WP_REG (BIT(21)) -#define SPI_WP_REG_M (BIT(21)) -#define SPI_WP_REG_V 0x1 -#define SPI_WP_REG_S 21 -/* SPI_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/ -#define SPI_FREAD_QUAD (BIT(20)) -#define SPI_FREAD_QUAD_M (BIT(20)) -#define SPI_FREAD_QUAD_V 0x1 -#define SPI_FREAD_QUAD_S 20 -/* SPI_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */ -/*description: The Device ID is read out to SPI_RD_STATUS register, this bit - combine with spi_flash_res bit. 1: enable 0: disable.*/ -#define SPI_RESANDRES (BIT(15)) -#define SPI_RESANDRES_M (BIT(15)) -#define SPI_RESANDRES_V 0x1 -#define SPI_RESANDRES_S 15 -/* SPI_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: In the read operations read-data phase apply 2 signals. 1: enable 0: disable.*/ -#define SPI_FREAD_DUAL (BIT(14)) -#define SPI_FREAD_DUAL_M (BIT(14)) -#define SPI_FREAD_DUAL_V 0x1 -#define SPI_FREAD_DUAL_S 14 -/* SPI_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: This bit enable the bits: spi_fread_qio spi_fread_dio spi_fread_qout - and spi_fread_dout. 1: enable 0: disable.*/ -#define SPI_FASTRD_MODE (BIT(13)) -#define SPI_FASTRD_MODE_M (BIT(13)) -#define SPI_FASTRD_MODE_V 0x1 -#define SPI_FASTRD_MODE_S 13 -/* SPI_WAIT_FLASH_IDLE_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: wait flash idle when program flash or erase flash. 1: enable 0: disable.*/ -#define SPI_WAIT_FLASH_IDLE_EN (BIT(12)) -#define SPI_WAIT_FLASH_IDLE_EN_M (BIT(12)) -#define SPI_WAIT_FLASH_IDLE_EN_V 0x1 -#define SPI_WAIT_FLASH_IDLE_EN_S 12 -/* SPI_TX_CRC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: For SPI1 enable crc32 when writing encrypted data to flash. - 1: enable 0:disable*/ -#define SPI_TX_CRC_EN (BIT(11)) -#define SPI_TX_CRC_EN_M (BIT(11)) -#define SPI_TX_CRC_EN_V 0x1 -#define SPI_TX_CRC_EN_S 11 -/* SPI_FCS_CRC_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: For SPI1 initialize crc32 module before writing encrypted data - to flash. Active low.*/ -#define SPI_FCS_CRC_EN (BIT(10)) -#define SPI_FCS_CRC_EN_M (BIT(10)) -#define SPI_FCS_CRC_EN_V 0x1 -#define SPI_FCS_CRC_EN_S 10 - -#define SPI_CTRL1_REG(i) (REG_SPI_BASE(i) + 0xC) -/* SPI_CS_HOLD_DELAY : R/W ;bitpos:[31:28] ;default: 4'h5 ; */ -/*description: SPI cs signal is delayed by spi clock cycles*/ -#define SPI_CS_HOLD_DELAY 0x0000000F -#define SPI_CS_HOLD_DELAY_M ((SPI_CS_HOLD_DELAY_V)<<(SPI_CS_HOLD_DELAY_S)) -#define SPI_CS_HOLD_DELAY_V 0xF -#define SPI_CS_HOLD_DELAY_S 28 -/* SPI_CS_HOLD_DELAY_RES : R/W ;bitpos:[27:16] ;default: 12'hfff ; */ -/*description: Delay cycles of resume Flash when resume Flash is enable by spi clock.*/ -#define SPI_CS_HOLD_DELAY_RES 0x00000FFF -#define SPI_CS_HOLD_DELAY_RES_M ((SPI_CS_HOLD_DELAY_RES_V)<<(SPI_CS_HOLD_DELAY_RES_S)) -#define SPI_CS_HOLD_DELAY_RES_V 0xFFF -#define SPI_CS_HOLD_DELAY_RES_S 16 - -#define SPI_RD_STATUS_REG(i) (REG_SPI_BASE(i) + 0x10) -/* SPI_STATUS_EXT : R/W ;bitpos:[31:24] ;default: 8'h00 ; */ -/*description: In the slave mode,it is the status for master to read out.*/ -#define SPI_STATUS_EXT 0x000000FF -#define SPI_STATUS_EXT_M ((SPI_STATUS_EXT_V)<<(SPI_STATUS_EXT_S)) -#define SPI_STATUS_EXT_V 0xFF -#define SPI_STATUS_EXT_S 24 -/* SPI_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */ -/*description: Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit.*/ -#define SPI_WB_MODE 0x000000FF -#define SPI_WB_MODE_M ((SPI_WB_MODE_V)<<(SPI_WB_MODE_S)) -#define SPI_WB_MODE_V 0xFF -#define SPI_WB_MODE_S 16 -/* SPI_STATUS : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ -/*description: In the slave mode, it is the status for master to read out.*/ -#define SPI_STATUS 0x0000FFFF -#define SPI_STATUS_M ((SPI_STATUS_V)<<(SPI_STATUS_S)) -#define SPI_STATUS_V 0xFFFF -#define SPI_STATUS_S 0 - -#define SPI_CTRL2_REG(i) (REG_SPI_BASE(i) + 0x14) -/* SPI_CS_DELAY_NUM : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: spi_cs signal is delayed by system clock cycles*/ -#define SPI_CS_DELAY_NUM 0x0000000F -#define SPI_CS_DELAY_NUM_M ((SPI_CS_DELAY_NUM_V)<<(SPI_CS_DELAY_NUM_S)) -#define SPI_CS_DELAY_NUM_V 0xF -#define SPI_CS_DELAY_NUM_S 28 -/* SPI_CS_DELAY_MODE : R/W ;bitpos:[27:26] ;default: 2'h0 ; */ -/*description: spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge - or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ -#define SPI_CS_DELAY_MODE 0x00000003 -#define SPI_CS_DELAY_MODE_M ((SPI_CS_DELAY_MODE_V)<<(SPI_CS_DELAY_MODE_S)) -#define SPI_CS_DELAY_MODE_V 0x3 -#define SPI_CS_DELAY_MODE_S 26 -/* SPI_MOSI_DELAY_NUM : R/W ;bitpos:[25:23] ;default: 3'h0 ; */ -/*description: MOSI signals are delayed by system clock cycles*/ -#define SPI_MOSI_DELAY_NUM 0x00000007 -#define SPI_MOSI_DELAY_NUM_M ((SPI_MOSI_DELAY_NUM_V)<<(SPI_MOSI_DELAY_NUM_S)) -#define SPI_MOSI_DELAY_NUM_V 0x7 -#define SPI_MOSI_DELAY_NUM_S 23 -/* SPI_MOSI_DELAY_MODE : R/W ;bitpos:[22:21] ;default: 2'h0 ; */ -/*description: MOSI signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge - or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ -#define SPI_MOSI_DELAY_MODE 0x00000003 -#define SPI_MOSI_DELAY_MODE_M ((SPI_MOSI_DELAY_MODE_V)<<(SPI_MOSI_DELAY_MODE_S)) -#define SPI_MOSI_DELAY_MODE_V 0x3 -#define SPI_MOSI_DELAY_MODE_S 21 -/* SPI_MISO_DELAY_NUM : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ -/*description: MISO signals are delayed by system clock cycles*/ -#define SPI_MISO_DELAY_NUM 0x00000007 -#define SPI_MISO_DELAY_NUM_M ((SPI_MISO_DELAY_NUM_V)<<(SPI_MISO_DELAY_NUM_S)) -#define SPI_MISO_DELAY_NUM_V 0x7 -#define SPI_MISO_DELAY_NUM_S 18 -/* SPI_MISO_DELAY_MODE : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: MISO signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge - or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ -#define SPI_MISO_DELAY_MODE 0x00000003 -#define SPI_MISO_DELAY_MODE_M ((SPI_MISO_DELAY_MODE_V)<<(SPI_MISO_DELAY_MODE_S)) -#define SPI_MISO_DELAY_MODE_V 0x3 -#define SPI_MISO_DELAY_MODE_S 16 -/* SPI_CK_OUT_HIGH_MODE : R/W ;bitpos:[15:12] ;default: 4'h0 ; */ -/*description: modify spi clock duty ratio when the value is lager than 8, - the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits.*/ -#define SPI_CK_OUT_HIGH_MODE 0x0000000F -#define SPI_CK_OUT_HIGH_MODE_M ((SPI_CK_OUT_HIGH_MODE_V)<<(SPI_CK_OUT_HIGH_MODE_S)) -#define SPI_CK_OUT_HIGH_MODE_V 0xF -#define SPI_CK_OUT_HIGH_MODE_S 12 -/* SPI_CK_OUT_LOW_MODE : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ -/*description: modify spi clock duty ratio when the value is lager than 8, - the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits.*/ -#define SPI_CK_OUT_LOW_MODE 0x0000000F -#define SPI_CK_OUT_LOW_MODE_M ((SPI_CK_OUT_LOW_MODE_V)<<(SPI_CK_OUT_LOW_MODE_S)) -#define SPI_CK_OUT_LOW_MODE_V 0xF -#define SPI_CK_OUT_LOW_MODE_S 8 -/* SPI_HOLD_TIME : R/W ;bitpos:[7:4] ;default: 4'h1 ; */ -/*description: delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit.*/ -#define SPI_HOLD_TIME 0x0000000F -#define SPI_HOLD_TIME_M ((SPI_HOLD_TIME_V)<<(SPI_HOLD_TIME_S)) -#define SPI_HOLD_TIME_V 0xF -#define SPI_HOLD_TIME_S 4 -/* SPI_SETUP_TIME : R/W ;bitpos:[3:0] ;default: 4'h1 ; */ -/*description: (cycles-1) of ¡°prepare¡± phase by spi clock, this bits combined - with spi_cs_setup bit.*/ -#define SPI_SETUP_TIME 0x0000000F -#define SPI_SETUP_TIME_M ((SPI_SETUP_TIME_V)<<(SPI_SETUP_TIME_S)) -#define SPI_SETUP_TIME_V 0xF -#define SPI_SETUP_TIME_S 0 - -#define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0x18) -/* SPI_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b1 ; */ -/*description: In the master mode 1: spi_clk is eqaul to system 0: spi_clk is - divided from system clock.*/ -#define SPI_CLK_EQU_SYSCLK (BIT(31)) -#define SPI_CLK_EQU_SYSCLK_M (BIT(31)) -#define SPI_CLK_EQU_SYSCLK_V 0x1 -#define SPI_CLK_EQU_SYSCLK_S 31 -/* SPI_CLKDIV_PRE : R/W ;bitpos:[30:18] ;default: 13'b0 ; */ -/*description: In the master mode it is pre-divider of spi_clk.*/ -#define SPI_CLKDIV_PRE 0x00001FFF -#define SPI_CLKDIV_PRE_M ((SPI_CLKDIV_PRE_V)<<(SPI_CLKDIV_PRE_S)) -#define SPI_CLKDIV_PRE_V 0x1FFF -#define SPI_CLKDIV_PRE_S 18 -/* SPI_CLKCNT_N : R/W ;bitpos:[17:12] ;default: 6'h3 ; */ -/*description: In the master mode it is the divider of spi_clk. So spi_clk frequency - is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)*/ -#define SPI_CLKCNT_N 0x0000003F -#define SPI_CLKCNT_N_M ((SPI_CLKCNT_N_V)<<(SPI_CLKCNT_N_S)) -#define SPI_CLKCNT_N_V 0x3F -#define SPI_CLKCNT_N_S 12 -/* SPI_CLKCNT_H : R/W ;bitpos:[11:6] ;default: 6'h1 ; */ -/*description: In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In - the slave mode it must be 0.*/ -#define SPI_CLKCNT_H 0x0000003F -#define SPI_CLKCNT_H_M ((SPI_CLKCNT_H_V)<<(SPI_CLKCNT_H_S)) -#define SPI_CLKCNT_H_V 0x3F -#define SPI_CLKCNT_H_S 6 -/* SPI_CLKCNT_L : R/W ;bitpos:[5:0] ;default: 6'h3 ; */ -/*description: In the master mode it must be equal to spi_clkcnt_N. In the slave - mode it must be 0.*/ -#define SPI_CLKCNT_L 0x0000003F -#define SPI_CLKCNT_L_M ((SPI_CLKCNT_L_V)<<(SPI_CLKCNT_L_S)) -#define SPI_CLKCNT_L_V 0x3F -#define SPI_CLKCNT_L_S 0 - -#define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x1C) -/* SPI_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */ -/*description: This bit enable the command phase of an operation.*/ -#define SPI_USR_COMMAND (BIT(31)) -#define SPI_USR_COMMAND_M (BIT(31)) -#define SPI_USR_COMMAND_V 0x1 -#define SPI_USR_COMMAND_S 31 -/* SPI_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: This bit enable the address phase of an operation.*/ -#define SPI_USR_ADDR (BIT(30)) -#define SPI_USR_ADDR_M (BIT(30)) -#define SPI_USR_ADDR_V 0x1 -#define SPI_USR_ADDR_S 30 -/* SPI_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: This bit enable the dummy phase of an operation.*/ -#define SPI_USR_DUMMY (BIT(29)) -#define SPI_USR_DUMMY_M (BIT(29)) -#define SPI_USR_DUMMY_V 0x1 -#define SPI_USR_DUMMY_S 29 -/* SPI_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: This bit enable the read-data phase of an operation.*/ -#define SPI_USR_MISO (BIT(28)) -#define SPI_USR_MISO_M (BIT(28)) -#define SPI_USR_MISO_V 0x1 -#define SPI_USR_MISO_S 28 -/* SPI_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: This bit enable the write-data phase of an operation.*/ -#define SPI_USR_MOSI (BIT(27)) -#define SPI_USR_MOSI_M (BIT(27)) -#define SPI_USR_MOSI_V 0x1 -#define SPI_USR_MOSI_S 27 -/* SPI_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: spi clock is disable in dummy phase when the bit is enable.*/ -#define SPI_USR_DUMMY_IDLE (BIT(26)) -#define SPI_USR_DUMMY_IDLE_M (BIT(26)) -#define SPI_USR_DUMMY_IDLE_V 0x1 -#define SPI_USR_DUMMY_IDLE_S 26 -/* SPI_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: write-data phase only access to high-part of the buffer spi_w8~spi_w15. - 1: enable 0: disable.*/ -#define SPI_USR_MOSI_HIGHPART (BIT(25)) -#define SPI_USR_MOSI_HIGHPART_M (BIT(25)) -#define SPI_USR_MOSI_HIGHPART_V 0x1 -#define SPI_USR_MOSI_HIGHPART_S 25 -/* SPI_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: read-data phase only access to high-part of the buffer spi_w8~spi_w15. - 1: enable 0: disable.*/ -#define SPI_USR_MISO_HIGHPART (BIT(24)) -#define SPI_USR_MISO_HIGHPART_M (BIT(24)) -#define SPI_USR_MISO_HIGHPART_V 0x1 -#define SPI_USR_MISO_HIGHPART_S 24 -/* SPI_USR_PREP_HOLD : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: spi is hold at prepare state the bit combined with spi_usr_hold_pol bit.*/ -#define SPI_USR_PREP_HOLD (BIT(23)) -#define SPI_USR_PREP_HOLD_M (BIT(23)) -#define SPI_USR_PREP_HOLD_V 0x1 -#define SPI_USR_PREP_HOLD_S 23 -/* SPI_USR_CMD_HOLD : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: spi is hold at command state the bit combined with spi_usr_hold_pol bit.*/ -#define SPI_USR_CMD_HOLD (BIT(22)) -#define SPI_USR_CMD_HOLD_M (BIT(22)) -#define SPI_USR_CMD_HOLD_V 0x1 -#define SPI_USR_CMD_HOLD_S 22 -/* SPI_USR_ADDR_HOLD : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: spi is hold at address state the bit combined with spi_usr_hold_pol bit.*/ -#define SPI_USR_ADDR_HOLD (BIT(21)) -#define SPI_USR_ADDR_HOLD_M (BIT(21)) -#define SPI_USR_ADDR_HOLD_V 0x1 -#define SPI_USR_ADDR_HOLD_S 21 -/* SPI_USR_DUMMY_HOLD : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: spi is hold at dummy state the bit combined with spi_usr_hold_pol bit.*/ -#define SPI_USR_DUMMY_HOLD (BIT(20)) -#define SPI_USR_DUMMY_HOLD_M (BIT(20)) -#define SPI_USR_DUMMY_HOLD_V 0x1 -#define SPI_USR_DUMMY_HOLD_S 20 -/* SPI_USR_DIN_HOLD : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: spi is hold at data in state the bit combined with spi_usr_hold_pol bit.*/ -#define SPI_USR_DIN_HOLD (BIT(19)) -#define SPI_USR_DIN_HOLD_M (BIT(19)) -#define SPI_USR_DIN_HOLD_V 0x1 -#define SPI_USR_DIN_HOLD_S 19 -/* SPI_USR_DOUT_HOLD : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: spi is hold at data out state the bit combined with spi_usr_hold_pol bit.*/ -#define SPI_USR_DOUT_HOLD (BIT(18)) -#define SPI_USR_DOUT_HOLD_M (BIT(18)) -#define SPI_USR_DOUT_HOLD_V 0x1 -#define SPI_USR_DOUT_HOLD_S 18 -/* SPI_USR_HOLD_POL : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: It is combined with hold bits to set the polarity of spi hold - line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low*/ -#define SPI_USR_HOLD_POL (BIT(17)) -#define SPI_USR_HOLD_POL_M (BIT(17)) -#define SPI_USR_HOLD_POL_V 0x1 -#define SPI_USR_HOLD_POL_S 17 -/* SPI_SIO : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: Set the bit to enable 3-line half duplex communication mosi - and miso signals share the same pin. 1: enable 0: disable.*/ -#define SPI_SIO (BIT(16)) -#define SPI_SIO_M (BIT(16)) -#define SPI_SIO_V 0x1 -#define SPI_SIO_S 16 -/* SPI_FWRITE_QIO : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: In the write operations address phase and read-data phase apply 4 signals.*/ -#define SPI_FWRITE_QIO (BIT(15)) -#define SPI_FWRITE_QIO_M (BIT(15)) -#define SPI_FWRITE_QIO_V 0x1 -#define SPI_FWRITE_QIO_S 15 -/* SPI_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: In the write operations address phase and read-data phase apply 2 signals.*/ -#define SPI_FWRITE_DIO (BIT(14)) -#define SPI_FWRITE_DIO_M (BIT(14)) -#define SPI_FWRITE_DIO_V 0x1 -#define SPI_FWRITE_DIO_S 14 -/* SPI_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: In the write operations read-data phase apply 4 signals*/ -#define SPI_FWRITE_QUAD (BIT(13)) -#define SPI_FWRITE_QUAD_M (BIT(13)) -#define SPI_FWRITE_QUAD_V 0x1 -#define SPI_FWRITE_QUAD_S 13 -/* SPI_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: In the write operations read-data phase apply 2 signals*/ -#define SPI_FWRITE_DUAL (BIT(12)) -#define SPI_FWRITE_DUAL_M (BIT(12)) -#define SPI_FWRITE_DUAL_V 0x1 -#define SPI_FWRITE_DUAL_S 12 -/* SPI_WR_BYTE_ORDER : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: In command address write-data (MOSI) phases 1: big-endian 0: litte_endian*/ -#define SPI_WR_BYTE_ORDER (BIT(11)) -#define SPI_WR_BYTE_ORDER_M (BIT(11)) -#define SPI_WR_BYTE_ORDER_V 0x1 -#define SPI_WR_BYTE_ORDER_S 11 -/* SPI_RD_BYTE_ORDER : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: In read-data (MISO) phase 1: big-endian 0: little_endian*/ -#define SPI_RD_BYTE_ORDER (BIT(10)) -#define SPI_RD_BYTE_ORDER_M (BIT(10)) -#define SPI_RD_BYTE_ORDER_V 0x1 -#define SPI_RD_BYTE_ORDER_S 10 -/* SPI_CK_OUT_EDGE : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode.*/ -#define SPI_CK_OUT_EDGE (BIT(7)) -#define SPI_CK_OUT_EDGE_M (BIT(7)) -#define SPI_CK_OUT_EDGE_V 0x1 -#define SPI_CK_OUT_EDGE_S 7 -/* SPI_CK_I_EDGE : R/W ;bitpos:[6] ;default: 1'b1 ; */ -/*description: In the slave mode the bit is same as spi_ck_out_edge in master - mode. It is combined with spi_miso_delay_mode bits.*/ -#define SPI_CK_I_EDGE (BIT(6)) -#define SPI_CK_I_EDGE_M (BIT(6)) -#define SPI_CK_I_EDGE_V 0x1 -#define SPI_CK_I_EDGE_S 6 -/* SPI_CS_SETUP : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: spi cs is enable when spi is in ¡°prepare¡± phase. 1: enable 0: disable.*/ -#define SPI_CS_SETUP (BIT(5)) -#define SPI_CS_SETUP_M (BIT(5)) -#define SPI_CS_SETUP_V 0x1 -#define SPI_CS_SETUP_S 5 -/* SPI_CS_HOLD : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: spi cs keep low when spi is in ¡°done¡± phase. 1: enable 0: disable.*/ -#define SPI_CS_HOLD (BIT(4)) -#define SPI_CS_HOLD_M (BIT(4)) -#define SPI_CS_HOLD_V 0x1 -#define SPI_CS_HOLD_S 4 -/* SPI_DOUTDIN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set the bit to enable full duplex communication. 1: enable 0: disable.*/ -#define SPI_DOUTDIN (BIT(0)) -#define SPI_DOUTDIN_M (BIT(0)) -#define SPI_DOUTDIN_V 0x1 -#define SPI_DOUTDIN_S 0 - -#define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x20) -/* SPI_USR_ADDR_BITLEN : RO ;bitpos:[31:26] ;default: 6'd23 ; */ -/*description: The length in bits of address phase. The register value shall be (bit_num-1).*/ -#define SPI_USR_ADDR_BITLEN 0x0000003F -#define SPI_USR_ADDR_BITLEN_M ((SPI_USR_ADDR_BITLEN_V)<<(SPI_USR_ADDR_BITLEN_S)) -#define SPI_USR_ADDR_BITLEN_V 0x3F -#define SPI_USR_ADDR_BITLEN_S 26 -/* SPI_USR_DUMMY_CYCLELEN : R/W ;bitpos:[7:0] ;default: 8'd7 ; */ -/*description: The length in spi_clk cycles of dummy phase. The register value - shall be (cycle_num-1).*/ -#define SPI_USR_DUMMY_CYCLELEN 0x000000FF -#define SPI_USR_DUMMY_CYCLELEN_M ((SPI_USR_DUMMY_CYCLELEN_V)<<(SPI_USR_DUMMY_CYCLELEN_S)) -#define SPI_USR_DUMMY_CYCLELEN_V 0xFF -#define SPI_USR_DUMMY_CYCLELEN_S 0 - -#define SPI_USER2_REG(i) (REG_SPI_BASE(i) + 0x24) -/* SPI_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */ -/*description: The length in bits of command phase. The register value shall be (bit_num-1)*/ -#define SPI_USR_COMMAND_BITLEN 0x0000000F -#define SPI_USR_COMMAND_BITLEN_M ((SPI_USR_COMMAND_BITLEN_V)<<(SPI_USR_COMMAND_BITLEN_S)) -#define SPI_USR_COMMAND_BITLEN_V 0xF -#define SPI_USR_COMMAND_BITLEN_S 28 -/* SPI_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ -/*description: The value of command.*/ -#define SPI_USR_COMMAND_VALUE 0x0000FFFF -#define SPI_USR_COMMAND_VALUE_M ((SPI_USR_COMMAND_VALUE_V)<<(SPI_USR_COMMAND_VALUE_S)) -#define SPI_USR_COMMAND_VALUE_V 0xFFFF -#define SPI_USR_COMMAND_VALUE_S 0 - -#define SPI_MOSI_DLEN_REG(i) (REG_SPI_BASE(i) + 0x28) -/* SPI_USR_MOSI_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: The length in bits of write-data. The register value shall be (bit_num-1).*/ -#define SPI_USR_MOSI_DBITLEN 0x00FFFFFF -#define SPI_USR_MOSI_DBITLEN_M ((SPI_USR_MOSI_DBITLEN_V)<<(SPI_USR_MOSI_DBITLEN_S)) -#define SPI_USR_MOSI_DBITLEN_V 0xFFFFFF -#define SPI_USR_MOSI_DBITLEN_S 0 - -#define SPI_MISO_DLEN_REG(i) (REG_SPI_BASE(i) + 0x2C) -/* SPI_USR_MISO_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: The length in bits of read-data. The register value shall be (bit_num-1).*/ -#define SPI_USR_MISO_DBITLEN 0x00FFFFFF -#define SPI_USR_MISO_DBITLEN_M ((SPI_USR_MISO_DBITLEN_V)<<(SPI_USR_MISO_DBITLEN_S)) -#define SPI_USR_MISO_DBITLEN_V 0xFFFFFF -#define SPI_USR_MISO_DBITLEN_S 0 - -#define SPI_SLV_WR_STATUS_REG(i) (REG_SPI_BASE(i) + 0x30) -/* SPI_SLV_WR_ST : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: In the slave mode this register are the status register for the - master to write into. In the master mode this register are the higher 32bits in the 64 bits address condition.*/ -#define SPI_SLV_WR_ST 0xFFFFFFFF -#define SPI_SLV_WR_ST_M ((SPI_SLV_WR_ST_V)<<(SPI_SLV_WR_ST_S)) -#define SPI_SLV_WR_ST_V 0xFFFFFFFF -#define SPI_SLV_WR_ST_S 0 - -#define SPI_PIN_REG(i) (REG_SPI_BASE(i) + 0x34) -/* SPI_CS_KEEP_ACTIVE : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: spi cs line keep low when the bit is set.*/ -#define SPI_CS_KEEP_ACTIVE (BIT(30)) -#define SPI_CS_KEEP_ACTIVE_M (BIT(30)) -#define SPI_CS_KEEP_ACTIVE_V 0x1 -#define SPI_CS_KEEP_ACTIVE_S 30 -/* SPI_CK_IDLE_EDGE : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: 1: spi clk line is high when idle 0: spi clk line is low when idle*/ -#define SPI_CK_IDLE_EDGE (BIT(29)) -#define SPI_CK_IDLE_EDGE_M (BIT(29)) -#define SPI_CK_IDLE_EDGE_V 0x1 -#define SPI_CK_IDLE_EDGE_S 29 -/* SPI_MASTER_CK_SEL : R/W ;bitpos:[13:11] ;default: 3'b0 ; */ -/*description: In the master mode spi cs line is enable as spi clk it is combined - with spi_cs0_dis spi_cs1_dis spi_cs2_dis.*/ -#define SPI_MASTER_CK_SEL 0x00000007 -#define SPI_MASTER_CK_SEL_M ((SPI_MASTER_CK_SEL_V)<<(SPI_MASTER_CK_SEL_S)) -#define SPI_MASTER_CK_SEL_V 0x07 -#define SPI_MASTER_CK_SEL_S 11 -/* SPI_MASTER_CS_POL : R/W ;bitpos:[8:6] ;default: 3'b0 ; */ -/*description: In the master mode the bits are the polarity of spi cs line - the value is equivalent to spi_cs ^ spi_master_cs_pol.*/ -#define SPI_MASTER_CS_POL 0x00000007 -#define SPI_MASTER_CS_POL_M ((SPI_MASTER_CS_POL_V)<<(SPI_MASTER_CS_POL_S)) -#define SPI_MASTER_CS_POL_V 0x7 -#define SPI_MASTER_CS_POL_S 6 -/* SPI_CK_DIS : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: 1: spi clk out disable 0: spi clk out enable*/ -#define SPI_CK_DIS (BIT(5)) -#define SPI_CK_DIS_M (BIT(5)) -#define SPI_CK_DIS_V 0x1 -#define SPI_CK_DIS_S 5 -/* SPI_CS2_DIS : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin*/ -#define SPI_CS2_DIS (BIT(2)) -#define SPI_CS2_DIS_M (BIT(2)) -#define SPI_CS2_DIS_V 0x1 -#define SPI_CS2_DIS_S 2 -/* SPI_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin*/ -#define SPI_CS1_DIS (BIT(1)) -#define SPI_CS1_DIS_M (BIT(1)) -#define SPI_CS1_DIS_V 0x1 -#define SPI_CS1_DIS_S 1 -/* SPI_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin*/ -#define SPI_CS0_DIS (BIT(0)) -#define SPI_CS0_DIS_M (BIT(0)) -#define SPI_CS0_DIS_V 0x1 -#define SPI_CS0_DIS_S 0 - -#define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0x38) -/* SPI_SYNC_RESET : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: Software reset enable, reset the spi clock line cs line and data lines.*/ -#define SPI_SYNC_RESET (BIT(31)) -#define SPI_SYNC_RESET_M (BIT(31)) -#define SPI_SYNC_RESET_V 0x1 -#define SPI_SYNC_RESET_S 31 -/* SPI_SLAVE_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: 1: slave mode 0: master mode.*/ -#define SPI_SLAVE_MODE (BIT(30)) -#define SPI_SLAVE_MODE_M (BIT(30)) -#define SPI_SLAVE_MODE_V 0x1 -#define SPI_SLAVE_MODE_S 30 -/* SPI_SLV_WR_RD_BUF_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: write and read buffer enable in the slave mode*/ -#define SPI_SLV_WR_RD_BUF_EN (BIT(29)) -#define SPI_SLV_WR_RD_BUF_EN_M (BIT(29)) -#define SPI_SLV_WR_RD_BUF_EN_V 0x1 -#define SPI_SLV_WR_RD_BUF_EN_S 29 -/* SPI_SLV_WR_RD_STA_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: write and read status enable in the slave mode*/ -#define SPI_SLV_WR_RD_STA_EN (BIT(28)) -#define SPI_SLV_WR_RD_STA_EN_M (BIT(28)) -#define SPI_SLV_WR_RD_STA_EN_V 0x1 -#define SPI_SLV_WR_RD_STA_EN_S 28 -/* SPI_SLV_CMD_DEFINE : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: 1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode - commands are fixed as: 1: write-status 2: write-buffer and 3: read-buffer.*/ -#define SPI_SLV_CMD_DEFINE (BIT(27)) -#define SPI_SLV_CMD_DEFINE_M (BIT(27)) -#define SPI_SLV_CMD_DEFINE_V 0x1 -#define SPI_SLV_CMD_DEFINE_S 27 -/* SPI_TRANS_CNT : RO ;bitpos:[26:23] ;default: 4'b0 ; */ -/*description: The operations counter in both the master mode and the slave - mode. 4: read-status*/ -#define SPI_TRANS_CNT 0x0000000F -#define SPI_TRANS_CNT_M ((SPI_TRANS_CNT_V)<<(SPI_TRANS_CNT_S)) -#define SPI_TRANS_CNT_V 0xF -#define SPI_TRANS_CNT_S 23 -/* SPI_SLV_LAST_STATE : RO ;bitpos:[22:20] ;default: 3'b0 ; */ -/*description: In the slave mode it is the state of spi state machine.*/ -#define SPI_SLV_LAST_STATE 0x00000007 -#define SPI_SLV_LAST_STATE_M ((SPI_SLV_LAST_STATE_V)<<(SPI_SLV_LAST_STATE_S)) -#define SPI_SLV_LAST_STATE_V 0x7 -#define SPI_SLV_LAST_STATE_S 20 -/* SPI_SLV_LAST_COMMAND : RO ;bitpos:[19:17] ;default: 3'b0 ; */ -/*description: In the slave mode it is the value of command.*/ -#define SPI_SLV_LAST_COMMAND 0x00000007 -#define SPI_SLV_LAST_COMMAND_M ((SPI_SLV_LAST_COMMAND_V)<<(SPI_SLV_LAST_COMMAND_S)) -#define SPI_SLV_LAST_COMMAND_V 0x7 -#define SPI_SLV_LAST_COMMAND_S 17 -/* SPI_CS_I_MODE : R/W ;bitpos:[11:10] ;default: 2'b0 ; */ -/*description: In the slave mode this bits used to synchronize the input spi - cs signal and eliminate spi cs jitter.*/ -#define SPI_CS_I_MODE 0x00000003 -#define SPI_CS_I_MODE_M ((SPI_CS_I_MODE_V)<<(SPI_CS_I_MODE_S)) -#define SPI_CS_I_MODE_V 0x3 -#define SPI_CS_I_MODE_S 10 -/* SPI_INT_EN : R/W ;bitpos:[9:5] ;default: 5'b1_0000 ; */ -/*description: Interrupt enable bits for the below 5 sources*/ -#define SPI_INT_EN 0x0000001F -#define SPI_INT_EN_M ((SPI_INT_EN_V)<<(SPI_INT_EN_S)) -#define SPI_INT_EN_V 0x1F -#define SPI_INT_EN_S 5 -/* SPI_TRANS_DONE : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for the completion of any operation in - both the master mode and the slave mode.*/ -#define SPI_TRANS_DONE (BIT(4)) -#define SPI_TRANS_DONE_M (BIT(4)) -#define SPI_TRANS_DONE_V 0x1 -#define SPI_TRANS_DONE_S 4 -/* SPI_SLV_WR_STA_DONE : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for the completion of write-status operation - in the slave mode.*/ -#define SPI_SLV_WR_STA_DONE (BIT(3)) -#define SPI_SLV_WR_STA_DONE_M (BIT(3)) -#define SPI_SLV_WR_STA_DONE_V 0x1 -#define SPI_SLV_WR_STA_DONE_S 3 -/* SPI_SLV_RD_STA_DONE : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for the completion of read-status operation - in the slave mode.*/ -#define SPI_SLV_RD_STA_DONE (BIT(2)) -#define SPI_SLV_RD_STA_DONE_M (BIT(2)) -#define SPI_SLV_RD_STA_DONE_V 0x1 -#define SPI_SLV_RD_STA_DONE_S 2 -/* SPI_SLV_WR_BUF_DONE : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for the completion of write-buffer operation - in the slave mode.*/ -#define SPI_SLV_WR_BUF_DONE (BIT(1)) -#define SPI_SLV_WR_BUF_DONE_M (BIT(1)) -#define SPI_SLV_WR_BUF_DONE_V 0x1 -#define SPI_SLV_WR_BUF_DONE_S 1 -/* SPI_SLV_RD_BUF_DONE : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for the completion of read-buffer operation - in the slave mode.*/ -#define SPI_SLV_RD_BUF_DONE (BIT(0)) -#define SPI_SLV_RD_BUF_DONE_M (BIT(0)) -#define SPI_SLV_RD_BUF_DONE_V 0x1 -#define SPI_SLV_RD_BUF_DONE_S 0 - -#define SPI_SLAVE1_REG(i) (REG_SPI_BASE(i) + 0x3C) -/* SPI_SLV_STATUS_BITLEN : R/W ;bitpos:[31:27] ;default: 5'b0 ; */ -/*description: In the slave mode it is the length of status bit.*/ -#define SPI_SLV_STATUS_BITLEN 0x0000001F -#define SPI_SLV_STATUS_BITLEN_M ((SPI_SLV_STATUS_BITLEN_V)<<(SPI_SLV_STATUS_BITLEN_S)) -#define SPI_SLV_STATUS_BITLEN_V 0x1F -#define SPI_SLV_STATUS_BITLEN_S 27 -/* SPI_SLV_STATUS_FAST_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: In the slave mode enable fast read status.*/ -#define SPI_SLV_STATUS_FAST_EN (BIT(26)) -#define SPI_SLV_STATUS_FAST_EN_M (BIT(26)) -#define SPI_SLV_STATUS_FAST_EN_V 0x1 -#define SPI_SLV_STATUS_FAST_EN_S 26 -/* SPI_SLV_STATUS_READBACK : R/W ;bitpos:[25] ;default: 1'b1 ; */ -/*description: In the slave mode 1:read register of SPI_SLV_WR_STATUS 0: read - register of SPI_RD_STATUS.*/ -#define SPI_SLV_STATUS_READBACK (BIT(25)) -#define SPI_SLV_STATUS_READBACK_M (BIT(25)) -#define SPI_SLV_STATUS_READBACK_V 0x1 -#define SPI_SLV_STATUS_READBACK_S 25 -/* SPI_SLV_RD_ADDR_BITLEN : R/W ;bitpos:[15:10] ;default: 6'h0 ; */ -/*description: In the slave mode it is the address length in bits for read-buffer - operation. The register value shall be (bit_num-1).*/ -#define SPI_SLV_RD_ADDR_BITLEN 0x0000003F -#define SPI_SLV_RD_ADDR_BITLEN_M ((SPI_SLV_RD_ADDR_BITLEN_V)<<(SPI_SLV_RD_ADDR_BITLEN_S)) -#define SPI_SLV_RD_ADDR_BITLEN_V 0x3F -#define SPI_SLV_RD_ADDR_BITLEN_S 10 -/* SPI_SLV_WR_ADDR_BITLEN : R/W ;bitpos:[9:4] ;default: 6'h0 ; */ -/*description: In the slave mode it is the address length in bits for write-buffer - operation. The register value shall be (bit_num-1).*/ -#define SPI_SLV_WR_ADDR_BITLEN 0x0000003F -#define SPI_SLV_WR_ADDR_BITLEN_M ((SPI_SLV_WR_ADDR_BITLEN_V)<<(SPI_SLV_WR_ADDR_BITLEN_S)) -#define SPI_SLV_WR_ADDR_BITLEN_V 0x3F -#define SPI_SLV_WR_ADDR_BITLEN_S 4 -/* SPI_SLV_WRSTA_DUMMY_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: In the slave mode it is the enable bit of dummy phase for write-status - operations.*/ -#define SPI_SLV_WRSTA_DUMMY_EN (BIT(3)) -#define SPI_SLV_WRSTA_DUMMY_EN_M (BIT(3)) -#define SPI_SLV_WRSTA_DUMMY_EN_V 0x1 -#define SPI_SLV_WRSTA_DUMMY_EN_S 3 -/* SPI_SLV_RDSTA_DUMMY_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: In the slave mode it is the enable bit of dummy phase for read-status - operations.*/ -#define SPI_SLV_RDSTA_DUMMY_EN (BIT(2)) -#define SPI_SLV_RDSTA_DUMMY_EN_M (BIT(2)) -#define SPI_SLV_RDSTA_DUMMY_EN_V 0x1 -#define SPI_SLV_RDSTA_DUMMY_EN_S 2 -/* SPI_SLV_WRBUF_DUMMY_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: In the slave mode it is the enable bit of dummy phase for write-buffer - operations.*/ -#define SPI_SLV_WRBUF_DUMMY_EN (BIT(1)) -#define SPI_SLV_WRBUF_DUMMY_EN_M (BIT(1)) -#define SPI_SLV_WRBUF_DUMMY_EN_V 0x1 -#define SPI_SLV_WRBUF_DUMMY_EN_S 1 -/* SPI_SLV_RDBUF_DUMMY_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: In the slave mode it is the enable bit of dummy phase for read-buffer - operations.*/ -#define SPI_SLV_RDBUF_DUMMY_EN (BIT(0)) -#define SPI_SLV_RDBUF_DUMMY_EN_M (BIT(0)) -#define SPI_SLV_RDBUF_DUMMY_EN_V 0x1 -#define SPI_SLV_RDBUF_DUMMY_EN_S 0 - -#define SPI_SLAVE2_REG(i) (REG_SPI_BASE(i) + 0x40) -/* SPI_SLV_WRBUF_DUMMY_CYCLELEN : R/W ;bitpos:[31:24] ;default: 8'b0 ; */ -/*description: In the slave mode it is the length in spi_clk cycles of dummy - phase for write-buffer operations. The register value shall be (cycle_num-1).*/ -#define SPI_SLV_WRBUF_DUMMY_CYCLELEN 0x000000FF -#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_M ((SPI_SLV_WRBUF_DUMMY_CYCLELEN_V)<<(SPI_SLV_WRBUF_DUMMY_CYCLELEN_S)) -#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_V 0xFF -#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_S 24 -/* SPI_SLV_RDBUF_DUMMY_CYCLELEN : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ -/*description: In the slave mode it is the length in spi_clk cycles of dummy - phase for read-buffer operations. The register value shall be (cycle_num-1).*/ -#define SPI_SLV_RDBUF_DUMMY_CYCLELEN 0x000000FF -#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_M ((SPI_SLV_RDBUF_DUMMY_CYCLELEN_V)<<(SPI_SLV_RDBUF_DUMMY_CYCLELEN_S)) -#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_V 0xFF -#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_S 16 -/* SPI_SLV_WRSTA_DUMMY_CYCLELEN : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: In the slave mode it is the length in spi_clk cycles of dummy - phase for write-status operations. The register value shall be (cycle_num-1).*/ -#define SPI_SLV_WRSTA_DUMMY_CYCLELEN 0x000000FF -#define SPI_SLV_WRSTA_DUMMY_CYCLELEN_M ((SPI_SLV_WRSTA_DUMMY_CYCLELEN_V)<<(SPI_SLV_WRSTA_DUMMY_CYCLELEN_S)) -#define SPI_SLV_WRSTA_DUMMY_CYCLELEN_V 0xFF -#define SPI_SLV_WRSTA_DUMMY_CYCLELEN_S 8 -/* SPI_SLV_RDSTA_DUMMY_CYCLELEN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: In the slave mode it is the length in spi_clk cycles of dummy - phase for read-status operations. The register value shall be (cycle_num-1).*/ -#define SPI_SLV_RDSTA_DUMMY_CYCLELEN 0x000000FF -#define SPI_SLV_RDSTA_DUMMY_CYCLELEN_M ((SPI_SLV_RDSTA_DUMMY_CYCLELEN_V)<<(SPI_SLV_RDSTA_DUMMY_CYCLELEN_S)) -#define SPI_SLV_RDSTA_DUMMY_CYCLELEN_V 0xFF -#define SPI_SLV_RDSTA_DUMMY_CYCLELEN_S 0 - -#define SPI_SLAVE3_REG(i) (REG_SPI_BASE(i) + 0x44) -/* SPI_SLV_WRSTA_CMD_VALUE : R/W ;bitpos:[31:24] ;default: 8'b0 ; */ -/*description: In the slave mode it is the value of write-status command.*/ -#define SPI_SLV_WRSTA_CMD_VALUE 0x000000FF -#define SPI_SLV_WRSTA_CMD_VALUE_M ((SPI_SLV_WRSTA_CMD_VALUE_V)<<(SPI_SLV_WRSTA_CMD_VALUE_S)) -#define SPI_SLV_WRSTA_CMD_VALUE_V 0xFF -#define SPI_SLV_WRSTA_CMD_VALUE_S 24 -/* SPI_SLV_RDSTA_CMD_VALUE : R/W ;bitpos:[23:16] ;default: 8'b0 ; */ -/*description: In the slave mode it is the value of read-status command.*/ -#define SPI_SLV_RDSTA_CMD_VALUE 0x000000FF -#define SPI_SLV_RDSTA_CMD_VALUE_M ((SPI_SLV_RDSTA_CMD_VALUE_V)<<(SPI_SLV_RDSTA_CMD_VALUE_S)) -#define SPI_SLV_RDSTA_CMD_VALUE_V 0xFF -#define SPI_SLV_RDSTA_CMD_VALUE_S 16 -/* SPI_SLV_WRBUF_CMD_VALUE : R/W ;bitpos:[15:8] ;default: 8'b0 ; */ -/*description: In the slave mode it is the value of write-buffer command.*/ -#define SPI_SLV_WRBUF_CMD_VALUE 0x000000FF -#define SPI_SLV_WRBUF_CMD_VALUE_M ((SPI_SLV_WRBUF_CMD_VALUE_V)<<(SPI_SLV_WRBUF_CMD_VALUE_S)) -#define SPI_SLV_WRBUF_CMD_VALUE_V 0xFF -#define SPI_SLV_WRBUF_CMD_VALUE_S 8 -/* SPI_SLV_RDBUF_CMD_VALUE : R/W ;bitpos:[7:0] ;default: 8'b0 ; */ -/*description: In the slave mode it is the value of read-buffer command.*/ -#define SPI_SLV_RDBUF_CMD_VALUE 0x000000FF -#define SPI_SLV_RDBUF_CMD_VALUE_M ((SPI_SLV_RDBUF_CMD_VALUE_V)<<(SPI_SLV_RDBUF_CMD_VALUE_S)) -#define SPI_SLV_RDBUF_CMD_VALUE_V 0xFF -#define SPI_SLV_RDBUF_CMD_VALUE_S 0 - -#define SPI_SLV_WRBUF_DLEN_REG(i) (REG_SPI_BASE(i) + 0x48) -/* SPI_SLV_WRBUF_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: In the slave mode it is the length in bits for write-buffer operations. - The register value shall be (bit_num-1).*/ -#define SPI_SLV_WRBUF_DBITLEN 0x00FFFFFF -#define SPI_SLV_WRBUF_DBITLEN_M ((SPI_SLV_WRBUF_DBITLEN_V)<<(SPI_SLV_WRBUF_DBITLEN_S)) -#define SPI_SLV_WRBUF_DBITLEN_V 0xFFFFFF -#define SPI_SLV_WRBUF_DBITLEN_S 0 - -#define SPI_SLV_RDBUF_DLEN_REG(i) (REG_SPI_BASE(i) + 0x4C) -/* SPI_SLV_RDBUF_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: In the slave mode it is the length in bits for read-buffer operations. - The register value shall be (bit_num-1).*/ -#define SPI_SLV_RDBUF_DBITLEN 0x00FFFFFF -#define SPI_SLV_RDBUF_DBITLEN_M ((SPI_SLV_RDBUF_DBITLEN_V)<<(SPI_SLV_RDBUF_DBITLEN_S)) -#define SPI_SLV_RDBUF_DBITLEN_V 0xFFFFFF -#define SPI_SLV_RDBUF_DBITLEN_S 0 - -#define SPI_CACHE_FCTRL_REG(i) (REG_SPI_BASE(i) + 0x50) -/* SPI_CACHE_FLASH_PES_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: For SPI0 spi1 send suspend command before cache read flash - 1: enable 0:disable.*/ -#define SPI_CACHE_FLASH_PES_EN (BIT(3)) -#define SPI_CACHE_FLASH_PES_EN_M (BIT(3)) -#define SPI_CACHE_FLASH_PES_EN_V 0x1 -#define SPI_CACHE_FLASH_PES_EN_S 3 -/* SPI_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: For SPI0 cache read flash for user define command 1: enable 0:disable.*/ -#define SPI_CACHE_FLASH_USR_CMD (BIT(2)) -#define SPI_CACHE_FLASH_USR_CMD_M (BIT(2)) -#define SPI_CACHE_FLASH_USR_CMD_V 0x1 -#define SPI_CACHE_FLASH_USR_CMD_S 2 -/* SPI_CACHE_USR_CMD_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: For SPI0 cache read flash with 4 bytes command 1: enable 0:disable.*/ -#define SPI_CACHE_USR_CMD_4BYTE (BIT(1)) -#define SPI_CACHE_USR_CMD_4BYTE_M (BIT(1)) -#define SPI_CACHE_USR_CMD_4BYTE_V 0x1 -#define SPI_CACHE_USR_CMD_4BYTE_S 1 -/* SPI_CACHE_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: For SPI0 Cache access enable 1: enable 0:disable.*/ -#define SPI_CACHE_REQ_EN (BIT(0)) -#define SPI_CACHE_REQ_EN_M (BIT(0)) -#define SPI_CACHE_REQ_EN_V 0x1 -#define SPI_CACHE_REQ_EN_S 0 - -#define SPI_CACHE_SCTRL_REG(i) (REG_SPI_BASE(i) + 0x54) -/* SPI_CACHE_SRAM_USR_WCMD : R/W ;bitpos:[28] ;default: 1'b1 ; */ -/*description: For SPI0 In the spi sram mode cache write sram for user define command*/ -#define SPI_CACHE_SRAM_USR_WCMD (BIT(28)) -#define SPI_CACHE_SRAM_USR_WCMD_M (BIT(28)) -#define SPI_CACHE_SRAM_USR_WCMD_V 0x1 -#define SPI_CACHE_SRAM_USR_WCMD_S 28 -/* SPI_SRAM_ADDR_BITLEN : R/W ;bitpos:[27:22] ;default: 6'd23 ; */ -/*description: For SPI0 In the sram mode it is the length in bits of address - phase. The register value shall be (bit_num-1).*/ -#define SPI_SRAM_ADDR_BITLEN 0x0000003F -#define SPI_SRAM_ADDR_BITLEN_M ((SPI_SRAM_ADDR_BITLEN_V)<<(SPI_SRAM_ADDR_BITLEN_S)) -#define SPI_SRAM_ADDR_BITLEN_V 0x3F -#define SPI_SRAM_ADDR_BITLEN_S 22 -/* SPI_SRAM_DUMMY_CYCLELEN : R/W ;bitpos:[21:14] ;default: 8'b1 ; */ -/*description: For SPI0 In the sram mode it is the length in bits of address - phase. The register value shall be (bit_num-1).*/ -#define SPI_SRAM_DUMMY_CYCLELEN 0x000000FF -#define SPI_SRAM_DUMMY_CYCLELEN_M ((SPI_SRAM_DUMMY_CYCLELEN_V)<<(SPI_SRAM_DUMMY_CYCLELEN_S)) -#define SPI_SRAM_DUMMY_CYCLELEN_V 0xFF -#define SPI_SRAM_DUMMY_CYCLELEN_S 14 -/* SPI_SRAM_BYTES_LEN : R/W ;bitpos:[13:6] ;default: 8'b32 ; */ -/*description: For SPI0 In the sram mode it is the byte length of spi read sram data.*/ -#define SPI_SRAM_BYTES_LEN 0x000000FF -#define SPI_SRAM_BYTES_LEN_M ((SPI_SRAM_BYTES_LEN_V)<<(SPI_SRAM_BYTES_LEN_S)) -#define SPI_SRAM_BYTES_LEN_V 0xFF -#define SPI_SRAM_BYTES_LEN_S 6 -/* SPI_CACHE_SRAM_USR_RCMD : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: For SPI0 In the spi sram mode cache read sram for user define command.*/ -#define SPI_CACHE_SRAM_USR_RCMD (BIT(5)) -#define SPI_CACHE_SRAM_USR_RCMD_M (BIT(5)) -#define SPI_CACHE_SRAM_USR_RCMD_V 0x1 -#define SPI_CACHE_SRAM_USR_RCMD_S 5 -/* SPI_USR_RD_SRAM_DUMMY : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: For SPI0 In the spi sram mode it is the enable bit of dummy - phase for read operations.*/ -#define SPI_USR_RD_SRAM_DUMMY (BIT(4)) -#define SPI_USR_RD_SRAM_DUMMY_M (BIT(4)) -#define SPI_USR_RD_SRAM_DUMMY_V 0x1 -#define SPI_USR_RD_SRAM_DUMMY_S 4 -/* SPI_USR_WR_SRAM_DUMMY : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: For SPI0 In the spi sram mode it is the enable bit of dummy - phase for write operations.*/ -#define SPI_USR_WR_SRAM_DUMMY (BIT(3)) -#define SPI_USR_WR_SRAM_DUMMY_M (BIT(3)) -#define SPI_USR_WR_SRAM_DUMMY_V 0x1 -#define SPI_USR_WR_SRAM_DUMMY_S 3 -/* SPI_USR_SRAM_QIO : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: For SPI0 In the spi sram mode spi quad I/O mode enable 1: enable 0:disable*/ -#define SPI_USR_SRAM_QIO (BIT(2)) -#define SPI_USR_SRAM_QIO_M (BIT(2)) -#define SPI_USR_SRAM_QIO_V 0x1 -#define SPI_USR_SRAM_QIO_S 2 -/* SPI_USR_SRAM_DIO : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable*/ -#define SPI_USR_SRAM_DIO (BIT(1)) -#define SPI_USR_SRAM_DIO_M (BIT(1)) -#define SPI_USR_SRAM_DIO_V 0x1 -#define SPI_USR_SRAM_DIO_S 1 - -#define SPI_SRAM_CMD_REG(i) (REG_SPI_BASE(i) + 0x58) -/* SPI_SRAM_RSTIO : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: For SPI0 SRAM IO mode reset enable. SRAM IO mode reset operation - will be triggered when the bit is set. The bit will be cleared once the operation done*/ -#define SPI_SRAM_RSTIO (BIT(4)) -#define SPI_SRAM_RSTIO_M (BIT(4)) -#define SPI_SRAM_RSTIO_V 0x1 -#define SPI_SRAM_RSTIO_S 4 -/* SPI_SRAM_QIO : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: For SPI0 SRAM QIO mode enable . SRAM QIO enable command will - be send when the bit is set. The bit will be cleared once the operation done.*/ -#define SPI_SRAM_QIO (BIT(1)) -#define SPI_SRAM_QIO_M (BIT(1)) -#define SPI_SRAM_QIO_V 0x1 -#define SPI_SRAM_QIO_S 1 -/* SPI_SRAM_DIO : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: For SPI0 SRAM DIO mode enable . SRAM DIO enable command will - be send when the bit is set. The bit will be cleared once the operation done.*/ -#define SPI_SRAM_DIO (BIT(0)) -#define SPI_SRAM_DIO_M (BIT(0)) -#define SPI_SRAM_DIO_V 0x1 -#define SPI_SRAM_DIO_S 0 - -#define SPI_SRAM_DRD_CMD_REG(i) (REG_SPI_BASE(i) + 0x5C) -/* SPI_CACHE_SRAM_USR_RD_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: For SPI0 When cache mode is enable it is the length in bits of - command phase for SRAM. The register value shall be (bit_num-1).*/ -#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000F -#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_M ((SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V)<<(SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S)) -#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V 0xF -#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S 28 -/* SPI_CACHE_SRAM_USR_RD_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: For SPI0 When cache mode is enable it is the read command value - of command phase for SRAM.*/ -#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFF -#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE_M ((SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V)<<(SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S)) -#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V 0xFFFF -#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S 0 - -#define SPI_SRAM_DWR_CMD_REG(i) (REG_SPI_BASE(i) + 0x60) -/* SPI_CACHE_SRAM_USR_WR_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: For SPI0 When cache mode is enable it is the in bits of command - phase for SRAM. The register value shall be (bit_num-1).*/ -#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000F -#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_M ((SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_V)<<(SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S)) -#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_V 0xF -#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S 28 -/* SPI_CACHE_SRAM_USR_WR_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: For SPI0 When cache mode is enable it is the write command value - of command phase for SRAM.*/ -#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFF -#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE_M ((SPI_CACHE_SRAM_USR_WR_CMD_VALUE_V)<<(SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S)) -#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE_V 0xFFFF -#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S 0 - -#define SPI_SLV_RD_BIT_REG(i) (REG_SPI_BASE(i) + 0x64) -/* SPI_SLV_RDATA_BIT : RW ;bitpos:[23:0] ;default: 24'b0 ; */ -/*description: In the slave mode it is the bit length of read data. The value - is the length - 1.*/ -#define SPI_SLV_RDATA_BIT 0x00FFFFFF -#define SPI_SLV_RDATA_BIT_M ((SPI_SLV_RDATA_BIT_V)<<(SPI_SLV_RDATA_BIT_S)) -#define SPI_SLV_RDATA_BIT_V 0xFFFFFF -#define SPI_SLV_RDATA_BIT_S 0 - -#define SPI_W0_REG(i) (REG_SPI_BASE(i) + 0x80) -/* SPI_BUF0 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_BUF0 0xFFFFFFFF -#define SPI_BUF0_M ((SPI_BUF0_V)<<(SPI_BUF0_S)) -#define SPI_BUF0_V 0xFFFFFFFF -#define SPI_BUF0_S 0 - -#define SPI_W1_REG(i) (REG_SPI_BASE(i) + 0x84) -/* SPI_BUF1 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_BUF1 0xFFFFFFFF -#define SPI_BUF1_M ((SPI_BUF1_V)<<(SPI_BUF1_S)) -#define SPI_BUF1_V 0xFFFFFFFF -#define SPI_BUF1_S 0 - -#define SPI_W2_REG(i) (REG_SPI_BASE(i) + 0x88) -/* SPI_BUF2 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_BUF2 0xFFFFFFFF -#define SPI_BUF2_M ((SPI_BUF2_V)<<(SPI_BUF2_S)) -#define SPI_BUF2_V 0xFFFFFFFF -#define SPI_BUF2_S 0 - -#define SPI_W3_REG(i) (REG_SPI_BASE(i) + 0x8C) -/* SPI_BUF3 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_BUF3 0xFFFFFFFF -#define SPI_BUF3_M ((SPI_BUF3_V)<<(SPI_BUF3_S)) -#define SPI_BUF3_V 0xFFFFFFFF -#define SPI_BUF3_S 0 - -#define SPI_W4_REG(i) (REG_SPI_BASE(i) + 0x90) -/* SPI_BUF4 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_BUF4 0xFFFFFFFF -#define SPI_BUF4_M ((SPI_BUF4_V)<<(SPI_BUF4_S)) -#define SPI_BUF4_V 0xFFFFFFFF -#define SPI_BUF4_S 0 - -#define SPI_W5_REG(i) (REG_SPI_BASE(i) + 0x94) -/* SPI_BUF5 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_BUF5 0xFFFFFFFF -#define SPI_BUF5_M ((SPI_BUF5_V)<<(SPI_BUF5_S)) -#define SPI_BUF5_V 0xFFFFFFFF -#define SPI_BUF5_S 0 - -#define SPI_W6_REG(i) (REG_SPI_BASE(i) + 0x98) -/* SPI_BUF6 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_BUF6 0xFFFFFFFF -#define SPI_BUF6_M ((SPI_BUF6_V)<<(SPI_BUF6_S)) -#define SPI_BUF6_V 0xFFFFFFFF -#define SPI_BUF6_S 0 - -#define SPI_W7_REG(i) (REG_SPI_BASE(i) + 0x9C) -/* SPI_BUF7 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_BUF7 0xFFFFFFFF -#define SPI_BUF7_M ((SPI_BUF7_V)<<(SPI_BUF7_S)) -#define SPI_BUF7_V 0xFFFFFFFF -#define SPI_BUF7_S 0 - -#define SPI_W8_REG(i) (REG_SPI_BASE(i) + 0xA0) -/* SPI_BUF8 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_BUF8 0xFFFFFFFF -#define SPI_BUF8_M ((SPI_BUF8_V)<<(SPI_BUF8_S)) -#define SPI_BUF8_V 0xFFFFFFFF -#define SPI_BUF8_S 0 - -#define SPI_W9_REG(i) (REG_SPI_BASE(i) + 0xA4) -/* SPI_BUF9 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_BUF9 0xFFFFFFFF -#define SPI_BUF9_M ((SPI_BUF9_V)<<(SPI_BUF9_S)) -#define SPI_BUF9_V 0xFFFFFFFF -#define SPI_BUF9_S 0 - -#define SPI_W10_REG(i) (REG_SPI_BASE(i) + 0xA8) -/* SPI_BUF10 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_BUF10 0xFFFFFFFF -#define SPI_BUF10_M ((SPI_BUF10_V)<<(SPI_BUF10_S)) -#define SPI_BUF10_V 0xFFFFFFFF -#define SPI_BUF10_S 0 - -#define SPI_W11_REG(i) (REG_SPI_BASE(i) + 0xAC) -/* SPI_BUF11 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_BUF11 0xFFFFFFFF -#define SPI_BUF11_M ((SPI_BUF11_V)<<(SPI_BUF11_S)) -#define SPI_BUF11_V 0xFFFFFFFF -#define SPI_BUF11_S 0 - -#define SPI_W12_REG(i) (REG_SPI_BASE(i) + 0xB0) -/* SPI_BUF12 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_BUF12 0xFFFFFFFF -#define SPI_BUF12_M ((SPI_BUF12_V)<<(SPI_BUF12_S)) -#define SPI_BUF12_V 0xFFFFFFFF -#define SPI_BUF12_S 0 - -#define SPI_W13_REG(i) (REG_SPI_BASE(i) + 0xB4) -/* SPI_BUF13 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_BUF13 0xFFFFFFFF -#define SPI_BUF13_M ((SPI_BUF13_V)<<(SPI_BUF13_S)) -#define SPI_BUF13_V 0xFFFFFFFF -#define SPI_BUF13_S 0 - -#define SPI_W14_REG(i) (REG_SPI_BASE(i) + 0xB8) -/* SPI_BUF14 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_BUF14 0xFFFFFFFF -#define SPI_BUF14_M ((SPI_BUF14_V)<<(SPI_BUF14_S)) -#define SPI_BUF14_V 0xFFFFFFFF -#define SPI_BUF14_S 0 - -#define SPI_W15_REG(i) (REG_SPI_BASE(i) + 0xBC) -/* SPI_BUF15 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer*/ -#define SPI_BUF15 0xFFFFFFFF -#define SPI_BUF15_M ((SPI_BUF15_V)<<(SPI_BUF15_S)) -#define SPI_BUF15_V 0xFFFFFFFF -#define SPI_BUF15_S 0 - -#define SPI_TX_CRC_REG(i) (REG_SPI_BASE(i) + 0xC0) -/* SPI_TX_CRC_DATA : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: For SPI1 the value of crc32 for 256 bits data.*/ -#define SPI_TX_CRC_DATA 0xFFFFFFFF -#define SPI_TX_CRC_DATA_M ((SPI_TX_CRC_DATA_V)<<(SPI_TX_CRC_DATA_S)) -#define SPI_TX_CRC_DATA_V 0xFFFFFFFF -#define SPI_TX_CRC_DATA_S 0 - -#define SPI_EXT0_REG(i) (REG_SPI_BASE(i) + 0xF0) -/* SPI_T_PP_ENA : R/W ;bitpos:[31] ;default: 1'b1 ; */ -/*description: page program delay enable.*/ -#define SPI_T_PP_ENA (BIT(31)) -#define SPI_T_PP_ENA_M (BIT(31)) -#define SPI_T_PP_ENA_V 0x1 -#define SPI_T_PP_ENA_S 31 -/* SPI_T_PP_SHIFT : R/W ;bitpos:[19:16] ;default: 4'd10 ; */ -/*description: page program delay time shift .*/ -#define SPI_T_PP_SHIFT 0x0000000F -#define SPI_T_PP_SHIFT_M ((SPI_T_PP_SHIFT_V)<<(SPI_T_PP_SHIFT_S)) -#define SPI_T_PP_SHIFT_V 0xF -#define SPI_T_PP_SHIFT_S 16 -/* SPI_T_PP_TIME : R/W ;bitpos:[11:0] ;default: 12'd80 ; */ -/*description: page program delay time by system clock.*/ -#define SPI_T_PP_TIME 0x00000FFF -#define SPI_T_PP_TIME_M ((SPI_T_PP_TIME_V)<<(SPI_T_PP_TIME_S)) -#define SPI_T_PP_TIME_V 0xFFF -#define SPI_T_PP_TIME_S 0 - -#define SPI_EXT1_REG(i) (REG_SPI_BASE(i) + 0xF4) -/* SPI_T_ERASE_ENA : R/W ;bitpos:[31] ;default: 1'b1 ; */ -/*description: erase flash delay enable.*/ -#define SPI_T_ERASE_ENA (BIT(31)) -#define SPI_T_ERASE_ENA_M (BIT(31)) -#define SPI_T_ERASE_ENA_V 0x1 -#define SPI_T_ERASE_ENA_S 31 -/* SPI_T_ERASE_SHIFT : R/W ;bitpos:[19:16] ;default: 4'd15 ; */ -/*description: erase flash delay time shift.*/ -#define SPI_T_ERASE_SHIFT 0x0000000F -#define SPI_T_ERASE_SHIFT_M ((SPI_T_ERASE_SHIFT_V)<<(SPI_T_ERASE_SHIFT_S)) -#define SPI_T_ERASE_SHIFT_V 0xF -#define SPI_T_ERASE_SHIFT_S 16 -/* SPI_T_ERASE_TIME : R/W ;bitpos:[11:0] ;default: 12'd0 ; */ -/*description: erase flash delay time by system clock.*/ -#define SPI_T_ERASE_TIME 0x00000FFF -#define SPI_T_ERASE_TIME_M ((SPI_T_ERASE_TIME_V)<<(SPI_T_ERASE_TIME_S)) -#define SPI_T_ERASE_TIME_V 0xFFF -#define SPI_T_ERASE_TIME_S 0 - -#define SPI_EXT2_REG(i) (REG_SPI_BASE(i) + 0xF8) -/* SPI_ST : RO ;bitpos:[2:0] ;default: 3'b0 ; */ -/*description: The status of spi state machine .*/ -#define SPI_ST 0x00000007 -#define SPI_ST_M ((SPI_ST_V)<<(SPI_ST_S)) -#define SPI_ST_V 0x7 -#define SPI_ST_S 0 - -#define SPI_EXT3_REG(i) (REG_SPI_BASE(i) + 0xFC) -/* SPI_INT_HOLD_ENA : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: This register is for two SPI masters to share the same cs clock - and data signals. The bits of one SPI are set if the other SPI is busy the SPI will be hold. 1(3): hold at ¡°idle¡± phase 2: hold at ¡°prepare¡± phase.*/ -#define SPI_INT_HOLD_ENA 0x00000003 -#define SPI_INT_HOLD_ENA_M ((SPI_INT_HOLD_ENA_V)<<(SPI_INT_HOLD_ENA_S)) -#define SPI_INT_HOLD_ENA_V 0x3 -#define SPI_INT_HOLD_ENA_S 0 - -#define SPI_DMA_CONF_REG(i) (REG_SPI_BASE(i) + 0x100) -/* SPI_DMA_CONTINUE : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: spi dma continue tx/rx data.*/ -#define SPI_DMA_CONTINUE (BIT(16)) -#define SPI_DMA_CONTINUE_M (BIT(16)) -#define SPI_DMA_CONTINUE_V 0x1 -#define SPI_DMA_CONTINUE_S 16 -/* SPI_DMA_TX_STOP : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: spi dma write data stop when in continue tx/rx mode.*/ -#define SPI_DMA_TX_STOP (BIT(15)) -#define SPI_DMA_TX_STOP_M (BIT(15)) -#define SPI_DMA_TX_STOP_V 0x1 -#define SPI_DMA_TX_STOP_S 15 -/* SPI_DMA_RX_STOP : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: spi dma read data stop when in continue tx/rx mode.*/ -#define SPI_DMA_RX_STOP (BIT(14)) -#define SPI_DMA_RX_STOP_M (BIT(14)) -#define SPI_DMA_RX_STOP_V 0x1 -#define SPI_DMA_RX_STOP_S 14 -/* SPI_OUT_DATA_BURST_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: spi dma read data from memory in burst mode.*/ -#define SPI_OUT_DATA_BURST_EN (BIT(12)) -#define SPI_OUT_DATA_BURST_EN_M (BIT(12)) -#define SPI_OUT_DATA_BURST_EN_V 0x1 -#define SPI_OUT_DATA_BURST_EN_S 12 -/* SPI_INDSCR_BURST_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: read descriptor use burst mode when write data to memory.*/ -#define SPI_INDSCR_BURST_EN (BIT(11)) -#define SPI_INDSCR_BURST_EN_M (BIT(11)) -#define SPI_INDSCR_BURST_EN_V 0x1 -#define SPI_INDSCR_BURST_EN_S 11 -/* SPI_OUTDSCR_BURST_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: read descriptor use burst mode when read data for memory.*/ -#define SPI_OUTDSCR_BURST_EN (BIT(10)) -#define SPI_OUTDSCR_BURST_EN_M (BIT(10)) -#define SPI_OUTDSCR_BURST_EN_V 0x1 -#define SPI_OUTDSCR_BURST_EN_S 10 -/* SPI_OUT_EOF_MODE : R/W ;bitpos:[9] ;default: 1'b1 ; */ -/*description: out eof flag generation mode . 1: when dma pop all data from - fifo 0:when ahb push all data to fifo.*/ -#define SPI_OUT_EOF_MODE (BIT(9)) -#define SPI_OUT_EOF_MODE_M (BIT(9)) -#define SPI_OUT_EOF_MODE_V 0x1 -#define SPI_OUT_EOF_MODE_S 9 -/* SPI_OUT_AUTO_WRBACK : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: when the link is empty jump to next automatically.*/ -#define SPI_OUT_AUTO_WRBACK (BIT(8)) -#define SPI_OUT_AUTO_WRBACK_M (BIT(8)) -#define SPI_OUT_AUTO_WRBACK_V 0x1 -#define SPI_OUT_AUTO_WRBACK_S 8 -/* SPI_OUT_LOOP_TEST : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set bit to test out link.*/ -#define SPI_OUT_LOOP_TEST (BIT(7)) -#define SPI_OUT_LOOP_TEST_M (BIT(7)) -#define SPI_OUT_LOOP_TEST_V 0x1 -#define SPI_OUT_LOOP_TEST_S 7 -/* SPI_IN_LOOP_TEST : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set bit to test in link.*/ -#define SPI_IN_LOOP_TEST (BIT(6)) -#define SPI_IN_LOOP_TEST_M (BIT(6)) -#define SPI_IN_LOOP_TEST_V 0x1 -#define SPI_IN_LOOP_TEST_S 6 -/* SPI_AHBM_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: reset spi dma ahb master.*/ -#define SPI_AHBM_RST (BIT(5)) -#define SPI_AHBM_RST_M (BIT(5)) -#define SPI_AHBM_RST_V 0x1 -#define SPI_AHBM_RST_S 5 -/* SPI_AHBM_FIFO_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: reset spi dma ahb master fifo pointer.*/ -#define SPI_AHBM_FIFO_RST (BIT(4)) -#define SPI_AHBM_FIFO_RST_M (BIT(4)) -#define SPI_AHBM_FIFO_RST_V 0x1 -#define SPI_AHBM_FIFO_RST_S 4 -/* SPI_OUT_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The bit is used to reset out dma fsm and out data fifo pointer.*/ -#define SPI_OUT_RST (BIT(3)) -#define SPI_OUT_RST_M (BIT(3)) -#define SPI_OUT_RST_V 0x1 -#define SPI_OUT_RST_S 3 -/* SPI_IN_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The bit is used to reset in dma fsm and in data fifo pointer.*/ -#define SPI_IN_RST (BIT(2)) -#define SPI_IN_RST_M (BIT(2)) -#define SPI_IN_RST_V 0x1 -#define SPI_IN_RST_S 2 - -#define SPI_DMA_OUT_LINK_REG(i) (REG_SPI_BASE(i) + 0x104) -/* SPI_OUTLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Set the bit to mount on new outlink descriptors.*/ -#define SPI_OUTLINK_RESTART (BIT(30)) -#define SPI_OUTLINK_RESTART_M (BIT(30)) -#define SPI_OUTLINK_RESTART_V 0x1 -#define SPI_OUTLINK_RESTART_S 30 -/* SPI_OUTLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: Set the bit to start to use outlink descriptor.*/ -#define SPI_OUTLINK_START (BIT(29)) -#define SPI_OUTLINK_START_M (BIT(29)) -#define SPI_OUTLINK_START_V 0x1 -#define SPI_OUTLINK_START_S 29 -/* SPI_OUTLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: Set the bit to stop to use outlink descriptor.*/ -#define SPI_OUTLINK_STOP (BIT(28)) -#define SPI_OUTLINK_STOP_M (BIT(28)) -#define SPI_OUTLINK_STOP_V 0x1 -#define SPI_OUTLINK_STOP_S 28 -/* SPI_OUTLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The address of the first outlink descriptor.*/ -#define SPI_OUTLINK_ADDR 0x000FFFFF -#define SPI_OUTLINK_ADDR_M ((SPI_OUTLINK_ADDR_V)<<(SPI_OUTLINK_ADDR_S)) -#define SPI_OUTLINK_ADDR_V 0xFFFFF -#define SPI_OUTLINK_ADDR_S 0 - -#define SPI_DMA_IN_LINK_REG(i) (REG_SPI_BASE(i) + 0x108) -/* SPI_INLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Set the bit to mount on new inlink descriptors.*/ -#define SPI_INLINK_RESTART (BIT(30)) -#define SPI_INLINK_RESTART_M (BIT(30)) -#define SPI_INLINK_RESTART_V 0x1 -#define SPI_INLINK_RESTART_S 30 -/* SPI_INLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: Set the bit to start to use inlink descriptor.*/ -#define SPI_INLINK_START (BIT(29)) -#define SPI_INLINK_START_M (BIT(29)) -#define SPI_INLINK_START_V 0x1 -#define SPI_INLINK_START_S 29 -/* SPI_INLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: Set the bit to stop to use inlink descriptor.*/ -#define SPI_INLINK_STOP (BIT(28)) -#define SPI_INLINK_STOP_M (BIT(28)) -#define SPI_INLINK_STOP_V 0x1 -#define SPI_INLINK_STOP_S 28 -/* SPI_INLINK_AUTO_RET : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: when the bit is set inlink descriptor returns to the next descriptor - while a packet is wrong*/ -#define SPI_INLINK_AUTO_RET (BIT(20)) -#define SPI_INLINK_AUTO_RET_M (BIT(20)) -#define SPI_INLINK_AUTO_RET_V 0x1 -#define SPI_INLINK_AUTO_RET_S 20 -/* SPI_INLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The address of the first inlink descriptor.*/ -#define SPI_INLINK_ADDR 0x000FFFFF -#define SPI_INLINK_ADDR_M ((SPI_INLINK_ADDR_V)<<(SPI_INLINK_ADDR_S)) -#define SPI_INLINK_ADDR_V 0xFFFFF -#define SPI_INLINK_ADDR_S 0 - -#define SPI_DMA_STATUS_REG(i) (REG_SPI_BASE(i) + 0x10C) -/* SPI_DMA_TX_EN : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: spi dma write data status bit.*/ -#define SPI_DMA_TX_EN (BIT(1)) -#define SPI_DMA_TX_EN_M (BIT(1)) -#define SPI_DMA_TX_EN_V 0x1 -#define SPI_DMA_TX_EN_S 1 -/* SPI_DMA_RX_EN : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: spi dma read data status bit.*/ -#define SPI_DMA_RX_EN (BIT(0)) -#define SPI_DMA_RX_EN_M (BIT(0)) -#define SPI_DMA_RX_EN_V 0x1 -#define SPI_DMA_RX_EN_S 0 - -#define SPI_DMA_INT_ENA_REG(i) (REG_SPI_BASE(i) + 0x110) -/* SPI_OUT_TOTAL_EOF_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The enable bit for sending all the packets to host done.*/ -#define SPI_OUT_TOTAL_EOF_INT_ENA (BIT(8)) -#define SPI_OUT_TOTAL_EOF_INT_ENA_M (BIT(8)) -#define SPI_OUT_TOTAL_EOF_INT_ENA_V 0x1 -#define SPI_OUT_TOTAL_EOF_INT_ENA_S 8 -/* SPI_OUT_EOF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The enable bit for sending a packet to host done.*/ -#define SPI_OUT_EOF_INT_ENA (BIT(7)) -#define SPI_OUT_EOF_INT_ENA_M (BIT(7)) -#define SPI_OUT_EOF_INT_ENA_V 0x1 -#define SPI_OUT_EOF_INT_ENA_S 7 -/* SPI_OUT_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The enable bit for completing usage of a outlink descriptor .*/ -#define SPI_OUT_DONE_INT_ENA (BIT(6)) -#define SPI_OUT_DONE_INT_ENA_M (BIT(6)) -#define SPI_OUT_DONE_INT_ENA_V 0x1 -#define SPI_OUT_DONE_INT_ENA_S 6 -/* SPI_IN_SUC_EOF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The enable bit for completing receiving all the packets from host.*/ -#define SPI_IN_SUC_EOF_INT_ENA (BIT(5)) -#define SPI_IN_SUC_EOF_INT_ENA_M (BIT(5)) -#define SPI_IN_SUC_EOF_INT_ENA_V 0x1 -#define SPI_IN_SUC_EOF_INT_ENA_S 5 -/* SPI_IN_ERR_EOF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The enable bit for receiving error.*/ -#define SPI_IN_ERR_EOF_INT_ENA (BIT(4)) -#define SPI_IN_ERR_EOF_INT_ENA_M (BIT(4)) -#define SPI_IN_ERR_EOF_INT_ENA_V 0x1 -#define SPI_IN_ERR_EOF_INT_ENA_S 4 -/* SPI_IN_DONE_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The enable bit for completing usage of a inlink descriptor.*/ -#define SPI_IN_DONE_INT_ENA (BIT(3)) -#define SPI_IN_DONE_INT_ENA_M (BIT(3)) -#define SPI_IN_DONE_INT_ENA_V 0x1 -#define SPI_IN_DONE_INT_ENA_S 3 -/* SPI_INLINK_DSCR_ERROR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The enable bit for inlink descriptor error.*/ -#define SPI_INLINK_DSCR_ERROR_INT_ENA (BIT(2)) -#define SPI_INLINK_DSCR_ERROR_INT_ENA_M (BIT(2)) -#define SPI_INLINK_DSCR_ERROR_INT_ENA_V 0x1 -#define SPI_INLINK_DSCR_ERROR_INT_ENA_S 2 -/* SPI_OUTLINK_DSCR_ERROR_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The enable bit for outlink descriptor error.*/ -#define SPI_OUTLINK_DSCR_ERROR_INT_ENA (BIT(1)) -#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_M (BIT(1)) -#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_V 0x1 -#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_S 1 -/* SPI_INLINK_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The enable bit for lack of enough inlink descriptors.*/ -#define SPI_INLINK_DSCR_EMPTY_INT_ENA (BIT(0)) -#define SPI_INLINK_DSCR_EMPTY_INT_ENA_M (BIT(0)) -#define SPI_INLINK_DSCR_EMPTY_INT_ENA_V 0x1 -#define SPI_INLINK_DSCR_EMPTY_INT_ENA_S 0 - -#define SPI_DMA_INT_RAW_REG(i) (REG_SPI_BASE(i) + 0x114) -/* SPI_OUT_TOTAL_EOF_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The raw bit for sending all the packets to host done.*/ -#define SPI_OUT_TOTAL_EOF_INT_RAW (BIT(8)) -#define SPI_OUT_TOTAL_EOF_INT_RAW_M (BIT(8)) -#define SPI_OUT_TOTAL_EOF_INT_RAW_V 0x1 -#define SPI_OUT_TOTAL_EOF_INT_RAW_S 8 -/* SPI_OUT_EOF_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The raw bit for sending a packet to host done.*/ -#define SPI_OUT_EOF_INT_RAW (BIT(7)) -#define SPI_OUT_EOF_INT_RAW_M (BIT(7)) -#define SPI_OUT_EOF_INT_RAW_V 0x1 -#define SPI_OUT_EOF_INT_RAW_S 7 -/* SPI_OUT_DONE_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The raw bit for completing usage of a outlink descriptor.*/ -#define SPI_OUT_DONE_INT_RAW (BIT(6)) -#define SPI_OUT_DONE_INT_RAW_M (BIT(6)) -#define SPI_OUT_DONE_INT_RAW_V 0x1 -#define SPI_OUT_DONE_INT_RAW_S 6 -/* SPI_IN_SUC_EOF_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The raw bit for completing receiving all the packets from host.*/ -#define SPI_IN_SUC_EOF_INT_RAW (BIT(5)) -#define SPI_IN_SUC_EOF_INT_RAW_M (BIT(5)) -#define SPI_IN_SUC_EOF_INT_RAW_V 0x1 -#define SPI_IN_SUC_EOF_INT_RAW_S 5 -/* SPI_IN_ERR_EOF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw bit for receiving error.*/ -#define SPI_IN_ERR_EOF_INT_RAW (BIT(4)) -#define SPI_IN_ERR_EOF_INT_RAW_M (BIT(4)) -#define SPI_IN_ERR_EOF_INT_RAW_V 0x1 -#define SPI_IN_ERR_EOF_INT_RAW_S 4 -/* SPI_IN_DONE_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw bit for completing usage of a inlink descriptor.*/ -#define SPI_IN_DONE_INT_RAW (BIT(3)) -#define SPI_IN_DONE_INT_RAW_M (BIT(3)) -#define SPI_IN_DONE_INT_RAW_V 0x1 -#define SPI_IN_DONE_INT_RAW_S 3 -/* SPI_INLINK_DSCR_ERROR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw bit for inlink descriptor error.*/ -#define SPI_INLINK_DSCR_ERROR_INT_RAW (BIT(2)) -#define SPI_INLINK_DSCR_ERROR_INT_RAW_M (BIT(2)) -#define SPI_INLINK_DSCR_ERROR_INT_RAW_V 0x1 -#define SPI_INLINK_DSCR_ERROR_INT_RAW_S 2 -/* SPI_OUTLINK_DSCR_ERROR_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw bit for outlink descriptor error.*/ -#define SPI_OUTLINK_DSCR_ERROR_INT_RAW (BIT(1)) -#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_M (BIT(1)) -#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_V 0x1 -#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_S 1 -/* SPI_INLINK_DSCR_EMPTY_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw bit for lack of enough inlink descriptors.*/ -#define SPI_INLINK_DSCR_EMPTY_INT_RAW (BIT(0)) -#define SPI_INLINK_DSCR_EMPTY_INT_RAW_M (BIT(0)) -#define SPI_INLINK_DSCR_EMPTY_INT_RAW_V 0x1 -#define SPI_INLINK_DSCR_EMPTY_INT_RAW_S 0 - -#define SPI_DMA_INT_ST_REG(i) (REG_SPI_BASE(i) + 0x118) -/* SPI_OUT_TOTAL_EOF_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The status bit for sending all the packets to host done.*/ -#define SPI_OUT_TOTAL_EOF_INT_ST (BIT(8)) -#define SPI_OUT_TOTAL_EOF_INT_ST_M (BIT(8)) -#define SPI_OUT_TOTAL_EOF_INT_ST_V 0x1 -#define SPI_OUT_TOTAL_EOF_INT_ST_S 8 -/* SPI_OUT_EOF_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The status bit for sending a packet to host done.*/ -#define SPI_OUT_EOF_INT_ST (BIT(7)) -#define SPI_OUT_EOF_INT_ST_M (BIT(7)) -#define SPI_OUT_EOF_INT_ST_V 0x1 -#define SPI_OUT_EOF_INT_ST_S 7 -/* SPI_OUT_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The status bit for completing usage of a outlink descriptor.*/ -#define SPI_OUT_DONE_INT_ST (BIT(6)) -#define SPI_OUT_DONE_INT_ST_M (BIT(6)) -#define SPI_OUT_DONE_INT_ST_V 0x1 -#define SPI_OUT_DONE_INT_ST_S 6 -/* SPI_IN_SUC_EOF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The status bit for completing receiving all the packets from host.*/ -#define SPI_IN_SUC_EOF_INT_ST (BIT(5)) -#define SPI_IN_SUC_EOF_INT_ST_M (BIT(5)) -#define SPI_IN_SUC_EOF_INT_ST_V 0x1 -#define SPI_IN_SUC_EOF_INT_ST_S 5 -/* SPI_IN_ERR_EOF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The status bit for receiving error.*/ -#define SPI_IN_ERR_EOF_INT_ST (BIT(4)) -#define SPI_IN_ERR_EOF_INT_ST_M (BIT(4)) -#define SPI_IN_ERR_EOF_INT_ST_V 0x1 -#define SPI_IN_ERR_EOF_INT_ST_S 4 -/* SPI_IN_DONE_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The status bit for completing usage of a inlink descriptor.*/ -#define SPI_IN_DONE_INT_ST (BIT(3)) -#define SPI_IN_DONE_INT_ST_M (BIT(3)) -#define SPI_IN_DONE_INT_ST_V 0x1 -#define SPI_IN_DONE_INT_ST_S 3 -/* SPI_INLINK_DSCR_ERROR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The status bit for inlink descriptor error.*/ -#define SPI_INLINK_DSCR_ERROR_INT_ST (BIT(2)) -#define SPI_INLINK_DSCR_ERROR_INT_ST_M (BIT(2)) -#define SPI_INLINK_DSCR_ERROR_INT_ST_V 0x1 -#define SPI_INLINK_DSCR_ERROR_INT_ST_S 2 -/* SPI_OUTLINK_DSCR_ERROR_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The status bit for outlink descriptor error.*/ -#define SPI_OUTLINK_DSCR_ERROR_INT_ST (BIT(1)) -#define SPI_OUTLINK_DSCR_ERROR_INT_ST_M (BIT(1)) -#define SPI_OUTLINK_DSCR_ERROR_INT_ST_V 0x1 -#define SPI_OUTLINK_DSCR_ERROR_INT_ST_S 1 -/* SPI_INLINK_DSCR_EMPTY_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The status bit for lack of enough inlink descriptors.*/ -#define SPI_INLINK_DSCR_EMPTY_INT_ST (BIT(0)) -#define SPI_INLINK_DSCR_EMPTY_INT_ST_M (BIT(0)) -#define SPI_INLINK_DSCR_EMPTY_INT_ST_V 0x1 -#define SPI_INLINK_DSCR_EMPTY_INT_ST_S 0 - -#define SPI_DMA_INT_CLR_REG(i) (REG_SPI_BASE(i) + 0x11C) -/* SPI_OUT_TOTAL_EOF_INT_CLR : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The clear bit for sending all the packets to host done.*/ -#define SPI_OUT_TOTAL_EOF_INT_CLR (BIT(8)) -#define SPI_OUT_TOTAL_EOF_INT_CLR_M (BIT(8)) -#define SPI_OUT_TOTAL_EOF_INT_CLR_V 0x1 -#define SPI_OUT_TOTAL_EOF_INT_CLR_S 8 -/* SPI_OUT_EOF_INT_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The clear bit for sending a packet to host done.*/ -#define SPI_OUT_EOF_INT_CLR (BIT(7)) -#define SPI_OUT_EOF_INT_CLR_M (BIT(7)) -#define SPI_OUT_EOF_INT_CLR_V 0x1 -#define SPI_OUT_EOF_INT_CLR_S 7 -/* SPI_OUT_DONE_INT_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The clear bit for completing usage of a outlink descriptor.*/ -#define SPI_OUT_DONE_INT_CLR (BIT(6)) -#define SPI_OUT_DONE_INT_CLR_M (BIT(6)) -#define SPI_OUT_DONE_INT_CLR_V 0x1 -#define SPI_OUT_DONE_INT_CLR_S 6 -/* SPI_IN_SUC_EOF_INT_CLR : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The clear bit for completing receiving all the packets from host.*/ -#define SPI_IN_SUC_EOF_INT_CLR (BIT(5)) -#define SPI_IN_SUC_EOF_INT_CLR_M (BIT(5)) -#define SPI_IN_SUC_EOF_INT_CLR_V 0x1 -#define SPI_IN_SUC_EOF_INT_CLR_S 5 -/* SPI_IN_ERR_EOF_INT_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The clear bit for receiving error.*/ -#define SPI_IN_ERR_EOF_INT_CLR (BIT(4)) -#define SPI_IN_ERR_EOF_INT_CLR_M (BIT(4)) -#define SPI_IN_ERR_EOF_INT_CLR_V 0x1 -#define SPI_IN_ERR_EOF_INT_CLR_S 4 -/* SPI_IN_DONE_INT_CLR : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The clear bit for completing usage of a inlink descriptor.*/ -#define SPI_IN_DONE_INT_CLR (BIT(3)) -#define SPI_IN_DONE_INT_CLR_M (BIT(3)) -#define SPI_IN_DONE_INT_CLR_V 0x1 -#define SPI_IN_DONE_INT_CLR_S 3 -/* SPI_INLINK_DSCR_ERROR_INT_CLR : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The clear bit for inlink descriptor error.*/ -#define SPI_INLINK_DSCR_ERROR_INT_CLR (BIT(2)) -#define SPI_INLINK_DSCR_ERROR_INT_CLR_M (BIT(2)) -#define SPI_INLINK_DSCR_ERROR_INT_CLR_V 0x1 -#define SPI_INLINK_DSCR_ERROR_INT_CLR_S 2 -/* SPI_OUTLINK_DSCR_ERROR_INT_CLR : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The clear bit for outlink descriptor error.*/ -#define SPI_OUTLINK_DSCR_ERROR_INT_CLR (BIT(1)) -#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_M (BIT(1)) -#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_V 0x1 -#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_S 1 -/* SPI_INLINK_DSCR_EMPTY_INT_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The clear bit for lack of enough inlink descriptors.*/ -#define SPI_INLINK_DSCR_EMPTY_INT_CLR (BIT(0)) -#define SPI_INLINK_DSCR_EMPTY_INT_CLR_M (BIT(0)) -#define SPI_INLINK_DSCR_EMPTY_INT_CLR_V 0x1 -#define SPI_INLINK_DSCR_EMPTY_INT_CLR_S 0 - -#define SPI_IN_ERR_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x120) -/* SPI_DMA_IN_ERR_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The inlink descriptor address when spi dma produce receiving error.*/ -#define SPI_DMA_IN_ERR_EOF_DES_ADDR 0xFFFFFFFF -#define SPI_DMA_IN_ERR_EOF_DES_ADDR_M ((SPI_DMA_IN_ERR_EOF_DES_ADDR_V)<<(SPI_DMA_IN_ERR_EOF_DES_ADDR_S)) -#define SPI_DMA_IN_ERR_EOF_DES_ADDR_V 0xFFFFFFFF -#define SPI_DMA_IN_ERR_EOF_DES_ADDR_S 0 - -#define SPI_IN_SUC_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x124) -/* SPI_DMA_IN_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The last inlink descriptor address when spi dma produce from_suc_eof.*/ -#define SPI_DMA_IN_SUC_EOF_DES_ADDR 0xFFFFFFFF -#define SPI_DMA_IN_SUC_EOF_DES_ADDR_M ((SPI_DMA_IN_SUC_EOF_DES_ADDR_V)<<(SPI_DMA_IN_SUC_EOF_DES_ADDR_S)) -#define SPI_DMA_IN_SUC_EOF_DES_ADDR_V 0xFFFFFFFF -#define SPI_DMA_IN_SUC_EOF_DES_ADDR_S 0 - -#define SPI_INLINK_DSCR_REG(i) (REG_SPI_BASE(i) + 0x128) -/* SPI_DMA_INLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The content of current in descriptor pointer.*/ -#define SPI_DMA_INLINK_DSCR 0xFFFFFFFF -#define SPI_DMA_INLINK_DSCR_M ((SPI_DMA_INLINK_DSCR_V)<<(SPI_DMA_INLINK_DSCR_S)) -#define SPI_DMA_INLINK_DSCR_V 0xFFFFFFFF -#define SPI_DMA_INLINK_DSCR_S 0 - -#define SPI_INLINK_DSCR_BF0_REG(i) (REG_SPI_BASE(i) + 0x12C) -/* SPI_DMA_INLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The content of next in descriptor pointer.*/ -#define SPI_DMA_INLINK_DSCR_BF0 0xFFFFFFFF -#define SPI_DMA_INLINK_DSCR_BF0_M ((SPI_DMA_INLINK_DSCR_BF0_V)<<(SPI_DMA_INLINK_DSCR_BF0_S)) -#define SPI_DMA_INLINK_DSCR_BF0_V 0xFFFFFFFF -#define SPI_DMA_INLINK_DSCR_BF0_S 0 - -#define SPI_INLINK_DSCR_BF1_REG(i) (REG_SPI_BASE(i) + 0x130) -/* SPI_DMA_INLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The content of current in descriptor data buffer pointer.*/ -#define SPI_DMA_INLINK_DSCR_BF1 0xFFFFFFFF -#define SPI_DMA_INLINK_DSCR_BF1_M ((SPI_DMA_INLINK_DSCR_BF1_V)<<(SPI_DMA_INLINK_DSCR_BF1_S)) -#define SPI_DMA_INLINK_DSCR_BF1_V 0xFFFFFFFF -#define SPI_DMA_INLINK_DSCR_BF1_S 0 - -#define SPI_OUT_EOF_BFR_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x134) -/* SPI_DMA_OUT_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of buffer relative to the outlink descriptor that produce eof.*/ -#define SPI_DMA_OUT_EOF_BFR_DES_ADDR 0xFFFFFFFF -#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_M ((SPI_DMA_OUT_EOF_BFR_DES_ADDR_V)<<(SPI_DMA_OUT_EOF_BFR_DES_ADDR_S)) -#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_V 0xFFFFFFFF -#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_S 0 - -#define SPI_OUT_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x138) -/* SPI_DMA_OUT_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The last outlink descriptor address when spi dma produce to_eof.*/ -#define SPI_DMA_OUT_EOF_DES_ADDR 0xFFFFFFFF -#define SPI_DMA_OUT_EOF_DES_ADDR_M ((SPI_DMA_OUT_EOF_DES_ADDR_V)<<(SPI_DMA_OUT_EOF_DES_ADDR_S)) -#define SPI_DMA_OUT_EOF_DES_ADDR_V 0xFFFFFFFF -#define SPI_DMA_OUT_EOF_DES_ADDR_S 0 - -#define SPI_OUTLINK_DSCR_REG(i) (REG_SPI_BASE(i) + 0x13C) -/* SPI_DMA_OUTLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The content of current out descriptor pointer.*/ -#define SPI_DMA_OUTLINK_DSCR 0xFFFFFFFF -#define SPI_DMA_OUTLINK_DSCR_M ((SPI_DMA_OUTLINK_DSCR_V)<<(SPI_DMA_OUTLINK_DSCR_S)) -#define SPI_DMA_OUTLINK_DSCR_V 0xFFFFFFFF -#define SPI_DMA_OUTLINK_DSCR_S 0 - -#define SPI_OUTLINK_DSCR_BF0_REG(i) (REG_SPI_BASE(i) + 0x140) -/* SPI_DMA_OUTLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The content of next out descriptor pointer.*/ -#define SPI_DMA_OUTLINK_DSCR_BF0 0xFFFFFFFF -#define SPI_DMA_OUTLINK_DSCR_BF0_M ((SPI_DMA_OUTLINK_DSCR_BF0_V)<<(SPI_DMA_OUTLINK_DSCR_BF0_S)) -#define SPI_DMA_OUTLINK_DSCR_BF0_V 0xFFFFFFFF -#define SPI_DMA_OUTLINK_DSCR_BF0_S 0 - -#define SPI_OUTLINK_DSCR_BF1_REG(i) (REG_SPI_BASE(i) + 0x144) -/* SPI_DMA_OUTLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The content of current out descriptor data buffer pointer.*/ -#define SPI_DMA_OUTLINK_DSCR_BF1 0xFFFFFFFF -#define SPI_DMA_OUTLINK_DSCR_BF1_M ((SPI_DMA_OUTLINK_DSCR_BF1_V)<<(SPI_DMA_OUTLINK_DSCR_BF1_S)) -#define SPI_DMA_OUTLINK_DSCR_BF1_V 0xFFFFFFFF -#define SPI_DMA_OUTLINK_DSCR_BF1_S 0 - -#define SPI_DMA_RSTATUS_REG(i) (REG_SPI_BASE(i) + 0x148) -/* SPI_DMA_OUT_STATUS : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: spi dma read data from memory status.*/ -#define SPI_DMA_OUT_STATUS 0xFFFFFFFF -#define SPI_DMA_OUT_STATUS_M ((SPI_DMA_OUT_STATUS_V)<<(SPI_DMA_OUT_STATUS_S)) -#define SPI_DMA_OUT_STATUS_V 0xFFFFFFFF -#define SPI_DMA_OUT_STATUS_S 0 - -#define SPI_DMA_TSTATUS_REG(i) (REG_SPI_BASE(i) + 0x14C) -/* SPI_DMA_IN_STATUS : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: spi dma write data to memory status.*/ -#define SPI_DMA_IN_STATUS 0xFFFFFFFF -#define SPI_DMA_IN_STATUS_M ((SPI_DMA_IN_STATUS_V)<<(SPI_DMA_IN_STATUS_S)) -#define SPI_DMA_IN_STATUS_V 0xFFFFFFFF -#define SPI_DMA_IN_STATUS_S 0 - -#define SPI_DATE_REG(i) (REG_SPI_BASE(i) + 0x3FC) -/* SPI_DATE : RO ;bitpos:[27:0] ;default: 32'h1604270 ; */ -/*description: SPI register version.*/ -#define SPI_DATE 0x0FFFFFFF -#define SPI_DATE_M ((SPI_DATE_V)<<(SPI_DATE_S)) -#define SPI_DATE_V 0xFFFFFFF -#define SPI_DATE_S 0 - - - - -#endif /*__SPI_REG_H__ */ - - + +#define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8) +/* SPI_WR_BIT_ORDER : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: In command address write-data (MOSI) phases 1: LSB firs 0: MSB first*/ +#define SPI_WR_BIT_ORDER (BIT(26)) +#define SPI_WR_BIT_ORDER_M (BIT(26)) +#define SPI_WR_BIT_ORDER_V 0x1 +#define SPI_WR_BIT_ORDER_S 26 +/* SPI_RD_BIT_ORDER : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: In read-data (MISO) phase 1: LSB first 0: MSB first*/ +#define SPI_RD_BIT_ORDER (BIT(25)) +#define SPI_RD_BIT_ORDER_M (BIT(25)) +#define SPI_RD_BIT_ORDER_V 0x1 +#define SPI_RD_BIT_ORDER_S 25 +/* SPI_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: In the read operations address phase and read-data phase apply + 4 signals. 1: enable 0: disable.*/ +#define SPI_FREAD_QIO (BIT(24)) +#define SPI_FREAD_QIO_M (BIT(24)) +#define SPI_FREAD_QIO_V 0x1 +#define SPI_FREAD_QIO_S 24 +/* SPI_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: In the read operations address phase and read-data phase apply + 2 signals. 1: enable 0: disable.*/ +#define SPI_FREAD_DIO (BIT(23)) +#define SPI_FREAD_DIO_M (BIT(23)) +#define SPI_FREAD_DIO_V 0x1 +#define SPI_FREAD_DIO_S 23 +/* SPI_WRSR_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: two bytes data will be written to status register when it is + set. 1: enable 0: disable.*/ +#define SPI_WRSR_2B (BIT(22)) +#define SPI_WRSR_2B_M (BIT(22)) +#define SPI_WRSR_2B_V 0x1 +#define SPI_WRSR_2B_S 22 +/* SPI_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */ +/*description: Write protect signal output when SPI is idle. 1: output high 0: output low.*/ +#define SPI_WP_REG (BIT(21)) +#define SPI_WP_REG_M (BIT(21)) +#define SPI_WP_REG_V 0x1 +#define SPI_WP_REG_S 21 +/* SPI_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/ +#define SPI_FREAD_QUAD (BIT(20)) +#define SPI_FREAD_QUAD_M (BIT(20)) +#define SPI_FREAD_QUAD_V 0x1 +#define SPI_FREAD_QUAD_S 20 +/* SPI_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */ +/*description: The Device ID is read out to SPI_RD_STATUS register, this bit + combine with spi_flash_res bit. 1: enable 0: disable.*/ +#define SPI_RESANDRES (BIT(15)) +#define SPI_RESANDRES_M (BIT(15)) +#define SPI_RESANDRES_V 0x1 +#define SPI_RESANDRES_S 15 +/* SPI_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: In the read operations read-data phase apply 2 signals. 1: enable 0: disable.*/ +#define SPI_FREAD_DUAL (BIT(14)) +#define SPI_FREAD_DUAL_M (BIT(14)) +#define SPI_FREAD_DUAL_V 0x1 +#define SPI_FREAD_DUAL_S 14 +/* SPI_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This bit enable the bits: spi_fread_qio spi_fread_dio spi_fread_qout + and spi_fread_dout. 1: enable 0: disable.*/ +#define SPI_FASTRD_MODE (BIT(13)) +#define SPI_FASTRD_MODE_M (BIT(13)) +#define SPI_FASTRD_MODE_V 0x1 +#define SPI_FASTRD_MODE_S 13 +/* SPI_WAIT_FLASH_IDLE_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: wait flash idle when program flash or erase flash. 1: enable 0: disable.*/ +#define SPI_WAIT_FLASH_IDLE_EN (BIT(12)) +#define SPI_WAIT_FLASH_IDLE_EN_M (BIT(12)) +#define SPI_WAIT_FLASH_IDLE_EN_V 0x1 +#define SPI_WAIT_FLASH_IDLE_EN_S 12 +/* SPI_TX_CRC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: For SPI1 enable crc32 when writing encrypted data to flash. + 1: enable 0:disable*/ +#define SPI_TX_CRC_EN (BIT(11)) +#define SPI_TX_CRC_EN_M (BIT(11)) +#define SPI_TX_CRC_EN_V 0x1 +#define SPI_TX_CRC_EN_S 11 +/* SPI_FCS_CRC_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: For SPI1 initialize crc32 module before writing encrypted data + to flash. Active low.*/ +#define SPI_FCS_CRC_EN (BIT(10)) +#define SPI_FCS_CRC_EN_M (BIT(10)) +#define SPI_FCS_CRC_EN_V 0x1 +#define SPI_FCS_CRC_EN_S 10 + +#define SPI_CTRL1_REG(i) (REG_SPI_BASE(i) + 0xC) +/* SPI_CS_HOLD_DELAY : R/W ;bitpos:[31:28] ;default: 4'h5 ; */ +/*description: SPI cs signal is delayed by spi clock cycles*/ +#define SPI_CS_HOLD_DELAY 0x0000000F +#define SPI_CS_HOLD_DELAY_M ((SPI_CS_HOLD_DELAY_V)<<(SPI_CS_HOLD_DELAY_S)) +#define SPI_CS_HOLD_DELAY_V 0xF +#define SPI_CS_HOLD_DELAY_S 28 +/* SPI_CS_HOLD_DELAY_RES : R/W ;bitpos:[27:16] ;default: 12'hfff ; */ +/*description: Delay cycles of resume Flash when resume Flash is enable by spi clock.*/ +#define SPI_CS_HOLD_DELAY_RES 0x00000FFF +#define SPI_CS_HOLD_DELAY_RES_M ((SPI_CS_HOLD_DELAY_RES_V)<<(SPI_CS_HOLD_DELAY_RES_S)) +#define SPI_CS_HOLD_DELAY_RES_V 0xFFF +#define SPI_CS_HOLD_DELAY_RES_S 16 + +#define SPI_RD_STATUS_REG(i) (REG_SPI_BASE(i) + 0x10) +/* SPI_STATUS_EXT : R/W ;bitpos:[31:24] ;default: 8'h00 ; */ +/*description: In the slave mode,it is the status for master to read out.*/ +#define SPI_STATUS_EXT 0x000000FF +#define SPI_STATUS_EXT_M ((SPI_STATUS_EXT_V)<<(SPI_STATUS_EXT_S)) +#define SPI_STATUS_EXT_V 0xFF +#define SPI_STATUS_EXT_S 24 +/* SPI_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */ +/*description: Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit.*/ +#define SPI_WB_MODE 0x000000FF +#define SPI_WB_MODE_M ((SPI_WB_MODE_V)<<(SPI_WB_MODE_S)) +#define SPI_WB_MODE_V 0xFF +#define SPI_WB_MODE_S 16 +/* SPI_STATUS : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: In the slave mode, it is the status for master to read out.*/ +#define SPI_STATUS 0x0000FFFF +#define SPI_STATUS_M ((SPI_STATUS_V)<<(SPI_STATUS_S)) +#define SPI_STATUS_V 0xFFFF +#define SPI_STATUS_S 0 + +#define SPI_CTRL2_REG(i) (REG_SPI_BASE(i) + 0x14) +/* SPI_CS_DELAY_NUM : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: spi_cs signal is delayed by system clock cycles*/ +#define SPI_CS_DELAY_NUM 0x0000000F +#define SPI_CS_DELAY_NUM_M ((SPI_CS_DELAY_NUM_V)<<(SPI_CS_DELAY_NUM_S)) +#define SPI_CS_DELAY_NUM_V 0xF +#define SPI_CS_DELAY_NUM_S 28 +/* SPI_CS_DELAY_MODE : R/W ;bitpos:[27:26] ;default: 2'h0 ; */ +/*description: spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge + or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ +#define SPI_CS_DELAY_MODE 0x00000003 +#define SPI_CS_DELAY_MODE_M ((SPI_CS_DELAY_MODE_V)<<(SPI_CS_DELAY_MODE_S)) +#define SPI_CS_DELAY_MODE_V 0x3 +#define SPI_CS_DELAY_MODE_S 26 +/* SPI_MOSI_DELAY_NUM : R/W ;bitpos:[25:23] ;default: 3'h0 ; */ +/*description: MOSI signals are delayed by system clock cycles*/ +#define SPI_MOSI_DELAY_NUM 0x00000007 +#define SPI_MOSI_DELAY_NUM_M ((SPI_MOSI_DELAY_NUM_V)<<(SPI_MOSI_DELAY_NUM_S)) +#define SPI_MOSI_DELAY_NUM_V 0x7 +#define SPI_MOSI_DELAY_NUM_S 23 +/* SPI_MOSI_DELAY_MODE : R/W ;bitpos:[22:21] ;default: 2'h0 ; */ +/*description: MOSI signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge + or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ +#define SPI_MOSI_DELAY_MODE 0x00000003 +#define SPI_MOSI_DELAY_MODE_M ((SPI_MOSI_DELAY_MODE_V)<<(SPI_MOSI_DELAY_MODE_S)) +#define SPI_MOSI_DELAY_MODE_V 0x3 +#define SPI_MOSI_DELAY_MODE_S 21 +/* SPI_MISO_DELAY_NUM : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ +/*description: MISO signals are delayed by system clock cycles*/ +#define SPI_MISO_DELAY_NUM 0x00000007 +#define SPI_MISO_DELAY_NUM_M ((SPI_MISO_DELAY_NUM_V)<<(SPI_MISO_DELAY_NUM_S)) +#define SPI_MISO_DELAY_NUM_V 0x7 +#define SPI_MISO_DELAY_NUM_S 18 +/* SPI_MISO_DELAY_MODE : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ +/*description: MISO signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge + or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ +#define SPI_MISO_DELAY_MODE 0x00000003 +#define SPI_MISO_DELAY_MODE_M ((SPI_MISO_DELAY_MODE_V)<<(SPI_MISO_DELAY_MODE_S)) +#define SPI_MISO_DELAY_MODE_V 0x3 +#define SPI_MISO_DELAY_MODE_S 16 +/* SPI_CK_OUT_HIGH_MODE : R/W ;bitpos:[15:12] ;default: 4'h0 ; */ +/*description: modify spi clock duty ratio when the value is lager than 8, + the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits.*/ +#define SPI_CK_OUT_HIGH_MODE 0x0000000F +#define SPI_CK_OUT_HIGH_MODE_M ((SPI_CK_OUT_HIGH_MODE_V)<<(SPI_CK_OUT_HIGH_MODE_S)) +#define SPI_CK_OUT_HIGH_MODE_V 0xF +#define SPI_CK_OUT_HIGH_MODE_S 12 +/* SPI_CK_OUT_LOW_MODE : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ +/*description: modify spi clock duty ratio when the value is lager than 8, + the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits.*/ +#define SPI_CK_OUT_LOW_MODE 0x0000000F +#define SPI_CK_OUT_LOW_MODE_M ((SPI_CK_OUT_LOW_MODE_V)<<(SPI_CK_OUT_LOW_MODE_S)) +#define SPI_CK_OUT_LOW_MODE_V 0xF +#define SPI_CK_OUT_LOW_MODE_S 8 +/* SPI_HOLD_TIME : R/W ;bitpos:[7:4] ;default: 4'h1 ; */ +/*description: delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit.*/ +#define SPI_HOLD_TIME 0x0000000F +#define SPI_HOLD_TIME_M ((SPI_HOLD_TIME_V)<<(SPI_HOLD_TIME_S)) +#define SPI_HOLD_TIME_V 0xF +#define SPI_HOLD_TIME_S 4 +/* SPI_SETUP_TIME : R/W ;bitpos:[3:0] ;default: 4'h1 ; */ +/*description: (cycles-1) of ¡°prepare¡± phase by spi clock, this bits combined + with spi_cs_setup bit.*/ +#define SPI_SETUP_TIME 0x0000000F +#define SPI_SETUP_TIME_M ((SPI_SETUP_TIME_V)<<(SPI_SETUP_TIME_S)) +#define SPI_SETUP_TIME_V 0xF +#define SPI_SETUP_TIME_S 0 + +#define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0x18) +/* SPI_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: In the master mode 1: spi_clk is eqaul to system 0: spi_clk is + divided from system clock.*/ +#define SPI_CLK_EQU_SYSCLK (BIT(31)) +#define SPI_CLK_EQU_SYSCLK_M (BIT(31)) +#define SPI_CLK_EQU_SYSCLK_V 0x1 +#define SPI_CLK_EQU_SYSCLK_S 31 +/* SPI_CLKDIV_PRE : R/W ;bitpos:[30:18] ;default: 13'b0 ; */ +/*description: In the master mode it is pre-divider of spi_clk.*/ +#define SPI_CLKDIV_PRE 0x00001FFF +#define SPI_CLKDIV_PRE_M ((SPI_CLKDIV_PRE_V)<<(SPI_CLKDIV_PRE_S)) +#define SPI_CLKDIV_PRE_V 0x1FFF +#define SPI_CLKDIV_PRE_S 18 +/* SPI_CLKCNT_N : R/W ;bitpos:[17:12] ;default: 6'h3 ; */ +/*description: In the master mode it is the divider of spi_clk. So spi_clk frequency + is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)*/ +#define SPI_CLKCNT_N 0x0000003F +#define SPI_CLKCNT_N_M ((SPI_CLKCNT_N_V)<<(SPI_CLKCNT_N_S)) +#define SPI_CLKCNT_N_V 0x3F +#define SPI_CLKCNT_N_S 12 +/* SPI_CLKCNT_H : R/W ;bitpos:[11:6] ;default: 6'h1 ; */ +/*description: In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In + the slave mode it must be 0.*/ +#define SPI_CLKCNT_H 0x0000003F +#define SPI_CLKCNT_H_M ((SPI_CLKCNT_H_V)<<(SPI_CLKCNT_H_S)) +#define SPI_CLKCNT_H_V 0x3F +#define SPI_CLKCNT_H_S 6 +/* SPI_CLKCNT_L : R/W ;bitpos:[5:0] ;default: 6'h3 ; */ +/*description: In the master mode it must be equal to spi_clkcnt_N. In the slave + mode it must be 0.*/ +#define SPI_CLKCNT_L 0x0000003F +#define SPI_CLKCNT_L_M ((SPI_CLKCNT_L_V)<<(SPI_CLKCNT_L_S)) +#define SPI_CLKCNT_L_V 0x3F +#define SPI_CLKCNT_L_S 0 + +#define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x1C) +/* SPI_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: This bit enable the command phase of an operation.*/ +#define SPI_USR_COMMAND (BIT(31)) +#define SPI_USR_COMMAND_M (BIT(31)) +#define SPI_USR_COMMAND_V 0x1 +#define SPI_USR_COMMAND_S 31 +/* SPI_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: This bit enable the address phase of an operation.*/ +#define SPI_USR_ADDR (BIT(30)) +#define SPI_USR_ADDR_M (BIT(30)) +#define SPI_USR_ADDR_V 0x1 +#define SPI_USR_ADDR_S 30 +/* SPI_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: This bit enable the dummy phase of an operation.*/ +#define SPI_USR_DUMMY (BIT(29)) +#define SPI_USR_DUMMY_M (BIT(29)) +#define SPI_USR_DUMMY_V 0x1 +#define SPI_USR_DUMMY_S 29 +/* SPI_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: This bit enable the read-data phase of an operation.*/ +#define SPI_USR_MISO (BIT(28)) +#define SPI_USR_MISO_M (BIT(28)) +#define SPI_USR_MISO_V 0x1 +#define SPI_USR_MISO_S 28 +/* SPI_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: This bit enable the write-data phase of an operation.*/ +#define SPI_USR_MOSI (BIT(27)) +#define SPI_USR_MOSI_M (BIT(27)) +#define SPI_USR_MOSI_V 0x1 +#define SPI_USR_MOSI_S 27 +/* SPI_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: spi clock is disable in dummy phase when the bit is enable.*/ +#define SPI_USR_DUMMY_IDLE (BIT(26)) +#define SPI_USR_DUMMY_IDLE_M (BIT(26)) +#define SPI_USR_DUMMY_IDLE_V 0x1 +#define SPI_USR_DUMMY_IDLE_S 26 +/* SPI_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: write-data phase only access to high-part of the buffer spi_w8~spi_w15. + 1: enable 0: disable.*/ +#define SPI_USR_MOSI_HIGHPART (BIT(25)) +#define SPI_USR_MOSI_HIGHPART_M (BIT(25)) +#define SPI_USR_MOSI_HIGHPART_V 0x1 +#define SPI_USR_MOSI_HIGHPART_S 25 +/* SPI_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: read-data phase only access to high-part of the buffer spi_w8~spi_w15. + 1: enable 0: disable.*/ +#define SPI_USR_MISO_HIGHPART (BIT(24)) +#define SPI_USR_MISO_HIGHPART_M (BIT(24)) +#define SPI_USR_MISO_HIGHPART_V 0x1 +#define SPI_USR_MISO_HIGHPART_S 24 +/* SPI_USR_PREP_HOLD : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: spi is hold at prepare state the bit combined with spi_usr_hold_pol bit.*/ +#define SPI_USR_PREP_HOLD (BIT(23)) +#define SPI_USR_PREP_HOLD_M (BIT(23)) +#define SPI_USR_PREP_HOLD_V 0x1 +#define SPI_USR_PREP_HOLD_S 23 +/* SPI_USR_CMD_HOLD : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: spi is hold at command state the bit combined with spi_usr_hold_pol bit.*/ +#define SPI_USR_CMD_HOLD (BIT(22)) +#define SPI_USR_CMD_HOLD_M (BIT(22)) +#define SPI_USR_CMD_HOLD_V 0x1 +#define SPI_USR_CMD_HOLD_S 22 +/* SPI_USR_ADDR_HOLD : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: spi is hold at address state the bit combined with spi_usr_hold_pol bit.*/ +#define SPI_USR_ADDR_HOLD (BIT(21)) +#define SPI_USR_ADDR_HOLD_M (BIT(21)) +#define SPI_USR_ADDR_HOLD_V 0x1 +#define SPI_USR_ADDR_HOLD_S 21 +/* SPI_USR_DUMMY_HOLD : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: spi is hold at dummy state the bit combined with spi_usr_hold_pol bit.*/ +#define SPI_USR_DUMMY_HOLD (BIT(20)) +#define SPI_USR_DUMMY_HOLD_M (BIT(20)) +#define SPI_USR_DUMMY_HOLD_V 0x1 +#define SPI_USR_DUMMY_HOLD_S 20 +/* SPI_USR_DIN_HOLD : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: spi is hold at data in state the bit combined with spi_usr_hold_pol bit.*/ +#define SPI_USR_DIN_HOLD (BIT(19)) +#define SPI_USR_DIN_HOLD_M (BIT(19)) +#define SPI_USR_DIN_HOLD_V 0x1 +#define SPI_USR_DIN_HOLD_S 19 +/* SPI_USR_DOUT_HOLD : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: spi is hold at data out state the bit combined with spi_usr_hold_pol bit.*/ +#define SPI_USR_DOUT_HOLD (BIT(18)) +#define SPI_USR_DOUT_HOLD_M (BIT(18)) +#define SPI_USR_DOUT_HOLD_V 0x1 +#define SPI_USR_DOUT_HOLD_S 18 +/* SPI_USR_HOLD_POL : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: It is combined with hold bits to set the polarity of spi hold + line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low*/ +#define SPI_USR_HOLD_POL (BIT(17)) +#define SPI_USR_HOLD_POL_M (BIT(17)) +#define SPI_USR_HOLD_POL_V 0x1 +#define SPI_USR_HOLD_POL_S 17 +/* SPI_SIO : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: Set the bit to enable 3-line half duplex communication mosi + and miso signals share the same pin. 1: enable 0: disable.*/ +#define SPI_SIO (BIT(16)) +#define SPI_SIO_M (BIT(16)) +#define SPI_SIO_V 0x1 +#define SPI_SIO_S 16 +/* SPI_FWRITE_QIO : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: In the write operations address phase and read-data phase apply 4 signals.*/ +#define SPI_FWRITE_QIO (BIT(15)) +#define SPI_FWRITE_QIO_M (BIT(15)) +#define SPI_FWRITE_QIO_V 0x1 +#define SPI_FWRITE_QIO_S 15 +/* SPI_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: In the write operations address phase and read-data phase apply 2 signals.*/ +#define SPI_FWRITE_DIO (BIT(14)) +#define SPI_FWRITE_DIO_M (BIT(14)) +#define SPI_FWRITE_DIO_V 0x1 +#define SPI_FWRITE_DIO_S 14 +/* SPI_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: In the write operations read-data phase apply 4 signals*/ +#define SPI_FWRITE_QUAD (BIT(13)) +#define SPI_FWRITE_QUAD_M (BIT(13)) +#define SPI_FWRITE_QUAD_V 0x1 +#define SPI_FWRITE_QUAD_S 13 +/* SPI_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: In the write operations read-data phase apply 2 signals*/ +#define SPI_FWRITE_DUAL (BIT(12)) +#define SPI_FWRITE_DUAL_M (BIT(12)) +#define SPI_FWRITE_DUAL_V 0x1 +#define SPI_FWRITE_DUAL_S 12 +/* SPI_WR_BYTE_ORDER : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: In command address write-data (MOSI) phases 1: big-endian 0: litte_endian*/ +#define SPI_WR_BYTE_ORDER (BIT(11)) +#define SPI_WR_BYTE_ORDER_M (BIT(11)) +#define SPI_WR_BYTE_ORDER_V 0x1 +#define SPI_WR_BYTE_ORDER_S 11 +/* SPI_RD_BYTE_ORDER : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: In read-data (MISO) phase 1: big-endian 0: little_endian*/ +#define SPI_RD_BYTE_ORDER (BIT(10)) +#define SPI_RD_BYTE_ORDER_M (BIT(10)) +#define SPI_RD_BYTE_ORDER_V 0x1 +#define SPI_RD_BYTE_ORDER_S 10 +/* SPI_CK_OUT_EDGE : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode.*/ +#define SPI_CK_OUT_EDGE (BIT(7)) +#define SPI_CK_OUT_EDGE_M (BIT(7)) +#define SPI_CK_OUT_EDGE_V 0x1 +#define SPI_CK_OUT_EDGE_S 7 +/* SPI_CK_I_EDGE : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: In the slave mode the bit is same as spi_ck_out_edge in master + mode. It is combined with spi_miso_delay_mode bits.*/ +#define SPI_CK_I_EDGE (BIT(6)) +#define SPI_CK_I_EDGE_M (BIT(6)) +#define SPI_CK_I_EDGE_V 0x1 +#define SPI_CK_I_EDGE_S 6 +/* SPI_CS_SETUP : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: spi cs is enable when spi is in ¡°prepare¡± phase. 1: enable 0: disable.*/ +#define SPI_CS_SETUP (BIT(5)) +#define SPI_CS_SETUP_M (BIT(5)) +#define SPI_CS_SETUP_V 0x1 +#define SPI_CS_SETUP_S 5 +/* SPI_CS_HOLD : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: spi cs keep low when spi is in ¡°done¡± phase. 1: enable 0: disable.*/ +#define SPI_CS_HOLD (BIT(4)) +#define SPI_CS_HOLD_M (BIT(4)) +#define SPI_CS_HOLD_V 0x1 +#define SPI_CS_HOLD_S 4 +/* SPI_DOUTDIN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set the bit to enable full duplex communication. 1: enable 0: disable.*/ +#define SPI_DOUTDIN (BIT(0)) +#define SPI_DOUTDIN_M (BIT(0)) +#define SPI_DOUTDIN_V 0x1 +#define SPI_DOUTDIN_S 0 + +#define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x20) +/* SPI_USR_ADDR_BITLEN : RO ;bitpos:[31:26] ;default: 6'd23 ; */ +/*description: The length in bits of address phase. The register value shall be (bit_num-1).*/ +#define SPI_USR_ADDR_BITLEN 0x0000003F +#define SPI_USR_ADDR_BITLEN_M ((SPI_USR_ADDR_BITLEN_V)<<(SPI_USR_ADDR_BITLEN_S)) +#define SPI_USR_ADDR_BITLEN_V 0x3F +#define SPI_USR_ADDR_BITLEN_S 26 +/* SPI_USR_DUMMY_CYCLELEN : R/W ;bitpos:[7:0] ;default: 8'd7 ; */ +/*description: The length in spi_clk cycles of dummy phase. The register value + shall be (cycle_num-1).*/ +#define SPI_USR_DUMMY_CYCLELEN 0x000000FF +#define SPI_USR_DUMMY_CYCLELEN_M ((SPI_USR_DUMMY_CYCLELEN_V)<<(SPI_USR_DUMMY_CYCLELEN_S)) +#define SPI_USR_DUMMY_CYCLELEN_V 0xFF +#define SPI_USR_DUMMY_CYCLELEN_S 0 + +#define SPI_USER2_REG(i) (REG_SPI_BASE(i) + 0x24) +/* SPI_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */ +/*description: The length in bits of command phase. The register value shall be (bit_num-1)*/ +#define SPI_USR_COMMAND_BITLEN 0x0000000F +#define SPI_USR_COMMAND_BITLEN_M ((SPI_USR_COMMAND_BITLEN_V)<<(SPI_USR_COMMAND_BITLEN_S)) +#define SPI_USR_COMMAND_BITLEN_V 0xF +#define SPI_USR_COMMAND_BITLEN_S 28 +/* SPI_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: The value of command.*/ +#define SPI_USR_COMMAND_VALUE 0x0000FFFF +#define SPI_USR_COMMAND_VALUE_M ((SPI_USR_COMMAND_VALUE_V)<<(SPI_USR_COMMAND_VALUE_S)) +#define SPI_USR_COMMAND_VALUE_V 0xFFFF +#define SPI_USR_COMMAND_VALUE_S 0 + +#define SPI_MOSI_DLEN_REG(i) (REG_SPI_BASE(i) + 0x28) +/* SPI_USR_MOSI_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: The length in bits of write-data. The register value shall be (bit_num-1).*/ +#define SPI_USR_MOSI_DBITLEN 0x00FFFFFF +#define SPI_USR_MOSI_DBITLEN_M ((SPI_USR_MOSI_DBITLEN_V)<<(SPI_USR_MOSI_DBITLEN_S)) +#define SPI_USR_MOSI_DBITLEN_V 0xFFFFFF +#define SPI_USR_MOSI_DBITLEN_S 0 + +#define SPI_MISO_DLEN_REG(i) (REG_SPI_BASE(i) + 0x2C) +/* SPI_USR_MISO_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: The length in bits of read-data. The register value shall be (bit_num-1).*/ +#define SPI_USR_MISO_DBITLEN 0x00FFFFFF +#define SPI_USR_MISO_DBITLEN_M ((SPI_USR_MISO_DBITLEN_V)<<(SPI_USR_MISO_DBITLEN_S)) +#define SPI_USR_MISO_DBITLEN_V 0xFFFFFF +#define SPI_USR_MISO_DBITLEN_S 0 + +#define SPI_SLV_WR_STATUS_REG(i) (REG_SPI_BASE(i) + 0x30) +/* SPI_SLV_WR_ST : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: In the slave mode this register are the status register for the + master to write into. In the master mode this register are the higher 32bits in the 64 bits address condition.*/ +#define SPI_SLV_WR_ST 0xFFFFFFFF +#define SPI_SLV_WR_ST_M ((SPI_SLV_WR_ST_V)<<(SPI_SLV_WR_ST_S)) +#define SPI_SLV_WR_ST_V 0xFFFFFFFF +#define SPI_SLV_WR_ST_S 0 + +#define SPI_PIN_REG(i) (REG_SPI_BASE(i) + 0x34) +/* SPI_CS_KEEP_ACTIVE : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: spi cs line keep low when the bit is set.*/ +#define SPI_CS_KEEP_ACTIVE (BIT(30)) +#define SPI_CS_KEEP_ACTIVE_M (BIT(30)) +#define SPI_CS_KEEP_ACTIVE_V 0x1 +#define SPI_CS_KEEP_ACTIVE_S 30 +/* SPI_CK_IDLE_EDGE : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: 1: spi clk line is high when idle 0: spi clk line is low when idle*/ +#define SPI_CK_IDLE_EDGE (BIT(29)) +#define SPI_CK_IDLE_EDGE_M (BIT(29)) +#define SPI_CK_IDLE_EDGE_V 0x1 +#define SPI_CK_IDLE_EDGE_S 29 +/* SPI_MASTER_CK_SEL : R/W ;bitpos:[13:11] ;default: 3'b0 ; */ +/*description: In the master mode spi cs line is enable as spi clk it is combined + with spi_cs0_dis spi_cs1_dis spi_cs2_dis.*/ +#define SPI_MASTER_CK_SEL 0x00000007 +#define SPI_MASTER_CK_SEL_M ((SPI_MASTER_CK_SEL_V)<<(SPI_MASTER_CK_SEL_S)) +#define SPI_MASTER_CK_SEL_V 0x07 +#define SPI_MASTER_CK_SEL_S 11 +/* SPI_MASTER_CS_POL : R/W ;bitpos:[8:6] ;default: 3'b0 ; */ +/*description: In the master mode the bits are the polarity of spi cs line + the value is equivalent to spi_cs ^ spi_master_cs_pol.*/ +#define SPI_MASTER_CS_POL 0x00000007 +#define SPI_MASTER_CS_POL_M ((SPI_MASTER_CS_POL_V)<<(SPI_MASTER_CS_POL_S)) +#define SPI_MASTER_CS_POL_V 0x7 +#define SPI_MASTER_CS_POL_S 6 +/* SPI_CK_DIS : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: 1: spi clk out disable 0: spi clk out enable*/ +#define SPI_CK_DIS (BIT(5)) +#define SPI_CK_DIS_M (BIT(5)) +#define SPI_CK_DIS_V 0x1 +#define SPI_CK_DIS_S 5 +/* SPI_CS2_DIS : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin*/ +#define SPI_CS2_DIS (BIT(2)) +#define SPI_CS2_DIS_M (BIT(2)) +#define SPI_CS2_DIS_V 0x1 +#define SPI_CS2_DIS_S 2 +/* SPI_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin*/ +#define SPI_CS1_DIS (BIT(1)) +#define SPI_CS1_DIS_M (BIT(1)) +#define SPI_CS1_DIS_V 0x1 +#define SPI_CS1_DIS_S 1 +/* SPI_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin*/ +#define SPI_CS0_DIS (BIT(0)) +#define SPI_CS0_DIS_M (BIT(0)) +#define SPI_CS0_DIS_V 0x1 +#define SPI_CS0_DIS_S 0 + +#define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0x38) +/* SPI_SYNC_RESET : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Software reset enable, reset the spi clock line cs line and data lines.*/ +#define SPI_SYNC_RESET (BIT(31)) +#define SPI_SYNC_RESET_M (BIT(31)) +#define SPI_SYNC_RESET_V 0x1 +#define SPI_SYNC_RESET_S 31 +/* SPI_SLAVE_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: 1: slave mode 0: master mode.*/ +#define SPI_SLAVE_MODE (BIT(30)) +#define SPI_SLAVE_MODE_M (BIT(30)) +#define SPI_SLAVE_MODE_V 0x1 +#define SPI_SLAVE_MODE_S 30 +/* SPI_SLV_WR_RD_BUF_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: write and read buffer enable in the slave mode*/ +#define SPI_SLV_WR_RD_BUF_EN (BIT(29)) +#define SPI_SLV_WR_RD_BUF_EN_M (BIT(29)) +#define SPI_SLV_WR_RD_BUF_EN_V 0x1 +#define SPI_SLV_WR_RD_BUF_EN_S 29 +/* SPI_SLV_WR_RD_STA_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: write and read status enable in the slave mode*/ +#define SPI_SLV_WR_RD_STA_EN (BIT(28)) +#define SPI_SLV_WR_RD_STA_EN_M (BIT(28)) +#define SPI_SLV_WR_RD_STA_EN_V 0x1 +#define SPI_SLV_WR_RD_STA_EN_S 28 +/* SPI_SLV_CMD_DEFINE : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: 1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode + commands are fixed as: 1: write-status 2: write-buffer and 3: read-buffer.*/ +#define SPI_SLV_CMD_DEFINE (BIT(27)) +#define SPI_SLV_CMD_DEFINE_M (BIT(27)) +#define SPI_SLV_CMD_DEFINE_V 0x1 +#define SPI_SLV_CMD_DEFINE_S 27 +/* SPI_TRANS_CNT : RO ;bitpos:[26:23] ;default: 4'b0 ; */ +/*description: The operations counter in both the master mode and the slave + mode. 4: read-status*/ +#define SPI_TRANS_CNT 0x0000000F +#define SPI_TRANS_CNT_M ((SPI_TRANS_CNT_V)<<(SPI_TRANS_CNT_S)) +#define SPI_TRANS_CNT_V 0xF +#define SPI_TRANS_CNT_S 23 +/* SPI_SLV_LAST_STATE : RO ;bitpos:[22:20] ;default: 3'b0 ; */ +/*description: In the slave mode it is the state of spi state machine.*/ +#define SPI_SLV_LAST_STATE 0x00000007 +#define SPI_SLV_LAST_STATE_M ((SPI_SLV_LAST_STATE_V)<<(SPI_SLV_LAST_STATE_S)) +#define SPI_SLV_LAST_STATE_V 0x7 +#define SPI_SLV_LAST_STATE_S 20 +/* SPI_SLV_LAST_COMMAND : RO ;bitpos:[19:17] ;default: 3'b0 ; */ +/*description: In the slave mode it is the value of command.*/ +#define SPI_SLV_LAST_COMMAND 0x00000007 +#define SPI_SLV_LAST_COMMAND_M ((SPI_SLV_LAST_COMMAND_V)<<(SPI_SLV_LAST_COMMAND_S)) +#define SPI_SLV_LAST_COMMAND_V 0x7 +#define SPI_SLV_LAST_COMMAND_S 17 +/* SPI_CS_I_MODE : R/W ;bitpos:[11:10] ;default: 2'b0 ; */ +/*description: In the slave mode this bits used to synchronize the input spi + cs signal and eliminate spi cs jitter.*/ +#define SPI_CS_I_MODE 0x00000003 +#define SPI_CS_I_MODE_M ((SPI_CS_I_MODE_V)<<(SPI_CS_I_MODE_S)) +#define SPI_CS_I_MODE_V 0x3 +#define SPI_CS_I_MODE_S 10 +/* SPI_INT_EN : R/W ;bitpos:[9:5] ;default: 5'b1_0000 ; */ +/*description: Interrupt enable bits for the below 5 sources*/ +#define SPI_INT_EN 0x0000001F +#define SPI_INT_EN_M ((SPI_INT_EN_V)<<(SPI_INT_EN_S)) +#define SPI_INT_EN_V 0x1F +#define SPI_INT_EN_S 5 +/* SPI_TRANS_DONE : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for the completion of any operation in + both the master mode and the slave mode.*/ +#define SPI_TRANS_DONE (BIT(4)) +#define SPI_TRANS_DONE_M (BIT(4)) +#define SPI_TRANS_DONE_V 0x1 +#define SPI_TRANS_DONE_S 4 +/* SPI_SLV_WR_STA_DONE : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for the completion of write-status operation + in the slave mode.*/ +#define SPI_SLV_WR_STA_DONE (BIT(3)) +#define SPI_SLV_WR_STA_DONE_M (BIT(3)) +#define SPI_SLV_WR_STA_DONE_V 0x1 +#define SPI_SLV_WR_STA_DONE_S 3 +/* SPI_SLV_RD_STA_DONE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for the completion of read-status operation + in the slave mode.*/ +#define SPI_SLV_RD_STA_DONE (BIT(2)) +#define SPI_SLV_RD_STA_DONE_M (BIT(2)) +#define SPI_SLV_RD_STA_DONE_V 0x1 +#define SPI_SLV_RD_STA_DONE_S 2 +/* SPI_SLV_WR_BUF_DONE : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for the completion of write-buffer operation + in the slave mode.*/ +#define SPI_SLV_WR_BUF_DONE (BIT(1)) +#define SPI_SLV_WR_BUF_DONE_M (BIT(1)) +#define SPI_SLV_WR_BUF_DONE_V 0x1 +#define SPI_SLV_WR_BUF_DONE_S 1 +/* SPI_SLV_RD_BUF_DONE : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt raw bit for the completion of read-buffer operation + in the slave mode.*/ +#define SPI_SLV_RD_BUF_DONE (BIT(0)) +#define SPI_SLV_RD_BUF_DONE_M (BIT(0)) +#define SPI_SLV_RD_BUF_DONE_V 0x1 +#define SPI_SLV_RD_BUF_DONE_S 0 + +#define SPI_SLAVE1_REG(i) (REG_SPI_BASE(i) + 0x3C) +/* SPI_SLV_STATUS_BITLEN : R/W ;bitpos:[31:27] ;default: 5'b0 ; */ +/*description: In the slave mode it is the length of status bit.*/ +#define SPI_SLV_STATUS_BITLEN 0x0000001F +#define SPI_SLV_STATUS_BITLEN_M ((SPI_SLV_STATUS_BITLEN_V)<<(SPI_SLV_STATUS_BITLEN_S)) +#define SPI_SLV_STATUS_BITLEN_V 0x1F +#define SPI_SLV_STATUS_BITLEN_S 27 +/* SPI_SLV_STATUS_FAST_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: In the slave mode enable fast read status.*/ +#define SPI_SLV_STATUS_FAST_EN (BIT(26)) +#define SPI_SLV_STATUS_FAST_EN_M (BIT(26)) +#define SPI_SLV_STATUS_FAST_EN_V 0x1 +#define SPI_SLV_STATUS_FAST_EN_S 26 +/* SPI_SLV_STATUS_READBACK : R/W ;bitpos:[25] ;default: 1'b1 ; */ +/*description: In the slave mode 1:read register of SPI_SLV_WR_STATUS 0: read + register of SPI_RD_STATUS.*/ +#define SPI_SLV_STATUS_READBACK (BIT(25)) +#define SPI_SLV_STATUS_READBACK_M (BIT(25)) +#define SPI_SLV_STATUS_READBACK_V 0x1 +#define SPI_SLV_STATUS_READBACK_S 25 +/* SPI_SLV_RD_ADDR_BITLEN : R/W ;bitpos:[15:10] ;default: 6'h0 ; */ +/*description: In the slave mode it is the address length in bits for read-buffer + operation. The register value shall be (bit_num-1).*/ +#define SPI_SLV_RD_ADDR_BITLEN 0x0000003F +#define SPI_SLV_RD_ADDR_BITLEN_M ((SPI_SLV_RD_ADDR_BITLEN_V)<<(SPI_SLV_RD_ADDR_BITLEN_S)) +#define SPI_SLV_RD_ADDR_BITLEN_V 0x3F +#define SPI_SLV_RD_ADDR_BITLEN_S 10 +/* SPI_SLV_WR_ADDR_BITLEN : R/W ;bitpos:[9:4] ;default: 6'h0 ; */ +/*description: In the slave mode it is the address length in bits for write-buffer + operation. The register value shall be (bit_num-1).*/ +#define SPI_SLV_WR_ADDR_BITLEN 0x0000003F +#define SPI_SLV_WR_ADDR_BITLEN_M ((SPI_SLV_WR_ADDR_BITLEN_V)<<(SPI_SLV_WR_ADDR_BITLEN_S)) +#define SPI_SLV_WR_ADDR_BITLEN_V 0x3F +#define SPI_SLV_WR_ADDR_BITLEN_S 4 +/* SPI_SLV_WRSTA_DUMMY_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: In the slave mode it is the enable bit of dummy phase for write-status + operations.*/ +#define SPI_SLV_WRSTA_DUMMY_EN (BIT(3)) +#define SPI_SLV_WRSTA_DUMMY_EN_M (BIT(3)) +#define SPI_SLV_WRSTA_DUMMY_EN_V 0x1 +#define SPI_SLV_WRSTA_DUMMY_EN_S 3 +/* SPI_SLV_RDSTA_DUMMY_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: In the slave mode it is the enable bit of dummy phase for read-status + operations.*/ +#define SPI_SLV_RDSTA_DUMMY_EN (BIT(2)) +#define SPI_SLV_RDSTA_DUMMY_EN_M (BIT(2)) +#define SPI_SLV_RDSTA_DUMMY_EN_V 0x1 +#define SPI_SLV_RDSTA_DUMMY_EN_S 2 +/* SPI_SLV_WRBUF_DUMMY_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: In the slave mode it is the enable bit of dummy phase for write-buffer + operations.*/ +#define SPI_SLV_WRBUF_DUMMY_EN (BIT(1)) +#define SPI_SLV_WRBUF_DUMMY_EN_M (BIT(1)) +#define SPI_SLV_WRBUF_DUMMY_EN_V 0x1 +#define SPI_SLV_WRBUF_DUMMY_EN_S 1 +/* SPI_SLV_RDBUF_DUMMY_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: In the slave mode it is the enable bit of dummy phase for read-buffer + operations.*/ +#define SPI_SLV_RDBUF_DUMMY_EN (BIT(0)) +#define SPI_SLV_RDBUF_DUMMY_EN_M (BIT(0)) +#define SPI_SLV_RDBUF_DUMMY_EN_V 0x1 +#define SPI_SLV_RDBUF_DUMMY_EN_S 0 + +#define SPI_SLAVE2_REG(i) (REG_SPI_BASE(i) + 0x40) +/* SPI_SLV_WRBUF_DUMMY_CYCLELEN : R/W ;bitpos:[31:24] ;default: 8'b0 ; */ +/*description: In the slave mode it is the length in spi_clk cycles of dummy + phase for write-buffer operations. The register value shall be (cycle_num-1).*/ +#define SPI_SLV_WRBUF_DUMMY_CYCLELEN 0x000000FF +#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_M ((SPI_SLV_WRBUF_DUMMY_CYCLELEN_V)<<(SPI_SLV_WRBUF_DUMMY_CYCLELEN_S)) +#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_V 0xFF +#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_S 24 +/* SPI_SLV_RDBUF_DUMMY_CYCLELEN : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: In the slave mode it is the length in spi_clk cycles of dummy + phase for read-buffer operations. The register value shall be (cycle_num-1).*/ +#define SPI_SLV_RDBUF_DUMMY_CYCLELEN 0x000000FF +#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_M ((SPI_SLV_RDBUF_DUMMY_CYCLELEN_V)<<(SPI_SLV_RDBUF_DUMMY_CYCLELEN_S)) +#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_V 0xFF +#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_S 16 +/* SPI_SLV_WRSTA_DUMMY_CYCLELEN : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: In the slave mode it is the length in spi_clk cycles of dummy + phase for write-status operations. The register value shall be (cycle_num-1).*/ +#define SPI_SLV_WRSTA_DUMMY_CYCLELEN 0x000000FF +#define SPI_SLV_WRSTA_DUMMY_CYCLELEN_M ((SPI_SLV_WRSTA_DUMMY_CYCLELEN_V)<<(SPI_SLV_WRSTA_DUMMY_CYCLELEN_S)) +#define SPI_SLV_WRSTA_DUMMY_CYCLELEN_V 0xFF +#define SPI_SLV_WRSTA_DUMMY_CYCLELEN_S 8 +/* SPI_SLV_RDSTA_DUMMY_CYCLELEN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: In the slave mode it is the length in spi_clk cycles of dummy + phase for read-status operations. The register value shall be (cycle_num-1).*/ +#define SPI_SLV_RDSTA_DUMMY_CYCLELEN 0x000000FF +#define SPI_SLV_RDSTA_DUMMY_CYCLELEN_M ((SPI_SLV_RDSTA_DUMMY_CYCLELEN_V)<<(SPI_SLV_RDSTA_DUMMY_CYCLELEN_S)) +#define SPI_SLV_RDSTA_DUMMY_CYCLELEN_V 0xFF +#define SPI_SLV_RDSTA_DUMMY_CYCLELEN_S 0 + +#define SPI_SLAVE3_REG(i) (REG_SPI_BASE(i) + 0x44) +/* SPI_SLV_WRSTA_CMD_VALUE : R/W ;bitpos:[31:24] ;default: 8'b0 ; */ +/*description: In the slave mode it is the value of write-status command.*/ +#define SPI_SLV_WRSTA_CMD_VALUE 0x000000FF +#define SPI_SLV_WRSTA_CMD_VALUE_M ((SPI_SLV_WRSTA_CMD_VALUE_V)<<(SPI_SLV_WRSTA_CMD_VALUE_S)) +#define SPI_SLV_WRSTA_CMD_VALUE_V 0xFF +#define SPI_SLV_WRSTA_CMD_VALUE_S 24 +/* SPI_SLV_RDSTA_CMD_VALUE : R/W ;bitpos:[23:16] ;default: 8'b0 ; */ +/*description: In the slave mode it is the value of read-status command.*/ +#define SPI_SLV_RDSTA_CMD_VALUE 0x000000FF +#define SPI_SLV_RDSTA_CMD_VALUE_M ((SPI_SLV_RDSTA_CMD_VALUE_V)<<(SPI_SLV_RDSTA_CMD_VALUE_S)) +#define SPI_SLV_RDSTA_CMD_VALUE_V 0xFF +#define SPI_SLV_RDSTA_CMD_VALUE_S 16 +/* SPI_SLV_WRBUF_CMD_VALUE : R/W ;bitpos:[15:8] ;default: 8'b0 ; */ +/*description: In the slave mode it is the value of write-buffer command.*/ +#define SPI_SLV_WRBUF_CMD_VALUE 0x000000FF +#define SPI_SLV_WRBUF_CMD_VALUE_M ((SPI_SLV_WRBUF_CMD_VALUE_V)<<(SPI_SLV_WRBUF_CMD_VALUE_S)) +#define SPI_SLV_WRBUF_CMD_VALUE_V 0xFF +#define SPI_SLV_WRBUF_CMD_VALUE_S 8 +/* SPI_SLV_RDBUF_CMD_VALUE : R/W ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: In the slave mode it is the value of read-buffer command.*/ +#define SPI_SLV_RDBUF_CMD_VALUE 0x000000FF +#define SPI_SLV_RDBUF_CMD_VALUE_M ((SPI_SLV_RDBUF_CMD_VALUE_V)<<(SPI_SLV_RDBUF_CMD_VALUE_S)) +#define SPI_SLV_RDBUF_CMD_VALUE_V 0xFF +#define SPI_SLV_RDBUF_CMD_VALUE_S 0 + +#define SPI_SLV_WRBUF_DLEN_REG(i) (REG_SPI_BASE(i) + 0x48) +/* SPI_SLV_WRBUF_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: In the slave mode it is the length in bits for write-buffer operations. + The register value shall be (bit_num-1).*/ +#define SPI_SLV_WRBUF_DBITLEN 0x00FFFFFF +#define SPI_SLV_WRBUF_DBITLEN_M ((SPI_SLV_WRBUF_DBITLEN_V)<<(SPI_SLV_WRBUF_DBITLEN_S)) +#define SPI_SLV_WRBUF_DBITLEN_V 0xFFFFFF +#define SPI_SLV_WRBUF_DBITLEN_S 0 + +#define SPI_SLV_RDBUF_DLEN_REG(i) (REG_SPI_BASE(i) + 0x4C) +/* SPI_SLV_RDBUF_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: In the slave mode it is the length in bits for read-buffer operations. + The register value shall be (bit_num-1).*/ +#define SPI_SLV_RDBUF_DBITLEN 0x00FFFFFF +#define SPI_SLV_RDBUF_DBITLEN_M ((SPI_SLV_RDBUF_DBITLEN_V)<<(SPI_SLV_RDBUF_DBITLEN_S)) +#define SPI_SLV_RDBUF_DBITLEN_V 0xFFFFFF +#define SPI_SLV_RDBUF_DBITLEN_S 0 + +#define SPI_CACHE_FCTRL_REG(i) (REG_SPI_BASE(i) + 0x50) +/* SPI_CACHE_FLASH_PES_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: For SPI0 spi1 send suspend command before cache read flash + 1: enable 0:disable.*/ +#define SPI_CACHE_FLASH_PES_EN (BIT(3)) +#define SPI_CACHE_FLASH_PES_EN_M (BIT(3)) +#define SPI_CACHE_FLASH_PES_EN_V 0x1 +#define SPI_CACHE_FLASH_PES_EN_S 3 +/* SPI_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: For SPI0 cache read flash for user define command 1: enable 0:disable.*/ +#define SPI_CACHE_FLASH_USR_CMD (BIT(2)) +#define SPI_CACHE_FLASH_USR_CMD_M (BIT(2)) +#define SPI_CACHE_FLASH_USR_CMD_V 0x1 +#define SPI_CACHE_FLASH_USR_CMD_S 2 +/* SPI_CACHE_USR_CMD_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: For SPI0 cache read flash with 4 bytes command 1: enable 0:disable.*/ +#define SPI_CACHE_USR_CMD_4BYTE (BIT(1)) +#define SPI_CACHE_USR_CMD_4BYTE_M (BIT(1)) +#define SPI_CACHE_USR_CMD_4BYTE_V 0x1 +#define SPI_CACHE_USR_CMD_4BYTE_S 1 +/* SPI_CACHE_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: For SPI0 Cache access enable 1: enable 0:disable.*/ +#define SPI_CACHE_REQ_EN (BIT(0)) +#define SPI_CACHE_REQ_EN_M (BIT(0)) +#define SPI_CACHE_REQ_EN_V 0x1 +#define SPI_CACHE_REQ_EN_S 0 + +#define SPI_CACHE_SCTRL_REG(i) (REG_SPI_BASE(i) + 0x54) +/* SPI_CACHE_SRAM_USR_WCMD : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: For SPI0 In the spi sram mode cache write sram for user define command*/ +#define SPI_CACHE_SRAM_USR_WCMD (BIT(28)) +#define SPI_CACHE_SRAM_USR_WCMD_M (BIT(28)) +#define SPI_CACHE_SRAM_USR_WCMD_V 0x1 +#define SPI_CACHE_SRAM_USR_WCMD_S 28 +/* SPI_SRAM_ADDR_BITLEN : R/W ;bitpos:[27:22] ;default: 6'd23 ; */ +/*description: For SPI0 In the sram mode it is the length in bits of address + phase. The register value shall be (bit_num-1).*/ +#define SPI_SRAM_ADDR_BITLEN 0x0000003F +#define SPI_SRAM_ADDR_BITLEN_M ((SPI_SRAM_ADDR_BITLEN_V)<<(SPI_SRAM_ADDR_BITLEN_S)) +#define SPI_SRAM_ADDR_BITLEN_V 0x3F +#define SPI_SRAM_ADDR_BITLEN_S 22 +/* SPI_SRAM_DUMMY_CYCLELEN : R/W ;bitpos:[21:14] ;default: 8'b1 ; */ +/*description: For SPI0 In the sram mode it is the length in bits of address + phase. The register value shall be (bit_num-1).*/ +#define SPI_SRAM_DUMMY_CYCLELEN 0x000000FF +#define SPI_SRAM_DUMMY_CYCLELEN_M ((SPI_SRAM_DUMMY_CYCLELEN_V)<<(SPI_SRAM_DUMMY_CYCLELEN_S)) +#define SPI_SRAM_DUMMY_CYCLELEN_V 0xFF +#define SPI_SRAM_DUMMY_CYCLELEN_S 14 +/* SPI_SRAM_BYTES_LEN : R/W ;bitpos:[13:6] ;default: 8'b32 ; */ +/*description: For SPI0 In the sram mode it is the byte length of spi read sram data.*/ +#define SPI_SRAM_BYTES_LEN 0x000000FF +#define SPI_SRAM_BYTES_LEN_M ((SPI_SRAM_BYTES_LEN_V)<<(SPI_SRAM_BYTES_LEN_S)) +#define SPI_SRAM_BYTES_LEN_V 0xFF +#define SPI_SRAM_BYTES_LEN_S 6 +/* SPI_CACHE_SRAM_USR_RCMD : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: For SPI0 In the spi sram mode cache read sram for user define command.*/ +#define SPI_CACHE_SRAM_USR_RCMD (BIT(5)) +#define SPI_CACHE_SRAM_USR_RCMD_M (BIT(5)) +#define SPI_CACHE_SRAM_USR_RCMD_V 0x1 +#define SPI_CACHE_SRAM_USR_RCMD_S 5 +/* SPI_USR_RD_SRAM_DUMMY : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: For SPI0 In the spi sram mode it is the enable bit of dummy + phase for read operations.*/ +#define SPI_USR_RD_SRAM_DUMMY (BIT(4)) +#define SPI_USR_RD_SRAM_DUMMY_M (BIT(4)) +#define SPI_USR_RD_SRAM_DUMMY_V 0x1 +#define SPI_USR_RD_SRAM_DUMMY_S 4 +/* SPI_USR_WR_SRAM_DUMMY : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: For SPI0 In the spi sram mode it is the enable bit of dummy + phase for write operations.*/ +#define SPI_USR_WR_SRAM_DUMMY (BIT(3)) +#define SPI_USR_WR_SRAM_DUMMY_M (BIT(3)) +#define SPI_USR_WR_SRAM_DUMMY_V 0x1 +#define SPI_USR_WR_SRAM_DUMMY_S 3 +/* SPI_USR_SRAM_QIO : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: For SPI0 In the spi sram mode spi quad I/O mode enable 1: enable 0:disable*/ +#define SPI_USR_SRAM_QIO (BIT(2)) +#define SPI_USR_SRAM_QIO_M (BIT(2)) +#define SPI_USR_SRAM_QIO_V 0x1 +#define SPI_USR_SRAM_QIO_S 2 +/* SPI_USR_SRAM_DIO : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable*/ +#define SPI_USR_SRAM_DIO (BIT(1)) +#define SPI_USR_SRAM_DIO_M (BIT(1)) +#define SPI_USR_SRAM_DIO_V 0x1 +#define SPI_USR_SRAM_DIO_S 1 + +#define SPI_SRAM_CMD_REG(i) (REG_SPI_BASE(i) + 0x58) +/* SPI_SRAM_RSTIO : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: For SPI0 SRAM IO mode reset enable. SRAM IO mode reset operation + will be triggered when the bit is set. The bit will be cleared once the operation done*/ +#define SPI_SRAM_RSTIO (BIT(4)) +#define SPI_SRAM_RSTIO_M (BIT(4)) +#define SPI_SRAM_RSTIO_V 0x1 +#define SPI_SRAM_RSTIO_S 4 +/* SPI_SRAM_QIO : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: For SPI0 SRAM QIO mode enable . SRAM QIO enable command will + be send when the bit is set. The bit will be cleared once the operation done.*/ +#define SPI_SRAM_QIO (BIT(1)) +#define SPI_SRAM_QIO_M (BIT(1)) +#define SPI_SRAM_QIO_V 0x1 +#define SPI_SRAM_QIO_S 1 +/* SPI_SRAM_DIO : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: For SPI0 SRAM DIO mode enable . SRAM DIO enable command will + be send when the bit is set. The bit will be cleared once the operation done.*/ +#define SPI_SRAM_DIO (BIT(0)) +#define SPI_SRAM_DIO_M (BIT(0)) +#define SPI_SRAM_DIO_V 0x1 +#define SPI_SRAM_DIO_S 0 + +#define SPI_SRAM_DRD_CMD_REG(i) (REG_SPI_BASE(i) + 0x5C) +/* SPI_CACHE_SRAM_USR_RD_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: For SPI0 When cache mode is enable it is the length in bits of + command phase for SRAM. The register value shall be (bit_num-1).*/ +#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000F +#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_M ((SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V)<<(SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S)) +#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V 0xF +#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S 28 +/* SPI_CACHE_SRAM_USR_RD_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: For SPI0 When cache mode is enable it is the read command value + of command phase for SRAM.*/ +#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFF +#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE_M ((SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V)<<(SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S)) +#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V 0xFFFF +#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S 0 + +#define SPI_SRAM_DWR_CMD_REG(i) (REG_SPI_BASE(i) + 0x60) +/* SPI_CACHE_SRAM_USR_WR_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: For SPI0 When cache mode is enable it is the in bits of command + phase for SRAM. The register value shall be (bit_num-1).*/ +#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000F +#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_M ((SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_V)<<(SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S)) +#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_V 0xF +#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S 28 +/* SPI_CACHE_SRAM_USR_WR_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: For SPI0 When cache mode is enable it is the write command value + of command phase for SRAM.*/ +#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFF +#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE_M ((SPI_CACHE_SRAM_USR_WR_CMD_VALUE_V)<<(SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S)) +#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE_V 0xFFFF +#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S 0 + +#define SPI_SLV_RD_BIT_REG(i) (REG_SPI_BASE(i) + 0x64) +/* SPI_SLV_RDATA_BIT : RW ;bitpos:[23:0] ;default: 24'b0 ; */ +/*description: In the slave mode it is the bit length of read data. The value + is the length - 1.*/ +#define SPI_SLV_RDATA_BIT 0x00FFFFFF +#define SPI_SLV_RDATA_BIT_M ((SPI_SLV_RDATA_BIT_V)<<(SPI_SLV_RDATA_BIT_S)) +#define SPI_SLV_RDATA_BIT_V 0xFFFFFF +#define SPI_SLV_RDATA_BIT_S 0 + +#define SPI_W0_REG(i) (REG_SPI_BASE(i) + 0x80) +/* SPI_BUF0 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF0 0xFFFFFFFF +#define SPI_BUF0_M ((SPI_BUF0_V)<<(SPI_BUF0_S)) +#define SPI_BUF0_V 0xFFFFFFFF +#define SPI_BUF0_S 0 + +#define SPI_W1_REG(i) (REG_SPI_BASE(i) + 0x84) +/* SPI_BUF1 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF1 0xFFFFFFFF +#define SPI_BUF1_M ((SPI_BUF1_V)<<(SPI_BUF1_S)) +#define SPI_BUF1_V 0xFFFFFFFF +#define SPI_BUF1_S 0 + +#define SPI_W2_REG(i) (REG_SPI_BASE(i) + 0x88) +/* SPI_BUF2 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF2 0xFFFFFFFF +#define SPI_BUF2_M ((SPI_BUF2_V)<<(SPI_BUF2_S)) +#define SPI_BUF2_V 0xFFFFFFFF +#define SPI_BUF2_S 0 + +#define SPI_W3_REG(i) (REG_SPI_BASE(i) + 0x8C) +/* SPI_BUF3 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF3 0xFFFFFFFF +#define SPI_BUF3_M ((SPI_BUF3_V)<<(SPI_BUF3_S)) +#define SPI_BUF3_V 0xFFFFFFFF +#define SPI_BUF3_S 0 + +#define SPI_W4_REG(i) (REG_SPI_BASE(i) + 0x90) +/* SPI_BUF4 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF4 0xFFFFFFFF +#define SPI_BUF4_M ((SPI_BUF4_V)<<(SPI_BUF4_S)) +#define SPI_BUF4_V 0xFFFFFFFF +#define SPI_BUF4_S 0 + +#define SPI_W5_REG(i) (REG_SPI_BASE(i) + 0x94) +/* SPI_BUF5 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF5 0xFFFFFFFF +#define SPI_BUF5_M ((SPI_BUF5_V)<<(SPI_BUF5_S)) +#define SPI_BUF5_V 0xFFFFFFFF +#define SPI_BUF5_S 0 + +#define SPI_W6_REG(i) (REG_SPI_BASE(i) + 0x98) +/* SPI_BUF6 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF6 0xFFFFFFFF +#define SPI_BUF6_M ((SPI_BUF6_V)<<(SPI_BUF6_S)) +#define SPI_BUF6_V 0xFFFFFFFF +#define SPI_BUF6_S 0 + +#define SPI_W7_REG(i) (REG_SPI_BASE(i) + 0x9C) +/* SPI_BUF7 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF7 0xFFFFFFFF +#define SPI_BUF7_M ((SPI_BUF7_V)<<(SPI_BUF7_S)) +#define SPI_BUF7_V 0xFFFFFFFF +#define SPI_BUF7_S 0 + +#define SPI_W8_REG(i) (REG_SPI_BASE(i) + 0xA0) +/* SPI_BUF8 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF8 0xFFFFFFFF +#define SPI_BUF8_M ((SPI_BUF8_V)<<(SPI_BUF8_S)) +#define SPI_BUF8_V 0xFFFFFFFF +#define SPI_BUF8_S 0 + +#define SPI_W9_REG(i) (REG_SPI_BASE(i) + 0xA4) +/* SPI_BUF9 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF9 0xFFFFFFFF +#define SPI_BUF9_M ((SPI_BUF9_V)<<(SPI_BUF9_S)) +#define SPI_BUF9_V 0xFFFFFFFF +#define SPI_BUF9_S 0 + +#define SPI_W10_REG(i) (REG_SPI_BASE(i) + 0xA8) +/* SPI_BUF10 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF10 0xFFFFFFFF +#define SPI_BUF10_M ((SPI_BUF10_V)<<(SPI_BUF10_S)) +#define SPI_BUF10_V 0xFFFFFFFF +#define SPI_BUF10_S 0 + +#define SPI_W11_REG(i) (REG_SPI_BASE(i) + 0xAC) +/* SPI_BUF11 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF11 0xFFFFFFFF +#define SPI_BUF11_M ((SPI_BUF11_V)<<(SPI_BUF11_S)) +#define SPI_BUF11_V 0xFFFFFFFF +#define SPI_BUF11_S 0 + +#define SPI_W12_REG(i) (REG_SPI_BASE(i) + 0xB0) +/* SPI_BUF12 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF12 0xFFFFFFFF +#define SPI_BUF12_M ((SPI_BUF12_V)<<(SPI_BUF12_S)) +#define SPI_BUF12_V 0xFFFFFFFF +#define SPI_BUF12_S 0 + +#define SPI_W13_REG(i) (REG_SPI_BASE(i) + 0xB4) +/* SPI_BUF13 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF13 0xFFFFFFFF +#define SPI_BUF13_M ((SPI_BUF13_V)<<(SPI_BUF13_S)) +#define SPI_BUF13_V 0xFFFFFFFF +#define SPI_BUF13_S 0 + +#define SPI_W14_REG(i) (REG_SPI_BASE(i) + 0xB8) +/* SPI_BUF14 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF14 0xFFFFFFFF +#define SPI_BUF14_M ((SPI_BUF14_V)<<(SPI_BUF14_S)) +#define SPI_BUF14_V 0xFFFFFFFF +#define SPI_BUF14_S 0 + +#define SPI_W15_REG(i) (REG_SPI_BASE(i) + 0xBC) +/* SPI_BUF15 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: data buffer*/ +#define SPI_BUF15 0xFFFFFFFF +#define SPI_BUF15_M ((SPI_BUF15_V)<<(SPI_BUF15_S)) +#define SPI_BUF15_V 0xFFFFFFFF +#define SPI_BUF15_S 0 + +#define SPI_TX_CRC_REG(i) (REG_SPI_BASE(i) + 0xC0) +/* SPI_TX_CRC_DATA : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: For SPI1 the value of crc32 for 256 bits data.*/ +#define SPI_TX_CRC_DATA 0xFFFFFFFF +#define SPI_TX_CRC_DATA_M ((SPI_TX_CRC_DATA_V)<<(SPI_TX_CRC_DATA_S)) +#define SPI_TX_CRC_DATA_V 0xFFFFFFFF +#define SPI_TX_CRC_DATA_S 0 + +#define SPI_EXT0_REG(i) (REG_SPI_BASE(i) + 0xF0) +/* SPI_T_PP_ENA : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: page program delay enable.*/ +#define SPI_T_PP_ENA (BIT(31)) +#define SPI_T_PP_ENA_M (BIT(31)) +#define SPI_T_PP_ENA_V 0x1 +#define SPI_T_PP_ENA_S 31 +/* SPI_T_PP_SHIFT : R/W ;bitpos:[19:16] ;default: 4'd10 ; */ +/*description: page program delay time shift .*/ +#define SPI_T_PP_SHIFT 0x0000000F +#define SPI_T_PP_SHIFT_M ((SPI_T_PP_SHIFT_V)<<(SPI_T_PP_SHIFT_S)) +#define SPI_T_PP_SHIFT_V 0xF +#define SPI_T_PP_SHIFT_S 16 +/* SPI_T_PP_TIME : R/W ;bitpos:[11:0] ;default: 12'd80 ; */ +/*description: page program delay time by system clock.*/ +#define SPI_T_PP_TIME 0x00000FFF +#define SPI_T_PP_TIME_M ((SPI_T_PP_TIME_V)<<(SPI_T_PP_TIME_S)) +#define SPI_T_PP_TIME_V 0xFFF +#define SPI_T_PP_TIME_S 0 + +#define SPI_EXT1_REG(i) (REG_SPI_BASE(i) + 0xF4) +/* SPI_T_ERASE_ENA : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: erase flash delay enable.*/ +#define SPI_T_ERASE_ENA (BIT(31)) +#define SPI_T_ERASE_ENA_M (BIT(31)) +#define SPI_T_ERASE_ENA_V 0x1 +#define SPI_T_ERASE_ENA_S 31 +/* SPI_T_ERASE_SHIFT : R/W ;bitpos:[19:16] ;default: 4'd15 ; */ +/*description: erase flash delay time shift.*/ +#define SPI_T_ERASE_SHIFT 0x0000000F +#define SPI_T_ERASE_SHIFT_M ((SPI_T_ERASE_SHIFT_V)<<(SPI_T_ERASE_SHIFT_S)) +#define SPI_T_ERASE_SHIFT_V 0xF +#define SPI_T_ERASE_SHIFT_S 16 +/* SPI_T_ERASE_TIME : R/W ;bitpos:[11:0] ;default: 12'd0 ; */ +/*description: erase flash delay time by system clock.*/ +#define SPI_T_ERASE_TIME 0x00000FFF +#define SPI_T_ERASE_TIME_M ((SPI_T_ERASE_TIME_V)<<(SPI_T_ERASE_TIME_S)) +#define SPI_T_ERASE_TIME_V 0xFFF +#define SPI_T_ERASE_TIME_S 0 + +#define SPI_EXT2_REG(i) (REG_SPI_BASE(i) + 0xF8) +/* SPI_ST : RO ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: The status of spi state machine .*/ +#define SPI_ST 0x00000007 +#define SPI_ST_M ((SPI_ST_V)<<(SPI_ST_S)) +#define SPI_ST_V 0x7 +#define SPI_ST_S 0 + +#define SPI_EXT3_REG(i) (REG_SPI_BASE(i) + 0xFC) +/* SPI_INT_HOLD_ENA : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: This register is for two SPI masters to share the same cs clock + and data signals. The bits of one SPI are set if the other SPI is busy the SPI will be hold. 1(3): hold at ¡°idle¡± phase 2: hold at ¡°prepare¡± phase.*/ +#define SPI_INT_HOLD_ENA 0x00000003 +#define SPI_INT_HOLD_ENA_M ((SPI_INT_HOLD_ENA_V)<<(SPI_INT_HOLD_ENA_S)) +#define SPI_INT_HOLD_ENA_V 0x3 +#define SPI_INT_HOLD_ENA_S 0 + +#define SPI_DMA_CONF_REG(i) (REG_SPI_BASE(i) + 0x100) +/* SPI_DMA_CONTINUE : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: spi dma continue tx/rx data.*/ +#define SPI_DMA_CONTINUE (BIT(16)) +#define SPI_DMA_CONTINUE_M (BIT(16)) +#define SPI_DMA_CONTINUE_V 0x1 +#define SPI_DMA_CONTINUE_S 16 +/* SPI_DMA_TX_STOP : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: spi dma write data stop when in continue tx/rx mode.*/ +#define SPI_DMA_TX_STOP (BIT(15)) +#define SPI_DMA_TX_STOP_M (BIT(15)) +#define SPI_DMA_TX_STOP_V 0x1 +#define SPI_DMA_TX_STOP_S 15 +/* SPI_DMA_RX_STOP : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: spi dma read data stop when in continue tx/rx mode.*/ +#define SPI_DMA_RX_STOP (BIT(14)) +#define SPI_DMA_RX_STOP_M (BIT(14)) +#define SPI_DMA_RX_STOP_V 0x1 +#define SPI_DMA_RX_STOP_S 14 +/* SPI_OUT_DATA_BURST_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: spi dma read data from memory in burst mode.*/ +#define SPI_OUT_DATA_BURST_EN (BIT(12)) +#define SPI_OUT_DATA_BURST_EN_M (BIT(12)) +#define SPI_OUT_DATA_BURST_EN_V 0x1 +#define SPI_OUT_DATA_BURST_EN_S 12 +/* SPI_INDSCR_BURST_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: read descriptor use burst mode when write data to memory.*/ +#define SPI_INDSCR_BURST_EN (BIT(11)) +#define SPI_INDSCR_BURST_EN_M (BIT(11)) +#define SPI_INDSCR_BURST_EN_V 0x1 +#define SPI_INDSCR_BURST_EN_S 11 +/* SPI_OUTDSCR_BURST_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: read descriptor use burst mode when read data for memory.*/ +#define SPI_OUTDSCR_BURST_EN (BIT(10)) +#define SPI_OUTDSCR_BURST_EN_M (BIT(10)) +#define SPI_OUTDSCR_BURST_EN_V 0x1 +#define SPI_OUTDSCR_BURST_EN_S 10 +/* SPI_OUT_EOF_MODE : R/W ;bitpos:[9] ;default: 1'b1 ; */ +/*description: out eof flag generation mode . 1: when dma pop all data from + fifo 0:when ahb push all data to fifo.*/ +#define SPI_OUT_EOF_MODE (BIT(9)) +#define SPI_OUT_EOF_MODE_M (BIT(9)) +#define SPI_OUT_EOF_MODE_V 0x1 +#define SPI_OUT_EOF_MODE_S 9 +/* SPI_OUT_AUTO_WRBACK : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: when the link is empty jump to next automatically.*/ +#define SPI_OUT_AUTO_WRBACK (BIT(8)) +#define SPI_OUT_AUTO_WRBACK_M (BIT(8)) +#define SPI_OUT_AUTO_WRBACK_V 0x1 +#define SPI_OUT_AUTO_WRBACK_S 8 +/* SPI_OUT_LOOP_TEST : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set bit to test out link.*/ +#define SPI_OUT_LOOP_TEST (BIT(7)) +#define SPI_OUT_LOOP_TEST_M (BIT(7)) +#define SPI_OUT_LOOP_TEST_V 0x1 +#define SPI_OUT_LOOP_TEST_S 7 +/* SPI_IN_LOOP_TEST : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set bit to test in link.*/ +#define SPI_IN_LOOP_TEST (BIT(6)) +#define SPI_IN_LOOP_TEST_M (BIT(6)) +#define SPI_IN_LOOP_TEST_V 0x1 +#define SPI_IN_LOOP_TEST_S 6 +/* SPI_AHBM_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: reset spi dma ahb master.*/ +#define SPI_AHBM_RST (BIT(5)) +#define SPI_AHBM_RST_M (BIT(5)) +#define SPI_AHBM_RST_V 0x1 +#define SPI_AHBM_RST_S 5 +/* SPI_AHBM_FIFO_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: reset spi dma ahb master fifo pointer.*/ +#define SPI_AHBM_FIFO_RST (BIT(4)) +#define SPI_AHBM_FIFO_RST_M (BIT(4)) +#define SPI_AHBM_FIFO_RST_V 0x1 +#define SPI_AHBM_FIFO_RST_S 4 +/* SPI_OUT_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The bit is used to reset out dma fsm and out data fifo pointer.*/ +#define SPI_OUT_RST (BIT(3)) +#define SPI_OUT_RST_M (BIT(3)) +#define SPI_OUT_RST_V 0x1 +#define SPI_OUT_RST_S 3 +/* SPI_IN_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to reset in dma fsm and in data fifo pointer.*/ +#define SPI_IN_RST (BIT(2)) +#define SPI_IN_RST_M (BIT(2)) +#define SPI_IN_RST_V 0x1 +#define SPI_IN_RST_S 2 + +#define SPI_DMA_OUT_LINK_REG(i) (REG_SPI_BASE(i) + 0x104) +/* SPI_OUTLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Set the bit to mount on new outlink descriptors.*/ +#define SPI_OUTLINK_RESTART (BIT(30)) +#define SPI_OUTLINK_RESTART_M (BIT(30)) +#define SPI_OUTLINK_RESTART_V 0x1 +#define SPI_OUTLINK_RESTART_S 30 +/* SPI_OUTLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Set the bit to start to use outlink descriptor.*/ +#define SPI_OUTLINK_START (BIT(29)) +#define SPI_OUTLINK_START_M (BIT(29)) +#define SPI_OUTLINK_START_V 0x1 +#define SPI_OUTLINK_START_S 29 +/* SPI_OUTLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Set the bit to stop to use outlink descriptor.*/ +#define SPI_OUTLINK_STOP (BIT(28)) +#define SPI_OUTLINK_STOP_M (BIT(28)) +#define SPI_OUTLINK_STOP_V 0x1 +#define SPI_OUTLINK_STOP_S 28 +/* SPI_OUTLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The address of the first outlink descriptor.*/ +#define SPI_OUTLINK_ADDR 0x000FFFFF +#define SPI_OUTLINK_ADDR_M ((SPI_OUTLINK_ADDR_V)<<(SPI_OUTLINK_ADDR_S)) +#define SPI_OUTLINK_ADDR_V 0xFFFFF +#define SPI_OUTLINK_ADDR_S 0 + +#define SPI_DMA_IN_LINK_REG(i) (REG_SPI_BASE(i) + 0x108) +/* SPI_INLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Set the bit to mount on new inlink descriptors.*/ +#define SPI_INLINK_RESTART (BIT(30)) +#define SPI_INLINK_RESTART_M (BIT(30)) +#define SPI_INLINK_RESTART_V 0x1 +#define SPI_INLINK_RESTART_S 30 +/* SPI_INLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Set the bit to start to use inlink descriptor.*/ +#define SPI_INLINK_START (BIT(29)) +#define SPI_INLINK_START_M (BIT(29)) +#define SPI_INLINK_START_V 0x1 +#define SPI_INLINK_START_S 29 +/* SPI_INLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Set the bit to stop to use inlink descriptor.*/ +#define SPI_INLINK_STOP (BIT(28)) +#define SPI_INLINK_STOP_M (BIT(28)) +#define SPI_INLINK_STOP_V 0x1 +#define SPI_INLINK_STOP_S 28 +/* SPI_INLINK_AUTO_RET : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: when the bit is set inlink descriptor returns to the next descriptor + while a packet is wrong*/ +#define SPI_INLINK_AUTO_RET (BIT(20)) +#define SPI_INLINK_AUTO_RET_M (BIT(20)) +#define SPI_INLINK_AUTO_RET_V 0x1 +#define SPI_INLINK_AUTO_RET_S 20 +/* SPI_INLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The address of the first inlink descriptor.*/ +#define SPI_INLINK_ADDR 0x000FFFFF +#define SPI_INLINK_ADDR_M ((SPI_INLINK_ADDR_V)<<(SPI_INLINK_ADDR_S)) +#define SPI_INLINK_ADDR_V 0xFFFFF +#define SPI_INLINK_ADDR_S 0 + +#define SPI_DMA_STATUS_REG(i) (REG_SPI_BASE(i) + 0x10C) +/* SPI_DMA_TX_EN : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: spi dma write data status bit.*/ +#define SPI_DMA_TX_EN (BIT(1)) +#define SPI_DMA_TX_EN_M (BIT(1)) +#define SPI_DMA_TX_EN_V 0x1 +#define SPI_DMA_TX_EN_S 1 +/* SPI_DMA_RX_EN : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: spi dma read data status bit.*/ +#define SPI_DMA_RX_EN (BIT(0)) +#define SPI_DMA_RX_EN_M (BIT(0)) +#define SPI_DMA_RX_EN_V 0x1 +#define SPI_DMA_RX_EN_S 0 + +#define SPI_DMA_INT_ENA_REG(i) (REG_SPI_BASE(i) + 0x110) +/* SPI_OUT_TOTAL_EOF_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The enable bit for sending all the packets to host done.*/ +#define SPI_OUT_TOTAL_EOF_INT_ENA (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_ENA_M (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_ENA_V 0x1 +#define SPI_OUT_TOTAL_EOF_INT_ENA_S 8 +/* SPI_OUT_EOF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The enable bit for sending a packet to host done.*/ +#define SPI_OUT_EOF_INT_ENA (BIT(7)) +#define SPI_OUT_EOF_INT_ENA_M (BIT(7)) +#define SPI_OUT_EOF_INT_ENA_V 0x1 +#define SPI_OUT_EOF_INT_ENA_S 7 +/* SPI_OUT_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The enable bit for completing usage of a outlink descriptor .*/ +#define SPI_OUT_DONE_INT_ENA (BIT(6)) +#define SPI_OUT_DONE_INT_ENA_M (BIT(6)) +#define SPI_OUT_DONE_INT_ENA_V 0x1 +#define SPI_OUT_DONE_INT_ENA_S 6 +/* SPI_IN_SUC_EOF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The enable bit for completing receiving all the packets from host.*/ +#define SPI_IN_SUC_EOF_INT_ENA (BIT(5)) +#define SPI_IN_SUC_EOF_INT_ENA_M (BIT(5)) +#define SPI_IN_SUC_EOF_INT_ENA_V 0x1 +#define SPI_IN_SUC_EOF_INT_ENA_S 5 +/* SPI_IN_ERR_EOF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The enable bit for receiving error.*/ +#define SPI_IN_ERR_EOF_INT_ENA (BIT(4)) +#define SPI_IN_ERR_EOF_INT_ENA_M (BIT(4)) +#define SPI_IN_ERR_EOF_INT_ENA_V 0x1 +#define SPI_IN_ERR_EOF_INT_ENA_S 4 +/* SPI_IN_DONE_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The enable bit for completing usage of a inlink descriptor.*/ +#define SPI_IN_DONE_INT_ENA (BIT(3)) +#define SPI_IN_DONE_INT_ENA_M (BIT(3)) +#define SPI_IN_DONE_INT_ENA_V 0x1 +#define SPI_IN_DONE_INT_ENA_S 3 +/* SPI_INLINK_DSCR_ERROR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The enable bit for inlink descriptor error.*/ +#define SPI_INLINK_DSCR_ERROR_INT_ENA (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_ENA_M (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_ENA_V 0x1 +#define SPI_INLINK_DSCR_ERROR_INT_ENA_S 2 +/* SPI_OUTLINK_DSCR_ERROR_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The enable bit for outlink descriptor error.*/ +#define SPI_OUTLINK_DSCR_ERROR_INT_ENA (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_M (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_V 0x1 +#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_S 1 +/* SPI_INLINK_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The enable bit for lack of enough inlink descriptors.*/ +#define SPI_INLINK_DSCR_EMPTY_INT_ENA (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_ENA_M (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_ENA_V 0x1 +#define SPI_INLINK_DSCR_EMPTY_INT_ENA_S 0 + +#define SPI_DMA_INT_RAW_REG(i) (REG_SPI_BASE(i) + 0x114) +/* SPI_OUT_TOTAL_EOF_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The raw bit for sending all the packets to host done.*/ +#define SPI_OUT_TOTAL_EOF_INT_RAW (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_RAW_M (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_RAW_V 0x1 +#define SPI_OUT_TOTAL_EOF_INT_RAW_S 8 +/* SPI_OUT_EOF_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw bit for sending a packet to host done.*/ +#define SPI_OUT_EOF_INT_RAW (BIT(7)) +#define SPI_OUT_EOF_INT_RAW_M (BIT(7)) +#define SPI_OUT_EOF_INT_RAW_V 0x1 +#define SPI_OUT_EOF_INT_RAW_S 7 +/* SPI_OUT_DONE_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw bit for completing usage of a outlink descriptor.*/ +#define SPI_OUT_DONE_INT_RAW (BIT(6)) +#define SPI_OUT_DONE_INT_RAW_M (BIT(6)) +#define SPI_OUT_DONE_INT_RAW_V 0x1 +#define SPI_OUT_DONE_INT_RAW_S 6 +/* SPI_IN_SUC_EOF_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw bit for completing receiving all the packets from host.*/ +#define SPI_IN_SUC_EOF_INT_RAW (BIT(5)) +#define SPI_IN_SUC_EOF_INT_RAW_M (BIT(5)) +#define SPI_IN_SUC_EOF_INT_RAW_V 0x1 +#define SPI_IN_SUC_EOF_INT_RAW_S 5 +/* SPI_IN_ERR_EOF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw bit for receiving error.*/ +#define SPI_IN_ERR_EOF_INT_RAW (BIT(4)) +#define SPI_IN_ERR_EOF_INT_RAW_M (BIT(4)) +#define SPI_IN_ERR_EOF_INT_RAW_V 0x1 +#define SPI_IN_ERR_EOF_INT_RAW_S 4 +/* SPI_IN_DONE_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw bit for completing usage of a inlink descriptor.*/ +#define SPI_IN_DONE_INT_RAW (BIT(3)) +#define SPI_IN_DONE_INT_RAW_M (BIT(3)) +#define SPI_IN_DONE_INT_RAW_V 0x1 +#define SPI_IN_DONE_INT_RAW_S 3 +/* SPI_INLINK_DSCR_ERROR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw bit for inlink descriptor error.*/ +#define SPI_INLINK_DSCR_ERROR_INT_RAW (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_RAW_M (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_RAW_V 0x1 +#define SPI_INLINK_DSCR_ERROR_INT_RAW_S 2 +/* SPI_OUTLINK_DSCR_ERROR_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw bit for outlink descriptor error.*/ +#define SPI_OUTLINK_DSCR_ERROR_INT_RAW (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_M (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_V 0x1 +#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_S 1 +/* SPI_INLINK_DSCR_EMPTY_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw bit for lack of enough inlink descriptors.*/ +#define SPI_INLINK_DSCR_EMPTY_INT_RAW (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_RAW_M (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_RAW_V 0x1 +#define SPI_INLINK_DSCR_EMPTY_INT_RAW_S 0 + +#define SPI_DMA_INT_ST_REG(i) (REG_SPI_BASE(i) + 0x118) +/* SPI_OUT_TOTAL_EOF_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The status bit for sending all the packets to host done.*/ +#define SPI_OUT_TOTAL_EOF_INT_ST (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_ST_M (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_ST_V 0x1 +#define SPI_OUT_TOTAL_EOF_INT_ST_S 8 +/* SPI_OUT_EOF_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The status bit for sending a packet to host done.*/ +#define SPI_OUT_EOF_INT_ST (BIT(7)) +#define SPI_OUT_EOF_INT_ST_M (BIT(7)) +#define SPI_OUT_EOF_INT_ST_V 0x1 +#define SPI_OUT_EOF_INT_ST_S 7 +/* SPI_OUT_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The status bit for completing usage of a outlink descriptor.*/ +#define SPI_OUT_DONE_INT_ST (BIT(6)) +#define SPI_OUT_DONE_INT_ST_M (BIT(6)) +#define SPI_OUT_DONE_INT_ST_V 0x1 +#define SPI_OUT_DONE_INT_ST_S 6 +/* SPI_IN_SUC_EOF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The status bit for completing receiving all the packets from host.*/ +#define SPI_IN_SUC_EOF_INT_ST (BIT(5)) +#define SPI_IN_SUC_EOF_INT_ST_M (BIT(5)) +#define SPI_IN_SUC_EOF_INT_ST_V 0x1 +#define SPI_IN_SUC_EOF_INT_ST_S 5 +/* SPI_IN_ERR_EOF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The status bit for receiving error.*/ +#define SPI_IN_ERR_EOF_INT_ST (BIT(4)) +#define SPI_IN_ERR_EOF_INT_ST_M (BIT(4)) +#define SPI_IN_ERR_EOF_INT_ST_V 0x1 +#define SPI_IN_ERR_EOF_INT_ST_S 4 +/* SPI_IN_DONE_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The status bit for completing usage of a inlink descriptor.*/ +#define SPI_IN_DONE_INT_ST (BIT(3)) +#define SPI_IN_DONE_INT_ST_M (BIT(3)) +#define SPI_IN_DONE_INT_ST_V 0x1 +#define SPI_IN_DONE_INT_ST_S 3 +/* SPI_INLINK_DSCR_ERROR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The status bit for inlink descriptor error.*/ +#define SPI_INLINK_DSCR_ERROR_INT_ST (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_ST_M (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_ST_V 0x1 +#define SPI_INLINK_DSCR_ERROR_INT_ST_S 2 +/* SPI_OUTLINK_DSCR_ERROR_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The status bit for outlink descriptor error.*/ +#define SPI_OUTLINK_DSCR_ERROR_INT_ST (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_ST_M (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_ST_V 0x1 +#define SPI_OUTLINK_DSCR_ERROR_INT_ST_S 1 +/* SPI_INLINK_DSCR_EMPTY_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The status bit for lack of enough inlink descriptors.*/ +#define SPI_INLINK_DSCR_EMPTY_INT_ST (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_ST_M (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_ST_V 0x1 +#define SPI_INLINK_DSCR_EMPTY_INT_ST_S 0 + +#define SPI_DMA_INT_CLR_REG(i) (REG_SPI_BASE(i) + 0x11C) +/* SPI_OUT_TOTAL_EOF_INT_CLR : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The clear bit for sending all the packets to host done.*/ +#define SPI_OUT_TOTAL_EOF_INT_CLR (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_CLR_M (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_CLR_V 0x1 +#define SPI_OUT_TOTAL_EOF_INT_CLR_S 8 +/* SPI_OUT_EOF_INT_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The clear bit for sending a packet to host done.*/ +#define SPI_OUT_EOF_INT_CLR (BIT(7)) +#define SPI_OUT_EOF_INT_CLR_M (BIT(7)) +#define SPI_OUT_EOF_INT_CLR_V 0x1 +#define SPI_OUT_EOF_INT_CLR_S 7 +/* SPI_OUT_DONE_INT_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The clear bit for completing usage of a outlink descriptor.*/ +#define SPI_OUT_DONE_INT_CLR (BIT(6)) +#define SPI_OUT_DONE_INT_CLR_M (BIT(6)) +#define SPI_OUT_DONE_INT_CLR_V 0x1 +#define SPI_OUT_DONE_INT_CLR_S 6 +/* SPI_IN_SUC_EOF_INT_CLR : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The clear bit for completing receiving all the packets from host.*/ +#define SPI_IN_SUC_EOF_INT_CLR (BIT(5)) +#define SPI_IN_SUC_EOF_INT_CLR_M (BIT(5)) +#define SPI_IN_SUC_EOF_INT_CLR_V 0x1 +#define SPI_IN_SUC_EOF_INT_CLR_S 5 +/* SPI_IN_ERR_EOF_INT_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The clear bit for receiving error.*/ +#define SPI_IN_ERR_EOF_INT_CLR (BIT(4)) +#define SPI_IN_ERR_EOF_INT_CLR_M (BIT(4)) +#define SPI_IN_ERR_EOF_INT_CLR_V 0x1 +#define SPI_IN_ERR_EOF_INT_CLR_S 4 +/* SPI_IN_DONE_INT_CLR : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The clear bit for completing usage of a inlink descriptor.*/ +#define SPI_IN_DONE_INT_CLR (BIT(3)) +#define SPI_IN_DONE_INT_CLR_M (BIT(3)) +#define SPI_IN_DONE_INT_CLR_V 0x1 +#define SPI_IN_DONE_INT_CLR_S 3 +/* SPI_INLINK_DSCR_ERROR_INT_CLR : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The clear bit for inlink descriptor error.*/ +#define SPI_INLINK_DSCR_ERROR_INT_CLR (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_CLR_M (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_CLR_V 0x1 +#define SPI_INLINK_DSCR_ERROR_INT_CLR_S 2 +/* SPI_OUTLINK_DSCR_ERROR_INT_CLR : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The clear bit for outlink descriptor error.*/ +#define SPI_OUTLINK_DSCR_ERROR_INT_CLR (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_M (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_V 0x1 +#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_S 1 +/* SPI_INLINK_DSCR_EMPTY_INT_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The clear bit for lack of enough inlink descriptors.*/ +#define SPI_INLINK_DSCR_EMPTY_INT_CLR (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_CLR_M (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_CLR_V 0x1 +#define SPI_INLINK_DSCR_EMPTY_INT_CLR_S 0 + +#define SPI_IN_ERR_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x120) +/* SPI_DMA_IN_ERR_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The inlink descriptor address when spi dma produce receiving error.*/ +#define SPI_DMA_IN_ERR_EOF_DES_ADDR 0xFFFFFFFF +#define SPI_DMA_IN_ERR_EOF_DES_ADDR_M ((SPI_DMA_IN_ERR_EOF_DES_ADDR_V)<<(SPI_DMA_IN_ERR_EOF_DES_ADDR_S)) +#define SPI_DMA_IN_ERR_EOF_DES_ADDR_V 0xFFFFFFFF +#define SPI_DMA_IN_ERR_EOF_DES_ADDR_S 0 + +#define SPI_IN_SUC_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x124) +/* SPI_DMA_IN_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The last inlink descriptor address when spi dma produce from_suc_eof.*/ +#define SPI_DMA_IN_SUC_EOF_DES_ADDR 0xFFFFFFFF +#define SPI_DMA_IN_SUC_EOF_DES_ADDR_M ((SPI_DMA_IN_SUC_EOF_DES_ADDR_V)<<(SPI_DMA_IN_SUC_EOF_DES_ADDR_S)) +#define SPI_DMA_IN_SUC_EOF_DES_ADDR_V 0xFFFFFFFF +#define SPI_DMA_IN_SUC_EOF_DES_ADDR_S 0 + +#define SPI_INLINK_DSCR_REG(i) (REG_SPI_BASE(i) + 0x128) +/* SPI_DMA_INLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The content of current in descriptor pointer.*/ +#define SPI_DMA_INLINK_DSCR 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_M ((SPI_DMA_INLINK_DSCR_V)<<(SPI_DMA_INLINK_DSCR_S)) +#define SPI_DMA_INLINK_DSCR_V 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_S 0 + +#define SPI_INLINK_DSCR_BF0_REG(i) (REG_SPI_BASE(i) + 0x12C) +/* SPI_DMA_INLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The content of next in descriptor pointer.*/ +#define SPI_DMA_INLINK_DSCR_BF0 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_BF0_M ((SPI_DMA_INLINK_DSCR_BF0_V)<<(SPI_DMA_INLINK_DSCR_BF0_S)) +#define SPI_DMA_INLINK_DSCR_BF0_V 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_BF0_S 0 + +#define SPI_INLINK_DSCR_BF1_REG(i) (REG_SPI_BASE(i) + 0x130) +/* SPI_DMA_INLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The content of current in descriptor data buffer pointer.*/ +#define SPI_DMA_INLINK_DSCR_BF1 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_BF1_M ((SPI_DMA_INLINK_DSCR_BF1_V)<<(SPI_DMA_INLINK_DSCR_BF1_S)) +#define SPI_DMA_INLINK_DSCR_BF1_V 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_BF1_S 0 + +#define SPI_OUT_EOF_BFR_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x134) +/* SPI_DMA_OUT_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of buffer relative to the outlink descriptor that produce eof.*/ +#define SPI_DMA_OUT_EOF_BFR_DES_ADDR 0xFFFFFFFF +#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_M ((SPI_DMA_OUT_EOF_BFR_DES_ADDR_V)<<(SPI_DMA_OUT_EOF_BFR_DES_ADDR_S)) +#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_V 0xFFFFFFFF +#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_S 0 + +#define SPI_OUT_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x138) +/* SPI_DMA_OUT_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The last outlink descriptor address when spi dma produce to_eof.*/ +#define SPI_DMA_OUT_EOF_DES_ADDR 0xFFFFFFFF +#define SPI_DMA_OUT_EOF_DES_ADDR_M ((SPI_DMA_OUT_EOF_DES_ADDR_V)<<(SPI_DMA_OUT_EOF_DES_ADDR_S)) +#define SPI_DMA_OUT_EOF_DES_ADDR_V 0xFFFFFFFF +#define SPI_DMA_OUT_EOF_DES_ADDR_S 0 + +#define SPI_OUTLINK_DSCR_REG(i) (REG_SPI_BASE(i) + 0x13C) +/* SPI_DMA_OUTLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The content of current out descriptor pointer.*/ +#define SPI_DMA_OUTLINK_DSCR 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_M ((SPI_DMA_OUTLINK_DSCR_V)<<(SPI_DMA_OUTLINK_DSCR_S)) +#define SPI_DMA_OUTLINK_DSCR_V 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_S 0 + +#define SPI_OUTLINK_DSCR_BF0_REG(i) (REG_SPI_BASE(i) + 0x140) +/* SPI_DMA_OUTLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The content of next out descriptor pointer.*/ +#define SPI_DMA_OUTLINK_DSCR_BF0 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_BF0_M ((SPI_DMA_OUTLINK_DSCR_BF0_V)<<(SPI_DMA_OUTLINK_DSCR_BF0_S)) +#define SPI_DMA_OUTLINK_DSCR_BF0_V 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_BF0_S 0 + +#define SPI_OUTLINK_DSCR_BF1_REG(i) (REG_SPI_BASE(i) + 0x144) +/* SPI_DMA_OUTLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The content of current out descriptor data buffer pointer.*/ +#define SPI_DMA_OUTLINK_DSCR_BF1 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_BF1_M ((SPI_DMA_OUTLINK_DSCR_BF1_V)<<(SPI_DMA_OUTLINK_DSCR_BF1_S)) +#define SPI_DMA_OUTLINK_DSCR_BF1_V 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_BF1_S 0 + +#define SPI_DMA_RSTATUS_REG(i) (REG_SPI_BASE(i) + 0x148) +/* SPI_DMA_OUT_STATUS : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: spi dma read data from memory status.*/ +#define SPI_DMA_OUT_STATUS 0xFFFFFFFF +#define SPI_DMA_OUT_STATUS_M ((SPI_DMA_OUT_STATUS_V)<<(SPI_DMA_OUT_STATUS_S)) +#define SPI_DMA_OUT_STATUS_V 0xFFFFFFFF +#define SPI_DMA_OUT_STATUS_S 0 + +#define SPI_DMA_TSTATUS_REG(i) (REG_SPI_BASE(i) + 0x14C) +/* SPI_DMA_IN_STATUS : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: spi dma write data to memory status.*/ +#define SPI_DMA_IN_STATUS 0xFFFFFFFF +#define SPI_DMA_IN_STATUS_M ((SPI_DMA_IN_STATUS_V)<<(SPI_DMA_IN_STATUS_S)) +#define SPI_DMA_IN_STATUS_V 0xFFFFFFFF +#define SPI_DMA_IN_STATUS_S 0 + +#define SPI_DATE_REG(i) (REG_SPI_BASE(i) + 0x3FC) +/* SPI_DATE : RO ;bitpos:[27:0] ;default: 32'h1604270 ; */ +/*description: SPI register version.*/ +#define SPI_DATE 0x0FFFFFFF +#define SPI_DATE_M ((SPI_DATE_V)<<(SPI_DATE_S)) +#define SPI_DATE_V 0xFFFFFFF +#define SPI_DATE_S 0 + + + + +#endif /*__SPI_REG_H__ */ + + diff --git a/components/soc/esp32/include/soc/uart_reg.h b/components/soc/esp32/include/soc/uart_reg.h index 8cac4bb83..df614a88d 100644 --- a/components/soc/esp32/include/soc/uart_reg.h +++ b/components/soc/esp32/include/soc/uart_reg.h @@ -1,1167 +1,1167 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef __UART_REG_H__ -#define __UART_REG_H__ - - -#include "soc.h" - -#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ( i > 1 ? 0xe000 : 0 ) ) -#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ( i > 1 ? 0xe000 : 0 ) ) -#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) -#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0) - -/* UART_RXFIFO_RD_BYTE : RO ;bitpos:[7:0] ;default: 8'b0 ; */ -/*description: This register stores one byte data read by rx fifo.*/ -#define UART_RXFIFO_RD_BYTE 0x000000FF -#define UART_RXFIFO_RD_BYTE_M ((UART_RXFIFO_RD_BYTE_V)<<(UART_RXFIFO_RD_BYTE_S)) -#define UART_RXFIFO_RD_BYTE_V 0xFF -#define UART_RXFIFO_RD_BYTE_S 0 - -#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4) -/* UART_AT_CMD_CHAR_DET_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when receiver detects - the configured at_cmd chars.*/ -#define UART_AT_CMD_CHAR_DET_INT_RAW (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_RAW_M (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_RAW_V 0x1 -#define UART_AT_CMD_CHAR_DET_INT_RAW_S 18 -/* UART_RS485_CLASH_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when rs485 detects - the clash between transmitter and receiver.*/ -#define UART_RS485_CLASH_INT_RAW (BIT(17)) -#define UART_RS485_CLASH_INT_RAW_M (BIT(17)) -#define UART_RS485_CLASH_INT_RAW_V 0x1 -#define UART_RS485_CLASH_INT_RAW_S 17 -/* UART_RS485_FRM_ERR_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when rs485 detects - the data frame error.*/ -#define UART_RS485_FRM_ERR_INT_RAW (BIT(16)) -#define UART_RS485_FRM_ERR_INT_RAW_M (BIT(16)) -#define UART_RS485_FRM_ERR_INT_RAW_V 0x1 -#define UART_RS485_FRM_ERR_INT_RAW_S 16 -/* UART_RS485_PARITY_ERR_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when rs485 detects the parity error.*/ -#define UART_RS485_PARITY_ERR_INT_RAW (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_RAW_M (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_RAW_V 0x1 -#define UART_RS485_PARITY_ERR_INT_RAW_S 15 -/* UART_TX_DONE_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when transmitter has - send all the data in fifo.*/ -#define UART_TX_DONE_INT_RAW (BIT(14)) -#define UART_TX_DONE_INT_RAW_M (BIT(14)) -#define UART_TX_DONE_INT_RAW_V 0x1 -#define UART_TX_DONE_INT_RAW_S 14 -/* UART_TX_BRK_IDLE_DONE_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when transmitter has - kept the shortest duration after the last data has been send.*/ -#define UART_TX_BRK_IDLE_DONE_INT_RAW (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_RAW_M (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_RAW_V 0x1 -#define UART_TX_BRK_IDLE_DONE_INT_RAW_S 13 -/* UART_TX_BRK_DONE_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when transmitter completes - sendding 0 after all the datas in transmitter's fifo are send.*/ -#define UART_TX_BRK_DONE_INT_RAW (BIT(12)) -#define UART_TX_BRK_DONE_INT_RAW_M (BIT(12)) -#define UART_TX_BRK_DONE_INT_RAW_V 0x1 -#define UART_TX_BRK_DONE_INT_RAW_S 12 -/* UART_GLITCH_DET_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when receiver detects the start bit.*/ -#define UART_GLITCH_DET_INT_RAW (BIT(11)) -#define UART_GLITCH_DET_INT_RAW_M (BIT(11)) -#define UART_GLITCH_DET_INT_RAW_V 0x1 -#define UART_GLITCH_DET_INT_RAW_S 11 -/* UART_SW_XOFF_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when receiver receives - xon char with uart_sw_flow_con_en is set to 1.*/ -#define UART_SW_XOFF_INT_RAW (BIT(10)) -#define UART_SW_XOFF_INT_RAW_M (BIT(10)) -#define UART_SW_XOFF_INT_RAW_V 0x1 -#define UART_SW_XOFF_INT_RAW_S 10 -/* UART_SW_XON_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when receiver receives - xoff char with uart_sw_flow_con_en is set to 1.*/ -#define UART_SW_XON_INT_RAW (BIT(9)) -#define UART_SW_XON_INT_RAW_M (BIT(9)) -#define UART_SW_XON_INT_RAW_V 0x1 -#define UART_SW_XON_INT_RAW_S 9 -/* UART_RXFIFO_TOUT_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when receiver takes - more time than rx_tout_thrhd to receive a byte.*/ -#define UART_RXFIFO_TOUT_INT_RAW (BIT(8)) -#define UART_RXFIFO_TOUT_INT_RAW_M (BIT(8)) -#define UART_RXFIFO_TOUT_INT_RAW_V 0x1 -#define UART_RXFIFO_TOUT_INT_RAW_S 8 -/* UART_BRK_DET_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when receiver detects - the 0 after the stop bit.*/ -#define UART_BRK_DET_INT_RAW (BIT(7)) -#define UART_BRK_DET_INT_RAW_M (BIT(7)) -#define UART_BRK_DET_INT_RAW_V 0x1 -#define UART_BRK_DET_INT_RAW_S 7 -/* UART_CTS_CHG_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when receiver detects - the edge change of ctsn signal.*/ -#define UART_CTS_CHG_INT_RAW (BIT(6)) -#define UART_CTS_CHG_INT_RAW_M (BIT(6)) -#define UART_CTS_CHG_INT_RAW_V 0x1 -#define UART_CTS_CHG_INT_RAW_S 6 -/* UART_DSR_CHG_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when receiver detects - the edge change of dsrn signal.*/ -#define UART_DSR_CHG_INT_RAW (BIT(5)) -#define UART_DSR_CHG_INT_RAW_M (BIT(5)) -#define UART_DSR_CHG_INT_RAW_V 0x1 -#define UART_DSR_CHG_INT_RAW_S 5 -/* UART_RXFIFO_OVF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when receiver receives - more data than the fifo can store.*/ -#define UART_RXFIFO_OVF_INT_RAW (BIT(4)) -#define UART_RXFIFO_OVF_INT_RAW_M (BIT(4)) -#define UART_RXFIFO_OVF_INT_RAW_V 0x1 -#define UART_RXFIFO_OVF_INT_RAW_S 4 -/* UART_FRM_ERR_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when receiver detects - data's frame error .*/ -#define UART_FRM_ERR_INT_RAW (BIT(3)) -#define UART_FRM_ERR_INT_RAW_M (BIT(3)) -#define UART_FRM_ERR_INT_RAW_V 0x1 -#define UART_FRM_ERR_INT_RAW_S 3 -/* UART_PARITY_ERR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when receiver detects - the parity error of data.*/ -#define UART_PARITY_ERR_INT_RAW (BIT(2)) -#define UART_PARITY_ERR_INT_RAW_M (BIT(2)) -#define UART_PARITY_ERR_INT_RAW_V 0x1 -#define UART_PARITY_ERR_INT_RAW_S 2 -/* UART_TXFIFO_EMPTY_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when the amount of - data in transmitter's fifo is less than ((tx_mem_cnttxfifo_cnt) .*/ -#define UART_TXFIFO_EMPTY_INT_RAW (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_RAW_M (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_RAW_V 0x1 -#define UART_TXFIFO_EMPTY_INT_RAW_S 1 -/* UART_RXFIFO_FULL_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This interrupt raw bit turns to high level when receiver receives - more data than (rx_flow_thrhd_h3 rx_flow_thrhd).*/ -#define UART_RXFIFO_FULL_INT_RAW (BIT(0)) -#define UART_RXFIFO_FULL_INT_RAW_M (BIT(0)) -#define UART_RXFIFO_FULL_INT_RAW_V 0x1 -#define UART_RXFIFO_FULL_INT_RAW_S 0 - -#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8) -/* UART_AT_CMD_CHAR_DET_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena - is set to 1.*/ -#define UART_AT_CMD_CHAR_DET_INT_ST (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_ST_M (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_ST_V 0x1 -#define UART_AT_CMD_CHAR_DET_INT_ST_S 18 -/* UART_RS485_CLASH_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena - is set to 1.*/ -#define UART_RS485_CLASH_INT_ST (BIT(17)) -#define UART_RS485_CLASH_INT_ST_M (BIT(17)) -#define UART_RS485_CLASH_INT_ST_V 0x1 -#define UART_RS485_CLASH_INT_ST_S 17 -/* UART_RS485_FRM_ERR_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: This is the status bit for rs485_fm_err_int_raw when rs485_fm_err_int_ena - is set to 1.*/ -#define UART_RS485_FRM_ERR_INT_ST (BIT(16)) -#define UART_RS485_FRM_ERR_INT_ST_M (BIT(16)) -#define UART_RS485_FRM_ERR_INT_ST_V 0x1 -#define UART_RS485_FRM_ERR_INT_ST_S 16 -/* UART_RS485_PARITY_ERR_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena - is set to 1.*/ -#define UART_RS485_PARITY_ERR_INT_ST (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_ST_M (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_ST_V 0x1 -#define UART_RS485_PARITY_ERR_INT_ST_S 15 -/* UART_TX_DONE_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/ -#define UART_TX_DONE_INT_ST (BIT(14)) -#define UART_TX_DONE_INT_ST_M (BIT(14)) -#define UART_TX_DONE_INT_ST_V 0x1 -#define UART_TX_DONE_INT_ST_S 14 -/* UART_TX_BRK_IDLE_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena - is set to 1.*/ -#define UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_ST_M (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_ST_V 0x1 -#define UART_TX_BRK_IDLE_DONE_INT_ST_S 13 -/* UART_TX_BRK_DONE_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena - is set to 1.*/ -#define UART_TX_BRK_DONE_INT_ST (BIT(12)) -#define UART_TX_BRK_DONE_INT_ST_M (BIT(12)) -#define UART_TX_BRK_DONE_INT_ST_V 0x1 -#define UART_TX_BRK_DONE_INT_ST_S 12 -/* UART_GLITCH_DET_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: This is the status bit for glitch_det_int_raw when glitch_det_int_ena - is set to 1.*/ -#define UART_GLITCH_DET_INT_ST (BIT(11)) -#define UART_GLITCH_DET_INT_ST_M (BIT(11)) -#define UART_GLITCH_DET_INT_ST_V 0x1 -#define UART_GLITCH_DET_INT_ST_S 11 -/* UART_SW_XOFF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/ -#define UART_SW_XOFF_INT_ST (BIT(10)) -#define UART_SW_XOFF_INT_ST_M (BIT(10)) -#define UART_SW_XOFF_INT_ST_V 0x1 -#define UART_SW_XOFF_INT_ST_S 10 -/* UART_SW_XON_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/ -#define UART_SW_XON_INT_ST (BIT(9)) -#define UART_SW_XON_INT_ST_M (BIT(9)) -#define UART_SW_XON_INT_ST_V 0x1 -#define UART_SW_XON_INT_ST_S 9 -/* UART_RXFIFO_TOUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena - is set to 1.*/ -#define UART_RXFIFO_TOUT_INT_ST (BIT(8)) -#define UART_RXFIFO_TOUT_INT_ST_M (BIT(8)) -#define UART_RXFIFO_TOUT_INT_ST_V 0x1 -#define UART_RXFIFO_TOUT_INT_ST_S 8 -/* UART_BRK_DET_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/ -#define UART_BRK_DET_INT_ST (BIT(7)) -#define UART_BRK_DET_INT_ST_M (BIT(7)) -#define UART_BRK_DET_INT_ST_V 0x1 -#define UART_BRK_DET_INT_ST_S 7 -/* UART_CTS_CHG_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/ -#define UART_CTS_CHG_INT_ST (BIT(6)) -#define UART_CTS_CHG_INT_ST_M (BIT(6)) -#define UART_CTS_CHG_INT_ST_V 0x1 -#define UART_CTS_CHG_INT_ST_S 6 -/* UART_DSR_CHG_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/ -#define UART_DSR_CHG_INT_ST (BIT(5)) -#define UART_DSR_CHG_INT_ST_M (BIT(5)) -#define UART_DSR_CHG_INT_ST_V 0x1 -#define UART_DSR_CHG_INT_ST_S 5 -/* UART_RXFIFO_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena - is set to 1.*/ -#define UART_RXFIFO_OVF_INT_ST (BIT(4)) -#define UART_RXFIFO_OVF_INT_ST_M (BIT(4)) -#define UART_RXFIFO_OVF_INT_ST_V 0x1 -#define UART_RXFIFO_OVF_INT_ST_S 4 -/* UART_FRM_ERR_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This is the status bit for frm_err_int_raw when fm_err_int_ena is set to 1.*/ -#define UART_FRM_ERR_INT_ST (BIT(3)) -#define UART_FRM_ERR_INT_ST_M (BIT(3)) -#define UART_FRM_ERR_INT_ST_V 0x1 -#define UART_FRM_ERR_INT_ST_S 3 -/* UART_PARITY_ERR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the status bit for parity_err_int_raw when parity_err_int_ena - is set to 1.*/ -#define UART_PARITY_ERR_INT_ST (BIT(2)) -#define UART_PARITY_ERR_INT_ST_M (BIT(2)) -#define UART_PARITY_ERR_INT_ST_V 0x1 -#define UART_PARITY_ERR_INT_ST_S 2 -/* UART_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena - is set to 1.*/ -#define UART_TXFIFO_EMPTY_INT_ST (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_ST_M (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_ST_V 0x1 -#define UART_TXFIFO_EMPTY_INT_ST_S 1 -/* UART_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena - is set to 1.*/ -#define UART_RXFIFO_FULL_INT_ST (BIT(0)) -#define UART_RXFIFO_FULL_INT_ST_M (BIT(0)) -#define UART_RXFIFO_FULL_INT_ST_V 0x1 -#define UART_RXFIFO_FULL_INT_ST_S 0 - -#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xC) -/* UART_AT_CMD_CHAR_DET_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: This is the enable bit for at_cmd_char_det_int_st register.*/ -#define UART_AT_CMD_CHAR_DET_INT_ENA (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_ENA_M (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_ENA_V 0x1 -#define UART_AT_CMD_CHAR_DET_INT_ENA_S 18 -/* UART_RS485_CLASH_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: This is the enable bit for rs485_clash_int_st register.*/ -#define UART_RS485_CLASH_INT_ENA (BIT(17)) -#define UART_RS485_CLASH_INT_ENA_M (BIT(17)) -#define UART_RS485_CLASH_INT_ENA_V 0x1 -#define UART_RS485_CLASH_INT_ENA_S 17 -/* UART_RS485_FRM_ERR_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: This is the enable bit for rs485_parity_err_int_st register.*/ -#define UART_RS485_FRM_ERR_INT_ENA (BIT(16)) -#define UART_RS485_FRM_ERR_INT_ENA_M (BIT(16)) -#define UART_RS485_FRM_ERR_INT_ENA_V 0x1 -#define UART_RS485_FRM_ERR_INT_ENA_S 16 -/* UART_RS485_PARITY_ERR_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: This is the enable bit for rs485_parity_err_int_st register.*/ -#define UART_RS485_PARITY_ERR_INT_ENA (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_ENA_M (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_ENA_V 0x1 -#define UART_RS485_PARITY_ERR_INT_ENA_S 15 -/* UART_TX_DONE_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: This is the enable bit for tx_done_int_st register.*/ -#define UART_TX_DONE_INT_ENA (BIT(14)) -#define UART_TX_DONE_INT_ENA_M (BIT(14)) -#define UART_TX_DONE_INT_ENA_V 0x1 -#define UART_TX_DONE_INT_ENA_S 14 -/* UART_TX_BRK_IDLE_DONE_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: This is the enable bit for tx_brk_idle_done_int_st register.*/ -#define UART_TX_BRK_IDLE_DONE_INT_ENA (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_ENA_M (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_ENA_V 0x1 -#define UART_TX_BRK_IDLE_DONE_INT_ENA_S 13 -/* UART_TX_BRK_DONE_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: This is the enable bit for tx_brk_done_int_st register.*/ -#define UART_TX_BRK_DONE_INT_ENA (BIT(12)) -#define UART_TX_BRK_DONE_INT_ENA_M (BIT(12)) -#define UART_TX_BRK_DONE_INT_ENA_V 0x1 -#define UART_TX_BRK_DONE_INT_ENA_S 12 -/* UART_GLITCH_DET_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: This is the enable bit for glitch_det_int_st register.*/ -#define UART_GLITCH_DET_INT_ENA (BIT(11)) -#define UART_GLITCH_DET_INT_ENA_M (BIT(11)) -#define UART_GLITCH_DET_INT_ENA_V 0x1 -#define UART_GLITCH_DET_INT_ENA_S 11 -/* UART_SW_XOFF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: This is the enable bit for sw_xoff_int_st register.*/ -#define UART_SW_XOFF_INT_ENA (BIT(10)) -#define UART_SW_XOFF_INT_ENA_M (BIT(10)) -#define UART_SW_XOFF_INT_ENA_V 0x1 -#define UART_SW_XOFF_INT_ENA_S 10 -/* UART_SW_XON_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: This is the enable bit for sw_xon_int_st register.*/ -#define UART_SW_XON_INT_ENA (BIT(9)) -#define UART_SW_XON_INT_ENA_M (BIT(9)) -#define UART_SW_XON_INT_ENA_V 0x1 -#define UART_SW_XON_INT_ENA_S 9 -/* UART_RXFIFO_TOUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: This is the enable bit for rxfifo_tout_int_st register.*/ -#define UART_RXFIFO_TOUT_INT_ENA (BIT(8)) -#define UART_RXFIFO_TOUT_INT_ENA_M (BIT(8)) -#define UART_RXFIFO_TOUT_INT_ENA_V 0x1 -#define UART_RXFIFO_TOUT_INT_ENA_S 8 -/* UART_BRK_DET_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: This is the enable bit for brk_det_int_st register.*/ -#define UART_BRK_DET_INT_ENA (BIT(7)) -#define UART_BRK_DET_INT_ENA_M (BIT(7)) -#define UART_BRK_DET_INT_ENA_V 0x1 -#define UART_BRK_DET_INT_ENA_S 7 -/* UART_CTS_CHG_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: This is the enable bit for cts_chg_int_st register.*/ -#define UART_CTS_CHG_INT_ENA (BIT(6)) -#define UART_CTS_CHG_INT_ENA_M (BIT(6)) -#define UART_CTS_CHG_INT_ENA_V 0x1 -#define UART_CTS_CHG_INT_ENA_S 6 -/* UART_DSR_CHG_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This is the enable bit for dsr_chg_int_st register.*/ -#define UART_DSR_CHG_INT_ENA (BIT(5)) -#define UART_DSR_CHG_INT_ENA_M (BIT(5)) -#define UART_DSR_CHG_INT_ENA_V 0x1 -#define UART_DSR_CHG_INT_ENA_S 5 -/* UART_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This is the enable bit for rxfifo_ovf_int_st register.*/ -#define UART_RXFIFO_OVF_INT_ENA (BIT(4)) -#define UART_RXFIFO_OVF_INT_ENA_M (BIT(4)) -#define UART_RXFIFO_OVF_INT_ENA_V 0x1 -#define UART_RXFIFO_OVF_INT_ENA_S 4 -/* UART_FRM_ERR_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This is the enable bit for frm_err_int_st register.*/ -#define UART_FRM_ERR_INT_ENA (BIT(3)) -#define UART_FRM_ERR_INT_ENA_M (BIT(3)) -#define UART_FRM_ERR_INT_ENA_V 0x1 -#define UART_FRM_ERR_INT_ENA_S 3 -/* UART_PARITY_ERR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the enable bit for parity_err_int_st register.*/ -#define UART_PARITY_ERR_INT_ENA (BIT(2)) -#define UART_PARITY_ERR_INT_ENA_M (BIT(2)) -#define UART_PARITY_ERR_INT_ENA_V 0x1 -#define UART_PARITY_ERR_INT_ENA_S 2 -/* UART_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: This is the enable bit for rxfifo_full_int_st register.*/ -#define UART_TXFIFO_EMPTY_INT_ENA (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_ENA_M (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_ENA_V 0x1 -#define UART_TXFIFO_EMPTY_INT_ENA_S 1 -/* UART_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This is the enable bit for rxfifo_full_int_st register.*/ -#define UART_RXFIFO_FULL_INT_ENA (BIT(0)) -#define UART_RXFIFO_FULL_INT_ENA_M (BIT(0)) -#define UART_RXFIFO_FULL_INT_ENA_V 0x1 -#define UART_RXFIFO_FULL_INT_ENA_S 0 - -#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10) -/* UART_AT_CMD_CHAR_DET_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/ -#define UART_AT_CMD_CHAR_DET_INT_CLR (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_CLR_M (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_CLR_V 0x1 -#define UART_AT_CMD_CHAR_DET_INT_CLR_S 18 -/* UART_RS485_CLASH_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rs485_clash_int_raw interrupt.*/ -#define UART_RS485_CLASH_INT_CLR (BIT(17)) -#define UART_RS485_CLASH_INT_CLR_M (BIT(17)) -#define UART_RS485_CLASH_INT_CLR_V 0x1 -#define UART_RS485_CLASH_INT_CLR_S 17 -/* UART_RS485_FRM_ERR_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rs485_frm_err_int_raw interrupt.*/ -#define UART_RS485_FRM_ERR_INT_CLR (BIT(16)) -#define UART_RS485_FRM_ERR_INT_CLR_M (BIT(16)) -#define UART_RS485_FRM_ERR_INT_CLR_V 0x1 -#define UART_RS485_FRM_ERR_INT_CLR_S 16 -/* UART_RS485_PARITY_ERR_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rs485_parity_err_int_raw interrupt.*/ -#define UART_RS485_PARITY_ERR_INT_CLR (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_CLR_M (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_CLR_V 0x1 -#define UART_RS485_PARITY_ERR_INT_CLR_S 15 -/* UART_TX_DONE_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Set this bit to clear the tx_done_int_raw interrupt.*/ -#define UART_TX_DONE_INT_CLR (BIT(14)) -#define UART_TX_DONE_INT_CLR_M (BIT(14)) -#define UART_TX_DONE_INT_CLR_V 0x1 -#define UART_TX_DONE_INT_CLR_S 14 -/* UART_TX_BRK_IDLE_DONE_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/ -#define UART_TX_BRK_IDLE_DONE_INT_CLR (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_CLR_M (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_CLR_V 0x1 -#define UART_TX_BRK_IDLE_DONE_INT_CLR_S 13 -/* UART_TX_BRK_DONE_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to clear the tx_brk_done_int_raw interrupt..*/ -#define UART_TX_BRK_DONE_INT_CLR (BIT(12)) -#define UART_TX_BRK_DONE_INT_CLR_M (BIT(12)) -#define UART_TX_BRK_DONE_INT_CLR_V 0x1 -#define UART_TX_BRK_DONE_INT_CLR_S 12 -/* UART_GLITCH_DET_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Set this bit to clear the glitch_det_int_raw interrupt.*/ -#define UART_GLITCH_DET_INT_CLR (BIT(11)) -#define UART_GLITCH_DET_INT_CLR_M (BIT(11)) -#define UART_GLITCH_DET_INT_CLR_V 0x1 -#define UART_GLITCH_DET_INT_CLR_S 11 -/* UART_SW_XOFF_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit to clear the sw_xon_int_raw interrupt.*/ -#define UART_SW_XOFF_INT_CLR (BIT(10)) -#define UART_SW_XOFF_INT_CLR_M (BIT(10)) -#define UART_SW_XOFF_INT_CLR_V 0x1 -#define UART_SW_XOFF_INT_CLR_S 10 -/* UART_SW_XON_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to clear the sw_xon_int_raw interrupt.*/ -#define UART_SW_XON_INT_CLR (BIT(9)) -#define UART_SW_XON_INT_CLR_M (BIT(9)) -#define UART_SW_XON_INT_CLR_V 0x1 -#define UART_SW_XON_INT_CLR_S 9 -/* UART_RXFIFO_TOUT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rxfifo_tout_int_raw interrupt.*/ -#define UART_RXFIFO_TOUT_INT_CLR (BIT(8)) -#define UART_RXFIFO_TOUT_INT_CLR_M (BIT(8)) -#define UART_RXFIFO_TOUT_INT_CLR_V 0x1 -#define UART_RXFIFO_TOUT_INT_CLR_S 8 -/* UART_BRK_DET_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to clear the brk_det_int_raw interrupt.*/ -#define UART_BRK_DET_INT_CLR (BIT(7)) -#define UART_BRK_DET_INT_CLR_M (BIT(7)) -#define UART_BRK_DET_INT_CLR_V 0x1 -#define UART_BRK_DET_INT_CLR_S 7 -/* UART_CTS_CHG_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to clear the cts_chg_int_raw interrupt.*/ -#define UART_CTS_CHG_INT_CLR (BIT(6)) -#define UART_CTS_CHG_INT_CLR_M (BIT(6)) -#define UART_CTS_CHG_INT_CLR_V 0x1 -#define UART_CTS_CHG_INT_CLR_S 6 -/* UART_DSR_CHG_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to clear the dsr_chg_int_raw interrupt.*/ -#define UART_DSR_CHG_INT_CLR (BIT(5)) -#define UART_DSR_CHG_INT_CLR_M (BIT(5)) -#define UART_DSR_CHG_INT_CLR_V 0x1 -#define UART_DSR_CHG_INT_CLR_S 5 -/* UART_RXFIFO_OVF_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to clear rxfifo_ovf_int_raw interrupt.*/ -#define UART_RXFIFO_OVF_INT_CLR (BIT(4)) -#define UART_RXFIFO_OVF_INT_CLR_M (BIT(4)) -#define UART_RXFIFO_OVF_INT_CLR_V 0x1 -#define UART_RXFIFO_OVF_INT_CLR_S 4 -/* UART_FRM_ERR_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to clear frm_err_int_raw interrupt.*/ -#define UART_FRM_ERR_INT_CLR (BIT(3)) -#define UART_FRM_ERR_INT_CLR_M (BIT(3)) -#define UART_FRM_ERR_INT_CLR_V 0x1 -#define UART_FRM_ERR_INT_CLR_S 3 -/* UART_PARITY_ERR_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to clear parity_err_int_raw interrupt.*/ -#define UART_PARITY_ERR_INT_CLR (BIT(2)) -#define UART_PARITY_ERR_INT_CLR_M (BIT(2)) -#define UART_PARITY_ERR_INT_CLR_V 0x1 -#define UART_PARITY_ERR_INT_CLR_S 2 -/* UART_TXFIFO_EMPTY_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to clear txfifo_empty_int_raw interrupt.*/ -#define UART_TXFIFO_EMPTY_INT_CLR (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_CLR_M (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_CLR_V 0x1 -#define UART_TXFIFO_EMPTY_INT_CLR_S 1 -/* UART_RXFIFO_FULL_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rxfifo_full_int_raw interrupt.*/ -#define UART_RXFIFO_FULL_INT_CLR (BIT(0)) -#define UART_RXFIFO_FULL_INT_CLR_M (BIT(0)) -#define UART_RXFIFO_FULL_INT_CLR_V 0x1 -#define UART_RXFIFO_FULL_INT_CLR_S 0 - -#define UART_CLKDIV_REG(i) (REG_UART_BASE(i) + 0x14) -/* UART_CLKDIV_FRAG : R/W ;bitpos:[23:20] ;default: 4'h0 ; */ -/*description: The register value is the decimal part of the frequency divider's factor.*/ -#define UART_CLKDIV_FRAG 0x0000000F -#define UART_CLKDIV_FRAG_M ((UART_CLKDIV_FRAG_V)<<(UART_CLKDIV_FRAG_S)) -#define UART_CLKDIV_FRAG_V 0xF -#define UART_CLKDIV_FRAG_S 20 -/* UART_CLKDIV : R/W ;bitpos:[19:0] ;default: 20'h2B6 ; */ -/*description: The register value is the integer part of the frequency divider's factor.*/ -#define UART_CLKDIV 0x000FFFFF -#define UART_CLKDIV_M ((UART_CLKDIV_V)<<(UART_CLKDIV_S)) -#define UART_CLKDIV_V 0xFFFFF -#define UART_CLKDIV_S 0 - -#define UART_AUTOBAUD_REG(i) (REG_UART_BASE(i) + 0x18) -/* UART_GLITCH_FILT : R/W ;bitpos:[15:8] ;default: 8'h10 ; */ -/*description: when input pulse width is lower then this value igore this pulse.this - register is used in autobaud detect process.*/ -#define UART_GLITCH_FILT 0x000000FF -#define UART_GLITCH_FILT_M ((UART_GLITCH_FILT_V)<<(UART_GLITCH_FILT_S)) -#define UART_GLITCH_FILT_V 0xFF -#define UART_GLITCH_FILT_S 8 -/* UART_AUTOBAUD_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This is the enable bit for detecting baudrate.*/ -#define UART_AUTOBAUD_EN (BIT(0)) -#define UART_AUTOBAUD_EN_M (BIT(0)) -#define UART_AUTOBAUD_EN_V 0x1 -#define UART_AUTOBAUD_EN_S 0 - -#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1C) -/* UART_TXD : RO ;bitpos:[31] ;default: 8'h0 ; */ -/*description: This register represent the level value of the internal uart rxd signal.*/ -#define UART_TXD (BIT(31)) -#define UART_TXD_M (BIT(31)) -#define UART_TXD_V 0x1 -#define UART_TXD_S 31 -/* UART_RTSN : RO ;bitpos:[30] ;default: 1'b0 ; */ -/*description: This register represent the level value of the internal uart cts signal.*/ -#define UART_RTSN (BIT(30)) -#define UART_RTSN_M (BIT(30)) -#define UART_RTSN_V 0x1 -#define UART_RTSN_S 30 -/* UART_DTRN : RO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: The register represent the level value of the internal uart dsr signal.*/ -#define UART_DTRN (BIT(29)) -#define UART_DTRN_M (BIT(29)) -#define UART_DTRN_V 0x1 -#define UART_DTRN_S 29 -/* UART_ST_UTX_OUT : RO ;bitpos:[27:24] ;default: 4'b0 ; */ -/*description: This register stores the value of transmitter's finite state - machine. 0:TX_IDLE 1:TX_STRT 2:TX_DAT0 3:TX_DAT1 4:TX_DAT2 5:TX_DAT3 6:TX_DAT4 7:TX_DAT5 8:TX_DAT6 9:TX_DAT7 10:TX_PRTY 11:TX_STP1 12:TX_STP2 13:TX_DL0 14:TX_DL1*/ -#define UART_ST_UTX_OUT 0x0000000F -#define UART_ST_UTX_OUT_M ((UART_ST_UTX_OUT_V)<<(UART_ST_UTX_OUT_S)) -#define UART_ST_UTX_OUT_V 0xF -#define UART_ST_UTX_OUT_S 24 -/* UART_TXFIFO_CNT : RO ;bitpos:[23:16] ;default: 8'b0 ; */ -/*description: (tx_mem_cnt txfifo_cnt) stores the byte num of valid datas in - transmitter's fifo.tx_mem_cnt stores the 3 most significant bits txfifo_cnt stores the 8 least significant bits.*/ -#define UART_TXFIFO_CNT 0x000000FF -#define UART_TXFIFO_CNT_M ((UART_TXFIFO_CNT_V)<<(UART_TXFIFO_CNT_S)) -#define UART_TXFIFO_CNT_V 0xFF -#define UART_TXFIFO_CNT_S 16 -/* UART_RXD : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: This register stores the level value of the internal uart rxd signal.*/ -#define UART_RXD (BIT(15)) -#define UART_RXD_M (BIT(15)) -#define UART_RXD_V 0x1 -#define UART_RXD_S 15 -/* UART_CTSN : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: This register stores the level value of the internal uart cts signal.*/ -#define UART_CTSN (BIT(14)) -#define UART_CTSN_M (BIT(14)) -#define UART_CTSN_V 0x1 -#define UART_CTSN_S 14 -/* UART_DSRN : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: This register stores the level value of the internal uart dsr signal.*/ -#define UART_DSRN (BIT(13)) -#define UART_DSRN_M (BIT(13)) -#define UART_DSRN_V 0x1 -#define UART_DSRN_S 13 -/* UART_ST_URX_OUT : RO ;bitpos:[11:8] ;default: 4'b0 ; */ -/*description: This register stores the value of receiver's finite state machine. - 0:RX_IDLE 1:RX_STRT 2:RX_DAT0 3:RX_DAT1 4:RX_DAT2 5:RX_DAT3 6:RX_DAT4 7:RX_DAT5 8:RX_DAT6 9:RX_DAT7 10:RX_PRTY 11:RX_STP1 12:RX_STP2 13:RX_DL1*/ -#define UART_ST_URX_OUT 0x0000000F -#define UART_ST_URX_OUT_M ((UART_ST_URX_OUT_V)<<(UART_ST_URX_OUT_S)) -#define UART_ST_URX_OUT_V 0xF -#define UART_ST_URX_OUT_S 8 -/* UART_RXFIFO_CNT : RO ;bitpos:[7:0] ;default: 8'b0 ; */ -/*description: (rx_mem_cnt rxfifo_cnt) stores the byte num of valid datas in - receiver's fifo. rx_mem_cnt register stores the 3 most significant bits rxfifo_cnt stores the 8 least significant bits.*/ -#define UART_RXFIFO_CNT 0x000000FF -#define UART_RXFIFO_CNT_M ((UART_RXFIFO_CNT_V)<<(UART_RXFIFO_CNT_S)) -#define UART_RXFIFO_CNT_V 0xFF -#define UART_RXFIFO_CNT_S 0 - -#define UART_CONF0_REG(i) (REG_UART_BASE(i) + 0x20) -/* UART_TICK_REF_ALWAYS_ON : R/W ;bitpos:[27] ;default: 1'b1 ; */ -/*description: This register is used to select the clock.1.apb clock 0:ref_tick*/ -#define UART_TICK_REF_ALWAYS_ON (BIT(27)) -#define UART_TICK_REF_ALWAYS_ON_M (BIT(27)) -#define UART_TICK_REF_ALWAYS_ON_V 0x1 -#define UART_TICK_REF_ALWAYS_ON_S 27 -/* UART_ERR_WR_MASK : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: 1.receiver stops storing data int fifo when data is wrong. - 0.receiver stores the data even if the received data is wrong.*/ -#define UART_ERR_WR_MASK (BIT(26)) -#define UART_ERR_WR_MASK_M (BIT(26)) -#define UART_ERR_WR_MASK_V 0x1 -#define UART_ERR_WR_MASK_S 26 -/* UART_CLK_EN : R/W ;bitpos:[25] ;default: 1'h0 ; */ -/*description: 1.force clock on for registers.support clock only when write registers*/ -#define UART_CLK_EN (BIT(25)) -#define UART_CLK_EN_M (BIT(25)) -#define UART_CLK_EN_V 0x1 -#define UART_CLK_EN_S 25 -/* UART_DTR_INV : R/W ;bitpos:[24] ;default: 1'h0 ; */ -/*description: Set this bit to inverse the level value of uart dtr signal.*/ -#define UART_DTR_INV (BIT(24)) -#define UART_DTR_INV_M (BIT(24)) -#define UART_DTR_INV_V 0x1 -#define UART_DTR_INV_S 24 -/* UART_RTS_INV : R/W ;bitpos:[23] ;default: 1'h0 ; */ -/*description: Set this bit to inverse the level value of uart rts signal.*/ -#define UART_RTS_INV (BIT(23)) -#define UART_RTS_INV_M (BIT(23)) -#define UART_RTS_INV_V 0x1 -#define UART_RTS_INV_S 23 -/* UART_TXD_INV : R/W ;bitpos:[22] ;default: 1'h0 ; */ -/*description: Set this bit to inverse the level value of uart txd signal.*/ -#define UART_TXD_INV (BIT(22)) -#define UART_TXD_INV_M (BIT(22)) -#define UART_TXD_INV_V 0x1 -#define UART_TXD_INV_S 22 -/* UART_DSR_INV : R/W ;bitpos:[21] ;default: 1'h0 ; */ -/*description: Set this bit to inverse the level value of uart dsr signal.*/ -#define UART_DSR_INV (BIT(21)) -#define UART_DSR_INV_M (BIT(21)) -#define UART_DSR_INV_V 0x1 -#define UART_DSR_INV_S 21 -/* UART_CTS_INV : R/W ;bitpos:[20] ;default: 1'h0 ; */ -/*description: Set this bit to inverse the level value of uart cts signal.*/ -#define UART_CTS_INV (BIT(20)) -#define UART_CTS_INV_M (BIT(20)) -#define UART_CTS_INV_V 0x1 -#define UART_CTS_INV_S 20 -/* UART_RXD_INV : R/W ;bitpos:[19] ;default: 1'h0 ; */ -/*description: Set this bit to inverse the level value of uart rxd signal.*/ -#define UART_RXD_INV (BIT(19)) -#define UART_RXD_INV_M (BIT(19)) -#define UART_RXD_INV_V 0x1 -#define UART_RXD_INV_S 19 -/* UART_TXFIFO_RST : R/W ;bitpos:[18] ;default: 1'h0 ; */ -/*description: Set this bit to reset uart transmitter's fifo.*/ -#define UART_TXFIFO_RST (BIT(18)) -#define UART_TXFIFO_RST_M (BIT(18)) -#define UART_TXFIFO_RST_V 0x1 -#define UART_TXFIFO_RST_S 18 -/* UART_RXFIFO_RST : R/W ;bitpos:[17] ;default: 1'h0 ; */ -/*description: Set this bit to reset uart receiver's fifo.*/ -#define UART_RXFIFO_RST (BIT(17)) -#define UART_RXFIFO_RST_M (BIT(17)) -#define UART_RXFIFO_RST_V 0x1 -#define UART_RXFIFO_RST_S 17 -/* UART_IRDA_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */ -/*description: Set this bit to enable irda protocol.*/ -#define UART_IRDA_EN (BIT(16)) -#define UART_IRDA_EN_M (BIT(16)) -#define UART_IRDA_EN_V 0x1 -#define UART_IRDA_EN_S 16 -/* UART_TX_FLOW_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: Set this bit to enable transmitter's flow control function.*/ -#define UART_TX_FLOW_EN (BIT(15)) -#define UART_TX_FLOW_EN_M (BIT(15)) -#define UART_TX_FLOW_EN_V 0x1 -#define UART_TX_FLOW_EN_S 15 -/* UART_LOOPBACK : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Set this bit to enable uart loopback test mode.*/ -#define UART_LOOPBACK (BIT(14)) -#define UART_LOOPBACK_M (BIT(14)) -#define UART_LOOPBACK_V 0x1 -#define UART_LOOPBACK_S 14 -/* UART_IRDA_RX_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Set this bit to inverse the level value of irda receiver's level.*/ -#define UART_IRDA_RX_INV (BIT(13)) -#define UART_IRDA_RX_INV_M (BIT(13)) -#define UART_IRDA_RX_INV_V 0x1 -#define UART_IRDA_RX_INV_S 13 -/* UART_IRDA_TX_INV : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to inverse the level value of irda transmitter's level.*/ -#define UART_IRDA_TX_INV (BIT(12)) -#define UART_IRDA_TX_INV_M (BIT(12)) -#define UART_IRDA_TX_INV_V 0x1 -#define UART_IRDA_TX_INV_S 12 -/* UART_IRDA_WCTL : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: 1.the irda transmitter's 11th bit is the same to the 10th bit. - 0.set irda transmitter's 11th bit to 0.*/ -#define UART_IRDA_WCTL (BIT(11)) -#define UART_IRDA_WCTL_M (BIT(11)) -#define UART_IRDA_WCTL_V 0x1 -#define UART_IRDA_WCTL_S 11 -/* UART_IRDA_TX_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: This is the start enable bit for irda transmitter.*/ -#define UART_IRDA_TX_EN (BIT(10)) -#define UART_IRDA_TX_EN_M (BIT(10)) -#define UART_IRDA_TX_EN_V 0x1 -#define UART_IRDA_TX_EN_S 10 -/* UART_IRDA_DPLX : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to enable irda loopback mode.*/ -#define UART_IRDA_DPLX (BIT(9)) -#define UART_IRDA_DPLX_M (BIT(9)) -#define UART_IRDA_DPLX_V 0x1 -#define UART_IRDA_DPLX_S 9 -/* UART_TXD_BRK : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to enbale transmitter to send 0 when the process - of sending data is done.*/ -#define UART_TXD_BRK (BIT(8)) -#define UART_TXD_BRK_M (BIT(8)) -#define UART_TXD_BRK_V 0x1 -#define UART_TXD_BRK_S 8 -/* UART_SW_DTR : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: This register is used to configure the software dtr signal which - is used in software flow control..*/ -#define UART_SW_DTR (BIT(7)) -#define UART_SW_DTR_M (BIT(7)) -#define UART_SW_DTR_V 0x1 -#define UART_SW_DTR_S 7 -/* UART_SW_RTS : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: This register is used to configure the software rts signal which - is used in software flow control.*/ -#define UART_SW_RTS (BIT(6)) -#define UART_SW_RTS_M (BIT(6)) -#define UART_SW_RTS_V 0x1 -#define UART_SW_RTS_S 6 -/* UART_STOP_BIT_NUM : R/W ;bitpos:[5:4] ;default: 2'd1 ; */ -/*description: This register is used to set the length of stop bit. 1:1bit 2:1.5bits 3:2bits*/ -#define UART_STOP_BIT_NUM 0x00000003 -#define UART_STOP_BIT_NUM_M ((UART_STOP_BIT_NUM_V)<<(UART_STOP_BIT_NUM_S)) -#define UART_STOP_BIT_NUM_V 0x3 -#define UART_STOP_BIT_NUM_S 4 -/* UART_BIT_NUM : R/W ;bitpos:[3:2] ;default: 2'd3 ; */ -/*description: This registe is used to set the length of data: 0:5bits 1:6bits 2:7bits 3:8bits*/ -#define UART_BIT_NUM 0x00000003 -#define UART_BIT_NUM_M ((UART_BIT_NUM_V)<<(UART_BIT_NUM_S)) -#define UART_BIT_NUM_V 0x3 -#define UART_BIT_NUM_S 2 -/* UART_PARITY_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to enable uart parity check.*/ -#define UART_PARITY_EN (BIT(1)) -#define UART_PARITY_EN_M (BIT(1)) -#define UART_PARITY_EN_V 0x1 -#define UART_PARITY_EN_S 1 -/* UART_PARITY : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This register is used to configure the parity check mode. 0:even 1:odd*/ -#define UART_PARITY (BIT(0)) -#define UART_PARITY_M (BIT(0)) -#define UART_PARITY_V 0x1 -#define UART_PARITY_S 0 - -#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24) -/* UART_RX_TOUT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: This is the enble bit for uart receiver's timeout function.*/ -#define UART_RX_TOUT_EN (BIT(31)) -#define UART_RX_TOUT_EN_M (BIT(31)) -#define UART_RX_TOUT_EN_V 0x1 -#define UART_RX_TOUT_EN_S 31 -/* UART_RX_TOUT_THRHD : R/W ;bitpos:[30:24] ;default: 7'b0 ; */ -/*description: This register is used to configure the timeout value for uart - receiver receiving a byte.*/ -#define UART_RX_TOUT_THRHD 0x0000007F -#define UART_RX_TOUT_THRHD_M ((UART_RX_TOUT_THRHD_V)<<(UART_RX_TOUT_THRHD_S)) -#define UART_RX_TOUT_THRHD_V 0x7F -#define UART_RX_TOUT_THRHD_S 24 -/* UART_RX_FLOW_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: This is the flow enable bit for uart receiver. 1:choose software - flow control with configuring sw_rts signal*/ -#define UART_RX_FLOW_EN (BIT(23)) -#define UART_RX_FLOW_EN_M (BIT(23)) -#define UART_RX_FLOW_EN_V 0x1 -#define UART_RX_FLOW_EN_S 23 -/* UART_RX_FLOW_THRHD : R/W ;bitpos:[22:16] ;default: 7'h0 ; */ -/*description: when receiver receives more data than its threshold value. - receiver produce signal to tell the transmitter stop transferring data. the threshold value is (rx_flow_thrhd_h3 rx_flow_thrhd).*/ -#define UART_RX_FLOW_THRHD 0x0000007F -#define UART_RX_FLOW_THRHD_M ((UART_RX_FLOW_THRHD_V)<<(UART_RX_FLOW_THRHD_S)) -#define UART_RX_FLOW_THRHD_V 0x7F -#define UART_RX_FLOW_THRHD_S 16 -/* UART_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[14:8] ;default: 7'h60 ; */ -/*description: when the data amount in transmitter fifo is less than its threshold - value. it will produce txfifo_empty_int_raw interrupt. the threshold value is (tx_mem_empty_thrhd txfifo_empty_thrhd)*/ -#define UART_TXFIFO_EMPTY_THRHD 0x0000007F -#define UART_TXFIFO_EMPTY_THRHD_M ((UART_TXFIFO_EMPTY_THRHD_V)<<(UART_TXFIFO_EMPTY_THRHD_S)) -#define UART_TXFIFO_EMPTY_THRHD_V 0x7F -#define UART_TXFIFO_EMPTY_THRHD_S 8 -/* UART_RXFIFO_FULL_THRHD : R/W ;bitpos:[6:0] ;default: 7'h60 ; */ -/*description: When receiver receives more data than its threshold value.receiver - will produce rxfifo_full_int_raw interrupt.the threshold value is (rx_flow_thrhd_h3 rxfifo_full_thrhd).*/ -#define UART_RXFIFO_FULL_THRHD 0x0000007F -#define UART_RXFIFO_FULL_THRHD_M ((UART_RXFIFO_FULL_THRHD_V)<<(UART_RXFIFO_FULL_THRHD_S)) -#define UART_RXFIFO_FULL_THRHD_V 0x7F -#define UART_RXFIFO_FULL_THRHD_S 0 - -#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x28) -/* UART_LOWPULSE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */ -/*description: This register stores the value of the minimum duration time for - the low level pulse. it is used in baudrate-detect process.*/ -#define UART_LOWPULSE_MIN_CNT 0x000FFFFF -#define UART_LOWPULSE_MIN_CNT_M ((UART_LOWPULSE_MIN_CNT_V)<<(UART_LOWPULSE_MIN_CNT_S)) -#define UART_LOWPULSE_MIN_CNT_V 0xFFFFF -#define UART_LOWPULSE_MIN_CNT_S 0 - -#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x2C) -/* UART_HIGHPULSE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */ -/*description: This register stores the value of the maxinum duration time - for the high level pulse. it is used in baudrate-detect process.*/ -#define UART_HIGHPULSE_MIN_CNT 0x000FFFFF -#define UART_HIGHPULSE_MIN_CNT_M ((UART_HIGHPULSE_MIN_CNT_V)<<(UART_HIGHPULSE_MIN_CNT_S)) -#define UART_HIGHPULSE_MIN_CNT_V 0xFFFFF -#define UART_HIGHPULSE_MIN_CNT_S 0 - -#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x30) -/* UART_RXD_EDGE_CNT : RO ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register stores the count of rxd edge change. it is used - in baudrate-detect process.*/ -#define UART_RXD_EDGE_CNT 0x000003FF -#define UART_RXD_EDGE_CNT_M ((UART_RXD_EDGE_CNT_V)<<(UART_RXD_EDGE_CNT_S)) -#define UART_RXD_EDGE_CNT_V 0x3FF -#define UART_RXD_EDGE_CNT_S 0 - -#define UART_FLOW_CONF_REG(i) (REG_UART_BASE(i) + 0x34) -/* UART_SEND_XOFF : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to send xoff char. it is cleared by hardware automatically.*/ -#define UART_SEND_XOFF (BIT(5)) -#define UART_SEND_XOFF_M (BIT(5)) -#define UART_SEND_XOFF_V 0x1 -#define UART_SEND_XOFF_S 5 -/* UART_SEND_XON : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to send xon char. it is cleared by hardware automatically.*/ -#define UART_SEND_XON (BIT(4)) -#define UART_SEND_XON_M (BIT(4)) -#define UART_SEND_XON_V 0x1 -#define UART_SEND_XON_S 4 -/* UART_FORCE_XOFF : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to set ctsn to enable the transmitter to go on sending data.*/ -#define UART_FORCE_XOFF (BIT(3)) -#define UART_FORCE_XOFF_M (BIT(3)) -#define UART_FORCE_XOFF_V 0x1 -#define UART_FORCE_XOFF_S 3 -/* UART_FORCE_XON : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to clear ctsn to stop the transmitter from sending data.*/ -#define UART_FORCE_XON (BIT(2)) -#define UART_FORCE_XON_M (BIT(2)) -#define UART_FORCE_XON_V 0x1 -#define UART_FORCE_XON_S 2 -/* UART_XONOFF_DEL : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to remove flow control char from the received data.*/ -#define UART_XONOFF_DEL (BIT(1)) -#define UART_XONOFF_DEL_M (BIT(1)) -#define UART_XONOFF_DEL_V 0x1 -#define UART_XONOFF_DEL_S 1 -/* UART_SW_FLOW_CON_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to enable software flow control. it is used with - register sw_xon or sw_xoff .*/ -#define UART_SW_FLOW_CON_EN (BIT(0)) -#define UART_SW_FLOW_CON_EN_M (BIT(0)) -#define UART_SW_FLOW_CON_EN_V 0x1 -#define UART_SW_FLOW_CON_EN_S 0 - -#define UART_SLEEP_CONF_REG(i) (REG_UART_BASE(i) + 0x38) -/* UART_ACTIVE_THRESHOLD : R/W ;bitpos:[9:0] ;default: 10'hf0 ; */ -/*description: When the input rxd edge changes more than this register value. - the uart is active from light sleeping mode.*/ -#define UART_ACTIVE_THRESHOLD 0x000003FF -#define UART_ACTIVE_THRESHOLD_M ((UART_ACTIVE_THRESHOLD_V)<<(UART_ACTIVE_THRESHOLD_S)) -#define UART_ACTIVE_THRESHOLD_V 0x3FF -#define UART_ACTIVE_THRESHOLD_S 0 - -#define UART_SWFC_CONF_REG(i) (REG_UART_BASE(i) + 0x3C) -/* UART_XOFF_CHAR : R/W ;bitpos:[31:24] ;default: 8'h13 ; */ -/*description: This register stores the xoff flow control char.*/ -#define UART_XOFF_CHAR 0x000000FF -#define UART_XOFF_CHAR_M ((UART_XOFF_CHAR_V)<<(UART_XOFF_CHAR_S)) -#define UART_XOFF_CHAR_V 0xFF -#define UART_XOFF_CHAR_S 24 -/* UART_XON_CHAR : R/W ;bitpos:[23:16] ;default: 8'h11 ; */ -/*description: This register stores the xon flow control char.*/ -#define UART_XON_CHAR 0x000000FF -#define UART_XON_CHAR_M ((UART_XON_CHAR_V)<<(UART_XON_CHAR_S)) -#define UART_XON_CHAR_V 0xFF -#define UART_XON_CHAR_S 16 -/* UART_XOFF_THRESHOLD : R/W ;bitpos:[15:8] ;default: 8'he0 ; */ -/*description: When the data amount in receiver's fifo is less than this register - value. it will send a xon char with uart_sw_flow_con_en set to 1.*/ -#define UART_XOFF_THRESHOLD 0x000000FF -#define UART_XOFF_THRESHOLD_M ((UART_XOFF_THRESHOLD_V)<<(UART_XOFF_THRESHOLD_S)) -#define UART_XOFF_THRESHOLD_V 0xFF -#define UART_XOFF_THRESHOLD_S 8 -/* UART_XON_THRESHOLD : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: when the data amount in receiver's fifo is more than this register - value. it will send a xoff char with uart_sw_flow_con_en set to 1.*/ -#define UART_XON_THRESHOLD 0x000000FF -#define UART_XON_THRESHOLD_M ((UART_XON_THRESHOLD_V)<<(UART_XON_THRESHOLD_S)) -#define UART_XON_THRESHOLD_V 0xFF -#define UART_XON_THRESHOLD_S 0 - -#define UART_IDLE_CONF_REG(i) (REG_UART_BASE(i) + 0x40) -/* UART_TX_BRK_NUM : R/W ;bitpos:[27:20] ;default: 8'ha ; */ -/*description: This register is used to configure the num of 0 send after the - process of sending data is done. it is active when txd_brk is set to 1.*/ -#define UART_TX_BRK_NUM 0x000000FF -#define UART_TX_BRK_NUM_M ((UART_TX_BRK_NUM_V)<<(UART_TX_BRK_NUM_S)) -#define UART_TX_BRK_NUM_V 0xFF -#define UART_TX_BRK_NUM_S 20 -/* UART_TX_IDLE_NUM : R/W ;bitpos:[19:10] ;default: 10'h100 ; */ -/*description: This register is used to configure the duration time between transfers.*/ -#define UART_TX_IDLE_NUM 0x000003FF -#define UART_TX_IDLE_NUM_M ((UART_TX_IDLE_NUM_V)<<(UART_TX_IDLE_NUM_S)) -#define UART_TX_IDLE_NUM_V 0x3FF -#define UART_TX_IDLE_NUM_S 10 -/* UART_RX_IDLE_THRHD : R/W ;bitpos:[9:0] ;default: 10'h100 ; */ -/*description: when receiver takes more time than this register value to receive - a byte data. it will produce frame end signal for uhci to stop receiving data.*/ -#define UART_RX_IDLE_THRHD 0x000003FF -#define UART_RX_IDLE_THRHD_M ((UART_RX_IDLE_THRHD_V)<<(UART_RX_IDLE_THRHD_S)) -#define UART_RX_IDLE_THRHD_V 0x3FF -#define UART_RX_IDLE_THRHD_S 0 - -#define UART_RS485_CONF_REG(i) (REG_UART_BASE(i) + 0x44) -/* UART_RS485_TX_DLY_NUM : R/W ;bitpos:[9:6] ;default: 4'b0 ; */ -/*description: This register is used to delay the transmitter's internal data signal.*/ -#define UART_RS485_TX_DLY_NUM 0x0000000F -#define UART_RS485_TX_DLY_NUM_M ((UART_RS485_TX_DLY_NUM_V)<<(UART_RS485_TX_DLY_NUM_S)) -#define UART_RS485_TX_DLY_NUM_V 0xF -#define UART_RS485_TX_DLY_NUM_S 6 -/* UART_RS485_RX_DLY_NUM : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This register is used to delay the receiver's internal data signal.*/ -#define UART_RS485_RX_DLY_NUM (BIT(5)) -#define UART_RS485_RX_DLY_NUM_M (BIT(5)) -#define UART_RS485_RX_DLY_NUM_V 0x1 -#define UART_RS485_RX_DLY_NUM_S 5 -/* UART_RS485RXBY_TX_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: 1: enable rs485's transmitter to send data when rs485's receiver - is busy. 0:rs485's transmitter should not send data when its receiver is busy.*/ -#define UART_RS485RXBY_TX_EN (BIT(4)) -#define UART_RS485RXBY_TX_EN_M (BIT(4)) -#define UART_RS485RXBY_TX_EN_V 0x1 -#define UART_RS485RXBY_TX_EN_S 4 -/* UART_RS485TX_RX_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to enable loopback transmitter's output data signal - to receiver's input data signal.*/ -#define UART_RS485TX_RX_EN (BIT(3)) -#define UART_RS485TX_RX_EN_M (BIT(3)) -#define UART_RS485TX_RX_EN_V 0x1 -#define UART_RS485TX_RX_EN_S 3 -/* UART_DL1_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to delay the stop bit by 1 bit.*/ -#define UART_DL1_EN (BIT(2)) -#define UART_DL1_EN_M (BIT(2)) -#define UART_DL1_EN_V 0x1 -#define UART_DL1_EN_S 2 -/* UART_DL0_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to delay the stop bit by 1 bit.*/ -#define UART_DL0_EN (BIT(1)) -#define UART_DL0_EN_M (BIT(1)) -#define UART_DL0_EN_V 0x1 -#define UART_DL0_EN_S 1 -/* UART_RS485_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to choose rs485 mode.*/ -#define UART_RS485_EN (BIT(0)) -#define UART_RS485_EN_M (BIT(0)) -#define UART_RS485_EN_V 0x1 -#define UART_RS485_EN_S 0 - -#define UART_AT_CMD_PRECNT_REG(i) (REG_UART_BASE(i) + 0x48) -/* UART_PRE_IDLE_NUM : R/W ;bitpos:[23:0] ;default: 24'h186a00 ; */ -/*description: This register is used to configure the idle duration time before - the first at_cmd is received by receiver. when the the duration is less than this register value it will not take the next data received as at_cmd char.*/ -#define UART_PRE_IDLE_NUM 0x00FFFFFF -#define UART_PRE_IDLE_NUM_M ((UART_PRE_IDLE_NUM_V)<<(UART_PRE_IDLE_NUM_S)) -#define UART_PRE_IDLE_NUM_V 0xFFFFFF -#define UART_PRE_IDLE_NUM_S 0 - -#define UART_AT_CMD_POSTCNT_REG(i) (REG_UART_BASE(i) + 0x4c) -/* UART_POST_IDLE_NUM : R/W ;bitpos:[23:0] ;default: 24'h186a00 ; */ -/*description: This register is used to configure the duration time between - the last at_cmd and the next data. when the duration is less than this register value it will not take the previous data as at_cmd char.*/ -#define UART_POST_IDLE_NUM 0x00FFFFFF -#define UART_POST_IDLE_NUM_M ((UART_POST_IDLE_NUM_V)<<(UART_POST_IDLE_NUM_S)) -#define UART_POST_IDLE_NUM_V 0xFFFFFF -#define UART_POST_IDLE_NUM_S 0 - -#define UART_AT_CMD_GAPTOUT_REG(i) (REG_UART_BASE(i) + 0x50) -/* UART_RX_GAP_TOUT : R/W ;bitpos:[23:0] ;default: 24'h1e00 ; */ -/*description: This register is used to configure the duration time between - the at_cmd chars. when the duration time is less than this register value it will not take the datas as continous at_cmd chars.*/ -#define UART_RX_GAP_TOUT 0x00FFFFFF -#define UART_RX_GAP_TOUT_M ((UART_RX_GAP_TOUT_V)<<(UART_RX_GAP_TOUT_S)) -#define UART_RX_GAP_TOUT_V 0xFFFFFF -#define UART_RX_GAP_TOUT_S 0 - -#define UART_AT_CMD_CHAR_REG(i) (REG_UART_BASE(i) + 0x54) -/* UART_CHAR_NUM : R/W ;bitpos:[15:8] ;default: 8'h3 ; */ -/*description: This register is used to configure the num of continous at_cmd - chars received by receiver.*/ -#define UART_CHAR_NUM 0x000000FF -#define UART_CHAR_NUM_M ((UART_CHAR_NUM_V)<<(UART_CHAR_NUM_S)) -#define UART_CHAR_NUM_V 0xFF -#define UART_CHAR_NUM_S 8 -/* UART_AT_CMD_CHAR : R/W ;bitpos:[7:0] ;default: 8'h2b ; */ -/*description: This register is used to configure the content of at_cmd char.*/ -#define UART_AT_CMD_CHAR 0x000000FF -#define UART_AT_CMD_CHAR_M ((UART_AT_CMD_CHAR_V)<<(UART_AT_CMD_CHAR_S)) -#define UART_AT_CMD_CHAR_V 0xFF -#define UART_AT_CMD_CHAR_S 0 - -#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x58) -/* UART_TX_MEM_EMPTY_THRHD : R/W ;bitpos:[30:28] ;default: 3'h0 ; */ -/*description: refer to txfifo_empty_thrhd 's describtion.*/ -#define UART_TX_MEM_EMPTY_THRHD 0x00000007 -#define UART_TX_MEM_EMPTY_THRHD_M ((UART_TX_MEM_EMPTY_THRHD_V)<<(UART_TX_MEM_EMPTY_THRHD_S)) -#define UART_TX_MEM_EMPTY_THRHD_V 0x7 -#define UART_TX_MEM_EMPTY_THRHD_S 28 -/* UART_RX_MEM_FULL_THRHD : R/W ;bitpos:[27:25] ;default: 3'h0 ; */ -/*description: refer to the rxfifo_full_thrhd's describtion.*/ -#define UART_RX_MEM_FULL_THRHD 0x00000007 -#define UART_RX_MEM_FULL_THRHD_M ((UART_RX_MEM_FULL_THRHD_V)<<(UART_RX_MEM_FULL_THRHD_S)) -#define UART_RX_MEM_FULL_THRHD_V 0x7 -#define UART_RX_MEM_FULL_THRHD_S 25 -/* UART_XOFF_THRESHOLD_H2 : R/W ;bitpos:[24:23] ;default: 2'h0 ; */ -/*description: refer to the uart_xoff_threshold's describtion.*/ -#define UART_XOFF_THRESHOLD_H2 0x00000003 -#define UART_XOFF_THRESHOLD_H2_M ((UART_XOFF_THRESHOLD_H2_V)<<(UART_XOFF_THRESHOLD_H2_S)) -#define UART_XOFF_THRESHOLD_H2_V 0x3 -#define UART_XOFF_THRESHOLD_H2_S 23 -/* UART_XON_THRESHOLD_H2 : R/W ;bitpos:[22:21] ;default: 2'h0 ; */ -/*description: refer to the uart_xon_threshold's describtion.*/ -#define UART_XON_THRESHOLD_H2 0x00000003 -#define UART_XON_THRESHOLD_H2_M ((UART_XON_THRESHOLD_H2_V)<<(UART_XON_THRESHOLD_H2_S)) -#define UART_XON_THRESHOLD_H2_V 0x3 -#define UART_XON_THRESHOLD_H2_S 21 -/* UART_RX_TOUT_THRHD_H3 : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ -/*description: refer to the rx_tout_thrhd's describtion.*/ -#define UART_RX_TOUT_THRHD_H3 0x00000007 -#define UART_RX_TOUT_THRHD_H3_M ((UART_RX_TOUT_THRHD_H3_V)<<(UART_RX_TOUT_THRHD_H3_S)) -#define UART_RX_TOUT_THRHD_H3_V 0x7 -#define UART_RX_TOUT_THRHD_H3_S 18 -/* UART_RX_FLOW_THRHD_H3 : R/W ;bitpos:[17:15] ;default: 3'h0 ; */ -/*description: refer to the rx_flow_thrhd's describtion.*/ -#define UART_RX_FLOW_THRHD_H3 0x00000007 -#define UART_RX_FLOW_THRHD_H3_M ((UART_RX_FLOW_THRHD_H3_V)<<(UART_RX_FLOW_THRHD_H3_S)) -#define UART_RX_FLOW_THRHD_H3_V 0x7 -#define UART_RX_FLOW_THRHD_H3_S 15 -/* UART_TX_SIZE : R/W ;bitpos:[10:7] ;default: 4'h1 ; */ -/*description: This register is used to configure the amount of mem allocated - to transmitter's fifo.the default byte num is 128.*/ -#define UART_TX_SIZE 0x0000000F -#define UART_TX_SIZE_M ((UART_TX_SIZE_V)<<(UART_TX_SIZE_S)) -#define UART_TX_SIZE_V 0xF -#define UART_TX_SIZE_S 7 -/* UART_RX_SIZE : R/W ;bitpos:[6:3] ;default: 4'h1 ; */ -/*description: This register is used to configure the amount of mem allocated - to receiver's fifo. the default byte num is 128.*/ -#define UART_RX_SIZE 0x0000000F -#define UART_RX_SIZE_M ((UART_RX_SIZE_V)<<(UART_RX_SIZE_S)) -#define UART_RX_SIZE_V 0xF -#define UART_RX_SIZE_S 3 -/* UART_MEM_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to power down mem.when reg_mem_pd registers in - the 3 uarts are all set to 1 mem will enter low power mode.*/ -#define UART_MEM_PD (BIT(0)) -#define UART_MEM_PD_M (BIT(0)) -#define UART_MEM_PD_V 0x1 -#define UART_MEM_PD_S 0 - -#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x5c) -/* UART_MEM_TX_STATUS : RO ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: */ -#define UART_MEM_TX_STATUS 0x00FFFFFF -#define UART_MEM_TX_STATUS_M ((UART_MEM_TX_STATUS_V)<<(UART_MEM_TX_STATUS_S)) -#define UART_MEM_TX_STATUS_V 0xFFFFFF -#define UART_MEM_TX_STATUS_S 0 - -#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x60) -/* UART_MEM_RX_STATUS : RO ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: */ -#define UART_MEM_RX_STATUS 0x00FFFFFF -#define UART_MEM_RX_STATUS_M ((UART_MEM_RX_STATUS_V)<<(UART_MEM_RX_STATUS_S)) -#define UART_MEM_RX_STATUS_V 0xFFFFFF -#define UART_MEM_RX_STATUS_S 0 - -#define UART_MEM_CNT_STATUS_REG(i) (REG_UART_BASE(i) + 0x64) -/* UART_TX_MEM_CNT : RO ;bitpos:[5:3] ;default: 3'b0 ; */ -/*description: refer to the txfifo_cnt's describtion.*/ -#define UART_TX_MEM_CNT 0x00000007 -#define UART_TX_MEM_CNT_M ((UART_TX_MEM_CNT_V)<<(UART_TX_MEM_CNT_S)) -#define UART_TX_MEM_CNT_V 0x7 -#define UART_TX_MEM_CNT_S 3 -/* UART_RX_MEM_CNT : RO ;bitpos:[2:0] ;default: 3'b0 ; */ -/*description: refer to the rxfifo_cnt's describtion.*/ -#define UART_RX_MEM_CNT 0x00000007 -#define UART_RX_MEM_CNT_M ((UART_RX_MEM_CNT_V)<<(UART_RX_MEM_CNT_S)) -#define UART_RX_MEM_CNT_V 0x7 -#define UART_RX_MEM_CNT_S 0 - -#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x68) -/* UART_POSEDGE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */ -/*description: This register stores the count of rxd posedge edge. it is used - in boudrate-detect process.*/ -#define UART_POSEDGE_MIN_CNT 0x000FFFFF -#define UART_POSEDGE_MIN_CNT_M ((UART_POSEDGE_MIN_CNT_V)<<(UART_POSEDGE_MIN_CNT_S)) -#define UART_POSEDGE_MIN_CNT_V 0xFFFFF -#define UART_POSEDGE_MIN_CNT_S 0 - -#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x6c) -/* UART_NEGEDGE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */ -/*description: This register stores the count of rxd negedge edge. it is used - in boudrate-detect process.*/ -#define UART_NEGEDGE_MIN_CNT 0x000FFFFF -#define UART_NEGEDGE_MIN_CNT_M ((UART_NEGEDGE_MIN_CNT_V)<<(UART_NEGEDGE_MIN_CNT_S)) -#define UART_NEGEDGE_MIN_CNT_V 0xFFFFF -#define UART_NEGEDGE_MIN_CNT_S 0 - -#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x78) -/* UART_DATE : R/W ;bitpos:[31:0] ;default: 32'h15122500 ; */ -/*description: */ -#define UART_DATE 0xFFFFFFFF -#define UART_DATE_M ((UART_DATE_V)<<(UART_DATE_S)) -#define UART_DATE_V 0xFFFFFFFF -#define UART_DATE_S 0 - -#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x7C) -/* UART_ID : R/W ;bitpos:[31:0] ;default: 32'h0500 ; */ -/*description: */ -#define UART_ID 0xFFFFFFFF -#define UART_ID_M ((UART_ID_V)<<(UART_ID_S)) -#define UART_ID_V 0xFFFFFFFF -#define UART_ID_S 0 - - - - -#endif /*__UART_REG_H__ */ - - +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef __UART_REG_H__ +#define __UART_REG_H__ + + +#include "soc.h" + +#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ( i > 1 ? 0xe000 : 0 ) ) +#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ( i > 1 ? 0xe000 : 0 ) ) +#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) +#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0) + +/* UART_RXFIFO_RD_BYTE : RO ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: This register stores one byte data read by rx fifo.*/ +#define UART_RXFIFO_RD_BYTE 0x000000FF +#define UART_RXFIFO_RD_BYTE_M ((UART_RXFIFO_RD_BYTE_V)<<(UART_RXFIFO_RD_BYTE_S)) +#define UART_RXFIFO_RD_BYTE_V 0xFF +#define UART_RXFIFO_RD_BYTE_S 0 + +#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4) +/* UART_AT_CMD_CHAR_DET_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects + the configured at_cmd chars.*/ +#define UART_AT_CMD_CHAR_DET_INT_RAW (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_RAW_M (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_RAW_V 0x1 +#define UART_AT_CMD_CHAR_DET_INT_RAW_S 18 +/* UART_RS485_CLASH_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when rs485 detects + the clash between transmitter and receiver.*/ +#define UART_RS485_CLASH_INT_RAW (BIT(17)) +#define UART_RS485_CLASH_INT_RAW_M (BIT(17)) +#define UART_RS485_CLASH_INT_RAW_V 0x1 +#define UART_RS485_CLASH_INT_RAW_S 17 +/* UART_RS485_FRM_ERR_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when rs485 detects + the data frame error.*/ +#define UART_RS485_FRM_ERR_INT_RAW (BIT(16)) +#define UART_RS485_FRM_ERR_INT_RAW_M (BIT(16)) +#define UART_RS485_FRM_ERR_INT_RAW_V 0x1 +#define UART_RS485_FRM_ERR_INT_RAW_S 16 +/* UART_RS485_PARITY_ERR_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when rs485 detects the parity error.*/ +#define UART_RS485_PARITY_ERR_INT_RAW (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_RAW_M (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_RAW_V 0x1 +#define UART_RS485_PARITY_ERR_INT_RAW_S 15 +/* UART_TX_DONE_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when transmitter has + send all the data in fifo.*/ +#define UART_TX_DONE_INT_RAW (BIT(14)) +#define UART_TX_DONE_INT_RAW_M (BIT(14)) +#define UART_TX_DONE_INT_RAW_V 0x1 +#define UART_TX_DONE_INT_RAW_S 14 +/* UART_TX_BRK_IDLE_DONE_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when transmitter has + kept the shortest duration after the last data has been send.*/ +#define UART_TX_BRK_IDLE_DONE_INT_RAW (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_RAW_M (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_RAW_V 0x1 +#define UART_TX_BRK_IDLE_DONE_INT_RAW_S 13 +/* UART_TX_BRK_DONE_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when transmitter completes + sendding 0 after all the datas in transmitter's fifo are send.*/ +#define UART_TX_BRK_DONE_INT_RAW (BIT(12)) +#define UART_TX_BRK_DONE_INT_RAW_M (BIT(12)) +#define UART_TX_BRK_DONE_INT_RAW_V 0x1 +#define UART_TX_BRK_DONE_INT_RAW_S 12 +/* UART_GLITCH_DET_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects the start bit.*/ +#define UART_GLITCH_DET_INT_RAW (BIT(11)) +#define UART_GLITCH_DET_INT_RAW_M (BIT(11)) +#define UART_GLITCH_DET_INT_RAW_V 0x1 +#define UART_GLITCH_DET_INT_RAW_S 11 +/* UART_SW_XOFF_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver receives + xon char with uart_sw_flow_con_en is set to 1.*/ +#define UART_SW_XOFF_INT_RAW (BIT(10)) +#define UART_SW_XOFF_INT_RAW_M (BIT(10)) +#define UART_SW_XOFF_INT_RAW_V 0x1 +#define UART_SW_XOFF_INT_RAW_S 10 +/* UART_SW_XON_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver receives + xoff char with uart_sw_flow_con_en is set to 1.*/ +#define UART_SW_XON_INT_RAW (BIT(9)) +#define UART_SW_XON_INT_RAW_M (BIT(9)) +#define UART_SW_XON_INT_RAW_V 0x1 +#define UART_SW_XON_INT_RAW_S 9 +/* UART_RXFIFO_TOUT_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver takes + more time than rx_tout_thrhd to receive a byte.*/ +#define UART_RXFIFO_TOUT_INT_RAW (BIT(8)) +#define UART_RXFIFO_TOUT_INT_RAW_M (BIT(8)) +#define UART_RXFIFO_TOUT_INT_RAW_V 0x1 +#define UART_RXFIFO_TOUT_INT_RAW_S 8 +/* UART_BRK_DET_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects + the 0 after the stop bit.*/ +#define UART_BRK_DET_INT_RAW (BIT(7)) +#define UART_BRK_DET_INT_RAW_M (BIT(7)) +#define UART_BRK_DET_INT_RAW_V 0x1 +#define UART_BRK_DET_INT_RAW_S 7 +/* UART_CTS_CHG_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects + the edge change of ctsn signal.*/ +#define UART_CTS_CHG_INT_RAW (BIT(6)) +#define UART_CTS_CHG_INT_RAW_M (BIT(6)) +#define UART_CTS_CHG_INT_RAW_V 0x1 +#define UART_CTS_CHG_INT_RAW_S 6 +/* UART_DSR_CHG_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects + the edge change of dsrn signal.*/ +#define UART_DSR_CHG_INT_RAW (BIT(5)) +#define UART_DSR_CHG_INT_RAW_M (BIT(5)) +#define UART_DSR_CHG_INT_RAW_V 0x1 +#define UART_DSR_CHG_INT_RAW_S 5 +/* UART_RXFIFO_OVF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver receives + more data than the fifo can store.*/ +#define UART_RXFIFO_OVF_INT_RAW (BIT(4)) +#define UART_RXFIFO_OVF_INT_RAW_M (BIT(4)) +#define UART_RXFIFO_OVF_INT_RAW_V 0x1 +#define UART_RXFIFO_OVF_INT_RAW_S 4 +/* UART_FRM_ERR_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects + data's frame error .*/ +#define UART_FRM_ERR_INT_RAW (BIT(3)) +#define UART_FRM_ERR_INT_RAW_M (BIT(3)) +#define UART_FRM_ERR_INT_RAW_V 0x1 +#define UART_FRM_ERR_INT_RAW_S 3 +/* UART_PARITY_ERR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver detects + the parity error of data.*/ +#define UART_PARITY_ERR_INT_RAW (BIT(2)) +#define UART_PARITY_ERR_INT_RAW_M (BIT(2)) +#define UART_PARITY_ERR_INT_RAW_V 0x1 +#define UART_PARITY_ERR_INT_RAW_S 2 +/* UART_TXFIFO_EMPTY_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when the amount of + data in transmitter's fifo is less than ((tx_mem_cnttxfifo_cnt) .*/ +#define UART_TXFIFO_EMPTY_INT_RAW (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_RAW_M (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_RAW_V 0x1 +#define UART_TXFIFO_EMPTY_INT_RAW_S 1 +/* UART_RXFIFO_FULL_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This interrupt raw bit turns to high level when receiver receives + more data than (rx_flow_thrhd_h3 rx_flow_thrhd).*/ +#define UART_RXFIFO_FULL_INT_RAW (BIT(0)) +#define UART_RXFIFO_FULL_INT_RAW_M (BIT(0)) +#define UART_RXFIFO_FULL_INT_RAW_V 0x1 +#define UART_RXFIFO_FULL_INT_RAW_S 0 + +#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8) +/* UART_AT_CMD_CHAR_DET_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena + is set to 1.*/ +#define UART_AT_CMD_CHAR_DET_INT_ST (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ST_M (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ST_V 0x1 +#define UART_AT_CMD_CHAR_DET_INT_ST_S 18 +/* UART_RS485_CLASH_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena + is set to 1.*/ +#define UART_RS485_CLASH_INT_ST (BIT(17)) +#define UART_RS485_CLASH_INT_ST_M (BIT(17)) +#define UART_RS485_CLASH_INT_ST_V 0x1 +#define UART_RS485_CLASH_INT_ST_S 17 +/* UART_RS485_FRM_ERR_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This is the status bit for rs485_fm_err_int_raw when rs485_fm_err_int_ena + is set to 1.*/ +#define UART_RS485_FRM_ERR_INT_ST (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ST_M (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ST_V 0x1 +#define UART_RS485_FRM_ERR_INT_ST_S 16 +/* UART_RS485_PARITY_ERR_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena + is set to 1.*/ +#define UART_RS485_PARITY_ERR_INT_ST (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ST_M (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ST_V 0x1 +#define UART_RS485_PARITY_ERR_INT_ST_S 15 +/* UART_TX_DONE_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/ +#define UART_TX_DONE_INT_ST (BIT(14)) +#define UART_TX_DONE_INT_ST_M (BIT(14)) +#define UART_TX_DONE_INT_ST_V 0x1 +#define UART_TX_DONE_INT_ST_S 14 +/* UART_TX_BRK_IDLE_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena + is set to 1.*/ +#define UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ST_M (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ST_V 0x1 +#define UART_TX_BRK_IDLE_DONE_INT_ST_S 13 +/* UART_TX_BRK_DONE_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena + is set to 1.*/ +#define UART_TX_BRK_DONE_INT_ST (BIT(12)) +#define UART_TX_BRK_DONE_INT_ST_M (BIT(12)) +#define UART_TX_BRK_DONE_INT_ST_V 0x1 +#define UART_TX_BRK_DONE_INT_ST_S 12 +/* UART_GLITCH_DET_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: This is the status bit for glitch_det_int_raw when glitch_det_int_ena + is set to 1.*/ +#define UART_GLITCH_DET_INT_ST (BIT(11)) +#define UART_GLITCH_DET_INT_ST_M (BIT(11)) +#define UART_GLITCH_DET_INT_ST_V 0x1 +#define UART_GLITCH_DET_INT_ST_S 11 +/* UART_SW_XOFF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/ +#define UART_SW_XOFF_INT_ST (BIT(10)) +#define UART_SW_XOFF_INT_ST_M (BIT(10)) +#define UART_SW_XOFF_INT_ST_V 0x1 +#define UART_SW_XOFF_INT_ST_S 10 +/* UART_SW_XON_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/ +#define UART_SW_XON_INT_ST (BIT(9)) +#define UART_SW_XON_INT_ST_M (BIT(9)) +#define UART_SW_XON_INT_ST_V 0x1 +#define UART_SW_XON_INT_ST_S 9 +/* UART_RXFIFO_TOUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena + is set to 1.*/ +#define UART_RXFIFO_TOUT_INT_ST (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ST_M (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ST_V 0x1 +#define UART_RXFIFO_TOUT_INT_ST_S 8 +/* UART_BRK_DET_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/ +#define UART_BRK_DET_INT_ST (BIT(7)) +#define UART_BRK_DET_INT_ST_M (BIT(7)) +#define UART_BRK_DET_INT_ST_V 0x1 +#define UART_BRK_DET_INT_ST_S 7 +/* UART_CTS_CHG_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/ +#define UART_CTS_CHG_INT_ST (BIT(6)) +#define UART_CTS_CHG_INT_ST_M (BIT(6)) +#define UART_CTS_CHG_INT_ST_V 0x1 +#define UART_CTS_CHG_INT_ST_S 6 +/* UART_DSR_CHG_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/ +#define UART_DSR_CHG_INT_ST (BIT(5)) +#define UART_DSR_CHG_INT_ST_M (BIT(5)) +#define UART_DSR_CHG_INT_ST_V 0x1 +#define UART_DSR_CHG_INT_ST_S 5 +/* UART_RXFIFO_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena + is set to 1.*/ +#define UART_RXFIFO_OVF_INT_ST (BIT(4)) +#define UART_RXFIFO_OVF_INT_ST_M (BIT(4)) +#define UART_RXFIFO_OVF_INT_ST_V 0x1 +#define UART_RXFIFO_OVF_INT_ST_S 4 +/* UART_FRM_ERR_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This is the status bit for frm_err_int_raw when fm_err_int_ena is set to 1.*/ +#define UART_FRM_ERR_INT_ST (BIT(3)) +#define UART_FRM_ERR_INT_ST_M (BIT(3)) +#define UART_FRM_ERR_INT_ST_V 0x1 +#define UART_FRM_ERR_INT_ST_S 3 +/* UART_PARITY_ERR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the status bit for parity_err_int_raw when parity_err_int_ena + is set to 1.*/ +#define UART_PARITY_ERR_INT_ST (BIT(2)) +#define UART_PARITY_ERR_INT_ST_M (BIT(2)) +#define UART_PARITY_ERR_INT_ST_V 0x1 +#define UART_PARITY_ERR_INT_ST_S 2 +/* UART_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena + is set to 1.*/ +#define UART_TXFIFO_EMPTY_INT_ST (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ST_M (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ST_V 0x1 +#define UART_TXFIFO_EMPTY_INT_ST_S 1 +/* UART_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena + is set to 1.*/ +#define UART_RXFIFO_FULL_INT_ST (BIT(0)) +#define UART_RXFIFO_FULL_INT_ST_M (BIT(0)) +#define UART_RXFIFO_FULL_INT_ST_V 0x1 +#define UART_RXFIFO_FULL_INT_ST_S 0 + +#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xC) +/* UART_AT_CMD_CHAR_DET_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: This is the enable bit for at_cmd_char_det_int_st register.*/ +#define UART_AT_CMD_CHAR_DET_INT_ENA (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ENA_M (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ENA_V 0x1 +#define UART_AT_CMD_CHAR_DET_INT_ENA_S 18 +/* UART_RS485_CLASH_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This is the enable bit for rs485_clash_int_st register.*/ +#define UART_RS485_CLASH_INT_ENA (BIT(17)) +#define UART_RS485_CLASH_INT_ENA_M (BIT(17)) +#define UART_RS485_CLASH_INT_ENA_V 0x1 +#define UART_RS485_CLASH_INT_ENA_S 17 +/* UART_RS485_FRM_ERR_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This is the enable bit for rs485_parity_err_int_st register.*/ +#define UART_RS485_FRM_ERR_INT_ENA (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ENA_M (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ENA_V 0x1 +#define UART_RS485_FRM_ERR_INT_ENA_S 16 +/* UART_RS485_PARITY_ERR_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This is the enable bit for rs485_parity_err_int_st register.*/ +#define UART_RS485_PARITY_ERR_INT_ENA (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ENA_M (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ENA_V 0x1 +#define UART_RS485_PARITY_ERR_INT_ENA_S 15 +/* UART_TX_DONE_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This is the enable bit for tx_done_int_st register.*/ +#define UART_TX_DONE_INT_ENA (BIT(14)) +#define UART_TX_DONE_INT_ENA_M (BIT(14)) +#define UART_TX_DONE_INT_ENA_V 0x1 +#define UART_TX_DONE_INT_ENA_S 14 +/* UART_TX_BRK_IDLE_DONE_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: This is the enable bit for tx_brk_idle_done_int_st register.*/ +#define UART_TX_BRK_IDLE_DONE_INT_ENA (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ENA_M (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ENA_V 0x1 +#define UART_TX_BRK_IDLE_DONE_INT_ENA_S 13 +/* UART_TX_BRK_DONE_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: This is the enable bit for tx_brk_done_int_st register.*/ +#define UART_TX_BRK_DONE_INT_ENA (BIT(12)) +#define UART_TX_BRK_DONE_INT_ENA_M (BIT(12)) +#define UART_TX_BRK_DONE_INT_ENA_V 0x1 +#define UART_TX_BRK_DONE_INT_ENA_S 12 +/* UART_GLITCH_DET_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: This is the enable bit for glitch_det_int_st register.*/ +#define UART_GLITCH_DET_INT_ENA (BIT(11)) +#define UART_GLITCH_DET_INT_ENA_M (BIT(11)) +#define UART_GLITCH_DET_INT_ENA_V 0x1 +#define UART_GLITCH_DET_INT_ENA_S 11 +/* UART_SW_XOFF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: This is the enable bit for sw_xoff_int_st register.*/ +#define UART_SW_XOFF_INT_ENA (BIT(10)) +#define UART_SW_XOFF_INT_ENA_M (BIT(10)) +#define UART_SW_XOFF_INT_ENA_V 0x1 +#define UART_SW_XOFF_INT_ENA_S 10 +/* UART_SW_XON_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: This is the enable bit for sw_xon_int_st register.*/ +#define UART_SW_XON_INT_ENA (BIT(9)) +#define UART_SW_XON_INT_ENA_M (BIT(9)) +#define UART_SW_XON_INT_ENA_V 0x1 +#define UART_SW_XON_INT_ENA_S 9 +/* UART_RXFIFO_TOUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: This is the enable bit for rxfifo_tout_int_st register.*/ +#define UART_RXFIFO_TOUT_INT_ENA (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ENA_M (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ENA_V 0x1 +#define UART_RXFIFO_TOUT_INT_ENA_S 8 +/* UART_BRK_DET_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This is the enable bit for brk_det_int_st register.*/ +#define UART_BRK_DET_INT_ENA (BIT(7)) +#define UART_BRK_DET_INT_ENA_M (BIT(7)) +#define UART_BRK_DET_INT_ENA_V 0x1 +#define UART_BRK_DET_INT_ENA_S 7 +/* UART_CTS_CHG_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This is the enable bit for cts_chg_int_st register.*/ +#define UART_CTS_CHG_INT_ENA (BIT(6)) +#define UART_CTS_CHG_INT_ENA_M (BIT(6)) +#define UART_CTS_CHG_INT_ENA_V 0x1 +#define UART_CTS_CHG_INT_ENA_S 6 +/* UART_DSR_CHG_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This is the enable bit for dsr_chg_int_st register.*/ +#define UART_DSR_CHG_INT_ENA (BIT(5)) +#define UART_DSR_CHG_INT_ENA_M (BIT(5)) +#define UART_DSR_CHG_INT_ENA_V 0x1 +#define UART_DSR_CHG_INT_ENA_S 5 +/* UART_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: This is the enable bit for rxfifo_ovf_int_st register.*/ +#define UART_RXFIFO_OVF_INT_ENA (BIT(4)) +#define UART_RXFIFO_OVF_INT_ENA_M (BIT(4)) +#define UART_RXFIFO_OVF_INT_ENA_V 0x1 +#define UART_RXFIFO_OVF_INT_ENA_S 4 +/* UART_FRM_ERR_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: This is the enable bit for frm_err_int_st register.*/ +#define UART_FRM_ERR_INT_ENA (BIT(3)) +#define UART_FRM_ERR_INT_ENA_M (BIT(3)) +#define UART_FRM_ERR_INT_ENA_V 0x1 +#define UART_FRM_ERR_INT_ENA_S 3 +/* UART_PARITY_ERR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This is the enable bit for parity_err_int_st register.*/ +#define UART_PARITY_ERR_INT_ENA (BIT(2)) +#define UART_PARITY_ERR_INT_ENA_M (BIT(2)) +#define UART_PARITY_ERR_INT_ENA_V 0x1 +#define UART_PARITY_ERR_INT_ENA_S 2 +/* UART_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: This is the enable bit for rxfifo_full_int_st register.*/ +#define UART_TXFIFO_EMPTY_INT_ENA (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ENA_M (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ENA_V 0x1 +#define UART_TXFIFO_EMPTY_INT_ENA_S 1 +/* UART_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This is the enable bit for rxfifo_full_int_st register.*/ +#define UART_RXFIFO_FULL_INT_ENA (BIT(0)) +#define UART_RXFIFO_FULL_INT_ENA_M (BIT(0)) +#define UART_RXFIFO_FULL_INT_ENA_V 0x1 +#define UART_RXFIFO_FULL_INT_ENA_S 0 + +#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10) +/* UART_AT_CMD_CHAR_DET_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/ +#define UART_AT_CMD_CHAR_DET_INT_CLR (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_CLR_M (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_CLR_V 0x1 +#define UART_AT_CMD_CHAR_DET_INT_CLR_S 18 +/* UART_RS485_CLASH_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rs485_clash_int_raw interrupt.*/ +#define UART_RS485_CLASH_INT_CLR (BIT(17)) +#define UART_RS485_CLASH_INT_CLR_M (BIT(17)) +#define UART_RS485_CLASH_INT_CLR_V 0x1 +#define UART_RS485_CLASH_INT_CLR_S 17 +/* UART_RS485_FRM_ERR_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rs485_frm_err_int_raw interrupt.*/ +#define UART_RS485_FRM_ERR_INT_CLR (BIT(16)) +#define UART_RS485_FRM_ERR_INT_CLR_M (BIT(16)) +#define UART_RS485_FRM_ERR_INT_CLR_V 0x1 +#define UART_RS485_FRM_ERR_INT_CLR_S 16 +/* UART_RS485_PARITY_ERR_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rs485_parity_err_int_raw interrupt.*/ +#define UART_RS485_PARITY_ERR_INT_CLR (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_CLR_M (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_CLR_V 0x1 +#define UART_RS485_PARITY_ERR_INT_CLR_S 15 +/* UART_TX_DONE_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: Set this bit to clear the tx_done_int_raw interrupt.*/ +#define UART_TX_DONE_INT_CLR (BIT(14)) +#define UART_TX_DONE_INT_CLR_M (BIT(14)) +#define UART_TX_DONE_INT_CLR_V 0x1 +#define UART_TX_DONE_INT_CLR_S 14 +/* UART_TX_BRK_IDLE_DONE_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/ +#define UART_TX_BRK_IDLE_DONE_INT_CLR (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_CLR_M (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_CLR_V 0x1 +#define UART_TX_BRK_IDLE_DONE_INT_CLR_S 13 +/* UART_TX_BRK_DONE_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to clear the tx_brk_done_int_raw interrupt..*/ +#define UART_TX_BRK_DONE_INT_CLR (BIT(12)) +#define UART_TX_BRK_DONE_INT_CLR_M (BIT(12)) +#define UART_TX_BRK_DONE_INT_CLR_V 0x1 +#define UART_TX_BRK_DONE_INT_CLR_S 12 +/* UART_GLITCH_DET_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Set this bit to clear the glitch_det_int_raw interrupt.*/ +#define UART_GLITCH_DET_INT_CLR (BIT(11)) +#define UART_GLITCH_DET_INT_CLR_M (BIT(11)) +#define UART_GLITCH_DET_INT_CLR_V 0x1 +#define UART_GLITCH_DET_INT_CLR_S 11 +/* UART_SW_XOFF_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to clear the sw_xon_int_raw interrupt.*/ +#define UART_SW_XOFF_INT_CLR (BIT(10)) +#define UART_SW_XOFF_INT_CLR_M (BIT(10)) +#define UART_SW_XOFF_INT_CLR_V 0x1 +#define UART_SW_XOFF_INT_CLR_S 10 +/* UART_SW_XON_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to clear the sw_xon_int_raw interrupt.*/ +#define UART_SW_XON_INT_CLR (BIT(9)) +#define UART_SW_XON_INT_CLR_M (BIT(9)) +#define UART_SW_XON_INT_CLR_V 0x1 +#define UART_SW_XON_INT_CLR_S 9 +/* UART_RXFIFO_TOUT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rxfifo_tout_int_raw interrupt.*/ +#define UART_RXFIFO_TOUT_INT_CLR (BIT(8)) +#define UART_RXFIFO_TOUT_INT_CLR_M (BIT(8)) +#define UART_RXFIFO_TOUT_INT_CLR_V 0x1 +#define UART_RXFIFO_TOUT_INT_CLR_S 8 +/* UART_BRK_DET_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to clear the brk_det_int_raw interrupt.*/ +#define UART_BRK_DET_INT_CLR (BIT(7)) +#define UART_BRK_DET_INT_CLR_M (BIT(7)) +#define UART_BRK_DET_INT_CLR_V 0x1 +#define UART_BRK_DET_INT_CLR_S 7 +/* UART_CTS_CHG_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to clear the cts_chg_int_raw interrupt.*/ +#define UART_CTS_CHG_INT_CLR (BIT(6)) +#define UART_CTS_CHG_INT_CLR_M (BIT(6)) +#define UART_CTS_CHG_INT_CLR_V 0x1 +#define UART_CTS_CHG_INT_CLR_S 6 +/* UART_DSR_CHG_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to clear the dsr_chg_int_raw interrupt.*/ +#define UART_DSR_CHG_INT_CLR (BIT(5)) +#define UART_DSR_CHG_INT_CLR_M (BIT(5)) +#define UART_DSR_CHG_INT_CLR_V 0x1 +#define UART_DSR_CHG_INT_CLR_S 5 +/* UART_RXFIFO_OVF_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to clear rxfifo_ovf_int_raw interrupt.*/ +#define UART_RXFIFO_OVF_INT_CLR (BIT(4)) +#define UART_RXFIFO_OVF_INT_CLR_M (BIT(4)) +#define UART_RXFIFO_OVF_INT_CLR_V 0x1 +#define UART_RXFIFO_OVF_INT_CLR_S 4 +/* UART_FRM_ERR_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear frm_err_int_raw interrupt.*/ +#define UART_FRM_ERR_INT_CLR (BIT(3)) +#define UART_FRM_ERR_INT_CLR_M (BIT(3)) +#define UART_FRM_ERR_INT_CLR_V 0x1 +#define UART_FRM_ERR_INT_CLR_S 3 +/* UART_PARITY_ERR_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear parity_err_int_raw interrupt.*/ +#define UART_PARITY_ERR_INT_CLR (BIT(2)) +#define UART_PARITY_ERR_INT_CLR_M (BIT(2)) +#define UART_PARITY_ERR_INT_CLR_V 0x1 +#define UART_PARITY_ERR_INT_CLR_S 2 +/* UART_TXFIFO_EMPTY_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear txfifo_empty_int_raw interrupt.*/ +#define UART_TXFIFO_EMPTY_INT_CLR (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_CLR_M (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_CLR_V 0x1 +#define UART_TXFIFO_EMPTY_INT_CLR_S 1 +/* UART_RXFIFO_FULL_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear the rxfifo_full_int_raw interrupt.*/ +#define UART_RXFIFO_FULL_INT_CLR (BIT(0)) +#define UART_RXFIFO_FULL_INT_CLR_M (BIT(0)) +#define UART_RXFIFO_FULL_INT_CLR_V 0x1 +#define UART_RXFIFO_FULL_INT_CLR_S 0 + +#define UART_CLKDIV_REG(i) (REG_UART_BASE(i) + 0x14) +/* UART_CLKDIV_FRAG : R/W ;bitpos:[23:20] ;default: 4'h0 ; */ +/*description: The register value is the decimal part of the frequency divider's factor.*/ +#define UART_CLKDIV_FRAG 0x0000000F +#define UART_CLKDIV_FRAG_M ((UART_CLKDIV_FRAG_V)<<(UART_CLKDIV_FRAG_S)) +#define UART_CLKDIV_FRAG_V 0xF +#define UART_CLKDIV_FRAG_S 20 +/* UART_CLKDIV : R/W ;bitpos:[19:0] ;default: 20'h2B6 ; */ +/*description: The register value is the integer part of the frequency divider's factor.*/ +#define UART_CLKDIV 0x000FFFFF +#define UART_CLKDIV_M ((UART_CLKDIV_V)<<(UART_CLKDIV_S)) +#define UART_CLKDIV_V 0xFFFFF +#define UART_CLKDIV_S 0 + +#define UART_AUTOBAUD_REG(i) (REG_UART_BASE(i) + 0x18) +/* UART_GLITCH_FILT : R/W ;bitpos:[15:8] ;default: 8'h10 ; */ +/*description: when input pulse width is lower then this value igore this pulse.this + register is used in autobaud detect process.*/ +#define UART_GLITCH_FILT 0x000000FF +#define UART_GLITCH_FILT_M ((UART_GLITCH_FILT_V)<<(UART_GLITCH_FILT_S)) +#define UART_GLITCH_FILT_V 0xFF +#define UART_GLITCH_FILT_S 8 +/* UART_AUTOBAUD_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This is the enable bit for detecting baudrate.*/ +#define UART_AUTOBAUD_EN (BIT(0)) +#define UART_AUTOBAUD_EN_M (BIT(0)) +#define UART_AUTOBAUD_EN_V 0x1 +#define UART_AUTOBAUD_EN_S 0 + +#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1C) +/* UART_TXD : RO ;bitpos:[31] ;default: 8'h0 ; */ +/*description: This register represent the level value of the internal uart rxd signal.*/ +#define UART_TXD (BIT(31)) +#define UART_TXD_M (BIT(31)) +#define UART_TXD_V 0x1 +#define UART_TXD_S 31 +/* UART_RTSN : RO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: This register represent the level value of the internal uart cts signal.*/ +#define UART_RTSN (BIT(30)) +#define UART_RTSN_M (BIT(30)) +#define UART_RTSN_V 0x1 +#define UART_RTSN_S 30 +/* UART_DTRN : RO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: The register represent the level value of the internal uart dsr signal.*/ +#define UART_DTRN (BIT(29)) +#define UART_DTRN_M (BIT(29)) +#define UART_DTRN_V 0x1 +#define UART_DTRN_S 29 +/* UART_ST_UTX_OUT : RO ;bitpos:[27:24] ;default: 4'b0 ; */ +/*description: This register stores the value of transmitter's finite state + machine. 0:TX_IDLE 1:TX_STRT 2:TX_DAT0 3:TX_DAT1 4:TX_DAT2 5:TX_DAT3 6:TX_DAT4 7:TX_DAT5 8:TX_DAT6 9:TX_DAT7 10:TX_PRTY 11:TX_STP1 12:TX_STP2 13:TX_DL0 14:TX_DL1*/ +#define UART_ST_UTX_OUT 0x0000000F +#define UART_ST_UTX_OUT_M ((UART_ST_UTX_OUT_V)<<(UART_ST_UTX_OUT_S)) +#define UART_ST_UTX_OUT_V 0xF +#define UART_ST_UTX_OUT_S 24 +/* UART_TXFIFO_CNT : RO ;bitpos:[23:16] ;default: 8'b0 ; */ +/*description: (tx_mem_cnt txfifo_cnt) stores the byte num of valid datas in + transmitter's fifo.tx_mem_cnt stores the 3 most significant bits txfifo_cnt stores the 8 least significant bits.*/ +#define UART_TXFIFO_CNT 0x000000FF +#define UART_TXFIFO_CNT_M ((UART_TXFIFO_CNT_V)<<(UART_TXFIFO_CNT_S)) +#define UART_TXFIFO_CNT_V 0xFF +#define UART_TXFIFO_CNT_S 16 +/* UART_RXD : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This register stores the level value of the internal uart rxd signal.*/ +#define UART_RXD (BIT(15)) +#define UART_RXD_M (BIT(15)) +#define UART_RXD_V 0x1 +#define UART_RXD_S 15 +/* UART_CTSN : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This register stores the level value of the internal uart cts signal.*/ +#define UART_CTSN (BIT(14)) +#define UART_CTSN_M (BIT(14)) +#define UART_CTSN_V 0x1 +#define UART_CTSN_S 14 +/* UART_DSRN : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: This register stores the level value of the internal uart dsr signal.*/ +#define UART_DSRN (BIT(13)) +#define UART_DSRN_M (BIT(13)) +#define UART_DSRN_V 0x1 +#define UART_DSRN_S 13 +/* UART_ST_URX_OUT : RO ;bitpos:[11:8] ;default: 4'b0 ; */ +/*description: This register stores the value of receiver's finite state machine. + 0:RX_IDLE 1:RX_STRT 2:RX_DAT0 3:RX_DAT1 4:RX_DAT2 5:RX_DAT3 6:RX_DAT4 7:RX_DAT5 8:RX_DAT6 9:RX_DAT7 10:RX_PRTY 11:RX_STP1 12:RX_STP2 13:RX_DL1*/ +#define UART_ST_URX_OUT 0x0000000F +#define UART_ST_URX_OUT_M ((UART_ST_URX_OUT_V)<<(UART_ST_URX_OUT_S)) +#define UART_ST_URX_OUT_V 0xF +#define UART_ST_URX_OUT_S 8 +/* UART_RXFIFO_CNT : RO ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: (rx_mem_cnt rxfifo_cnt) stores the byte num of valid datas in + receiver's fifo. rx_mem_cnt register stores the 3 most significant bits rxfifo_cnt stores the 8 least significant bits.*/ +#define UART_RXFIFO_CNT 0x000000FF +#define UART_RXFIFO_CNT_M ((UART_RXFIFO_CNT_V)<<(UART_RXFIFO_CNT_S)) +#define UART_RXFIFO_CNT_V 0xFF +#define UART_RXFIFO_CNT_S 0 + +#define UART_CONF0_REG(i) (REG_UART_BASE(i) + 0x20) +/* UART_TICK_REF_ALWAYS_ON : R/W ;bitpos:[27] ;default: 1'b1 ; */ +/*description: This register is used to select the clock.1.apb clock 0:ref_tick*/ +#define UART_TICK_REF_ALWAYS_ON (BIT(27)) +#define UART_TICK_REF_ALWAYS_ON_M (BIT(27)) +#define UART_TICK_REF_ALWAYS_ON_V 0x1 +#define UART_TICK_REF_ALWAYS_ON_S 27 +/* UART_ERR_WR_MASK : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: 1.receiver stops storing data int fifo when data is wrong. + 0.receiver stores the data even if the received data is wrong.*/ +#define UART_ERR_WR_MASK (BIT(26)) +#define UART_ERR_WR_MASK_M (BIT(26)) +#define UART_ERR_WR_MASK_V 0x1 +#define UART_ERR_WR_MASK_S 26 +/* UART_CLK_EN : R/W ;bitpos:[25] ;default: 1'h0 ; */ +/*description: 1.force clock on for registers.support clock only when write registers*/ +#define UART_CLK_EN (BIT(25)) +#define UART_CLK_EN_M (BIT(25)) +#define UART_CLK_EN_V 0x1 +#define UART_CLK_EN_S 25 +/* UART_DTR_INV : R/W ;bitpos:[24] ;default: 1'h0 ; */ +/*description: Set this bit to inverse the level value of uart dtr signal.*/ +#define UART_DTR_INV (BIT(24)) +#define UART_DTR_INV_M (BIT(24)) +#define UART_DTR_INV_V 0x1 +#define UART_DTR_INV_S 24 +/* UART_RTS_INV : R/W ;bitpos:[23] ;default: 1'h0 ; */ +/*description: Set this bit to inverse the level value of uart rts signal.*/ +#define UART_RTS_INV (BIT(23)) +#define UART_RTS_INV_M (BIT(23)) +#define UART_RTS_INV_V 0x1 +#define UART_RTS_INV_S 23 +/* UART_TXD_INV : R/W ;bitpos:[22] ;default: 1'h0 ; */ +/*description: Set this bit to inverse the level value of uart txd signal.*/ +#define UART_TXD_INV (BIT(22)) +#define UART_TXD_INV_M (BIT(22)) +#define UART_TXD_INV_V 0x1 +#define UART_TXD_INV_S 22 +/* UART_DSR_INV : R/W ;bitpos:[21] ;default: 1'h0 ; */ +/*description: Set this bit to inverse the level value of uart dsr signal.*/ +#define UART_DSR_INV (BIT(21)) +#define UART_DSR_INV_M (BIT(21)) +#define UART_DSR_INV_V 0x1 +#define UART_DSR_INV_S 21 +/* UART_CTS_INV : R/W ;bitpos:[20] ;default: 1'h0 ; */ +/*description: Set this bit to inverse the level value of uart cts signal.*/ +#define UART_CTS_INV (BIT(20)) +#define UART_CTS_INV_M (BIT(20)) +#define UART_CTS_INV_V 0x1 +#define UART_CTS_INV_S 20 +/* UART_RXD_INV : R/W ;bitpos:[19] ;default: 1'h0 ; */ +/*description: Set this bit to inverse the level value of uart rxd signal.*/ +#define UART_RXD_INV (BIT(19)) +#define UART_RXD_INV_M (BIT(19)) +#define UART_RXD_INV_V 0x1 +#define UART_RXD_INV_S 19 +/* UART_TXFIFO_RST : R/W ;bitpos:[18] ;default: 1'h0 ; */ +/*description: Set this bit to reset uart transmitter's fifo.*/ +#define UART_TXFIFO_RST (BIT(18)) +#define UART_TXFIFO_RST_M (BIT(18)) +#define UART_TXFIFO_RST_V 0x1 +#define UART_TXFIFO_RST_S 18 +/* UART_RXFIFO_RST : R/W ;bitpos:[17] ;default: 1'h0 ; */ +/*description: Set this bit to reset uart receiver's fifo.*/ +#define UART_RXFIFO_RST (BIT(17)) +#define UART_RXFIFO_RST_M (BIT(17)) +#define UART_RXFIFO_RST_V 0x1 +#define UART_RXFIFO_RST_S 17 +/* UART_IRDA_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/*description: Set this bit to enable irda protocol.*/ +#define UART_IRDA_EN (BIT(16)) +#define UART_IRDA_EN_M (BIT(16)) +#define UART_IRDA_EN_V 0x1 +#define UART_IRDA_EN_S 16 +/* UART_TX_FLOW_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: Set this bit to enable transmitter's flow control function.*/ +#define UART_TX_FLOW_EN (BIT(15)) +#define UART_TX_FLOW_EN_M (BIT(15)) +#define UART_TX_FLOW_EN_V 0x1 +#define UART_TX_FLOW_EN_S 15 +/* UART_LOOPBACK : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: Set this bit to enable uart loopback test mode.*/ +#define UART_LOOPBACK (BIT(14)) +#define UART_LOOPBACK_M (BIT(14)) +#define UART_LOOPBACK_V 0x1 +#define UART_LOOPBACK_S 14 +/* UART_IRDA_RX_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Set this bit to inverse the level value of irda receiver's level.*/ +#define UART_IRDA_RX_INV (BIT(13)) +#define UART_IRDA_RX_INV_M (BIT(13)) +#define UART_IRDA_RX_INV_V 0x1 +#define UART_IRDA_RX_INV_S 13 +/* UART_IRDA_TX_INV : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to inverse the level value of irda transmitter's level.*/ +#define UART_IRDA_TX_INV (BIT(12)) +#define UART_IRDA_TX_INV_M (BIT(12)) +#define UART_IRDA_TX_INV_V 0x1 +#define UART_IRDA_TX_INV_S 12 +/* UART_IRDA_WCTL : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: 1.the irda transmitter's 11th bit is the same to the 10th bit. + 0.set irda transmitter's 11th bit to 0.*/ +#define UART_IRDA_WCTL (BIT(11)) +#define UART_IRDA_WCTL_M (BIT(11)) +#define UART_IRDA_WCTL_V 0x1 +#define UART_IRDA_WCTL_S 11 +/* UART_IRDA_TX_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: This is the start enable bit for irda transmitter.*/ +#define UART_IRDA_TX_EN (BIT(10)) +#define UART_IRDA_TX_EN_M (BIT(10)) +#define UART_IRDA_TX_EN_V 0x1 +#define UART_IRDA_TX_EN_S 10 +/* UART_IRDA_DPLX : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to enable irda loopback mode.*/ +#define UART_IRDA_DPLX (BIT(9)) +#define UART_IRDA_DPLX_M (BIT(9)) +#define UART_IRDA_DPLX_V 0x1 +#define UART_IRDA_DPLX_S 9 +/* UART_TXD_BRK : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to enbale transmitter to send 0 when the process + of sending data is done.*/ +#define UART_TXD_BRK (BIT(8)) +#define UART_TXD_BRK_M (BIT(8)) +#define UART_TXD_BRK_V 0x1 +#define UART_TXD_BRK_S 8 +/* UART_SW_DTR : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: This register is used to configure the software dtr signal which + is used in software flow control..*/ +#define UART_SW_DTR (BIT(7)) +#define UART_SW_DTR_M (BIT(7)) +#define UART_SW_DTR_V 0x1 +#define UART_SW_DTR_S 7 +/* UART_SW_RTS : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: This register is used to configure the software rts signal which + is used in software flow control.*/ +#define UART_SW_RTS (BIT(6)) +#define UART_SW_RTS_M (BIT(6)) +#define UART_SW_RTS_V 0x1 +#define UART_SW_RTS_S 6 +/* UART_STOP_BIT_NUM : R/W ;bitpos:[5:4] ;default: 2'd1 ; */ +/*description: This register is used to set the length of stop bit. 1:1bit 2:1.5bits 3:2bits*/ +#define UART_STOP_BIT_NUM 0x00000003 +#define UART_STOP_BIT_NUM_M ((UART_STOP_BIT_NUM_V)<<(UART_STOP_BIT_NUM_S)) +#define UART_STOP_BIT_NUM_V 0x3 +#define UART_STOP_BIT_NUM_S 4 +/* UART_BIT_NUM : R/W ;bitpos:[3:2] ;default: 2'd3 ; */ +/*description: This registe is used to set the length of data: 0:5bits 1:6bits 2:7bits 3:8bits*/ +#define UART_BIT_NUM 0x00000003 +#define UART_BIT_NUM_M ((UART_BIT_NUM_V)<<(UART_BIT_NUM_S)) +#define UART_BIT_NUM_V 0x3 +#define UART_BIT_NUM_S 2 +/* UART_PARITY_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to enable uart parity check.*/ +#define UART_PARITY_EN (BIT(1)) +#define UART_PARITY_EN_M (BIT(1)) +#define UART_PARITY_EN_V 0x1 +#define UART_PARITY_EN_S 1 +/* UART_PARITY : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This register is used to configure the parity check mode. 0:even 1:odd*/ +#define UART_PARITY (BIT(0)) +#define UART_PARITY_M (BIT(0)) +#define UART_PARITY_V 0x1 +#define UART_PARITY_S 0 + +#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24) +/* UART_RX_TOUT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: This is the enble bit for uart receiver's timeout function.*/ +#define UART_RX_TOUT_EN (BIT(31)) +#define UART_RX_TOUT_EN_M (BIT(31)) +#define UART_RX_TOUT_EN_V 0x1 +#define UART_RX_TOUT_EN_S 31 +/* UART_RX_TOUT_THRHD : R/W ;bitpos:[30:24] ;default: 7'b0 ; */ +/*description: This register is used to configure the timeout value for uart + receiver receiving a byte.*/ +#define UART_RX_TOUT_THRHD 0x0000007F +#define UART_RX_TOUT_THRHD_M ((UART_RX_TOUT_THRHD_V)<<(UART_RX_TOUT_THRHD_S)) +#define UART_RX_TOUT_THRHD_V 0x7F +#define UART_RX_TOUT_THRHD_S 24 +/* UART_RX_FLOW_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: This is the flow enable bit for uart receiver. 1:choose software + flow control with configuring sw_rts signal*/ +#define UART_RX_FLOW_EN (BIT(23)) +#define UART_RX_FLOW_EN_M (BIT(23)) +#define UART_RX_FLOW_EN_V 0x1 +#define UART_RX_FLOW_EN_S 23 +/* UART_RX_FLOW_THRHD : R/W ;bitpos:[22:16] ;default: 7'h0 ; */ +/*description: when receiver receives more data than its threshold value. + receiver produce signal to tell the transmitter stop transferring data. the threshold value is (rx_flow_thrhd_h3 rx_flow_thrhd).*/ +#define UART_RX_FLOW_THRHD 0x0000007F +#define UART_RX_FLOW_THRHD_M ((UART_RX_FLOW_THRHD_V)<<(UART_RX_FLOW_THRHD_S)) +#define UART_RX_FLOW_THRHD_V 0x7F +#define UART_RX_FLOW_THRHD_S 16 +/* UART_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[14:8] ;default: 7'h60 ; */ +/*description: when the data amount in transmitter fifo is less than its threshold + value. it will produce txfifo_empty_int_raw interrupt. the threshold value is (tx_mem_empty_thrhd txfifo_empty_thrhd)*/ +#define UART_TXFIFO_EMPTY_THRHD 0x0000007F +#define UART_TXFIFO_EMPTY_THRHD_M ((UART_TXFIFO_EMPTY_THRHD_V)<<(UART_TXFIFO_EMPTY_THRHD_S)) +#define UART_TXFIFO_EMPTY_THRHD_V 0x7F +#define UART_TXFIFO_EMPTY_THRHD_S 8 +/* UART_RXFIFO_FULL_THRHD : R/W ;bitpos:[6:0] ;default: 7'h60 ; */ +/*description: When receiver receives more data than its threshold value.receiver + will produce rxfifo_full_int_raw interrupt.the threshold value is (rx_flow_thrhd_h3 rxfifo_full_thrhd).*/ +#define UART_RXFIFO_FULL_THRHD 0x0000007F +#define UART_RXFIFO_FULL_THRHD_M ((UART_RXFIFO_FULL_THRHD_V)<<(UART_RXFIFO_FULL_THRHD_S)) +#define UART_RXFIFO_FULL_THRHD_V 0x7F +#define UART_RXFIFO_FULL_THRHD_S 0 + +#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x28) +/* UART_LOWPULSE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */ +/*description: This register stores the value of the minimum duration time for + the low level pulse. it is used in baudrate-detect process.*/ +#define UART_LOWPULSE_MIN_CNT 0x000FFFFF +#define UART_LOWPULSE_MIN_CNT_M ((UART_LOWPULSE_MIN_CNT_V)<<(UART_LOWPULSE_MIN_CNT_S)) +#define UART_LOWPULSE_MIN_CNT_V 0xFFFFF +#define UART_LOWPULSE_MIN_CNT_S 0 + +#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x2C) +/* UART_HIGHPULSE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */ +/*description: This register stores the value of the maxinum duration time + for the high level pulse. it is used in baudrate-detect process.*/ +#define UART_HIGHPULSE_MIN_CNT 0x000FFFFF +#define UART_HIGHPULSE_MIN_CNT_M ((UART_HIGHPULSE_MIN_CNT_V)<<(UART_HIGHPULSE_MIN_CNT_S)) +#define UART_HIGHPULSE_MIN_CNT_V 0xFFFFF +#define UART_HIGHPULSE_MIN_CNT_S 0 + +#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x30) +/* UART_RXD_EDGE_CNT : RO ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: This register stores the count of rxd edge change. it is used + in baudrate-detect process.*/ +#define UART_RXD_EDGE_CNT 0x000003FF +#define UART_RXD_EDGE_CNT_M ((UART_RXD_EDGE_CNT_V)<<(UART_RXD_EDGE_CNT_S)) +#define UART_RXD_EDGE_CNT_V 0x3FF +#define UART_RXD_EDGE_CNT_S 0 + +#define UART_FLOW_CONF_REG(i) (REG_UART_BASE(i) + 0x34) +/* UART_SEND_XOFF : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to send xoff char. it is cleared by hardware automatically.*/ +#define UART_SEND_XOFF (BIT(5)) +#define UART_SEND_XOFF_M (BIT(5)) +#define UART_SEND_XOFF_V 0x1 +#define UART_SEND_XOFF_S 5 +/* UART_SEND_XON : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to send xon char. it is cleared by hardware automatically.*/ +#define UART_SEND_XON (BIT(4)) +#define UART_SEND_XON_M (BIT(4)) +#define UART_SEND_XON_V 0x1 +#define UART_SEND_XON_S 4 +/* UART_FORCE_XOFF : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to set ctsn to enable the transmitter to go on sending data.*/ +#define UART_FORCE_XOFF (BIT(3)) +#define UART_FORCE_XOFF_M (BIT(3)) +#define UART_FORCE_XOFF_V 0x1 +#define UART_FORCE_XOFF_S 3 +/* UART_FORCE_XON : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear ctsn to stop the transmitter from sending data.*/ +#define UART_FORCE_XON (BIT(2)) +#define UART_FORCE_XON_M (BIT(2)) +#define UART_FORCE_XON_V 0x1 +#define UART_FORCE_XON_S 2 +/* UART_XONOFF_DEL : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to remove flow control char from the received data.*/ +#define UART_XONOFF_DEL (BIT(1)) +#define UART_XONOFF_DEL_M (BIT(1)) +#define UART_XONOFF_DEL_V 0x1 +#define UART_XONOFF_DEL_S 1 +/* UART_SW_FLOW_CON_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to enable software flow control. it is used with + register sw_xon or sw_xoff .*/ +#define UART_SW_FLOW_CON_EN (BIT(0)) +#define UART_SW_FLOW_CON_EN_M (BIT(0)) +#define UART_SW_FLOW_CON_EN_V 0x1 +#define UART_SW_FLOW_CON_EN_S 0 + +#define UART_SLEEP_CONF_REG(i) (REG_UART_BASE(i) + 0x38) +/* UART_ACTIVE_THRESHOLD : R/W ;bitpos:[9:0] ;default: 10'hf0 ; */ +/*description: When the input rxd edge changes more than this register value. + the uart is active from light sleeping mode.*/ +#define UART_ACTIVE_THRESHOLD 0x000003FF +#define UART_ACTIVE_THRESHOLD_M ((UART_ACTIVE_THRESHOLD_V)<<(UART_ACTIVE_THRESHOLD_S)) +#define UART_ACTIVE_THRESHOLD_V 0x3FF +#define UART_ACTIVE_THRESHOLD_S 0 + +#define UART_SWFC_CONF_REG(i) (REG_UART_BASE(i) + 0x3C) +/* UART_XOFF_CHAR : R/W ;bitpos:[31:24] ;default: 8'h13 ; */ +/*description: This register stores the xoff flow control char.*/ +#define UART_XOFF_CHAR 0x000000FF +#define UART_XOFF_CHAR_M ((UART_XOFF_CHAR_V)<<(UART_XOFF_CHAR_S)) +#define UART_XOFF_CHAR_V 0xFF +#define UART_XOFF_CHAR_S 24 +/* UART_XON_CHAR : R/W ;bitpos:[23:16] ;default: 8'h11 ; */ +/*description: This register stores the xon flow control char.*/ +#define UART_XON_CHAR 0x000000FF +#define UART_XON_CHAR_M ((UART_XON_CHAR_V)<<(UART_XON_CHAR_S)) +#define UART_XON_CHAR_V 0xFF +#define UART_XON_CHAR_S 16 +/* UART_XOFF_THRESHOLD : R/W ;bitpos:[15:8] ;default: 8'he0 ; */ +/*description: When the data amount in receiver's fifo is less than this register + value. it will send a xon char with uart_sw_flow_con_en set to 1.*/ +#define UART_XOFF_THRESHOLD 0x000000FF +#define UART_XOFF_THRESHOLD_M ((UART_XOFF_THRESHOLD_V)<<(UART_XOFF_THRESHOLD_S)) +#define UART_XOFF_THRESHOLD_V 0xFF +#define UART_XOFF_THRESHOLD_S 8 +/* UART_XON_THRESHOLD : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: when the data amount in receiver's fifo is more than this register + value. it will send a xoff char with uart_sw_flow_con_en set to 1.*/ +#define UART_XON_THRESHOLD 0x000000FF +#define UART_XON_THRESHOLD_M ((UART_XON_THRESHOLD_V)<<(UART_XON_THRESHOLD_S)) +#define UART_XON_THRESHOLD_V 0xFF +#define UART_XON_THRESHOLD_S 0 + +#define UART_IDLE_CONF_REG(i) (REG_UART_BASE(i) + 0x40) +/* UART_TX_BRK_NUM : R/W ;bitpos:[27:20] ;default: 8'ha ; */ +/*description: This register is used to configure the num of 0 send after the + process of sending data is done. it is active when txd_brk is set to 1.*/ +#define UART_TX_BRK_NUM 0x000000FF +#define UART_TX_BRK_NUM_M ((UART_TX_BRK_NUM_V)<<(UART_TX_BRK_NUM_S)) +#define UART_TX_BRK_NUM_V 0xFF +#define UART_TX_BRK_NUM_S 20 +/* UART_TX_IDLE_NUM : R/W ;bitpos:[19:10] ;default: 10'h100 ; */ +/*description: This register is used to configure the duration time between transfers.*/ +#define UART_TX_IDLE_NUM 0x000003FF +#define UART_TX_IDLE_NUM_M ((UART_TX_IDLE_NUM_V)<<(UART_TX_IDLE_NUM_S)) +#define UART_TX_IDLE_NUM_V 0x3FF +#define UART_TX_IDLE_NUM_S 10 +/* UART_RX_IDLE_THRHD : R/W ;bitpos:[9:0] ;default: 10'h100 ; */ +/*description: when receiver takes more time than this register value to receive + a byte data. it will produce frame end signal for uhci to stop receiving data.*/ +#define UART_RX_IDLE_THRHD 0x000003FF +#define UART_RX_IDLE_THRHD_M ((UART_RX_IDLE_THRHD_V)<<(UART_RX_IDLE_THRHD_S)) +#define UART_RX_IDLE_THRHD_V 0x3FF +#define UART_RX_IDLE_THRHD_S 0 + +#define UART_RS485_CONF_REG(i) (REG_UART_BASE(i) + 0x44) +/* UART_RS485_TX_DLY_NUM : R/W ;bitpos:[9:6] ;default: 4'b0 ; */ +/*description: This register is used to delay the transmitter's internal data signal.*/ +#define UART_RS485_TX_DLY_NUM 0x0000000F +#define UART_RS485_TX_DLY_NUM_M ((UART_RS485_TX_DLY_NUM_V)<<(UART_RS485_TX_DLY_NUM_S)) +#define UART_RS485_TX_DLY_NUM_V 0xF +#define UART_RS485_TX_DLY_NUM_S 6 +/* UART_RS485_RX_DLY_NUM : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: This register is used to delay the receiver's internal data signal.*/ +#define UART_RS485_RX_DLY_NUM (BIT(5)) +#define UART_RS485_RX_DLY_NUM_M (BIT(5)) +#define UART_RS485_RX_DLY_NUM_V 0x1 +#define UART_RS485_RX_DLY_NUM_S 5 +/* UART_RS485RXBY_TX_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: 1: enable rs485's transmitter to send data when rs485's receiver + is busy. 0:rs485's transmitter should not send data when its receiver is busy.*/ +#define UART_RS485RXBY_TX_EN (BIT(4)) +#define UART_RS485RXBY_TX_EN_M (BIT(4)) +#define UART_RS485RXBY_TX_EN_V 0x1 +#define UART_RS485RXBY_TX_EN_S 4 +/* UART_RS485TX_RX_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to enable loopback transmitter's output data signal + to receiver's input data signal.*/ +#define UART_RS485TX_RX_EN (BIT(3)) +#define UART_RS485TX_RX_EN_M (BIT(3)) +#define UART_RS485TX_RX_EN_V 0x1 +#define UART_RS485TX_RX_EN_S 3 +/* UART_DL1_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to delay the stop bit by 1 bit.*/ +#define UART_DL1_EN (BIT(2)) +#define UART_DL1_EN_M (BIT(2)) +#define UART_DL1_EN_V 0x1 +#define UART_DL1_EN_S 2 +/* UART_DL0_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to delay the stop bit by 1 bit.*/ +#define UART_DL0_EN (BIT(1)) +#define UART_DL0_EN_M (BIT(1)) +#define UART_DL0_EN_V 0x1 +#define UART_DL0_EN_S 1 +/* UART_RS485_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to choose rs485 mode.*/ +#define UART_RS485_EN (BIT(0)) +#define UART_RS485_EN_M (BIT(0)) +#define UART_RS485_EN_V 0x1 +#define UART_RS485_EN_S 0 + +#define UART_AT_CMD_PRECNT_REG(i) (REG_UART_BASE(i) + 0x48) +/* UART_PRE_IDLE_NUM : R/W ;bitpos:[23:0] ;default: 24'h186a00 ; */ +/*description: This register is used to configure the idle duration time before + the first at_cmd is received by receiver. when the the duration is less than this register value it will not take the next data received as at_cmd char.*/ +#define UART_PRE_IDLE_NUM 0x00FFFFFF +#define UART_PRE_IDLE_NUM_M ((UART_PRE_IDLE_NUM_V)<<(UART_PRE_IDLE_NUM_S)) +#define UART_PRE_IDLE_NUM_V 0xFFFFFF +#define UART_PRE_IDLE_NUM_S 0 + +#define UART_AT_CMD_POSTCNT_REG(i) (REG_UART_BASE(i) + 0x4c) +/* UART_POST_IDLE_NUM : R/W ;bitpos:[23:0] ;default: 24'h186a00 ; */ +/*description: This register is used to configure the duration time between + the last at_cmd and the next data. when the duration is less than this register value it will not take the previous data as at_cmd char.*/ +#define UART_POST_IDLE_NUM 0x00FFFFFF +#define UART_POST_IDLE_NUM_M ((UART_POST_IDLE_NUM_V)<<(UART_POST_IDLE_NUM_S)) +#define UART_POST_IDLE_NUM_V 0xFFFFFF +#define UART_POST_IDLE_NUM_S 0 + +#define UART_AT_CMD_GAPTOUT_REG(i) (REG_UART_BASE(i) + 0x50) +/* UART_RX_GAP_TOUT : R/W ;bitpos:[23:0] ;default: 24'h1e00 ; */ +/*description: This register is used to configure the duration time between + the at_cmd chars. when the duration time is less than this register value it will not take the datas as continous at_cmd chars.*/ +#define UART_RX_GAP_TOUT 0x00FFFFFF +#define UART_RX_GAP_TOUT_M ((UART_RX_GAP_TOUT_V)<<(UART_RX_GAP_TOUT_S)) +#define UART_RX_GAP_TOUT_V 0xFFFFFF +#define UART_RX_GAP_TOUT_S 0 + +#define UART_AT_CMD_CHAR_REG(i) (REG_UART_BASE(i) + 0x54) +/* UART_CHAR_NUM : R/W ;bitpos:[15:8] ;default: 8'h3 ; */ +/*description: This register is used to configure the num of continous at_cmd + chars received by receiver.*/ +#define UART_CHAR_NUM 0x000000FF +#define UART_CHAR_NUM_M ((UART_CHAR_NUM_V)<<(UART_CHAR_NUM_S)) +#define UART_CHAR_NUM_V 0xFF +#define UART_CHAR_NUM_S 8 +/* UART_AT_CMD_CHAR : R/W ;bitpos:[7:0] ;default: 8'h2b ; */ +/*description: This register is used to configure the content of at_cmd char.*/ +#define UART_AT_CMD_CHAR 0x000000FF +#define UART_AT_CMD_CHAR_M ((UART_AT_CMD_CHAR_V)<<(UART_AT_CMD_CHAR_S)) +#define UART_AT_CMD_CHAR_V 0xFF +#define UART_AT_CMD_CHAR_S 0 + +#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x58) +/* UART_TX_MEM_EMPTY_THRHD : R/W ;bitpos:[30:28] ;default: 3'h0 ; */ +/*description: refer to txfifo_empty_thrhd 's describtion.*/ +#define UART_TX_MEM_EMPTY_THRHD 0x00000007 +#define UART_TX_MEM_EMPTY_THRHD_M ((UART_TX_MEM_EMPTY_THRHD_V)<<(UART_TX_MEM_EMPTY_THRHD_S)) +#define UART_TX_MEM_EMPTY_THRHD_V 0x7 +#define UART_TX_MEM_EMPTY_THRHD_S 28 +/* UART_RX_MEM_FULL_THRHD : R/W ;bitpos:[27:25] ;default: 3'h0 ; */ +/*description: refer to the rxfifo_full_thrhd's describtion.*/ +#define UART_RX_MEM_FULL_THRHD 0x00000007 +#define UART_RX_MEM_FULL_THRHD_M ((UART_RX_MEM_FULL_THRHD_V)<<(UART_RX_MEM_FULL_THRHD_S)) +#define UART_RX_MEM_FULL_THRHD_V 0x7 +#define UART_RX_MEM_FULL_THRHD_S 25 +/* UART_XOFF_THRESHOLD_H2 : R/W ;bitpos:[24:23] ;default: 2'h0 ; */ +/*description: refer to the uart_xoff_threshold's describtion.*/ +#define UART_XOFF_THRESHOLD_H2 0x00000003 +#define UART_XOFF_THRESHOLD_H2_M ((UART_XOFF_THRESHOLD_H2_V)<<(UART_XOFF_THRESHOLD_H2_S)) +#define UART_XOFF_THRESHOLD_H2_V 0x3 +#define UART_XOFF_THRESHOLD_H2_S 23 +/* UART_XON_THRESHOLD_H2 : R/W ;bitpos:[22:21] ;default: 2'h0 ; */ +/*description: refer to the uart_xon_threshold's describtion.*/ +#define UART_XON_THRESHOLD_H2 0x00000003 +#define UART_XON_THRESHOLD_H2_M ((UART_XON_THRESHOLD_H2_V)<<(UART_XON_THRESHOLD_H2_S)) +#define UART_XON_THRESHOLD_H2_V 0x3 +#define UART_XON_THRESHOLD_H2_S 21 +/* UART_RX_TOUT_THRHD_H3 : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ +/*description: refer to the rx_tout_thrhd's describtion.*/ +#define UART_RX_TOUT_THRHD_H3 0x00000007 +#define UART_RX_TOUT_THRHD_H3_M ((UART_RX_TOUT_THRHD_H3_V)<<(UART_RX_TOUT_THRHD_H3_S)) +#define UART_RX_TOUT_THRHD_H3_V 0x7 +#define UART_RX_TOUT_THRHD_H3_S 18 +/* UART_RX_FLOW_THRHD_H3 : R/W ;bitpos:[17:15] ;default: 3'h0 ; */ +/*description: refer to the rx_flow_thrhd's describtion.*/ +#define UART_RX_FLOW_THRHD_H3 0x00000007 +#define UART_RX_FLOW_THRHD_H3_M ((UART_RX_FLOW_THRHD_H3_V)<<(UART_RX_FLOW_THRHD_H3_S)) +#define UART_RX_FLOW_THRHD_H3_V 0x7 +#define UART_RX_FLOW_THRHD_H3_S 15 +/* UART_TX_SIZE : R/W ;bitpos:[10:7] ;default: 4'h1 ; */ +/*description: This register is used to configure the amount of mem allocated + to transmitter's fifo.the default byte num is 128.*/ +#define UART_TX_SIZE 0x0000000F +#define UART_TX_SIZE_M ((UART_TX_SIZE_V)<<(UART_TX_SIZE_S)) +#define UART_TX_SIZE_V 0xF +#define UART_TX_SIZE_S 7 +/* UART_RX_SIZE : R/W ;bitpos:[6:3] ;default: 4'h1 ; */ +/*description: This register is used to configure the amount of mem allocated + to receiver's fifo. the default byte num is 128.*/ +#define UART_RX_SIZE 0x0000000F +#define UART_RX_SIZE_M ((UART_RX_SIZE_V)<<(UART_RX_SIZE_S)) +#define UART_RX_SIZE_V 0xF +#define UART_RX_SIZE_S 3 +/* UART_MEM_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to power down mem.when reg_mem_pd registers in + the 3 uarts are all set to 1 mem will enter low power mode.*/ +#define UART_MEM_PD (BIT(0)) +#define UART_MEM_PD_M (BIT(0)) +#define UART_MEM_PD_V 0x1 +#define UART_MEM_PD_S 0 + +#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x5c) +/* UART_MEM_TX_STATUS : RO ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: */ +#define UART_MEM_TX_STATUS 0x00FFFFFF +#define UART_MEM_TX_STATUS_M ((UART_MEM_TX_STATUS_V)<<(UART_MEM_TX_STATUS_S)) +#define UART_MEM_TX_STATUS_V 0xFFFFFF +#define UART_MEM_TX_STATUS_S 0 + +#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x60) +/* UART_MEM_RX_STATUS : RO ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: */ +#define UART_MEM_RX_STATUS 0x00FFFFFF +#define UART_MEM_RX_STATUS_M ((UART_MEM_RX_STATUS_V)<<(UART_MEM_RX_STATUS_S)) +#define UART_MEM_RX_STATUS_V 0xFFFFFF +#define UART_MEM_RX_STATUS_S 0 + +#define UART_MEM_CNT_STATUS_REG(i) (REG_UART_BASE(i) + 0x64) +/* UART_TX_MEM_CNT : RO ;bitpos:[5:3] ;default: 3'b0 ; */ +/*description: refer to the txfifo_cnt's describtion.*/ +#define UART_TX_MEM_CNT 0x00000007 +#define UART_TX_MEM_CNT_M ((UART_TX_MEM_CNT_V)<<(UART_TX_MEM_CNT_S)) +#define UART_TX_MEM_CNT_V 0x7 +#define UART_TX_MEM_CNT_S 3 +/* UART_RX_MEM_CNT : RO ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: refer to the rxfifo_cnt's describtion.*/ +#define UART_RX_MEM_CNT 0x00000007 +#define UART_RX_MEM_CNT_M ((UART_RX_MEM_CNT_V)<<(UART_RX_MEM_CNT_S)) +#define UART_RX_MEM_CNT_V 0x7 +#define UART_RX_MEM_CNT_S 0 + +#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x68) +/* UART_POSEDGE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */ +/*description: This register stores the count of rxd posedge edge. it is used + in boudrate-detect process.*/ +#define UART_POSEDGE_MIN_CNT 0x000FFFFF +#define UART_POSEDGE_MIN_CNT_M ((UART_POSEDGE_MIN_CNT_V)<<(UART_POSEDGE_MIN_CNT_S)) +#define UART_POSEDGE_MIN_CNT_V 0xFFFFF +#define UART_POSEDGE_MIN_CNT_S 0 + +#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x6c) +/* UART_NEGEDGE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */ +/*description: This register stores the count of rxd negedge edge. it is used + in boudrate-detect process.*/ +#define UART_NEGEDGE_MIN_CNT 0x000FFFFF +#define UART_NEGEDGE_MIN_CNT_M ((UART_NEGEDGE_MIN_CNT_V)<<(UART_NEGEDGE_MIN_CNT_S)) +#define UART_NEGEDGE_MIN_CNT_V 0xFFFFF +#define UART_NEGEDGE_MIN_CNT_S 0 + +#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x78) +/* UART_DATE : R/W ;bitpos:[31:0] ;default: 32'h15122500 ; */ +/*description: */ +#define UART_DATE 0xFFFFFFFF +#define UART_DATE_M ((UART_DATE_V)<<(UART_DATE_S)) +#define UART_DATE_V 0xFFFFFFFF +#define UART_DATE_S 0 + +#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x7C) +/* UART_ID : R/W ;bitpos:[31:0] ;default: 32'h0500 ; */ +/*description: */ +#define UART_ID 0xFFFFFFFF +#define UART_ID_M ((UART_ID_V)<<(UART_ID_S)) +#define UART_ID_V 0xFFFFFFFF +#define UART_ID_S 0 + + + + +#endif /*__UART_REG_H__ */ + + From 7ee8ee8b7e6764079e3c631c471e70630655e252 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Tue, 11 Apr 2017 15:44:43 +0800 Subject: [PATCH 4/5] soc: add source code of rtc_clk, rtc_pm --- components/bootloader/src/Makefile | 2 +- .../bootloader/src/main/bootloader_start.c | 27 +- components/bootloader/src/main/component.mk | 8 - components/esp32/Kconfig | 7 +- components/esp32/component.mk | 2 +- components/esp32/cpu_freq.c | 33 +- components/esp32/cpu_start.c | 3 +- components/esp32/deep_sleep.c | 97 ++-- components/esp32/include/rom/rtc.h | 3 + components/esp32/ld/esp32.common.ld | 3 +- components/esp32/phy.h | 5 + components/esp32/phy_init.c | 2 +- components/esp32/rtc.h | 146 ----- components/esp32/system_api.c | 4 +- components/soc/component.mk | 5 + components/{ => soc}/esp32/brownout.c | 0 components/{ => soc}/esp32/cpu_util.c | 0 components/soc/esp32/i2c_apll.h | 136 +++++ components/soc/esp32/i2c_bbpll.h | 208 +++++++ components/soc/esp32/i2c_rtc_clk.h | 48 ++ .../{ => soc}/esp32/include/esp_brownout.h | 0 components/soc/esp32/include/soc/bb_reg.h | 92 +-- components/soc/esp32/include/soc/boot_mode.h | 0 components/soc/esp32/include/soc/fe_reg.h | 33 ++ components/soc/esp32/include/soc/nrx_reg.h | 39 ++ components/soc/esp32/include/soc/rtc.h | 496 ++++++++++++++++ .../soc/esp32/include/soc/rtc_cntl_reg.h | 64 +++ components/soc/esp32/include/soc/rtc_io_reg.h | 2 + components/soc/esp32/include/soc/soc.h | 2 + components/soc/esp32/rtc_clk.c | 534 ++++++++++++++++++ components/soc/esp32/rtc_init.c | 96 ++++ components/soc/esp32/rtc_pm.c | 68 +++ components/soc/esp32/rtc_sleep.c | 225 ++++++++ components/soc/esp32/rtc_time.c | 116 ++++ components/soc/esp32/soc_log.h | 40 ++ components/soc/esp32/test/test_rtc_clk.c | 84 +++ components/soc/test/component.mk | 8 + 37 files changed, 2311 insertions(+), 327 deletions(-) delete mode 100644 components/esp32/rtc.h create mode 100755 components/soc/component.mk rename components/{ => soc}/esp32/brownout.c (100%) rename components/{ => soc}/esp32/cpu_util.c (100%) create mode 100644 components/soc/esp32/i2c_apll.h create mode 100644 components/soc/esp32/i2c_bbpll.h create mode 100644 components/soc/esp32/i2c_rtc_clk.h rename components/{ => soc}/esp32/include/esp_brownout.h (100%) mode change 100755 => 100644 components/soc/esp32/include/soc/bb_reg.h mode change 100755 => 100644 components/soc/esp32/include/soc/boot_mode.h create mode 100644 components/soc/esp32/include/soc/fe_reg.h create mode 100644 components/soc/esp32/include/soc/nrx_reg.h create mode 100644 components/soc/esp32/include/soc/rtc.h mode change 100755 => 100644 components/soc/esp32/include/soc/soc.h create mode 100644 components/soc/esp32/rtc_clk.c create mode 100644 components/soc/esp32/rtc_init.c create mode 100644 components/soc/esp32/rtc_pm.c create mode 100644 components/soc/esp32/rtc_sleep.c create mode 100644 components/soc/esp32/rtc_time.c create mode 100644 components/soc/esp32/soc_log.h create mode 100644 components/soc/esp32/test/test_rtc_clk.c create mode 100644 components/soc/test/component.mk diff --git a/components/bootloader/src/Makefile b/components/bootloader/src/Makefile index bb4e64d0b..ac71e2787 100644 --- a/components/bootloader/src/Makefile +++ b/components/bootloader/src/Makefile @@ -7,7 +7,7 @@ PROJECT_NAME := bootloader #We cannot include the esp32 component directly but we need its includes. #This is fixed by adding CFLAGS from Makefile.projbuild -COMPONENTS := esptool_py bootloader bootloader_support log spi_flash micro-ecc +COMPONENTS := esptool_py bootloader bootloader_support log spi_flash micro-ecc soc # The bootloader pseudo-component is also included in this build, for its Kconfig.projbuild to be included. # diff --git a/components/bootloader/src/main/bootloader_start.c b/components/bootloader/src/main/bootloader_start.c index 0df7d0294..d4b1f054c 100644 --- a/components/bootloader/src/main/bootloader_start.c +++ b/components/bootloader/src/main/bootloader_start.c @@ -29,6 +29,7 @@ #include "soc/soc.h" #include "soc/cpu.h" +#include "soc/rtc.h" #include "soc/dport_reg.h" #include "soc/io_mux_reg.h" #include "soc/efuse_reg.h" @@ -45,7 +46,7 @@ #include "bootloader_flash.h" #include "bootloader_random.h" #include "bootloader_config.h" -#include "rtc.h" + #include "flash_qio_mode.h" extern int _bss_start; @@ -234,12 +235,13 @@ static bool ota_select_valid(const esp_ota_select_entry_t *s) void bootloader_main() { - /* Set CPU to 80MHz. - Start by ensuring it is set to XTAL, as PLL must be off first - (may still be on due to soft reset.) - */ - rtc_set_cpu_freq(CPU_XTAL); - rtc_set_cpu_freq(CPU_80M); + /* Set CPU to 80MHz. Keep other clocks unmodified. */ + uart_tx_wait_idle(0); + rtc_clk_config_t clk_cfg = RTC_CLK_CONFIG_DEFAULT(); + clk_cfg.cpu_freq = RTC_CPU_FREQ_80M; + clk_cfg.slow_freq = rtc_clk_slow_freq_get(); + clk_cfg.fast_freq = rtc_clk_fast_freq_get(); + rtc_clk_init(clk_cfg); uart_console_configure(); ESP_LOGI(TAG, "ESP-IDF %s 2nd stage bootloader", IDF_VER); @@ -722,16 +724,7 @@ static void uart_console_configure(void) // Set configured UART console baud rate const int uart_baud = CONFIG_CONSOLE_UART_BAUDRATE; - uart_div_modify(uart_num, (APB_CLK_FREQ << 4) / uart_baud); + uart_div_modify(uart_num, (rtc_clk_apb_freq_get() << 4) / uart_baud); #endif // CONFIG_CONSOLE_UART_NONE } - -/* empty rtc_printf implementation, to work with librtc - linking. Can be removed once -lrtc is removed from bootloader's - main component.mk. -*/ -int rtc_printf(void) -{ - return 0; -} diff --git a/components/bootloader/src/main/component.mk b/components/bootloader/src/main/component.mk index b3d3c084f..9e61cc43f 100644 --- a/components/bootloader/src/main/component.mk +++ b/components/bootloader/src/main/component.mk @@ -14,11 +14,3 @@ LINKER_SCRIPTS := \ COMPONENT_ADD_LDFLAGS := -L $(COMPONENT_PATH) -lmain $(addprefix -T ,$(LINKER_SCRIPTS)) COMPONENT_ADD_LINKER_DEPS := $(LINKER_SCRIPTS) - -# following lines are a workaround to link librtc into the -# bootloader, until clock setting code is in a source-based esp-idf -# component. See also rtc_printf() in bootloader_start.c -# -# See also matching COMPONENT_SUBMODULES line in Makefile.projbuild -COMPONENT_ADD_LDFLAGS += -L $(IDF_PATH)/components/esp32/lib/ -lrtc_clk -lrtc -COMPONENT_EXTRA_INCLUDES += $(IDF_PATH)/components/esp32/ diff --git a/components/esp32/Kconfig b/components/esp32/Kconfig index a156b85c9..0db76f3d5 100644 --- a/components/esp32/Kconfig +++ b/components/esp32/Kconfig @@ -2,7 +2,7 @@ menu "ESP32-specific" choice ESP32_DEFAULT_CPU_FREQ_MHZ prompt "CPU frequency" - default ESP32_DEFAULT_CPU_FREQ_240 + default ESP32_DEFAULT_CPU_FREQ_160 help CPU frequency to be set on application startup. @@ -467,14 +467,11 @@ choice ESP32_RTC_CLOCK_SOURCE default ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC help Choose which clock is used as RTC clock source. - The only available option for now is to use internal - 150kHz RC oscillator. config ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC - bool "Internal RC" + bool "Internal 150kHz RC oscillator" config ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL bool "External 32kHz crystal" - depends on DOCUMENTATION_FOR_RTC_CNTL endchoice config ESP32_DEEP_SLEEP_WAKEUP_DELAY diff --git a/components/esp32/component.mk b/components/esp32/component.mk index ae0f331cd..a8109a0f5 100644 --- a/components/esp32/component.mk +++ b/components/esp32/component.mk @@ -3,7 +3,7 @@ # COMPONENT_SRCDIRS := . hwcrypto -LIBS := core rtc rtc_clk rtc_pm +LIBS := core rtc ifdef CONFIG_PHY_ENABLED # BT || WIFI LIBS += phy coexist endif diff --git a/components/esp32/cpu_freq.c b/components/esp32/cpu_freq.c index f5ccd13df..4efa825b5 100644 --- a/components/esp32/cpu_freq.c +++ b/components/esp32/cpu_freq.c @@ -17,8 +17,8 @@ #include "rom/ets_sys.h" #include "rom/uart.h" #include "sdkconfig.h" -#include "rtc.h" #include "soc/soc.h" +#include "soc/rtc.h" #include "soc/rtc_cntl_reg.h" /* @@ -31,38 +31,31 @@ void esp_set_cpu_freq(void) { uint32_t freq_mhz = CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ; - - // freq will be changed to 40MHz in rtc_init_lite, - // wait uart tx finish, otherwise some uart output will be lost - uart_tx_wait_idle(CONFIG_CONSOLE_UART_NUM); - - rtc_init_lite(XTAL_AUTO); - // work around a bug that RTC fast memory may be isolated - // from the system after rtc_init_lite - SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_NOISO_M); - - cpu_freq_t freq = CPU_80M; + rtc_cpu_freq_t freq = RTC_CPU_FREQ_80M; switch(freq_mhz) { case 240: - freq = CPU_240M; + freq = RTC_CPU_FREQ_240M; break; case 160: - freq = CPU_160M; + freq = RTC_CPU_FREQ_160M; break; default: freq_mhz = 80; /* no break */ case 80: - freq = CPU_80M; + freq = RTC_CPU_FREQ_80M; break; } - // freq will be changed to freq in rtc_set_cpu_freq, - // wait uart tx finish, otherwise some uart output will be lost + // Wait for UART TX to finish, otherwise some UART output will be lost + // when switching APB frequency uart_tx_wait_idle(CONFIG_CONSOLE_UART_NUM); - - rtc_set_cpu_freq(freq); - ets_update_cpu_frequency(freq_mhz); + rtc_config_t cfg = RTC_CONFIG_DEFAULT(); + rtc_init(cfg); + rtc_clk_cpu_freq_set(freq); +#if ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL + rtc_clk_slow_freq_set(RTC_SLOW_FREQ_32K_XTAL); +#endif } void IRAM_ATTR ets_update_cpu_frequency(uint32_t ticks_per_us) diff --git a/components/esp32/cpu_start.c b/components/esp32/cpu_start.c index e0ad356ab..61fd7f8b4 100644 --- a/components/esp32/cpu_start.c +++ b/components/esp32/cpu_start.c @@ -23,6 +23,7 @@ #include "rom/cache.h" #include "soc/cpu.h" +#include "soc/rtc.h" #include "soc/dport_reg.h" #include "soc/io_mux_reg.h" #include "soc/rtc_cntl_reg.h" @@ -201,7 +202,7 @@ void start_cpu0_default(void) #endif esp_set_cpu_freq(); // set CPU frequency configured in menuconfig #ifndef CONFIG_CONSOLE_UART_NONE - uart_div_modify(CONFIG_CONSOLE_UART_NUM, (APB_CLK_FREQ << 4) / CONFIG_CONSOLE_UART_BAUDRATE); + uart_div_modify(CONFIG_CONSOLE_UART_NUM, (rtc_clk_apb_freq_get() << 4) / CONFIG_CONSOLE_UART_BAUDRATE); #endif #if CONFIG_BROWNOUT_DET esp_brownout_init(); diff --git a/components/esp32/deep_sleep.c b/components/esp32/deep_sleep.c index d1666affe..23d3f4b1f 100644 --- a/components/esp32/deep_sleep.c +++ b/components/esp32/deep_sleep.c @@ -21,13 +21,14 @@ #include "rom/rtc.h" #include "rom/uart.h" #include "soc/cpu.h" +#include "soc/rtc.h" #include "soc/rtc_cntl_reg.h" +#include "soc/rtc_io_reg.h" #include "soc/sens_reg.h" #include "soc/dport_reg.h" #include "driver/rtc_io.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" -#include "rtc.h" #include "sdkconfig.h" /** @@ -57,6 +58,7 @@ static const char* TAG = "deepsleep"; static uint32_t get_power_down_flags(); static void ext0_wakeup_prepare(); static void ext1_wakeup_prepare(); +static void timer_wakeup_prepare(); /* Wake from deep sleep stub See esp_deepsleep.h esp_wake_deep_sleep() comments for details. @@ -119,19 +121,6 @@ void IRAM_ATTR esp_deep_sleep_start() SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR_M, 0, SENS_FORCE_XPD_SAR_S); - // Configure pins for external wakeup - if (s_config.wakeup_triggers & EXT_EVENT0_TRIG_EN) { - ext0_wakeup_prepare(); - } - if (s_config.wakeup_triggers & EXT_EVENT1_TRIG_EN) { - ext1_wakeup_prepare(); - } - if (s_config.wakeup_triggers & SAR_TRIG_EN) { - SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN); - } - // TODO: move timer wakeup configuration into a similar function - // once rtc_sleep is opensourced. - // Flush UARTs so that output is not lost due to APB frequency change uart_tx_wait_idle(0); uart_tx_wait_idle(1); @@ -141,19 +130,27 @@ void IRAM_ATTR esp_deep_sleep_start() esp_set_deep_sleep_wake_stub(esp_wake_deep_sleep); } - rtc_set_cpu_freq(CPU_XTAL); - uint32_t cycle_h = 0; - uint32_t cycle_l = 0; - // For timer wakeup, calibrate clock source against main XTAL - // This is hardcoded to use 150kHz internal oscillator for now - if (s_config.sleep_duration > 0) { - uint32_t period = rtc_slowck_cali(CALI_RTC_MUX, 128); - rtc_usec2rtc(s_config.sleep_duration >> 32, s_config.sleep_duration & UINT32_MAX, - period, &cycle_h, &cycle_l); + // Configure pins for external wakeup + if (s_config.wakeup_triggers & RTC_EXT0_TRIG_EN) { + ext0_wakeup_prepare(); } + if (s_config.wakeup_triggers & RTC_EXT1_TRIG_EN) { + ext1_wakeup_prepare(); + } + // Enable ULP wakeup + if (s_config.wakeup_triggers & RTC_ULP_TRIG_EN) { + SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN); + } + // Configure timer wakeup + if ((s_config.wakeup_triggers & RTC_TIMER_TRIG_EN) && + s_config.sleep_duration > 0) { + timer_wakeup_prepare(); + } + // Enter deep sleep - rtc_slp_prep_lite(pd_flags, 0); - rtc_sleep(cycle_h, cycle_l, s_config.wakeup_triggers, 0); + rtc_sleep_config_t config = RTC_SLEEP_CONFIG_DEFAULT(pd_flags); + rtc_sleep_init(config); + rtc_sleep_start(s_config.wakeup_triggers, 0); // Because RTC is in a slower clock domain than the CPU, it // can take several CPU cycles for the sleep mode to start. while (1) { @@ -166,11 +163,11 @@ void system_deep_sleep(uint64_t) __attribute__((alias("esp_deep_sleep"))); esp_err_t esp_deep_sleep_enable_ulp_wakeup() { #ifdef CONFIG_ULP_COPROC_ENABLED - if(s_config.wakeup_triggers & RTC_EXT_EVENT0_TRIG_EN) { + if(s_config.wakeup_triggers & RTC_EXT0_TRIG_EN) { ESP_LOGE(TAG, "Conflicting wake-up trigger: ext0"); return ESP_ERR_INVALID_STATE; } - s_config.wakeup_triggers |= RTC_SAR_TRIG_EN; + s_config.wakeup_triggers |= RTC_ULP_TRIG_EN; return ESP_OK; #else return ESP_ERR_INVALID_STATE; @@ -179,14 +176,28 @@ esp_err_t esp_deep_sleep_enable_ulp_wakeup() esp_err_t esp_deep_sleep_enable_timer_wakeup(uint64_t time_in_us) { - s_config.wakeup_triggers |= RTC_TIMER_EXPIRE_EN; + s_config.wakeup_triggers |= RTC_TIMER_TRIG_EN; s_config.sleep_duration = time_in_us; return ESP_OK; } +static void timer_wakeup_prepare() +{ + // Do calibration if not using 32k XTAL + uint32_t period; + if (rtc_clk_slow_freq_get() != RTC_SLOW_FREQ_32K_XTAL) { + period = rtc_clk_cal(RTC_CAL_RTC_MUX, 128); + } else { + period = (uint32_t) ((1000000ULL /* us*Hz */ << RTC_CLK_CAL_FRACT) / 32768 /* Hz */); + } + uint64_t rtc_count_delta = rtc_time_us_to_slowclk(s_config.sleep_duration, period); + uint64_t cur_rtc_count = rtc_time_get(); + rtc_sleep_set_wakeup_time(cur_rtc_count + rtc_count_delta); +} + esp_err_t esp_deep_sleep_enable_touchpad_wakeup() { - if (s_config.wakeup_triggers & (RTC_EXT_EVENT0_TRIG_EN)) { + if (s_config.wakeup_triggers & (RTC_EXT0_TRIG_EN)) { ESP_LOGE(TAG, "Conflicting wake-up trigger: ext0"); return ESP_ERR_INVALID_STATE; } @@ -212,13 +223,13 @@ esp_err_t esp_deep_sleep_enable_ext0_wakeup(gpio_num_t gpio_num, int level) if (!RTC_GPIO_IS_VALID_GPIO(gpio_num)) { return ESP_ERR_INVALID_ARG; } - if (s_config.wakeup_triggers & (RTC_TOUCH_TRIG_EN | RTC_SAR_TRIG_EN)) { + if (s_config.wakeup_triggers & (RTC_TOUCH_TRIG_EN | RTC_ULP_TRIG_EN)) { ESP_LOGE(TAG, "Conflicting wake-up triggers: touch / ULP"); return ESP_ERR_INVALID_STATE; } s_config.ext0_rtc_gpio_num = rtc_gpio_desc[gpio_num].rtc_num; s_config.ext0_trigger_level = level; - s_config.wakeup_triggers |= RTC_EXT_EVENT0_TRIG_EN; + s_config.wakeup_triggers |= RTC_EXT0_TRIG_EN; return ESP_OK; } @@ -262,7 +273,7 @@ esp_err_t esp_deep_sleep_enable_ext1_wakeup(uint64_t mask, esp_ext1_wakeup_mode_ } s_config.ext1_rtc_gpio_mask = rtc_gpio_mask; s_config.ext1_trigger_mode = mode; - s_config.wakeup_triggers |= RTC_EXT_EVENT1_TRIG_EN; + s_config.wakeup_triggers |= RTC_EXT1_TRIG_EN; return ESP_OK; } @@ -333,15 +344,15 @@ esp_deep_sleep_wakeup_cause_t esp_deep_sleep_get_wakeup_cause() } uint32_t wakeup_cause = REG_GET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_CAUSE); - if (wakeup_cause & RTC_EXT_EVENT0_TRIG) { + if (wakeup_cause & RTC_EXT0_TRIG_EN) { return ESP_DEEP_SLEEP_WAKEUP_EXT0; - } else if (wakeup_cause & RTC_EXT_EVENT1_TRIG) { + } else if (wakeup_cause & RTC_EXT1_TRIG_EN) { return ESP_DEEP_SLEEP_WAKEUP_EXT1; - } else if (wakeup_cause & RTC_TIMER_EXPIRE) { + } else if (wakeup_cause & RTC_TIMER_TRIG_EN) { return ESP_DEEP_SLEEP_WAKEUP_TIMER; - } else if (wakeup_cause & RTC_TOUCH_TRIG) { + } else if (wakeup_cause & RTC_TOUCH_TRIG_EN) { return ESP_DEEP_SLEEP_WAKEUP_TOUCHPAD; - } else if (wakeup_cause & RTC_SAR_TRIG) { + } else if (wakeup_cause & RTC_ULP_TRIG_EN) { return ESP_DEEP_SLEEP_WAKEUP_ULP; } else { return ESP_DEEP_SLEEP_WAKEUP_UNDEFINED; @@ -388,9 +399,9 @@ static uint32_t get_power_down_flags() // RTC_PERIPH is needed for EXT0 wakeup. // If RTC_PERIPH is auto, and EXT0 isn't enabled, power down RTC_PERIPH. if (s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] == ESP_PD_OPTION_AUTO) { - if (s_config.wakeup_triggers & RTC_EXT_EVENT0_TRIG_EN) { + if (s_config.wakeup_triggers & RTC_EXT0_TRIG_EN) { s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] = ESP_PD_OPTION_ON; - } else if (s_config.wakeup_triggers & (RTC_TOUCH_TRIG_EN | RTC_SAR_TRIG_EN)) { + } else if (s_config.wakeup_triggers & (RTC_TOUCH_TRIG_EN | RTC_ULP_TRIG_EN)) { // In both rev. 0 and rev. 1 of ESP32, forcing power up of RTC_PERIPH // prevents ULP timer and touch FSMs from working correctly. s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] = ESP_PD_OPTION_OFF; @@ -404,15 +415,15 @@ static uint32_t get_power_down_flags() option_str[s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM]]); // Prepare flags based on the selected options - uint32_t pd_flags = DEEP_SLEEP_PD_NORMAL; + uint32_t pd_flags = RTC_SLEEP_PD_DIG; if (s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM] != ESP_PD_OPTION_ON) { - pd_flags |= DEEP_SLEEP_PD_RTC_FAST_MEM; + pd_flags |= RTC_SLEEP_PD_RTC_FAST_MEM; } if (s_config.pd_options[ESP_PD_DOMAIN_RTC_SLOW_MEM] != ESP_PD_OPTION_ON) { - pd_flags |= DEEP_SLEEP_PD_RTC_SLOW_MEM; + pd_flags |= RTC_SLEEP_PD_RTC_SLOW_MEM; } if (s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] != ESP_PD_OPTION_ON) { - pd_flags |= DEEP_SLEEP_PD_RTC_PERIPH; + pd_flags |= RTC_SLEEP_PD_RTC_PERIPH; } return pd_flags; } diff --git a/components/esp32/include/rom/rtc.h b/components/esp32/include/rom/rtc.h index 9bcd9bd7e..9ea3126a9 100644 --- a/components/esp32/include/rom/rtc.h +++ b/components/esp32/include/rom/rtc.h @@ -61,8 +61,11 @@ extern "C" { * RTC_CNTL_STORE7_REG FAST_RTC_MEMORY_CRC ************************************************************************************* */ + #define RTC_BOOT_TIME_LOW_REG RTC_CNTL_STORE2_REG #define RTC_BOOT_TIME_HIGH_REG RTC_CNTL_STORE3_REG +#define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG +#define RTC_APB_FREQ_REG RTC_CNTL_STORE5_REG #define RTC_ENTRY_ADDR_REG RTC_CNTL_STORE6_REG #define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG diff --git a/components/esp32/ld/esp32.common.ld b/components/esp32/ld/esp32.common.ld index 8d5a9c427..c57c23df6 100644 --- a/components/esp32/ld/esp32.common.ld +++ b/components/esp32/ld/esp32.common.ld @@ -88,8 +88,7 @@ SECTIONS *libesp32.a:heap_alloc_caps.o(.literal .text .literal.* .text.*) *libphy.a:(.literal .text .literal.* .text.*) *librtc.a:(.literal .text .literal.* .text.*) - *librtc_clk.a:(.literal .text .literal.* .text.*) - *librtc_pm.a:(.literal .text .literal.* .text.*) + *libsoc.a:(.literal .text .literal.* .text.*) *libpp.a:pp.o(.literal .text .literal.* .text.*) *libpp.a:lmac.o(.literal .text .literal.* .text.*) *libpp.a:wdev.o(.literal .text .literal.* .text.*) diff --git a/components/esp32/phy.h b/components/esp32/phy.h index c0affb36e..71c44cd3d 100644 --- a/components/esp32/phy.h +++ b/components/esp32/phy.h @@ -57,6 +57,11 @@ void phy_set_wifi_mode_only(bool wifi_only); */ void coex_bt_high_prio(void); +/** + * @brief Shutdown PHY and RF. + */ +void phy_close_rf(void); + #ifdef __cplusplus } #endif diff --git a/components/esp32/phy_init.c b/components/esp32/phy_init.c index 4facaf47a..071807924 100644 --- a/components/esp32/phy_init.c +++ b/components/esp32/phy_init.c @@ -21,6 +21,7 @@ #include "rom/ets_sys.h" #include "rom/rtc.h" +#include "soc/rtc.h" #include "soc/dport_reg.h" #include "esp_err.h" @@ -34,7 +35,6 @@ #ifdef CONFIG_PHY_ENABLED #include "phy.h" #include "phy_init_data.h" -#include "rtc.h" #include "esp_coexist.h" static const char* TAG = "phy_init"; diff --git a/components/esp32/rtc.h b/components/esp32/rtc.h deleted file mode 100644 index e1262a1ca..000000000 --- a/components/esp32/rtc.h +++ /dev/null @@ -1,146 +0,0 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -/** - * @file rtc.h - * @brief Declarations of APIs provided by librtc.a - * - * This file is not in the include directory of esp32 component, so it is not - * part of the public API. As the source code of librtc.a is gradually moved - * into the ESP-IDF, some of these APIs will be exposed to applications. - * - * For now, only esp_deep_sleep function declared in esp_deepsleep.h - * is part of public API. - */ - -#pragma once -#include -#include -#include "soc/soc.h" - -#ifdef __cplusplus -extern "C" { -#endif - - -typedef enum{ - XTAL_40M = 40, - XTAL_26M = 26, - XTAL_24M = 24, - XTAL_AUTO = 0 -} xtal_freq_t; - -typedef enum{ - CPU_XTAL = 0, - CPU_80M = 1, - CPU_160M = 2, - CPU_240M = 3, - CPU_2M = 4 -} cpu_freq_t; - -typedef enum { - CALI_RTC_MUX = 0, - CALI_8MD256 = 1, - CALI_32K_XTAL = 2 -} cali_clk_t; - -/** - * This function must be called to initialize RTC library - * @param xtal_freq Frequency of main crystal - */ -void rtc_init_lite(xtal_freq_t xtal_freq); - -/** - * Switch CPU frequency - * @param cpu_freq new CPU frequency - */ -void rtc_set_cpu_freq(cpu_freq_t cpu_freq); - -/** - * @brief Return RTC slow clock's period - * @param cali_clk clock to calibrate - * @param slow_clk_cycles number of slow clock cycles to average - * @param xtal_freq chip's main XTAL freq - * @return average slow clock period in microseconds, Q13.19 fixed point format - */ -uint32_t rtc_slowck_cali(cali_clk_t cali_clk, uint32_t slow_clk_cycles); - -/** - * @brief Convert from microseconds to slow clock cycles - * @param time_in_us_h Time in microseconds, higher 32 bit part - * @param time_in_us_l Time in microseconds, lower 32 bit part - * @param slow_clk_period Period of slow clock in microseconds, Q13.19 fixed point format (as returned by rtc_slowck_cali). - * @param[out] cylces_h output, higher 32 bit part of number of slow clock cycles - * @param[out] cycles_l output, lower 32 bit part of number of slow clock cycles - */ -void rtc_usec2rtc(uint32_t time_in_us_h, uint32_t time_in_us_l, uint32_t slow_clk_period, uint32_t *cylces_h, uint32_t *cycles_l); - - -#define DEEP_SLEEP_PD_NORMAL BIT(0) /*!< Base deep sleep mode */ -#define DEEP_SLEEP_PD_RTC_PERIPH BIT(1) /*!< Power down RTC peripherals */ -#define DEEP_SLEEP_PD_RTC_SLOW_MEM BIT(2) /*!< Power down RTC SLOW memory */ -#define DEEP_SLEEP_PD_RTC_FAST_MEM BIT(3) /*!< Power down RTC FAST memory */ - -/** - * @brief Prepare for entering sleep mode - * @param deep_slp DEEP_SLEEP_PD_ flags combined with OR (DEEP_SLEEP_PD_NORMAL must be included) - * @param cpu_lp_mode for deep sleep, should be 0 - */ -void rtc_slp_prep_lite(uint32_t deep_slp, uint32_t cpu_lp_mode); - - -#define RTC_EXT_EVENT0_TRIG BIT(0) -#define RTC_EXT_EVENT1_TRIG BIT(1) -#define RTC_GPIO_TRIG BIT(2) -#define RTC_TIMER_EXPIRE BIT(3) -#define RTC_SDIO_TRIG BIT(4) -#define RTC_MAC_TRIG BIT(5) -#define RTC_UART0_TRIG BIT(6) -#define RTC_UART1_TRIG BIT(7) -#define RTC_TOUCH_TRIG BIT(8) -#define RTC_SAR_TRIG BIT(9) -#define RTC_BT_TRIG BIT(10) - - -#define RTC_EXT_EVENT0_TRIG_EN RTC_EXT_EVENT0_TRIG -#define RTC_EXT_EVENT1_TRIG_EN RTC_EXT_EVENT1_TRIG -#define RTC_GPIO_TRIG_EN RTC_GPIO_TRIG -#define RTC_TIMER_EXPIRE_EN RTC_TIMER_EXPIRE -#define RTC_SDIO_TRIG_EN RTC_SDIO_TRIG -#define RTC_MAC_TRIG_EN RTC_MAC_TRIG -#define RTC_UART0_TRIG_EN RTC_UART0_TRIG -#define RTC_UART1_TRIG_EN RTC_UART1_TRIG -#define RTC_TOUCH_TRIG_EN RTC_TOUCH_TRIG -#define RTC_SAR_TRIG_EN RTC_SAR_TRIG -#define RTC_BT_TRIG_EN RTC_BT_TRIG - -/** - * @brief Enter sleep mode for given number of cycles - * @param cycles_h higher 32 bit part of number of slow clock cycles - * @param cycles_l lower 32 bit part of number of slow clock cycles - * @param wakeup_opt wake up reason to enable (RTC_xxx_EN flags combined with OR) - * @param reject_opt reserved, should be 0 - * @return TBD - */ -uint32_t rtc_sleep(uint32_t cycles_h, uint32_t cycles_l, uint32_t wakeup_opt, uint32_t reject_opt); - -/** - * @brief Shutdown PHY and RF. TODO: convert this function to another one. - */ -void phy_close_rf(void); - -#ifdef __cplusplus -} -#endif - diff --git a/components/esp32/system_api.c b/components/esp32/system_api.c index 79ec1a396..028513718 100644 --- a/components/esp32/system_api.c +++ b/components/esp32/system_api.c @@ -29,10 +29,10 @@ #include "soc/timer_group_reg.h" #include "soc/timer_group_struct.h" #include "soc/cpu.h" +#include "soc/rtc.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "freertos/xtensa_api.h" -#include "rtc.h" static const char* TAG = "system_api"; @@ -224,7 +224,7 @@ void IRAM_ATTR esp_restart_noos() REG_WRITE(DPORT_PERIP_RST_EN_REG, 0); // Set CPU back to XTAL source, no PLL, same as hard reset - rtc_set_cpu_freq(CPU_XTAL); + rtc_clk_cpu_freq_set(RTC_CPU_FREQ_XTAL); // Reset CPUs if (core_id == 0) { diff --git a/components/soc/component.mk b/components/soc/component.mk new file mode 100755 index 000000000..1d5b621a9 --- /dev/null +++ b/components/soc/component.mk @@ -0,0 +1,5 @@ +# currently the only SoC supported; to be moved into Kconfig +SOC_NAME := esp32 + +COMPONENT_SRCDIRS := $(SOC_NAME) +COMPONENT_ADD_INCLUDEDIRS := $(SOC_NAME)/include diff --git a/components/esp32/brownout.c b/components/soc/esp32/brownout.c similarity index 100% rename from components/esp32/brownout.c rename to components/soc/esp32/brownout.c diff --git a/components/esp32/cpu_util.c b/components/soc/esp32/cpu_util.c similarity index 100% rename from components/esp32/cpu_util.c rename to components/soc/esp32/cpu_util.c diff --git a/components/soc/esp32/i2c_apll.h b/components/soc/esp32/i2c_apll.h new file mode 100644 index 000000000..935810afa --- /dev/null +++ b/components/soc/esp32/i2c_apll.h @@ -0,0 +1,136 @@ +// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +/** + * @file i2c_apll.h + * @brief Register definitions for audio PLL (APLL) + * + * This file lists register fields of APLL, located on an internal configuration + * bus. These definitions are used via macros defined in i2c_rtc_clk.h, by + * rtc_clk_apll_enable function in rtc_clk.c. + */ + +#define I2C_APLL 0X6D +#define I2C_APLL_HOSTID 3 + +#define I2C_APLL_IR_CAL_DELAY 0 +#define I2C_APLL_IR_CAL_DELAY_MSB 3 +#define I2C_APLL_IR_CAL_DELAY_LSB 0 + +#define I2C_APLL_IR_CAL_RSTB 0 +#define I2C_APLL_IR_CAL_RSTB_MSB 4 +#define I2C_APLL_IR_CAL_RSTB_LSB 4 + +#define I2C_APLL_IR_CAL_START 0 +#define I2C_APLL_IR_CAL_START_MSB 5 +#define I2C_APLL_IR_CAL_START_LSB 5 + +#define I2C_APLL_IR_CAL_UNSTOP 0 +#define I2C_APLL_IR_CAL_UNSTOP_MSB 6 +#define I2C_APLL_IR_CAL_UNSTOP_LSB 6 + +#define I2C_APLL_OC_ENB_FCAL 0 +#define I2C_APLL_OC_ENB_FCAL_MSB 7 +#define I2C_APLL_OC_ENB_FCAL_LSB 7 + +#define I2C_APLL_IR_CAL_EXT_CAP 1 +#define I2C_APLL_IR_CAL_EXT_CAP_MSB 4 +#define I2C_APLL_IR_CAL_EXT_CAP_LSB 0 + +#define I2C_APLL_IR_CAL_ENX_CAP 1 +#define I2C_APLL_IR_CAL_ENX_CAP_MSB 5 +#define I2C_APLL_IR_CAL_ENX_CAP_LSB 5 + +#define I2C_APLL_OC_LBW 1 +#define I2C_APLL_OC_LBW_MSB 6 +#define I2C_APLL_OC_LBW_LSB 6 + +#define I2C_APLL_IR_CAL_CK_DIV 2 +#define I2C_APLL_IR_CAL_CK_DIV_MSB 3 +#define I2C_APLL_IR_CAL_CK_DIV_LSB 0 + +#define I2C_APLL_OC_DCHGP 2 +#define I2C_APLL_OC_DCHGP_MSB 6 +#define I2C_APLL_OC_DCHGP_LSB 4 + +#define I2C_APLL_OC_ENB_VCON 2 +#define I2C_APLL_OC_ENB_VCON_MSB 7 +#define I2C_APLL_OC_ENB_VCON_LSB 7 + +#define I2C_APLL_OR_CAL_CAP 3 +#define I2C_APLL_OR_CAL_CAP_MSB 4 +#define I2C_APLL_OR_CAL_CAP_LSB 0 + +#define I2C_APLL_OR_CAL_UDF 3 +#define I2C_APLL_OR_CAL_UDF_MSB 5 +#define I2C_APLL_OR_CAL_UDF_LSB 5 + +#define I2C_APLL_OR_CAL_OVF 3 +#define I2C_APLL_OR_CAL_OVF_MSB 6 +#define I2C_APLL_OR_CAL_OVF_LSB 6 + +#define I2C_APLL_OR_CAL_END 3 +#define I2C_APLL_OR_CAL_END_MSB 7 +#define I2C_APLL_OR_CAL_END_LSB 7 + +#define I2C_APLL_OR_OUTPUT_DIV 4 +#define I2C_APLL_OR_OUTPUT_DIV_MSB 4 +#define I2C_APLL_OR_OUTPUT_DIV_LSB 0 + +#define I2C_APLL_OC_TSCHGP 4 +#define I2C_APLL_OC_TSCHGP_MSB 6 +#define I2C_APLL_OC_TSCHGP_LSB 6 + +#define I2C_APLL_EN_FAST_CAL 4 +#define I2C_APLL_EN_FAST_CAL_MSB 7 +#define I2C_APLL_EN_FAST_CAL_LSB 7 + +#define I2C_APLL_OC_DHREF_SEL 5 +#define I2C_APLL_OC_DHREF_SEL_MSB 1 +#define I2C_APLL_OC_DHREF_SEL_LSB 0 + +#define I2C_APLL_OC_DLREF_SEL 5 +#define I2C_APLL_OC_DLREF_SEL_MSB 3 +#define I2C_APLL_OC_DLREF_SEL_LSB 2 + +#define I2C_APLL_SDM_DITHER 5 +#define I2C_APLL_SDM_DITHER_MSB 4 +#define I2C_APLL_SDM_DITHER_LSB 4 + +#define I2C_APLL_SDM_STOP 5 +#define I2C_APLL_SDM_STOP_MSB 5 +#define I2C_APLL_SDM_STOP_LSB 5 + +#define I2C_APLL_SDM_RSTB 5 +#define I2C_APLL_SDM_RSTB_MSB 6 +#define I2C_APLL_SDM_RSTB_LSB 6 + +#define I2C_APLL_OC_DVDD 6 +#define I2C_APLL_OC_DVDD_MSB 4 +#define I2C_APLL_OC_DVDD_LSB 0 + +#define I2C_APLL_DSDM2 7 +#define I2C_APLL_DSDM2_MSB 5 +#define I2C_APLL_DSDM2_LSB 0 + +#define I2C_APLL_DSDM1 8 +#define I2C_APLL_DSDM1_MSB 7 +#define I2C_APLL_DSDM1_LSB 0 + +#define I2C_APLL_DSDM0 9 +#define I2C_APLL_DSDM0_MSB 7 +#define I2C_APLL_DSDM0_LSB 0 + diff --git a/components/soc/esp32/i2c_bbpll.h b/components/soc/esp32/i2c_bbpll.h new file mode 100644 index 000000000..6889bc732 --- /dev/null +++ b/components/soc/esp32/i2c_bbpll.h @@ -0,0 +1,208 @@ +// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +/** + * @file i2c_apll.h + * @brief Register definitions for digital PLL (BBPLL) + * + * This file lists register fields of BBPLL, located on an internal configuration + * bus. These definitions are used via macros defined in i2c_rtc_clk.h, by + * rtc_clk_cpu_freq_set function in rtc_clk.c. + */ + +#define I2C_BBPLL 0x66 +#define I2C_BBPLL_HOSTID 4 + +#define I2C_BBPLL_IR_CAL_DELAY 0 +#define I2C_BBPLL_IR_CAL_DELAY_MSB 3 +#define I2C_BBPLL_IR_CAL_DELAY_LSB 0 + +#define I2C_BBPLL_IR_CAL_CK_DIV 0 +#define I2C_BBPLL_IR_CAL_CK_DIV_MSB 7 +#define I2C_BBPLL_IR_CAL_CK_DIV_LSB 4 + +#define I2C_BBPLL_IR_CAL_EXT_CAP 1 +#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB 3 +#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB 0 + +#define I2C_BBPLL_IR_CAL_ENX_CAP 1 +#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB 4 +#define I2C_BBPLL_IR_CAL_ENX_CAP_LSB 4 + +#define I2C_BBPLL_IR_CAL_RSTB 1 +#define I2C_BBPLL_IR_CAL_RSTB_MSB 5 +#define I2C_BBPLL_IR_CAL_RSTB_LSB 5 + +#define I2C_BBPLL_IR_CAL_START 1 +#define I2C_BBPLL_IR_CAL_START_MSB 6 +#define I2C_BBPLL_IR_CAL_START_LSB 6 + +#define I2C_BBPLL_IR_CAL_UNSTOP 1 +#define I2C_BBPLL_IR_CAL_UNSTOP_MSB 7 +#define I2C_BBPLL_IR_CAL_UNSTOP_LSB 7 + +#define I2C_BBPLL_OC_REF_DIV 2 +#define I2C_BBPLL_OC_REF_DIV_MSB 3 +#define I2C_BBPLL_OC_REF_DIV_LSB 0 + +#define I2C_BBPLL_OC_DIV_10_8 2 +#define I2C_BBPLL_OC_DIV_10_8_MSB 6 +#define I2C_BBPLL_OC_DIV_10_8_LSB 4 + +#define I2C_BBPLL_OC_LREF 2 +#define I2C_BBPLL_OC_LREF_MSB 7 +#define I2C_BBPLL_OC_LREF_LSB 7 + +#define I2C_BBPLL_OC_DIV_7_0 3 +#define I2C_BBPLL_OC_DIV_7_0_MSB 7 +#define I2C_BBPLL_OC_DIV_7_0_LSB 0 + +#define I2C_BBPLL_OC_ENB_FCAL 4 +#define I2C_BBPLL_OC_ENB_FCAL_MSB 0 +#define I2C_BBPLL_OC_ENB_FCAL_LSB 0 + +#define I2C_BBPLL_OC_DCHGP 4 +#define I2C_BBPLL_OC_DCHGP_MSB 3 +#define I2C_BBPLL_OC_DCHGP_LSB 1 + +#define I2C_BBPLL_OC_DHREF_SEL 4 +#define I2C_BBPLL_OC_DHREF_SEL_MSB 5 +#define I2C_BBPLL_OC_DHREF_SEL_LSB 4 + +#define I2C_BBPLL_OC_DLREF_SEL 4 +#define I2C_BBPLL_OC_DLREF_SEL_MSB 7 +#define I2C_BBPLL_OC_DLREF_SEL_LSB 6 + +#define I2C_BBPLL_OC_DCUR 5 +#define I2C_BBPLL_OC_DCUR_MSB 2 +#define I2C_BBPLL_OC_DCUR_LSB 0 + +#define I2C_BBPLL_OC_BST_DIV 5 +#define I2C_BBPLL_OC_BST_DIV_MSB 3 +#define I2C_BBPLL_OC_BST_DIV_LSB 3 + +#define I2C_BBPLL_OC_BST_E2C 5 +#define I2C_BBPLL_OC_BST_E2C_MSB 4 +#define I2C_BBPLL_OC_BST_E2C_LSB 4 + +#define I2C_BBPLL_OC_TSCHGP 5 +#define I2C_BBPLL_OC_TSCHGP_MSB 5 +#define I2C_BBPLL_OC_TSCHGP_LSB 5 + +#define I2C_BBPLL_OC_BW 5 +#define I2C_BBPLL_OC_BW_MSB 7 +#define I2C_BBPLL_OC_BW_LSB 6 + +#define I2C_BBPLL_OR_LOCK1 6 +#define I2C_BBPLL_OR_LOCK1_MSB 0 +#define I2C_BBPLL_OR_LOCK1_LSB 0 + +#define I2C_BBPLL_OR_LOCK2 6 +#define I2C_BBPLL_OR_LOCK2_MSB 1 +#define I2C_BBPLL_OR_LOCK2_LSB 1 + +#define I2C_BBPLL_OR_CAL_CAP 7 +#define I2C_BBPLL_OR_CAL_CAP_MSB 3 +#define I2C_BBPLL_OR_CAL_CAP_LSB 0 + +#define I2C_BBPLL_OR_CAL_UDF 7 +#define I2C_BBPLL_OR_CAL_UDF_MSB 4 +#define I2C_BBPLL_OR_CAL_UDF_LSB 4 + +#define I2C_BBPLL_OR_CAL_OVF 7 +#define I2C_BBPLL_OR_CAL_OVF_MSB 5 +#define I2C_BBPLL_OR_CAL_OVF_LSB 5 + +#define I2C_BBPLL_OR_CAL_END 7 +#define I2C_BBPLL_OR_CAL_END_MSB 6 +#define I2C_BBPLL_OR_CAL_END_LSB 6 + +#define I2C_BBPLL_BBADC_DELAY1 8 +#define I2C_BBPLL_BBADC_DELAY1_MSB 1 +#define I2C_BBPLL_BBADC_DELAY1_LSB 0 + +#define I2C_BBPLL_BBADC_DELAY2 8 +#define I2C_BBPLL_BBADC_DELAY2_MSB 3 +#define I2C_BBPLL_BBADC_DELAY2_LSB 2 + +#define I2C_BBPLL_BBADC_DELAY3 8 +#define I2C_BBPLL_BBADC_DELAY3_MSB 5 +#define I2C_BBPLL_BBADC_DELAY3_LSB 4 + +#define I2C_BBPLL_BBADC_DELAY4 8 +#define I2C_BBPLL_BBADC_DELAY4_MSB 7 +#define I2C_BBPLL_BBADC_DELAY4_LSB 6 + +#define I2C_BBPLL_BBADC_DELAY5 9 +#define I2C_BBPLL_BBADC_DELAY5_MSB 1 +#define I2C_BBPLL_BBADC_DELAY5_LSB 0 + +#define I2C_BBPLL_BBADC_DELAY6 9 +#define I2C_BBPLL_BBADC_DELAY6_MSB 3 +#define I2C_BBPLL_BBADC_DELAY6_LSB 2 + +#define I2C_BBPLL_BBADC_DSMP 9 +#define I2C_BBPLL_BBADC_DSMP_MSB 7 +#define I2C_BBPLL_BBADC_DSMP_LSB 4 + +#define I2C_BBPLL_DTEST 10 +#define I2C_BBPLL_DTEST_MSB 1 +#define I2C_BBPLL_DTEST_LSB 0 + +#define I2C_BBPLL_ENT_ADC 10 +#define I2C_BBPLL_ENT_ADC_MSB 3 +#define I2C_BBPLL_ENT_ADC_LSB 2 + +#define I2C_BBPLL_BBADC_DIV 10 +#define I2C_BBPLL_BBADC_DIV_MSB 5 +#define I2C_BBPLL_BBADC_DIV_LSB 4 + +#define I2C_BBPLL_ENT_PLL 10 +#define I2C_BBPLL_ENT_PLL_MSB 6 +#define I2C_BBPLL_ENT_PLL_LSB 6 + +#define I2C_BBPLL_OC_ENB_VCON 10 +#define I2C_BBPLL_OC_ENB_VCON_MSB 7 +#define I2C_BBPLL_OC_ENB_VCON_LSB 7 + +#define I2C_BBPLL_DIV_DAC 11 +#define I2C_BBPLL_DIV_DAC_MSB 0 +#define I2C_BBPLL_DIV_DAC_LSB 0 + +#define I2C_BBPLL_DIV_CPU 11 +#define I2C_BBPLL_DIV_CPU_MSB 1 +#define I2C_BBPLL_DIV_CPU_LSB 1 + +#define I2C_BBPLL_BBADC_INPUT_SHORT 11 +#define I2C_BBPLL_BBADC_INPUT_SHORT_MSB 2 +#define I2C_BBPLL_BBADC_INPUT_SHORT_LSB 2 + +#define I2C_BBPLL_BBADC_CAL_9_8 11 +#define I2C_BBPLL_BBADC_CAL_9_8_MSB 4 +#define I2C_BBPLL_BBADC_CAL_9_8_LSB 3 + +#define I2C_BBPLL_BBADC_DCM 11 +#define I2C_BBPLL_BBADC_DCM_MSB 6 +#define I2C_BBPLL_BBADC_DCM_LSB 5 + +#define I2C_BBPLL_ENDIV5 11 +#define I2C_BBPLL_ENDIV5_MSB 7 +#define I2C_BBPLL_ENDIV5_LSB 7 + +#define I2C_BBPLL_BBADC_CAL_7_0 12 +#define I2C_BBPLL_BBADC_CAL_7_0_MSB 7 +#define I2C_BBPLL_BBADC_CAL_7_0_LSB 0 + diff --git a/components/soc/esp32/i2c_rtc_clk.h b/components/soc/esp32/i2c_rtc_clk.h new file mode 100644 index 000000000..a26b52100 --- /dev/null +++ b/components/soc/esp32/i2c_rtc_clk.h @@ -0,0 +1,48 @@ +// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "i2c_apll.h" +#include "i2c_bbpll.h" + +/* Analog function control register */ +#define ANA_CONFIG_REG 0x6000E044 +#define ANA_CONFIG_S (8) +#define ANA_CONFIG_M (0x3FF) +/* Clear to enable APLL */ +#define I2C_APLL_M (BIT(14)) +/* Clear to enable BBPLL */ +#define I2C_BBPLL_M (BIT(17)) + +/* ROM functions which read/write internal control bus */ +uint8_t rom_i2c_readReg(uint8_t block, uint8_t host_id, uint8_t reg_add); +uint8_t rom_i2c_readReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb); +void rom_i2c_writeReg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data); +void rom_i2c_writeReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data); + +/* Convenience macros for the above functions, these use register definitions + * from i2c_apll.h/i2c_bbpll.h header files. + */ +#define I2C_WRITEREG_MASK_RTC(block, reg_add, indata) \ + rom_i2c_writeReg_Mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB, indata) + +#define I2C_READREG_MASK_RTC(block, reg_add) \ + rom_i2c_readReg_Mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB) + +#define I2C_WRITEREG_RTC(block, reg_add, indata) \ + rom_i2c_writeReg(block, block##_HOSTID, reg_add, indata) + +#define I2C_READREG_RTC(block, reg_add) \ + rom_i2c_readReg(block, block##_HOSTID, reg_add) diff --git a/components/esp32/include/esp_brownout.h b/components/soc/esp32/include/esp_brownout.h similarity index 100% rename from components/esp32/include/esp_brownout.h rename to components/soc/esp32/include/esp_brownout.h diff --git a/components/soc/esp32/include/soc/bb_reg.h b/components/soc/esp32/include/soc/bb_reg.h old mode 100755 new mode 100644 index 0b52f66ae..fca84deb1 --- a/components/soc/esp32/include/soc/bb_reg.h +++ b/components/soc/esp32/include/soc/bb_reg.h @@ -15,88 +15,20 @@ #ifndef _SOC_BB_REG_H_ #define _SOC_BB_REG_H_ -#define apb_bb_offset 0x6001c000 +/* Some of the baseband control registers. + * PU/PD fields defined here are used in sleep related functions. + */ -#define BB_DLY apb_bb_offset + 0x00009b00 // reg 00 -#define BB_TEST apb_bb_offset + 0x00009b08 // reg 02 -#define BB_TM1 apb_bb_offset + 0x00009b0c // reg 03 -#define BB_TM_CNTL apb_bb_offset + 0x00009b14 // reg 05 -#define BB_DEL_CNTL apb_bb_offset + 0x00009b28 // reg 10 -#define BB_PARAL_CNTL apb_bb_offset + 0x00009b2c // reg 11 -#define BB_FSM1 apb_bb_offset + 0x00009b44 // reg 17 -#define BB_MXG apb_bb_offset + 0x00009b48 // reg 18 -#define BB_MNOF apb_bb_offset + 0x00009b4c // reg 19 -#define BB_SIZE apb_bb_offset + 0x00009b50 // reg 20 -#define BB_TM3a apb_bb_offset + 0x00009b54 // reg 21 -#define BB_TM4a apb_bb_offset + 0x00009b58 // reg 22 -#define BB_GAIN apb_bb_offset + 0x00009b5c // reg 23 -#define BB_CNTL apb_bb_offset + 0x00009b60 // reg 24 -#define BB_CAD apb_bb_offset + 0x00009b64 // reg 25 -#define BB_DET apb_bb_offset + 0x00009b68 // reg 26 -#define BB_DETL apb_bb_offset + 0x00009b6c // reg 27 +#define BBPD_CTRL (DR_REG_BB_BASE + 0x0054) +#define BB_FFT_FORCE_PU (BIT(3)) +#define BB_FFT_FORCE_PU_S 3 +#define BB_FFT_FORCE_PD (BIT(2)) +#define BB_FFT_FORCE_PD_S 2 +#define BB_DC_EST_FORCE_PU (BIT(1)) +#define BB_DC_EST_FORCE_PU_S 1 +#define BB_DC_EST_FORCE_PD (BIT(0)) +#define BB_DC_EST_FORCE_PD_S 0 -#define BB_MASK_PCLL apb_bb_offset + 0x00009d08 // reg 66 -#define BB_MASK_PCLH apb_bb_offset + 0x00009d0c // reg 67 -#define BB_RX_CTRL4 apb_bb_offset + 0x00009d10 // reg 68 -#define BB_RX_CTRL apb_bb_offset + 0x00009d1c // reg 71 -#define BB_RX_CTRL2 apb_bb_offset + 0x00009d20 // reg 72 -#define BB_RX_CTRL3 apb_bb_offset + 0x00009d24 // reg 73 -#define BB_DEL4 apb_bb_offset + 0x00009d40 // reg 80 -#define BB_TM5 apb_bb_offset + 0x00009d44 // reg 81 -#define BB_TM6 apb_bb_offset + 0x00009d48 // reg 82 -#define BB_PMCTRL apb_bb_offset + 0x00009d4c // reg 83 -#define BB_PWR apb_bb_offset + 0x00009d68 // reg 90 -#define BB_BCTRL2 apb_bb_offset + 0x00009d70 // reg 92 - -#define BB_MASK_PL apb_bb_offset + 0x00009884 // reg 97 -#define BB_MASK_PCHL apb_bb_offset + 0x00009888 // reg 98 -#define BB_MASK_PCHH apb_bb_offset + 0x0000988c // reg 99 - -#define BB_MASK_CL apb_bb_offset + 0x0000989c // reg 103 -#define BB_TONE apb_bb_offset + 0x000098a0 // reg 104 -#define BB_MASK_CH apb_bb_offset + 0x000098d4 // reg 117 -#define BB_SER apb_bb_offset + 0x000098ec // reg 123 -#define BB_GN_TB apb_bb_offset + 0x00009e00 // reg 128 - -#define BB_MODE apb_bb_offset + 0x00009c00 // reg 640 -#define BB_TXCTRL apb_bb_offset + 0x00009c04 // reg 641 -#define BB_BCTRL3 apb_bb_offset + 0x00009c08 // reg 642 -#define BB_BCTRL apb_bb_offset + 0x00009c28 // reg 650 -#define BB_SMCTRL apb_bb_offset + 0x00009c48 // reg 658 -#define BB_SMCTRL2 apb_bb_offset + 0x00009c4C // reg 659 -#define BB_TXCNT apb_bb_offset + 0x00009c58 // reg 662 -#define BB_RXCTRL apb_bb_offset + 0x00009c68 // reg 666 - -#define BB_TXGAIN apb_bb_offset + 0x00009900 // reg 704 - -#define BB_RXS_CNTL apb_bb_offset + 0x00009988 // reg 738 -#define BB_MASK2_PCLL apb_bb_offset + 0x000099a8 // reg 746 -#define BB_MASK2_PCLH apb_bb_offset + 0x000099ac // reg 747 -#define BB_MASK_PH apb_bb_offset + 0x000099b0 // reg 748 -#define BB_MASK2_PCHL apb_bb_offset + 0x000099b8 // reg 750 -#define BB_MASK2_PCHH apb_bb_offset + 0x000099bc // reg 751 -// -#define BB_TX_TONE_CNTL apb_bb_offset + 0x000099f0 // reg 764 -#define BB_ADD_CNTL0 apb_bb_offset + 0x00009a28 // reg 778 -#define BB_ADD_CNTL2 apb_bb_offset + 0x00009a2c // reg 779 -#define BB_GAIN_CNTL0 apb_bb_offset + 0x00009a34 // reg 781 -#define BB_GAIN_CNTL1 apb_bb_offset + 0x00009a38 // reg 782 -#define BB_GAIN_CNTL2 apb_bb_offset + 0x00009a3c // reg 783 -#define BB_AGCMEM_CTRL apb_bb_offset + 0x00009a68 // reg 794 - -#define BB_11B_RECORD apb_bb_offset + 0x00009808 // reg 802 -#define BB_FILTER_CNTL apb_bb_offset + 0x0000980c // reg 803 -#define BB_ANALOG_CTRL1 apb_bb_offset + 0x00009838 -#define BB_ANALOG_CTRL2 apb_bb_offset + 0x0000983c //reg 815 -#define BB_ANALOG_CTRL3 apb_bb_offset + 0x00009840 //reg 816 -#define BB_RFCFG_CTRL0 apb_bb_offset + 0x00009844 //reg 817 -#define BB_RFCFG_CTRL1 apb_bb_offset + 0x00009848 //reg 818 - -#define BB_ADD_CNTL1 apb_bb_offset + 0x00009860 //reg824 -#define BB_PA_CNTL apb_bb_offset + 0x00009864 //reg825 -#define BB_RFCFG_CTRL2 apb_bb_offset + 0x0000986c //reg827 -#define BB_RXDEL_CTRL apb_bb_offset + 0x00009d18 -#define BB_RXLENGTH_CTRL apb_bb_offset + 0x00009d1c #endif /* _SOC_BB_REG_H_ */ diff --git a/components/soc/esp32/include/soc/boot_mode.h b/components/soc/esp32/include/soc/boot_mode.h old mode 100755 new mode 100644 diff --git a/components/soc/esp32/include/soc/fe_reg.h b/components/soc/esp32/include/soc/fe_reg.h new file mode 100644 index 000000000..f8c2ce58f --- /dev/null +++ b/components/soc/esp32/include/soc/fe_reg.h @@ -0,0 +1,33 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "soc/soc.h" + +/* Some of the RF frontend control registers. + * PU/PD fields defined here are used in sleep related functions. + */ + +#define FE_GEN_CTRL (DR_REG_FE_BASE + 0x0090) +#define FE_IQ_EST_FORCE_PU (BIT(5)) +#define FE_IQ_EST_FORCE_PU_S 5 +#define FE_IQ_EST_FORCE_PD (BIT(4)) +#define FE_IQ_EST_FORCE_PD_S 4 + +#define FE2_TX_INTERP_CTRL (DR_REG_FE2_BASE + 0x00f0) +#define FE2_TX_INF_FORCE_PU (BIT(10)) +#define FE2_TX_INF_FORCE_PU_S 10 +#define FE2_TX_INF_FORCE_PD (BIT(9)) +#define FE2_TX_INF_FORCE_PD_S 9 diff --git a/components/soc/esp32/include/soc/nrx_reg.h b/components/soc/esp32/include/soc/nrx_reg.h new file mode 100644 index 000000000..cd13319c9 --- /dev/null +++ b/components/soc/esp32/include/soc/nrx_reg.h @@ -0,0 +1,39 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "soc/soc.h" + +/* Some of the WiFi RX control registers. + * PU/PD fields defined here are used in sleep related functions. + */ + +#define NRXPD_CTRL (DR_REG_NRX_BASE + 0x00d4) +#define NRX_CHAN_EST_FORCE_PU (BIT(7)) +#define NRX_CHAN_EST_FORCE_PU_S 7 +#define NRX_CHAN_EST_FORCE_PD (BIT(6)) +#define NRX_CHAN_EST_FORCE_PD_S 6 +#define NRX_RX_ROT_FORCE_PU (BIT(5)) +#define NRX_RX_ROT_FORCE_PU_S 5 +#define NRX_RX_ROT_FORCE_PD (BIT(4)) +#define NRX_RX_ROT_FORCE_PD_S 4 +#define NRX_VIT_FORCE_PU (BIT(3)) +#define NRX_VIT_FORCE_PU_S 3 +#define NRX_VIT_FORCE_PD (BIT(2)) +#define NRX_VIT_FORCE_PD_S 2 +#define NRX_DEMAP_FORCE_PU (BIT(1)) +#define NRX_DEMAP_FORCE_PU_S 1 +#define NRX_DEMAP_FORCE_PD (BIT(0)) +#define NRX_DEMAP_FORCE_PD_S 0 diff --git a/components/soc/esp32/include/soc/rtc.h b/components/soc/esp32/include/soc/rtc.h new file mode 100644 index 000000000..aecf76bec --- /dev/null +++ b/components/soc/esp32/include/soc/rtc.h @@ -0,0 +1,496 @@ +// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#include +#include +#include +#include "soc/soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @file rtc.h + * @brief Low-level RTC power, clock, and sleep functions. + * + * Functions in this file facilitate configuration of ESP32's RTC_CNTL peripheral. + * RTC_CNTL peripheral handles many functions: + * - enables/disables clocks and power to various parts of the chip; this is + * done using direct register access (forcing power up or power down) or by + * allowing state machines to control power and clocks automatically + * - handles sleep and wakeup functions + * - maintains a 48-bit counter which can be used for timekeeping + * + * These functions are not thread safe, and should not be viewed as high level + * APIs. For example, while this file provides a function which can switch + * CPU frequency, this function is on its own is not sufficient to implement + * frequency switching in ESP-IDF context: some coordination with RTOS, + * peripheral drivers, and WiFi/BT stacks is also required. + * + * These functions will normally not be used in applications directly. + * ESP-IDF provides, or will provide, drivers and other facilities to use + * RTC subsystem functionality. + * + * The functions are loosely split into the following groups: + * - rtc_clk: clock switching, calibration + * - rtc_time: reading RTC counter, conversion between counter values and time + * - rtc_sleep: entry into sleep modes + * - rtc_init: initialization + */ + + +/** + * @brief Possible main XTAL frequency values. + * + * Enum values should be equal to frequency in MHz. + */ +typedef enum { + RTC_XTAL_FREQ_AUTO = 0, //!< Automatic XTAL frequency detection + RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL + RTC_XTAL_FREQ_26M = 26, //!< 26 MHz XTAL + RTC_XTAL_FREQ_24M = 24, //!< 24 MHz XTAL +} rtc_xtal_freq_t; + +/** + * @brief CPU frequency values + */ +typedef enum { + RTC_CPU_FREQ_XTAL = 0, //!< Main XTAL frequency + RTC_CPU_FREQ_80M = 1, //!< 80 MHz + RTC_CPU_FREQ_160M = 2, //!< 160 MHz + RTC_CPU_FREQ_240M = 3, //!< 240 MHz + RTC_CPU_FREQ_2M = 4, //!< 2 MHz +} rtc_cpu_freq_t; + +/** + * @brief RTC SLOW_CLK frequency values + */ +typedef enum { + RTC_SLOW_FREQ_RTC = 0, //!< Internal 150 kHz RC oscillator + RTC_SLOW_FREQ_32K_XTAL = 1, //!< External 32 kHz XTAL + RTC_SLOW_FREQ_8MD256 = 2, //!< Internal 8 MHz RC oscillator, divided by 256 +} rtc_slow_freq_t; + +/** + * @brief RTC FAST_CLK frequency values + */ +typedef enum { + RTC_FAST_FREQ_XTALD4 = 0, //!< Main XTAL, divided by 4 + RTC_FAST_FREQ_8M = 1, //!< Internal 8 MHz RC oscillator +} rtc_fast_freq_t; + +/** + * @brief Clock source to be calibrated using rtc_clk_cal function + */ +typedef enum { + RTC_CAL_RTC_MUX = 0, //!< Currently selected RTC SLOW_CLK + RTC_CAL_8MD256 = 1, //!< Internal 8 MHz RC oscillator, divided by 256 + RTC_CAL_32K_XTAL = 2 //!< External 32 kHz XTAL +} rtc_cal_sel_t; + +/** + * Initialization parameters for rtc_clk_init + */ +typedef struct { + rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency + rtc_cpu_freq_t cpu_freq : 3; //!< CPU frequency to set + rtc_fast_freq_t fast_freq : 1; //!< RTC_FAST_CLK frequency to set + rtc_slow_freq_t slow_freq : 2; //!< RTC_SLOW_CLK frequency to set + uint32_t clk_8m_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency) + uint32_t slow_clk_dcap : 8; //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency) + uint32_t clk_8m_dfreq : 8; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency) +} rtc_clk_config_t; + +/** + * Default initializer for rtc_clk_config_t + */ +#define RTC_CLK_CONFIG_DEFAULT() { \ + .xtal_freq = RTC_XTAL_FREQ_AUTO, \ + .cpu_freq = RTC_CPU_FREQ_80M, \ + .fast_freq = RTC_FAST_FREQ_8M, \ + .slow_freq = RTC_SLOW_FREQ_RTC, \ + .clk_8m_div = 0, \ + .slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \ + .clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \ +} + +/** + * Initialize clocks and set CPU frequency + * + * If cfg.xtal_freq is set to RTC_XTAL_FREQ_AUTO, this function will attempt + * to auto detect XTAL frequency. Auto detection is performed by comparing + * XTAL frequency with the frequency of internal 8MHz oscillator. Note that at + * high temperatures the frequency of the internal 8MHz oscillator may drift + * enough for auto detection to be unreliable. + * Auto detection code will attempt to distinguish between 26MHz and 40MHz + * crystals. 24 MHz crystals are not supported by auto detection code. + * If XTAL frequency can not be auto detected, this 26MHz frequency will be used. + * + * @param cfg clock configuration as rtc_clk_config_t + */ +void rtc_clk_init(rtc_clk_config_t cfg); + +/** + * @brief Get main XTAL frequency + * + * This is the value passed to rtc_clk_init function, or if the value was + * RTC_XTAL_FREQ_AUTO, the detected XTAL frequency. + * + * @return XTAL frequency, one of rtc_xtal_freq_t + */ +rtc_xtal_freq_t rtc_clk_xtal_freq_get(); + +/** + * @brief Enable or disable 32 kHz XTAL oscillator + * @param en true to enable, false to disable + */ +void rtc_clk_32k_enable(bool en); + +/** + * @brief Get the state of 32k XTAL oscillator + * @return true if 32k XTAL oscillator has been enabled + */ +bool rtc_clk_32k_enabled(); + +/** + * @brief Enable or disable 8 MHz internal oscillator + * + * Output from 8 MHz internal oscillator is passed into a configurable + * divider, which by default divides the input clock frequency by 256. + * Output of the divider may be used as RTC_SLOW_CLK source. + * Output of the divider is referred to in register descriptions and code as + * 8md256 or simply d256. Divider values other than 256 may be configured, but + * this facility is not currently needed, so is not exposed in the code. + * + * When 8MHz/256 divided output is not needed, the divider should be disabled + * to reduce power consumption. + * + * @param clk_8m_en true to enable 8MHz generator + * @param d256_en true to enable /256 divider + */ +void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en); + +/** + * @brief Get the state of 8 MHz internal oscillator + * @return true if the oscillator is enabled + */ +bool rtc_clk_8m_enabled(); + +/** + * @brief Get the state of /256 divider which is applied to 8MHz clock + * @return true if the divided output is enabled + */ +bool rtc_clk_8md256_enabled(); + +/** + * @brief Enable or disable APLL + * + * Output frequency is given by the formula: + * apll_freq = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536)/((o_div + 2) * 2) + * + * The dividend in this expression should be in the range of 240 - 600 MHz. + * + * In rev. 0 of ESP32, sdm0 and sdm1 are unused and always set to 0. + * + * @param enable true to enable, false to disable + * @param sdm0 frequency adjustment parameter, 0..255 + * @param sdm1 frequency adjustment parameter, 0..255 + * @param sdm2 frequency adjustment parameter, 0..63 + * @param o_div frequency divider, 0..31 + */ +void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, + uint32_t sdm2, uint32_t o_div); + +/** + * @brief Select source for RTC_SLOW_CLK + * @param slow_freq clock source (one of rtc_slow_freq_t values) + */ +void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq); + +/** + * @brief Get the RTC_SLOW_CLK source + * @return currently selected clock source (one of rtc_slow_freq_t values) + */ +rtc_slow_freq_t rtc_clk_slow_freq_get(); + +/** + * @brief Select source for RTC_FAST_CLK + * @param fast_freq clock source (one of rtc_fast_freq_t values) + */ +void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq); + +/** + * @brief Get the RTC_FAST_CLK source + * @return currently selected clock source (one of rtc_fast_freq_t values) + */ +rtc_fast_freq_t rtc_clk_fast_freq_get(); + +/** + * @brief Switch CPU frequency + * + * If a PLL-derived frequency is requested (80, 160, 240 MHz), this function + * will enable the PLL. Otherwise, PLL will be disabled. + * Note: this function is not optimized for switching speed. It may take several + * hundred microseconds to perform frequency switch. + * + * @param cpu_freq new CPU frequency + */ +void rtc_clk_cpu_freq_set(rtc_cpu_freq_t cpu_freq); + +/** + * @brief Get the currently selected CPU frequency + * + * Although CPU can be clocked by APLL and RTC 8M sources, such support is not + * exposed through this library. As such, this function will not return + * meaningful values when these clock sources are configured (e.g. using direct + * access to clock selection registers). In debug builds, it will assert; in + * release builds, it will return RTC_CPU_FREQ_XTAL. + * + * @return CPU frequency (one of rtc_cpu_freq_t values) + */ +rtc_cpu_freq_t rtc_clk_cpu_freq_get(); + +/** + * @brief Get corresponding frequency value for rtc_cpu_freq_t enum value + * @param cpu_freq CPU frequency, on of rtc_cpu_freq_t values + * @return CPU frequency, in HZ + */ +uint32_t rtc_clk_cpu_freq_value(rtc_cpu_freq_t cpu_freq); + +/** + * @brief Store new APB frequency value into RTC_APB_FREQ_REG + * + * This function doesn't change any hardware clocks. + * + * Functions which perform frequency switching and change APB frequency call + * this function to update the value of APB frequency stored in RTC_APB_FREQ_REG + * (one of RTC general purpose retention registers). This should not normally + * be called from application code. + * + * @param apb_freq new APB frequency, in Hz + */ +void rtc_clk_apb_freq_update(uint32_t apb_freq); + +/** + * @brief Get the current stored APB frequency. + * @return The APB frequency value as last set via rtc_clk_apb_freq_update(), in Hz. + */ +uint32_t rtc_clk_apb_freq_get(); + +#define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal + +/** + * @brief Measure RTC slow clock's period, based on main XTAL frequency + * + * This function will time out and return 0 if the time for the given number + * of cycles to be counted exceeds the expected time twice. This may happen if + * 32k XTAL is being calibrated, but the oscillator has not started up (due to + * incorrect loading capacitance, board design issue, or lack of 32 XTAL on board). + * + * @param cal_clk clock to be measured + * @param slow_clk_cycles number of slow clock cycles to average + * @return average slow clock period in microseconds, Q13.19 fixed point format, + * or 0 if calibration has timed out + */ +uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles); + +/** + * @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles + * @param time_in_us Time interval in microseconds + * @param slow_clk_period Period of slow clock in microseconds, Q13.19 + * fixed point format (as returned by rtc_slowck_cali). + * @return number of slow clock cycles + */ +uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period); + +/** + * @brief Convert time interval from RTC_SLOW_CLK to microseconds + * @param time_in_us Time interval in RTC_SLOW_CLK cycles + * @param slow_clk_period Period of slow clock in microseconds, Q13.19 + * fixed point format (as returned by rtc_slowck_cali). + * @return time interval in microseconds + */ +uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period); + +/** + * @brief Get current value of RTC counter + * + * RTC has a 48-bit counter which is incremented by 2 every 2 RTC_SLOW_CLK + * cycles. Counter value is not writable by software. The value is not adjusted + * when switching to a different RTC_SLOW_CLK source. + * + * Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute + * + * @return current value of RTC counter + */ +uint64_t rtc_time_get(); + +/** + * @brief sleep configuration for rtc_sleep_init function + */ +typedef struct { + uint32_t soc_clk_sel : 2; //!< SoC clock select, see RTC_CNTL_SOC_CLK_SEL + uint32_t lslp_mem_inf_fpu : 1; //!< force normal voltage in sleep mode (digital domain memory) + uint32_t rtc_mem_inf_fpu : 1; //!< force normal voltage in sleep mode (RTC memory) + uint32_t rtc_mem_inf_follow_cpu : 1;//!< keep low voltage in sleep mode (even if ULP/touch is used) + uint32_t rtc_fastmem_pd_en : 1; //!< power down RTC fast memory + uint32_t rtc_slowmem_pd_en : 1; //!< power down RTC slow memory + uint32_t rtc_peri_pd_en : 1; //!< power down RTC peripherals + uint32_t wifi_pd_en : 1; //!< power down WiFi + uint32_t rom_mem_pd_en : 1; //!< power down main RAM and ROM + uint32_t deep_slp : 1; //!< power down digital domain + uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode + uint32_t dig_dbias_wak : 3; //!< set bias for digital domain, in active mode + uint32_t dig_dbias_slp : 3; //!< set bias for digital domain, in sleep mode + uint32_t rtc_dbias_wak : 3; //!< set bias for RTC domain, in active mode + uint32_t rtc_dbias_slp : 3; //!< set bias for RTC domain, in sleep mode + uint32_t lslp_meminf_pd : 1; //!< remove all peripheral force power up flags +} rtc_sleep_config_t; + +/** + * Default initializer for rtc_sleep_config_t + * + * This initializer sets all fields to "reasonable" values (e.g. suggested for + * production use) based on a combination of RTC_SLEEP_PD_x flags. + * + * @param RTC_SLEEP_PD_x flags combined using bitwise OR + */ +#define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \ + .soc_clk_sel = RTC_CNTL_SOC_CLK_SEL_XTL, \ + .lslp_mem_inf_fpu = 0, \ + .rtc_mem_inf_fpu = 0, \ + .rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, \ + .rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, \ + .rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \ + .rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \ + .wifi_pd_en = 0, \ + .rom_mem_pd_en = 0, \ + .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \ + .wdt_flashboot_mod_en = 0, \ + .dig_dbias_wak = RTC_CNTL_DBIAS_1V10, \ + .dig_dbias_slp = RTC_CNTL_DBIAS_0V90, \ + .rtc_dbias_wak = RTC_CNTL_DBIAS_0V90, \ + .rtc_dbias_slp = RTC_CNTL_DBIAS_0V90, \ + .lslp_meminf_pd = 1 \ +}; + +#define RTC_SLEEP_PD_DIG BIT(0) //!< Deep sleep (power down digital domain) +#define RTC_SLEEP_PD_RTC_PERIPH BIT(1) //!< Power down RTC peripherals +#define RTC_SLEEP_PD_RTC_SLOW_MEM BIT(2) //!< Power down RTC SLOW memory +#define RTC_SLEEP_PD_RTC_FAST_MEM BIT(3) //!< Power down RTC FAST memory +#define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4) //!< RTC FAST and SLOW memories are automatically powered up and down along with the CPU + +/** + * @brief Prepare the chip to enter sleep mode + * + * This function configures various power control state machines to handle + * entry into light sleep or deep sleep mode, switches APB and CPU clock source + * (usually to XTAL), and sets bias voltages for digital and RTC power domains. + * + * This function does not actually enter sleep mode; this is done using + * rtc_sleep_start function. Software may do some other actions between + * rtc_sleep_init and rtc_sleep_start, such as set wakeup timer and configure + * wakeup sources. + * @param cfg sleep mode configuration + */ +void rtc_sleep_init(rtc_sleep_config_t cfg); + + +/** + * @brief Set target value of RTC counter for RTC_TIMER_TRIG_EN wakeup source + * @param t value of RTC counter at which wakeup from sleep will happen; + * only the lower 48 bits are used + */ +void rtc_sleep_set_wakeup_time(uint64_t t); + + +#define RTC_EXT0_TRIG_EN BIT(0) //!< EXT0 GPIO wakeup +#define RTC_EXT1_TRIG_EN BIT(1) //!< EXT1 GPIO wakeup +#define RTC_GPIO_TRIG_EN BIT(2) //!< GPIO wakeup (light sleep only) +#define RTC_TIMER_TRIG_EN BIT(3) //!< Timer wakeup +#define RTC_SDIO_TRIG_EN BIT(4) //!< SDIO wakeup (light sleep only) +#define RTC_MAC_TRIG_EN BIT(5) //!< MAC wakeup (light sleep only) +#define RTC_UART0_TRIG_EN BIT(6) //!< UART0 wakeup (light sleep only) +#define RTC_UART1_TRIG_EN BIT(7) //!< UART1 wakeup (light sleep only) +#define RTC_TOUCH_TRIG_EN BIT(8) //!< Touch wakeup +#define RTC_ULP_TRIG_EN BIT(9) //!< ULP wakeup +#define RTC_BT_TRIG_EN BIT(10) //!< BT wakeup (light sleep only) + +/** + * @brief Enter deep or light sleep mode + * + * This function enters the sleep mode previously configured using rtc_sleep_init + * function. Before entering sleep, software should configure wake up sources + * appropriately (set up GPIO wakeup registers, timer wakeup registers, + * and so on). + * + * If deep sleep mode was configured using rtc_sleep_init, and sleep is not + * rejected by hardware (based on reject_opt flags), this function never returns. + * When the chip wakes up from deep sleep, CPU is reset and execution starts + * from ROM bootloader. + * + * If light sleep mode was configured using rtc_sleep_init, this function + * returns on wakeup, or if sleep is rejected by hardware. + * + * @param wakeup_opt bit mask wake up reasons to enable (RTC_xxx_TRIG_EN flags + * combined with OR) + * @param reject_opt bit mask of sleep reject reasons: + * - RTC_CNTL_GPIO_REJECT_EN + * - RTC_CNTL_SDIO_REJECT_EN + * These flags are used to prevent entering sleep when e.g. + * an external host is communicating via SDIO slave + * @return non-zero if sleep was rejected by hardware + */ +uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt); + +/** + * RTC power and clock control initialization settings + */ +typedef struct { + uint32_t ck8m_wait : 8; //!< Number of rtc_fast_clk cycles to wait for 8M clock to be ready + uint32_t xtal_wait : 8; //!< Number of rtc_fast_clk cycles to wait for XTAL clock to be ready + uint32_t pll_wait : 8; //!< Number of rtc_fast_clk cycles to wait for PLL to be ready + uint32_t clkctl_init : 1; //!< Perform clock control related initialization + uint32_t pwrctl_init : 1; //!< Perform power control related initialization + uint32_t rtc_dboost_fpd : 1; //!< Force power down RTC_DBOOST +} rtc_config_t; + +/** + * Default initializer of rtc_config_t. + * + * This initializer sets all fields to "reasonable" values (e.g. suggested for + * production use). + */ +#define RTC_CONFIG_DEFAULT() {\ + .ck8m_wait = RTC_CNTL_CK8M_WAIT_DEFAULT, \ + .xtal_wait = RTC_CNTL_XTL_BUF_WAIT_DEFAULT, \ + .pll_wait = RTC_CNTL_PLL_BUF_WAIT_DEFAULT, \ + .clkctl_init = 1, \ + .pwrctl_init = 1, \ + .rtc_dboost_fpd = 1 \ +} + +/** + * Initialize RTC clock and power control related functions + * @param cfg configuration options as rtc_config_t + */ +void rtc_init(rtc_config_t cfg); + + +#ifdef __cplusplus +} +#endif + diff --git a/components/soc/esp32/include/soc/rtc_cntl_reg.h b/components/soc/esp32/include/soc/rtc_cntl_reg.h index ae287fd67..067f2296f 100644 --- a/components/soc/esp32/include/soc/rtc_cntl_reg.h +++ b/components/soc/esp32/include/soc/rtc_cntl_reg.h @@ -321,18 +321,21 @@ #define RTC_CNTL_PLL_BUF_WAIT_M ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S)) #define RTC_CNTL_PLL_BUF_WAIT_V 0xFF #define RTC_CNTL_PLL_BUF_WAIT_S 24 +#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20 /* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; */ /*description: XTAL wait cycles in slow_clk_rtc*/ #define RTC_CNTL_XTL_BUF_WAIT 0x000003FF #define RTC_CNTL_XTL_BUF_WAIT_M ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S)) #define RTC_CNTL_XTL_BUF_WAIT_V 0x3FF #define RTC_CNTL_XTL_BUF_WAIT_S 14 +#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 20 /* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; */ /*description: CK8M wait cycles in slow_clk_rtc*/ #define RTC_CNTL_CK8M_WAIT 0x000000FF #define RTC_CNTL_CK8M_WAIT_M ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S)) #define RTC_CNTL_CK8M_WAIT_V 0xFF #define RTC_CNTL_CK8M_WAIT_S 6 +#define RTC_CNTL_CK8M_WAIT_DEFAULT 20 /* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */ /*description: CPU stall wait cycles in fast_clk_rtc*/ #define RTC_CNTL_CPU_STALL_WAIT 0x0000001F @@ -892,6 +895,10 @@ #define RTC_CNTL_SOC_CLK_SEL_M ((RTC_CNTL_SOC_CLK_SEL_V)<<(RTC_CNTL_SOC_CLK_SEL_S)) #define RTC_CNTL_SOC_CLK_SEL_V 0x3 #define RTC_CNTL_SOC_CLK_SEL_S 27 +#define RTC_CNTL_SOC_CLK_SEL_XTL 0 +#define RTC_CNTL_SOC_CLK_SEL_PLL 1 +#define RTC_CNTL_SOC_CLK_SEL_8M 2 +#define RTC_CNTL_SOC_CLK_SEL_APLL 3 /* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */ /*description: CK8M force power up*/ #define RTC_CNTL_CK8M_FORCE_PU (BIT(26)) @@ -910,6 +917,7 @@ #define RTC_CNTL_CK8M_DFREQ_M ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S)) #define RTC_CNTL_CK8M_DFREQ_V 0xFF #define RTC_CNTL_CK8M_DFREQ_S 17 +#define RTC_CNTL_CK8M_DFREQ_DEFAULT 172 /* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */ /*description: CK8M force no gating during sleep*/ #define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(16)) @@ -1109,6 +1117,7 @@ #define RTC_CNTL_SCK_DCAP_M ((RTC_CNTL_SCK_DCAP_V)<<(RTC_CNTL_SCK_DCAP_S)) #define RTC_CNTL_SCK_DCAP_V 0xFF #define RTC_CNTL_SCK_DCAP_S 14 +#define RTC_CNTL_SCK_DCAP_DEFAULT 255 /* RTC_CNTL_DIG_DBIAS_WAK : R/W ;bitpos:[13:11] ;default: 3'd4 ; */ /*description: DIG_REG_DBIAS during wakeup*/ #define RTC_CNTL_DIG_DBIAS_WAK 0x00000007 @@ -1128,6 +1137,19 @@ #define RTC_CNTL_SCK_DCAP_FORCE_V 0x1 #define RTC_CNTL_SCK_DCAP_FORCE_S 7 +/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP, + * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values. + * Valid if RTC_CNTL_DBG_ATTEN is 0. + */ +#define RTC_CNTL_DBIAS_0V90 0 +#define RTC_CNTL_DBIAS_0V95 1 +#define RTC_CNTL_DBIAS_1V00 2 +#define RTC_CNTL_DBIAS_1V05 3 +#define RTC_CNTL_DBIAS_1V10 4 +#define RTC_CNTL_DBIAS_1V15 5 +#define RTC_CNTL_DBIAS_1V20 6 +#define RTC_CNTL_DBIAS_1V25 7 + #define RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x80) /* RTC_CNTL_PD_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */ /*description: enable power down rtc_peri in sleep*/ @@ -1257,6 +1279,24 @@ #define RTC_CNTL_FASTMEM_FORCE_NOISO_V 0x1 #define RTC_CNTL_FASTMEM_FORCE_NOISO_S 0 +/* Useful groups of RTC_CNTL_PWC_REG bits */ +#define RTC_CNTL_MEM_FORCE_ISO \ + (RTC_CNTL_SLOWMEM_FORCE_ISO | RTC_CNTL_FASTMEM_FORCE_ISO) +#define RTC_CNTL_MEM_FORCE_NOISO \ + (RTC_CNTL_SLOWMEM_FORCE_NOISO | RTC_CNTL_FASTMEM_FORCE_NOISO) +#define RTC_CNTL_MEM_PD_EN \ + (RTC_CNTL_SLOWMEM_PD_EN | RTC_CNTL_FASTMEM_PD_EN) +#define RTC_CNTL_MEM_FORCE_PU \ + (RTC_CNTL_SLOWMEM_FORCE_PU | RTC_CNTL_FASTMEM_FORCE_PU) +#define RTC_CNTL_MEM_FORCE_PD \ + (RTC_CNTL_SLOWMEM_FORCE_PD | RTC_CNTL_FASTMEM_FORCE_PD) +#define RTC_CNTL_MEM_FOLW_CPU \ + (RTC_CNTL_SLOWMEM_FOLW_CPU | RTC_CNTL_FASTMEM_FOLW_CPU) +#define RTC_CNTL_MEM_FORCE_LPU \ + (RTC_CNTL_SLOWMEM_FORCE_LPU | RTC_CNTL_FASTMEM_FORCE_LPU) +#define RTC_CNTL_MEM_FORCE_LPD \ + (RTC_CNTL_SLOWMEM_FORCE_LPD | RTC_CNTL_FASTMEM_FORCE_LPD) + #define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0x84) /* RTC_CNTL_DG_WRAP_PD_EN : R/W ;bitpos:[31] ;default: 0 ; */ /*description: enable power down digital core in sleep*/ @@ -1415,6 +1455,20 @@ #define RTC_CNTL_LSLP_MEM_FORCE_PD_V 0x1 #define RTC_CNTL_LSLP_MEM_FORCE_PD_S 3 +/* Useful groups of RTC_CNTL_DIG_PWC_REG bits */ +#define RTC_CNTL_CPU_ROM_RAM_PD_EN \ + (RTC_CNTL_INTER_RAM4_PD_EN | RTC_CNTL_INTER_RAM3_PD_EN |\ + RTC_CNTL_INTER_RAM2_PD_EN | RTC_CNTL_INTER_RAM1_PD_EN |\ + RTC_CNTL_INTER_RAM0_PD_EN | RTC_CNTL_ROM0_PD_EN) +#define RTC_CNTL_CPU_ROM_RAM_FORCE_PU \ + (RTC_CNTL_INTER_RAM4_FORCE_PU | RTC_CNTL_INTER_RAM3_FORCE_PU |\ + RTC_CNTL_INTER_RAM2_FORCE_PU | RTC_CNTL_INTER_RAM1_FORCE_PU |\ + RTC_CNTL_INTER_RAM0_FORCE_PU | RTC_CNTL_ROM0_FORCE_PU) +#define RTC_CNTL_CPU_ROM_RAM_FORCE_PD \ + (RTC_CNTL_INTER_RAM4_FORCE_PD | RTC_CNTL_INTER_RAM3_FORCE_PD |\ + RTC_CNTL_INTER_RAM2_FORCE_PD | RTC_CNTL_INTER_RAM1_FORCE_PD |\ + RTC_CNTL_INTER_RAM0_FORCE_PD | RTC_CNTL_ROM0_FORCE_PD + #define RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0x88) /* RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W ;bitpos:[31] ;default: 1'd1 ; */ /*description: digital core force no ISO*/ @@ -1567,6 +1621,16 @@ #define RTC_CNTL_DIG_ISO_FORCE_OFF_V 0x1 #define RTC_CNTL_DIG_ISO_FORCE_OFF_S 7 +/* Useful groups of RTC_CNTL_DIG_ISO_REG bits */ +#define RTC_CNTL_CPU_ROM_RAM_FORCE_ISO \ + (RTC_CNTL_INTER_RAM4_FORCE_ISO | RTC_CNTL_INTER_RAM3_FORCE_ISO |\ + RTC_CNTL_INTER_RAM2_FORCE_ISO | RTC_CNTL_INTER_RAM1_FORCE_ISO |\ + RTC_CNTL_INTER_RAM0_FORCE_ISO | RTC_CNTL_ROM0_FORCE_ISO) +#define RTC_CNTL_CPU_ROM_RAM_FORCE_NOISO \ + (RTC_CNTL_INTER_RAM4_FORCE_NOISO | RTC_CNTL_INTER_RAM3_FORCE_NOISO |\ + RTC_CNTL_INTER_RAM2_FORCE_NOISO | RTC_CNTL_INTER_RAM1_FORCE_NOISO |\ + RTC_CNTL_INTER_RAM0_FORCE_NOISO | RTC_CNTL_ROM0_FORCE_NOISO) + #define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x8c) /* RTC_CNTL_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ /*description: enable RTC WDT*/ diff --git a/components/soc/esp32/include/soc/rtc_io_reg.h b/components/soc/esp32/include/soc/rtc_io_reg.h index 086e8b767..f6d0dac76 100644 --- a/components/soc/esp32/include/soc/rtc_io_reg.h +++ b/components/soc/esp32/include/soc/rtc_io_reg.h @@ -511,6 +511,8 @@ #define RTC_IO_DEBUG_SEL0_M ((RTC_IO_DEBUG_SEL0_V)<<(RTC_IO_DEBUG_SEL0_S)) #define RTC_IO_DEBUG_SEL0_V 0x1F #define RTC_IO_DEBUG_SEL0_S 0 +#define RTC_IO_DEBUG_SEL0_32K_XTAL 4 +#define RTC_IO_DEBUG_SEL0_150K_OSC 5 #define RTC_IO_DIG_PAD_HOLD_REG (DR_REG_RTCIO_BASE + 0x74) /* RTC_IO_DIG_PAD_HOLD : R/W ;bitpos:[31:0] ;default: 1'd0 ; */ diff --git a/components/soc/esp32/include/soc/soc.h b/components/soc/esp32/include/soc/soc.h old mode 100755 new mode 100644 index c17df3858..bcb49a66c --- a/components/soc/esp32/include/soc/soc.h +++ b/components/soc/esp32/include/soc/soc.h @@ -179,6 +179,8 @@ #define DR_REG_LEDC_BASE 0x3ff59000 #define DR_REG_EFUSE_BASE 0x3ff5A000 #define DR_REG_SPI_ENCRYPT_BASE 0x3ff5B000 +#define DR_REG_NRX_BASE 0x3ff5CC00 +#define DR_REG_BB_BASE 0x3ff5D000 #define DR_REG_PWM_BASE 0x3ff5E000 #define DR_REG_TIMERGROUP0_BASE 0x3ff5F000 #define DR_REG_TIMERGROUP1_BASE 0x3ff60000 diff --git a/components/soc/esp32/rtc_clk.c b/components/soc/esp32/rtc_clk.c new file mode 100644 index 000000000..79b56f993 --- /dev/null +++ b/components/soc/esp32/rtc_clk.c @@ -0,0 +1,534 @@ +// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include +#include +#include +#include +#include "rom/ets_sys.h" +#include "rom/rtc.h" +#include "rom/uart.h" +#include "soc/rtc.h" +#include "soc/rtc_cntl_reg.h" +#include "soc/rtc_io_reg.h" +#include "soc/sens_reg.h" +#include "soc/dport_reg.h" +#include "soc/efuse_reg.h" +#include "soc/apb_ctrl_reg.h" +#include "i2c_rtc_clk.h" +#include "soc_log.h" +#include "sdkconfig.h" + +#define MHZ (1000000) + +static const char* TAG = "rtc_clk"; + +/* Various constants related to the analog internals of the chip. + * Defined here because they don't have any use outside of this file. + */ + +#define BBPLL_ENDIV5_VAL_320M 0x43 +#define BBPLL_BBADC_DSMP_VAL_320M 0x84 +#define BBPLL_ENDIV5_VAL_480M 0xc3 +#define BBPLL_BBADC_DSMP_VAL_480M 0x74 + +#define APLL_SDM_STOP_VAL_1 0x09 +#define APLL_SDM_STOP_VAL_2_REV0 0x69 +#define APLL_SDM_STOP_VAL_2_REV1 0x49 + +#define APLL_CAL_DELAY_1 0x0f +#define APLL_CAL_DELAY_2 0x3f +#define APLL_CAL_DELAY_3 0x1f + +#define XTAL_32K_DAC_VAL 1 +#define XTAL_32K_DRES_VAL 3 +#define XTAL_32K_DBIAS_VAL 0 + +/* Delays for various clock sources to be enabled/switched. + * All values are in microseconds. + * TODO: some of these are excessive, and should be reduced. + */ +#define DELAY_CPU_FREQ_SWITCH_TO_XTAL 80 +#define DELAY_CPU_FREQ_SWITCH_TO_PLL 10 +#define DELAY_PLL_DBIAS_RAISE 3 +#define DELAY_PLL_ENABLE 80 +#define DELAY_FAST_CLK_SWITCH 3 +#define DELAY_SLOW_CLK_SWITCH 300 +#define DELAY_8M_ENABLE 50 + + +void rtc_clk_32k_enable(bool enable) +{ + if (enable) { + SET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32N_MUX_SEL | RTC_IO_X32P_MUX_SEL); + CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, + RTC_IO_X32P_RDE | RTC_IO_X32P_RUE | RTC_IO_X32N_RUE | + RTC_IO_X32N_RDE | RTC_IO_X32N_MUX_SEL | RTC_IO_X32P_MUX_SEL); + REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DAC_XTAL_32K, XTAL_32K_DAC_VAL); + REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DRES_XTAL_32K, XTAL_32K_DRES_VAL); + REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DBIAS_XTAL_32K, XTAL_32K_DBIAS_VAL); + SET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K); + } else { + CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K); + } +} + +bool rtc_clk_32k_enabled() +{ + return GET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K) != 0; +} + +void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en) +{ + if (clk_8m_en) { + CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M); + /* no need to wait once enabled by software */ + REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, 1); + if (d256_en) { + CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV); + } else { + SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV); + } + ets_delay_us(DELAY_8M_ENABLE); + } else { + SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M); + REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_DEFAULT); + } +} + +bool rtc_clk_8m_enabled() +{ + return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0; +} + +bool rtc_clk_8md256_enabled() +{ + return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0; +} + +void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2, uint32_t o_div) +{ + REG_SET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD, enable ? 0 : 1); + REG_SET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU, enable ? 1 : 0); + REG_SET_FIELD(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD, enable ? 0 : 1); + + if (!enable && + REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL) != RTC_CNTL_SOC_CLK_SEL_PLL) { + SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD); + } + + if (enable) { + uint8_t sdm_stop_val_2 = APLL_SDM_STOP_VAL_2_REV1; + uint32_t is_rev0 = (GET_PERI_REG_BITS2(EFUSE_BLK0_RDATA3_REG, 1, 15) == 0); + if (is_rev0) { + sdm0 = 0; + sdm1 = 0; + sdm_stop_val_2 = APLL_SDM_STOP_VAL_2_REV0; + } + I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_DSDM2, sdm2); + I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_DSDM0, sdm0); + I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_DSDM1, sdm1); + I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_SDM_STOP, APLL_SDM_STOP_VAL_1); + I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_SDM_STOP, sdm_stop_val_2); + I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_OR_OUTPUT_DIV, o_div); + + /* calibration */ + I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_1); + I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_2); + I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_3); + + /* wait for calibration end */ + while (!(I2C_READREG_MASK_RTC(I2C_APLL, I2C_APLL_OR_CAL_END))) { + /* use ets_delay_us so the RTC bus doesn't get flooded */ + ets_delay_us(1); + } + } +} + +void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq) +{ + REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL, slow_freq); + ets_delay_us(DELAY_SLOW_CLK_SWITCH); +} + +rtc_slow_freq_t rtc_clk_slow_freq_get() +{ + return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); +} + + +void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq) +{ + REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL, fast_freq); + ets_delay_us(DELAY_FAST_CLK_SWITCH); +} + +rtc_fast_freq_t rtc_clk_fast_freq_get() +{ + return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL); +} + +void rtc_clk_bbpll_set(rtc_xtal_freq_t xtal_freq, rtc_cpu_freq_t cpu_freq) +{ + uint8_t div_ref; + uint8_t div7_0; + uint8_t div10_8; + uint8_t lref; + uint8_t dcur; + uint8_t bw; + + if (cpu_freq != RTC_CPU_FREQ_240M) { + /* Configure 320M PLL */ + switch (xtal_freq) { + case RTC_XTAL_FREQ_40M: + div_ref = 0; + div7_0 = 32; + div10_8 = 0; + lref = 0; + dcur = 6; + bw = 3; + break; + case RTC_XTAL_FREQ_26M: + div_ref = 12; + div7_0 = 224; + div10_8 = 4; + lref = 1; + dcur = 0; + bw = 1; + break; + case RTC_XTAL_FREQ_24M: + div_ref = 11; + div7_0 = 224; + div10_8 = 4; + lref = 1; + dcur = 0; + bw = 1; + break; + default: + div_ref = 12; + div7_0 = 224; + div10_8 = 4; + lref = 0; + dcur = 0; + bw = 0; + break; + } + I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_ENDIV5, BBPLL_ENDIV5_VAL_320M); + I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_BBADC_DSMP, BBPLL_BBADC_DSMP_VAL_320M); + } else { + /* Raise the voltage */ + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DBIAS_1V25); + ets_delay_us(DELAY_PLL_DBIAS_RAISE); + /* Configure 480M PLL */ + switch (xtal_freq) { + case RTC_XTAL_FREQ_40M: + div_ref = 0; + div7_0 = 28; + div10_8 = 0; + lref = 0; + dcur = 6; + bw = 3; + break; + case RTC_XTAL_FREQ_26M: + div_ref = 12; + div7_0 = 144; + div10_8 = 4; + lref = 1; + dcur = 0; + bw = 1; + break; + case RTC_XTAL_FREQ_24M: + div_ref = 11; + div7_0 = 144; + div10_8 = 4; + lref = 1; + dcur = 0; + bw = 1; + break; + default: + div_ref = 12; + div7_0 = 224; + div10_8 = 4; + lref = 0; + dcur = 0; + bw = 0; + break; + } + I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_ENDIV5, BBPLL_ENDIV5_VAL_480M); + I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_BBADC_DSMP, BBPLL_BBADC_DSMP_VAL_480M); + } + + uint8_t i2c_bbpll_lref = (lref << 7) | (div10_8 << 4) | (div_ref); + uint8_t i2c_bbpll_div_7_0 = div7_0; + uint8_t i2c_bbpll_dcur = (bw << 6) | dcur; + I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_LREF, i2c_bbpll_lref); + I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0); + I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur); + ets_delay_us(DELAY_PLL_ENABLE); +} + +void rtc_clk_cpu_freq_set(rtc_cpu_freq_t cpu_freq) +{ + rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get(); + /* Switch CPU to XTAL frequency first */ + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DBIAS_1V10); + REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_XTL); + REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, 0); + ets_update_cpu_frequency(xtal_freq); + ets_delay_us(DELAY_CPU_FREQ_SWITCH_TO_XTAL); + REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 0); + SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, + RTC_CNTL_BB_I2C_FORCE_PD | RTC_CNTL_BBPLL_FORCE_PD | + RTC_CNTL_BBPLL_I2C_FORCE_PD); + rtc_clk_apb_freq_update(xtal_freq * MHZ); + + /* is APLL under force power down? */ + uint32_t apll_fpd = REG_GET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD); + if (apll_fpd) { + /* then also power down the internal I2C bus */ + SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD); + } + /* now switch to the desired frequency */ + if (cpu_freq == RTC_CPU_FREQ_XTAL) { + /* already at XTAL, nothing to do */ + } else if (cpu_freq == RTC_CPU_FREQ_2M) { + /* set up divider to produce 2MHz from XTAL */ + REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, (xtal_freq / 2) - 1); + ets_update_cpu_frequency(2); + rtc_clk_apb_freq_update(2 * MHZ); + /* lower the voltage */ + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DBIAS_1V00); + } else { + /* use PLL as clock source */ + CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, + RTC_CNTL_BIAS_I2C_FORCE_PD | RTC_CNTL_BB_I2C_FORCE_PD | + RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD); + rtc_clk_bbpll_set(xtal_freq, cpu_freq); + if (cpu_freq == RTC_CPU_FREQ_80M) { + REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 0); + ets_update_cpu_frequency(80); + } else if (cpu_freq == RTC_CPU_FREQ_160M) { + REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 1); + ets_update_cpu_frequency(160); + } else if (cpu_freq == RTC_CPU_FREQ_240M) { + REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 2); + ets_update_cpu_frequency(240); + } + REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_PLL); + ets_delay_us(DELAY_CPU_FREQ_SWITCH_TO_PLL); + rtc_clk_apb_freq_update(80 * MHZ); + } +} + +rtc_cpu_freq_t rtc_clk_cpu_freq_get() +{ + uint32_t soc_clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL); + switch (soc_clk_sel) { + case RTC_CNTL_SOC_CLK_SEL_XTL: { + uint32_t pre_div = REG_GET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT); + if (pre_div == 0) { + return RTC_CPU_FREQ_XTAL; + } else if (pre_div == rtc_clk_xtal_freq_get() / 2 - 1) { + return RTC_CPU_FREQ_2M; + } else { + assert(false && "unsupported frequency"); + } + break; + } + case RTC_CNTL_SOC_CLK_SEL_PLL: { + uint32_t cpuperiod_sel = REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL); + if (cpuperiod_sel == 0) { + return RTC_CPU_FREQ_80M; + } else if (cpuperiod_sel == 1) { + return RTC_CPU_FREQ_160M; + } else if (cpuperiod_sel == 2) { + return RTC_CPU_FREQ_240M; + } else { + assert(false && "unsupported frequency"); + } + break; + } + case RTC_CNTL_SOC_CLK_SEL_APLL: + case RTC_CNTL_SOC_CLK_SEL_8M: + default: + assert(false && "unsupported frequency"); + } + return RTC_CNTL_SOC_CLK_SEL_XTL; +} + +uint32_t rtc_clk_cpu_freq_value(rtc_cpu_freq_t cpu_freq) +{ + switch (cpu_freq) { + case RTC_CPU_FREQ_XTAL: + return ((uint32_t) rtc_clk_xtal_freq_get()) * MHZ; + case RTC_CPU_FREQ_2M: + return 2 * MHZ; + case RTC_CPU_FREQ_80M: + return 80 * MHZ; + case RTC_CPU_FREQ_160M: + return 160 * MHZ; + case RTC_CPU_FREQ_240M: + return 240 * MHZ; + default: + assert(false && "invalid rtc_cpu_freq_t value"); + return 0; + } +} + +/* Values of RTC_XTAL_FREQ_REG and RTC_APB_FREQ_REG are stored as two copies in + * lower and upper 16-bit halves. These are the routines to work with such a + * representation. + */ +static bool clk_val_is_valid(uint32_t val) { + return (val & 0xffff) == ((val >> 16) & 0xffff) && + val != 0 && + val != UINT32_MAX; +} + +static uint32_t reg_val_to_clk_val(uint32_t val) { + return val & UINT16_MAX; +} + +static uint32_t clk_val_to_reg_val(uint32_t val) { + return (val & UINT16_MAX) | ((val & UINT16_MAX) << 16); +} + +rtc_xtal_freq_t rtc_clk_xtal_freq_get() +{ + /* We may have already written XTAL value into RTC_XTAL_FREQ_REG */ + uint32_t xtal_freq_reg = READ_PERI_REG(RTC_XTAL_FREQ_REG); + if (!clk_val_is_valid(xtal_freq_reg)) { + SOC_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value: 0x%08x", xtal_freq_reg); + return RTC_XTAL_FREQ_AUTO; + } + return reg_val_to_clk_val(xtal_freq_reg); +} + +void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq) +{ + WRITE_PERI_REG(RTC_XTAL_FREQ_REG, clk_val_to_reg_val(xtal_freq)); +} + +static rtc_xtal_freq_t rtc_clk_xtal_freq_estimate() +{ + /* ROM startup code estimates XTAL frequency using an 8MD256 clock and stores + * the value into RTC_APB_FREQ_REG. The value is in Hz, right shifted by 12. + * Use this value to guess the real XTAL frequency. + * + * TODO: make this more robust by calibrating again after setting + * RTC_CNTL_CK8M_DFREQ. + */ + uint32_t apb_freq_reg = READ_PERI_REG(RTC_APB_FREQ_REG); + if (!clk_val_is_valid(apb_freq_reg)) { + SOC_LOGW(TAG, "invalid RTC_APB_FREQ_REG value: 0x%08x", apb_freq_reg); + return RTC_XTAL_FREQ_AUTO; + } + uint32_t freq_mhz = (reg_val_to_clk_val(apb_freq_reg) << 12) / MHZ; + /* Guess the XTAL type. For now, only 40 and 26MHz are supported. + */ + switch (freq_mhz) { + case 21 ... 31: + return RTC_XTAL_FREQ_26M; + case 32 ... 33: + SOC_LOGW(TAG, "Potentially bogus XTAL frequency: %d MHz, guessing 26 MHz", freq_mhz); + return RTC_XTAL_FREQ_26M; + case 34 ... 35: + SOC_LOGW(TAG, "Potentially bogus XTAL frequency: %d MHz, guessing 40 MHz", freq_mhz); + return RTC_XTAL_FREQ_40M; + case 36 ... 45: + return RTC_XTAL_FREQ_40M; + default: + SOC_LOGW(TAG, "Bogus XTAL frequency: %d MHz", freq_mhz); + return RTC_XTAL_FREQ_AUTO; + } +} + +void rtc_clk_apb_freq_update(uint32_t apb_freq) +{ + WRITE_PERI_REG(RTC_APB_FREQ_REG, clk_val_to_reg_val(apb_freq >> 12)); +} + +uint32_t rtc_clk_apb_freq_get() +{ + return reg_val_to_clk_val(READ_PERI_REG(RTC_APB_FREQ_REG)) << 12; +} + + +void rtc_clk_init(rtc_clk_config_t cfg) +{ + /* Set tuning parameters for 8M and 150k clocks. + * Note: this doesn't attempt to set the clocks to precise frequencies. + * Instead, we calibrate these clocks against XTAL frequency later, when necessary. + * - SCK_DCAP value controls tuning of 150k clock. + * The higher the value of DCAP is, the lower is the frequency. + * - CK8M_DFREQ value controls tuning of 8M clock. + * CLK_8M_DFREQ constant gives the best temperature characteristics. + */ + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_SCK_DCAP, cfg.slow_clk_dcap); + REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, cfg.clk_8m_dfreq); + + /* Configure 8M clock division */ + REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL, cfg.clk_8m_div); + + /* Enable the internal bus used to configure PLLs */ + SET_PERI_REG_BITS(ANA_CONFIG_REG, ANA_CONFIG_M, ANA_CONFIG_M, ANA_CONFIG_S); + CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, I2C_APLL_M | I2C_BBPLL_M); + + /* Estimate XTAL frequency if requested */ + rtc_xtal_freq_t xtal_freq = cfg.xtal_freq; + if (xtal_freq == RTC_XTAL_FREQ_AUTO) { + xtal_freq = rtc_clk_xtal_freq_estimate(); + if (xtal_freq == RTC_XTAL_FREQ_AUTO) { + SOC_LOGW(TAG, "Can't estimate XTAL frequency, assuming 26MHz"); + xtal_freq = RTC_XTAL_FREQ_26M; + } + } + rtc_clk_xtal_freq_update(xtal_freq); + rtc_clk_apb_freq_update(xtal_freq * MHZ); + /* Set CPU frequency */ + rtc_clk_cpu_freq_set(cfg.cpu_freq); + + /* Slow & fast clocks setup */ + if (cfg.slow_freq == RTC_SLOW_FREQ_32K_XTAL) { + rtc_clk_32k_enable(false); + } + if (cfg.fast_freq == RTC_FAST_FREQ_8M) { + bool need_8md256 = cfg.slow_freq == RTC_SLOW_FREQ_8MD256; + rtc_clk_8m_enable(true, need_8md256); + } + rtc_clk_fast_freq_set(cfg.fast_freq); + rtc_clk_slow_freq_set(cfg.slow_freq); +} + +/* Name used in libphy.a:phy_chip_v7.o + * TODO: update the library to use rtc_clk_xtal_freq_get + */ +rtc_xtal_freq_t rtc_get_xtal() __attribute__((alias("rtc_clk_xtal_freq_get"))); + + +/* Referenced in librtc.a:rtc.o. + * TODO: remove + */ +void rtc_uart_div_modify(int latch) +{ + +} + +/* Referenced in librtc.a:rtc.o. + * TODO: remove + */ +void rtc_uart_tx_wait_idle(int uart) +{ + +} diff --git a/components/soc/esp32/rtc_init.c b/components/soc/esp32/rtc_init.c new file mode 100644 index 000000000..ca0c3a9c7 --- /dev/null +++ b/components/soc/esp32/rtc_init.c @@ -0,0 +1,96 @@ +// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include + +#include "soc/soc.h" +#include "soc/rtc.h" +#include "soc/rtc_cntl_reg.h" +#include "soc/dport_reg.h" + + +void rtc_init(rtc_config_t cfg) +{ + CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PVTMON_PU); + + REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, cfg.pll_wait); + REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, cfg.xtal_wait); + REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, cfg.ck8m_wait); + + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN, 0x3); + SET_PERI_REG_MASK(RTC_CNTL_BIAS_CONF_REG, + RTC_CNTL_DEC_HEARTBEAT_WIDTH | RTC_CNTL_INC_HEARTBEAT_PERIOD); + + /* Reset RTC bias to default value (needed if waking up from deep sleep) */ + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_1V10); + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SLP, RTC_CNTL_DBIAS_1V10); + + if (cfg.clkctl_init) { + //clear CMMU clock force on + CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CMMU_FORCE_ON); + CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CMMU_FORCE_ON); + //clear rom clock force on + SET_PERI_REG_BITS(DPORT_ROM_FO_CTRL_REG, DPORT_SHARE_ROM_FO, 0, DPORT_SHARE_ROM_FO_S); + CLEAR_PERI_REG_MASK(DPORT_ROM_FO_CTRL_REG, DPORT_APP_ROM_FO); + CLEAR_PERI_REG_MASK(DPORT_ROM_FO_CTRL_REG, DPORT_PRO_ROM_FO); + //clear sram clock force on + SET_PERI_REG_BITS(DPORT_SRAM_FO_CTRL_0_REG, DPORT_SRAM_FO_0, 0, DPORT_SRAM_FO_0_S); + CLEAR_PERI_REG_MASK(DPORT_SRAM_FO_CTRL_0_REG, DPORT_SRAM_FO_1); + //clear tag clock force on + CLEAR_PERI_REG_MASK(DPORT_TAG_FO_CTRL_REG, DPORT_APP_CACHE_TAG_FORCE_ON); + CLEAR_PERI_REG_MASK(DPORT_TAG_FO_CTRL_REG, DPORT_PRO_CACHE_TAG_FORCE_ON); + } + + if (cfg.pwrctl_init) { + CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); + //cancel xtal force pu + CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU); + //cancel BIAS force pu + CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_CORE_FORCE_PU); + CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PU); + CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_FORCE_NOSLEEP); + // bias follow 8M + SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_CORE_FOLW_8M); + SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FOLW_8M); + SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_SLEEP_FOLW_8M); + // CLEAR APLL close + CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU); + SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD); + CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_FORCE_PU); + CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_I2C_FORCE_PU); + //cancel RTC REG force PU + CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_FORCE_PU); + CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PU); + if (cfg.rtc_dboost_fpd) { + SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PD); + } else { + CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PD); + } + //cancel digital pu force + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU); + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_FORCE_PU); + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PU); + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_ROM_RAM_FORCE_PU); + CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_PU); + CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PWC_FORCE_PU); + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_WRAP_FORCE_NOISO); + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO); + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CPU_ROM_RAM_FORCE_NOISO); + CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_NOISO); + CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FORCE_NOISO); + //cancel digital PADS force no iso + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD); + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_NOISO); + } +} diff --git a/components/soc/esp32/rtc_pm.c b/components/soc/esp32/rtc_pm.c new file mode 100644 index 000000000..2023bd824 --- /dev/null +++ b/components/soc/esp32/rtc_pm.c @@ -0,0 +1,68 @@ +// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include +#include +#include "soc/rtc.h" +#include "soc/rtc_cntl_reg.h" + +typedef enum { + PM_LIGHT_SLEEP = BIT(2), /*!< WiFi PD, memory in light sleep */ +} pm_sleep_mode_t; + +typedef enum{ + PM_SW_NOREJECT = 0, + PM_SW_REJECT = 1 +} pm_sw_reject_t; + + +/* These MAC-related functions are defined in the closed source part of + * RTC library + */ +extern void pm_mac_init(); +extern int pm_check_mac_idle(); +extern void pm_mac_deinit(); + +/* This sleep-related function is called from the closed source part of RTC + * library. + */ +pm_sw_reject_t pm_set_sleep_mode(pm_sleep_mode_t sleep_mode, void(*pmac_save_params)()) +{ + (void) pmac_save_params; /* unused */ + + pm_mac_deinit(); + if (pm_check_mac_idle()) { + pm_mac_init(); + return PM_SW_REJECT; + } + + rtc_sleep_config_t cfg = { 0 }; + cfg.soc_clk_sel = RTC_CNTL_SOC_CLK_SEL_XTL; + + switch (sleep_mode) { + case PM_LIGHT_SLEEP: + cfg.wifi_pd_en = 1; + cfg.dig_dbias_wak = 4; + cfg.dig_dbias_slp = 0; + cfg.rtc_dbias_wak = 0; + cfg.rtc_dbias_slp = 0; + cfg.lslp_meminf_pd = 1; + rtc_sleep_init(cfg); + break; + + default: + assert(0 && "unsupported sleep mode"); + } + return PM_SW_NOREJECT; +} diff --git a/components/soc/esp32/rtc_sleep.c b/components/soc/esp32/rtc_sleep.c new file mode 100644 index 000000000..5917d595d --- /dev/null +++ b/components/soc/esp32/rtc_sleep.c @@ -0,0 +1,225 @@ +// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include +#include "soc/soc.h" +#include "soc/rtc.h" +#include "soc/rtc_cntl_reg.h" +#include "soc/dport_reg.h" +#include "soc/rtc.h" +#include "soc/i2s_reg.h" +#include "soc/timer_group_reg.h" +#include "soc/bb_reg.h" +#include "soc/nrx_reg.h" +#include "soc/fe_reg.h" +#include "soc/rtc.h" +#include "rom/ets_sys.h" + +#define MHZ (1000000) + +/* Various delays to be programmed into power control state machines */ +#define ROM_RAM_POWERUP_DELAY 3 +#define ROM_RAM_WAIT_DELAY 3 +#define WIFI_POWERUP_DELAY 3 +#define WIFI_WAIT_DELAY 3 +#define RTC_POWERUP_DELAY 3 +#define RTC_WAIT_DELAY 3 +#define DG_WRAP_POWERUP_DELAY 3 +#define DG_WRAP_WAIT_DELAY 3 +#define RTC_MEM_POWERUP_DELAY 3 +#define RTC_MEM_WAIT_DELAY 3 + +/** + * @brief Power down flags for rtc_sleep_pd function + */ +typedef struct { + uint32_t dig_pd : 1; //!< Set to 1 to power down digital part in sleep + uint32_t rtc_pd : 1; //!< Set to 1 to power down RTC memories in sleep + uint32_t cpu_pd : 1; //!< Set to 1 to power down digital memories and CPU in sleep + uint32_t i2s_pd : 1; //!< Set to 1 to power down I2S in sleep + uint32_t bb_pd : 1; //!< Set to 1 to power down WiFi in sleep + uint32_t nrx_pd : 1; //!< Set to 1 to power down WiFi in sleep + uint32_t fe_pd : 1; //!< Set to 1 to power down WiFi in sleep +} rtc_sleep_pd_config_t; + +/** + * Initializer for rtc_sleep_pd_config_t which sets all flags to the same value + */ +#define RTC_SLEEP_PD_CONFIG_ALL(val) {\ + .dig_pd = (val), \ + .rtc_pd = (val), \ + .cpu_pd = (val), \ + .i2s_pd = (val), \ + .bb_pd = (val), \ + .nrx_pd = (val), \ + .fe_pd = (val), \ +} + +/** + * Configure whether certain peripherals are powered down in deep sleep + * @param cfg power down flags as rtc_sleep_pd_config_t structure + */ +static void rtc_sleep_pd(rtc_sleep_pd_config_t cfg) +{ + REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU, ~cfg.dig_pd); + REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_LPU, ~cfg.rtc_pd); + REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_LPU, ~cfg.rtc_pd); + REG_SET_FIELD(DPORT_MEM_PD_MASK_REG, DPORT_LSLP_MEM_PD_MASK, ~cfg.cpu_pd); + REG_SET_FIELD(I2S_PD_CONF_REG(0), I2S_PLC_MEM_FORCE_PU, ~cfg.i2s_pd); + REG_SET_FIELD(I2S_PD_CONF_REG(0), I2S_FIFO_FORCE_PU, ~cfg.i2s_pd); + REG_SET_FIELD(BBPD_CTRL, BB_FFT_FORCE_PU, ~cfg.bb_pd); + REG_SET_FIELD(BBPD_CTRL, BB_DC_EST_FORCE_PU, ~cfg.bb_pd); + REG_SET_FIELD(NRXPD_CTRL, NRX_RX_ROT_FORCE_PU, ~cfg.nrx_pd); + REG_SET_FIELD(NRXPD_CTRL, NRX_VIT_FORCE_PU, ~cfg.nrx_pd); + REG_SET_FIELD(NRXPD_CTRL, NRX_DEMAP_FORCE_PU, ~cfg.nrx_pd); + REG_SET_FIELD(FE_GEN_CTRL, FE_IQ_EST_FORCE_PU, ~cfg.fe_pd); + REG_SET_FIELD(FE2_TX_INTERP_CTRL, FE2_TX_INF_FORCE_PU, ~cfg.fe_pd); +} + +void rtc_sleep_init(rtc_sleep_config_t cfg) +{ + rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get(); + REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, cfg.soc_clk_sel); + + //set 5 PWC state machine times to fit in main state machine time + REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, 1); + REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, RTC_CNTL_XTL_BUF_WAIT_DEFAULT); + REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_DEFAULT); + //set rom&ram timer + REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_ROM_RAM_POWERUP_TIMER, ROM_RAM_POWERUP_DELAY); + REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_ROM_RAM_WAIT_TIMER, ROM_RAM_WAIT_DELAY); + //set wifi timer + REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_POWERUP_TIMER, WIFI_POWERUP_DELAY); + REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_WAIT_TIMER, WIFI_WAIT_DELAY); + //set rtc peri timer + REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_POWERUP_TIMER, RTC_POWERUP_DELAY); + REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_WAIT_TIMER, RTC_WAIT_DELAY); + //set digital wrap timer + REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_POWERUP_TIMER, DG_WRAP_POWERUP_DELAY); + REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_WAIT_TIMER, DG_WRAP_WAIT_DELAY); + //set rtc memory timer + REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_RTCMEM_POWERUP_TIMER, RTC_MEM_POWERUP_DELAY); + REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_RTCMEM_WAIT_TIMER, RTC_MEM_WAIT_DELAY); + + if (cfg.soc_clk_sel == RTC_CNTL_SOC_CLK_SEL_PLL) { + REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, RTC_CNTL_PLL_BUF_WAIT_DEFAULT); + } else if (cfg.soc_clk_sel == RTC_CNTL_SOC_CLK_SEL_XTL) { + ets_update_cpu_frequency(xtal_freq); + rtc_clk_apb_freq_update(xtal_freq * MHZ); + } else if (cfg.soc_clk_sel == RTC_CNTL_SOC_CLK_SEL_8M) { + ets_update_cpu_frequency(8); + rtc_clk_apb_freq_update(8 * MHZ); + } + + if (cfg.lslp_mem_inf_fpu) { + SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU); + } else { + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU); + } + + rtc_sleep_pd_config_t pd_cfg = RTC_SLEEP_PD_CONFIG_ALL(cfg.lslp_meminf_pd); + rtc_sleep_pd(pd_cfg); + + if (cfg.rtc_mem_inf_fpu) { + SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_PU); + } else { + CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_PU); + } + + if (cfg.rtc_mem_inf_follow_cpu) { + SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FOLW_CPU); + } else { + CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FOLW_CPU); + } + + if (cfg.rtc_fastmem_pd_en) { + SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_PD_EN); + CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_PU); + CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_NOISO); + } else { + CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_PD_EN); + SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_PU); + SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_NOISO); + } + + if (cfg.rtc_slowmem_pd_en) { + SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_PD_EN); + CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_PU); + CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_NOISO); + } else { + CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_PD_EN); + SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_PU); + SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_NOISO); + } + + if (cfg.rtc_peri_pd_en) { + SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PD_EN); + } else { + CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PD_EN); + } + + if (cfg.wifi_pd_en) { + SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN); + } else { + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN); + } + + if (cfg.rom_mem_pd_en) { + SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_ROM_RAM_PD_EN); + } else { + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_ROM_RAM_PD_EN); + } + + if (cfg.deep_slp) { + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, + RTC_CNTL_DG_PAD_FORCE_ISO | RTC_CNTL_DG_PAD_FORCE_NOISO); + SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, + RTC_CNTL_DG_WRAP_FORCE_PU | RTC_CNTL_DG_WRAP_FORCE_PD); + CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_FORCE_NOSLEEP); + } else { + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); + SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_FORCE_NOSLEEP); + } + + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SLP, cfg.rtc_dbias_slp); + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_WAK, cfg.rtc_dbias_wak); + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, cfg.dig_dbias_wak); + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_SLP, cfg.dig_dbias_slp); +} + +void rtc_sleep_set_wakeup_time(uint64_t t) +{ + WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX); + WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32); +} + +uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt) +{ + REG_SET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_ENA, wakeup_opt); + WRITE_PERI_REG(RTC_CNTL_SLP_REJECT_CONF_REG, reject_opt); + + /* Start entry into sleep mode */ + SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN); + + while (GET_PERI_REG_MASK(RTC_CNTL_INT_RAW_REG, + RTC_CNTL_SLP_REJECT_INT_RAW | RTC_CNTL_SLP_WAKEUP_INT_RAW) == 0) { + ; + } + /* In deep sleep mode, we never get here */ + uint32_t reject = REG_GET_FIELD(RTC_CNTL_INT_RAW_REG, RTC_CNTL_SLP_REJECT_INT_RAW); + SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, + RTC_CNTL_SLP_REJECT_INT_CLR | RTC_CNTL_SLP_WAKEUP_INT_CLR); + return reject; +} diff --git a/components/soc/esp32/rtc_time.c b/components/soc/esp32/rtc_time.c new file mode 100644 index 000000000..7b1fb45f3 --- /dev/null +++ b/components/soc/esp32/rtc_time.c @@ -0,0 +1,116 @@ +// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include +#include "rom/ets_sys.h" +#include "soc/rtc.h" +#include "soc/rtc_cntl_reg.h" +#include "soc/timer_group_reg.h" + +#define MHZ (1000000) + +/* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0. + * This feature counts the number of XTAL clock cycles within a given number of + * RTC_SLOW_CLK cycles. + * + * Slow clock calibration feature has two modes of operation: one-off and cycling. + * In cycling mode (which is enabled by default on SoC reset), counting of XTAL + * cycles within RTC_SLOW_CLK cycle is done continuously. Cycling mode is enabled + * using TIMG_RTC_CALI_START_CYCLING bit. In one-off mode counting is performed + * once, and TIMG_RTC_CALI_RDY bit is set when counting is done. One-off mode is + * enabled using TIMG_RTC_CALI_START bit. + */ +uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) +{ + rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get(); + /* Enable requested clock (150k clock is always on) */ + if (cal_clk == RTC_CAL_32K_XTAL) { + SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN); + } + if (cal_clk == RTC_CAL_8MD256) { + SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN); + } + /* Prepare calibration */ + REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cal_clk); + CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING); + REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles); + /* Figure out how long to wait for calibration to finish */ + uint32_t expected_freq; + rtc_slow_freq_t slow_freq = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); + if (cal_clk == RTC_CAL_32K_XTAL || + (cal_clk == RTC_CAL_RTC_MUX && slow_freq == RTC_SLOW_FREQ_32K_XTAL)) { + expected_freq = 32768; /* standard 32k XTAL */ + } else if (cal_clk == RTC_CAL_8MD256 || + (cal_clk == RTC_CAL_RTC_MUX && slow_freq == RTC_SLOW_FREQ_8MD256)) { + expected_freq = 8 * MHZ / 256; + } else { + expected_freq = 150000; /* 150k internal oscillator */ + } + uint32_t us_time_estimate = slowclk_cycles * MHZ / expected_freq; + /* Start calibration */ + CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START); + SET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START); + /* Wait the expected time calibration should take. + * TODO: if running under RTOS, and us_time_estimate > RTOS tick, use the + * RTOS delay function. + */ + ets_delay_us(us_time_estimate); + /* Wait for calibration to finish up to another us_time_estimate */ + int timeout_us = us_time_estimate; + while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY) && + timeout_us-- > 0) { + ets_delay_us(1); + } + if (cal_clk == RTC_CAL_32K_XTAL) { + CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN); + } + if (cal_clk == RTC_CAL_8MD256) { + CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN); + } + if (timeout_us == 0) { + /* timed out waiting for calibration */ + return 0; + } + + uint64_t xtal_cycles = REG_GET_FIELD(TIMG_RTCCALICFG1_REG(0), TIMG_RTC_CALI_VALUE); + uint64_t divider = ((uint64_t)xtal_freq) * slowclk_cycles; + uint64_t period_64 = (xtal_cycles << RTC_CLK_CAL_FRACT) / divider; + uint32_t period = (uint32_t)(period_64 & UINT32_MAX); + return period; +} + +uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period) +{ + /* Overflow will happen in this function if time_in_us >= 2^45, which is about 400 days. + * TODO: fix overflow. + */ + return (time_in_us << RTC_CLK_CAL_FRACT) / period; +} + +uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period) +{ + return (rtc_cycles * period) >> RTC_CLK_CAL_FRACT; +} + +uint64_t rtc_time_get() +{ + SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE); + while (GET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_VALID) == 0) { + ets_delay_us(1); // might take 1 RTC slowclk period, don't flood RTC bus + } + SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, RTC_CNTL_TIME_VALID_INT_CLR); + uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG); + t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32; + return t; +} diff --git a/components/soc/esp32/soc_log.h b/components/soc/esp32/soc_log.h new file mode 100644 index 000000000..14ba19344 --- /dev/null +++ b/components/soc/esp32/soc_log.h @@ -0,0 +1,40 @@ +// Copyright 2016-2017 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +/** + * @file soc_log.h + * @brief SOC library logging functions + * + * To make SOC library compatible with environments which don't use ESP-IDF, + * this header file provides wrappers for logging functions. + */ + +#ifdef ESP_PLATFORM +#include "esp_log.h" +#define SOC_LOGE(tag, fmt, ...) ESP_LOGE(tag, fmt, ##__VA_ARGS__) +#define SOC_LOGW(tag, fmt, ...) ESP_LOGW(tag, fmt, ##__VA_ARGS__) +#define SOC_LOGI(tag, fmt, ...) ESP_LOGI(tag, fmt, ##__VA_ARGS__) +#define SOC_LOGD(tag, fmt, ...) ESP_LOGD(tag, fmt, ##__VA_ARGS__) +#define SOC_LOGV(tag, fmt, ...) ESP_LOGV(tag, fmt, ##__VA_ARGS__) + +#else +#include "rom/ets_sys.h" +#define SOC_LOGE(tag, fmt, ...) ets_printf("%s(err): " fmt, tag, ##__VA_ARGS__) +#define SOC_LOGW(tag, fmt, ...) ets_printf("%s(warn): " fmt, tag, ##__VA_ARGS__) +#define SOC_LOGI(tag, fmt, ...) ets_printf("%s(info): " fmt, tag, ##__VA_ARGS__) +#define SOC_LOGD(tag, fmt, ...) ets_printf("%s(dbg): " fmt, tag, ##__VA_ARGS__) +#define SOC_LOGV(tag, fmt, ...) ets_printf("%s: " fmt, tag, ##__VA_ARGS__) +#endif //ESP_PLATFORM diff --git a/components/soc/esp32/test/test_rtc_clk.c b/components/soc/esp32/test/test_rtc_clk.c new file mode 100644 index 000000000..cad78297b --- /dev/null +++ b/components/soc/esp32/test/test_rtc_clk.c @@ -0,0 +1,84 @@ +#include +#include "unity.h" +#include "rom/ets_sys.h" +#include "soc/rtc.h" +#include "soc/rtc_cntl_reg.h" +#include "soc/rtc_io_reg.h" +#include "soc/sens_reg.h" +#include "soc/io_mux_reg.h" +#include "driver/rtc_io.h" + +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" + + +#define CALIBRATE_ONE(cali_clk) calibrate_one(cali_clk, #cali_clk) + +static uint32_t calibrate_one(rtc_cal_sel_t cal_clk, const char* name) +{ + const uint32_t cal_count = 1000; + const float factor = (1 << 19) * 1000.0f; + uint32_t cali_val; + printf("%s:\n", name); + for (int i = 0; i < 5; ++i) { + printf("calibrate (%d): ", i); + cali_val = rtc_clk_cal(cal_clk, cal_count); + printf("%.3f kHz\n", factor / (float) cali_val); + } + return cali_val; +} + +TEST_CASE("RTC_SLOW_CLK sources calibration", "[rtc_clk]") +{ + rtc_clk_32k_enable(true); + rtc_clk_8m_enable(true, true); + + CALIBRATE_ONE(RTC_CAL_RTC_MUX); + CALIBRATE_ONE(RTC_CAL_8MD256); + uint32_t cal_32k = CALIBRATE_ONE(RTC_CAL_32K_XTAL); + + if (cal_32k == 0) { + printf("32K XTAL OSC has not started up"); + } else { + printf("switching to RTC_SLOW_FREQ_32K_XTAL: "); + rtc_clk_slow_freq_set(RTC_SLOW_FREQ_32K_XTAL); + printf("done\n"); + + CALIBRATE_ONE(RTC_CAL_RTC_MUX); + CALIBRATE_ONE(RTC_CAL_8MD256); + CALIBRATE_ONE(RTC_CAL_32K_XTAL); + } + + printf("switching to RTC_SLOW_FREQ_8MD256: "); + rtc_clk_slow_freq_set(RTC_SLOW_FREQ_8MD256); + printf("done\n"); + + CALIBRATE_ONE(RTC_CAL_RTC_MUX); + CALIBRATE_ONE(RTC_CAL_8MD256); + CALIBRATE_ONE(RTC_CAL_32K_XTAL); +} + +/* The following two are not unit tests, but are added here to make it easy to + * check the frequency of 150k/32k oscillators. The following two "tests" will + * output either 32k or 150k clock to GPIO25. + */ + +static void pull_out_clk(int sel) +{ + REG_SET_BIT(RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_MUX_SEL_M); + REG_CLR_BIT(RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_RDE_M | RTC_IO_PDAC1_RUE_M); + REG_SET_FIELD(RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_FUN_SEL, 1); + REG_SET_FIELD(SENS_SAR_DAC_CTRL1_REG, SENS_DEBUG_BIT_SEL, 0); + REG_SET_FIELD(RTC_IO_RTC_DEBUG_SEL_REG, RTC_IO_DEBUG_SEL0, sel); +} + +TEST_CASE("Output 150k clock to GPIO25", "[rtc_clk][ignore]") +{ + pull_out_clk(RTC_IO_DEBUG_SEL0_150K_OSC); +} + +TEST_CASE("Output 32k XTAL clock to GPIO25", "[rtc_clk][ignore]") +{ + rtc_clk_32k_enable(true); + pull_out_clk(RTC_IO_DEBUG_SEL0_32K_XTAL); +} diff --git a/components/soc/test/component.mk b/components/soc/test/component.mk new file mode 100644 index 000000000..f8de6c86f --- /dev/null +++ b/components/soc/test/component.mk @@ -0,0 +1,8 @@ +# currently the only SoC supported; to be moved into Kconfig +SOC_NAME := esp32 + +COMPONENT_SRCDIRS := ../$(SOC_NAME)/test + +COMPONENT_ADD_LDFLAGS = -Wl,--whole-archive -l$(COMPONENT_NAME) -Wl,--no-whole-archive + + From 90e740eb5ff0dd7b677a6c32d5484ce351936ec9 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Tue, 11 Apr 2017 16:01:30 +0800 Subject: [PATCH 5/5] esp32: update libraries This removes librtc_{clk,pm}.a and updates librtc.a to use the new functions defined in ESP-IDF source code. --- components/esp32/lib | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/esp32/lib b/components/esp32/lib index ae20d8efc..8ac3a6e76 160000 --- a/components/esp32/lib +++ b/components/esp32/lib @@ -1 +1 @@ -Subproject commit ae20d8efce9c46dea9dc949b542d8dfaa3ea136c +Subproject commit 8ac3a6e76d11e3fec6bbbee5ca7d9b3a38435e4d