ethernet: support giving 50mhz rmii clock with both 40mhz and 26 mhz rtc xtal
Merges https://github.com/espressif/esp-idf/pull/3769 Closes https://github.com/espressif/esp-idf/pull/3704
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1 changed files with 29 additions and 4 deletions
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@ -20,6 +20,34 @@
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#define ETH_CRC_LENGTH (4)
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#define ETH_CRC_LENGTH (4)
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#if CONFIG_ETH_RMII_CLK_OUTPUT
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static void emac_config_apll_clock(void)
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{
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/* apll_freq = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536)/((o_div + 2) * 2) */
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rtc_xtal_freq_t rtc_xtal_freq = rtc_clk_xtal_freq_get();
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switch (rtc_xtal_freq) {
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case RTC_XTAL_FREQ_40M: // Recommended
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/* 50 MHz = 40MHz * (4 + 6) / (2 * (2 + 2) = 50.000 */
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/* sdm0 = 0, sdm1 = 0, sdm2 = 6, o_div = 2 */
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rtc_clk_apll_enable(true, 0, 0, 6, 2);
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break;
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case RTC_XTAL_FREQ_26M:
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/* 50 MHz = 26MHz * (4 + 15 + 118 / 256 + 39/65536) / ((3 + 2) * 2) = 49.999992 */
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/* sdm0 = 39, sdm1 = 118, sdm2 = 15, o_div = 3 */
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rtc_clk_apll_enable(true, 39, 118, 15, 3);
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break;
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case RTC_XTAL_FREQ_24M:
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/* 50 MHz = 24MHz * (4 + 12 + 255 / 256 + 255/65536) / ((2 + 2) * 2) = 49.499977 */
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/* sdm0 = 255, sdm1 = 255, sdm2 = 12, o_div = 2 */
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rtc_clk_apll_enable(true, 255, 255, 12, 2);
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break;
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default: // Assume we have a 40M xtal
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rtc_clk_apll_enable(true, 0, 0, 6, 2);
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break;
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}
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}
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#endif
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void emac_hal_init(emac_hal_context_t *hal, void *descriptors,
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void emac_hal_init(emac_hal_context_t *hal, void *descriptors,
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uint8_t **rx_buf, uint8_t **tx_buf)
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uint8_t **rx_buf, uint8_t **tx_buf)
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{
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{
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@ -91,10 +119,7 @@ void emac_hal_lowlevel_init(emac_hal_context_t *hal)
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hal->ext_regs->ex_clk_ctrl.ext_en = 0;
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hal->ext_regs->ex_clk_ctrl.ext_en = 0;
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hal->ext_regs->ex_clk_ctrl.int_en = 1;
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hal->ext_regs->ex_clk_ctrl.int_en = 1;
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hal->ext_regs->ex_oscclk_conf.clk_sel = 0;
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hal->ext_regs->ex_oscclk_conf.clk_sel = 0;
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/* apll_freq = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536)/((o_div + 2) * 2) */
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emac_config_apll_clock();
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/* 50 MHz = 40MHz * (4 + 6) / (2 * (2 + 2) = 400MHz / 8 */
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/* sdm2 = 6, sdm1 = 0, sdm0 = 0, o_div = 2 */
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rtc_clk_apll_enable(true, 0, 0, 6, 2);
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hal->ext_regs->ex_clkout_conf.div_num = 0;
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hal->ext_regs->ex_clkout_conf.div_num = 0;
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hal->ext_regs->ex_clkout_conf.h_div_num = 0;
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hal->ext_regs->ex_clkout_conf.h_div_num = 0;
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#if CONFIG_ETH_RMII_CLK_OUTPUT_GPIO0
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#if CONFIG_ETH_RMII_CLK_OUTPUT_GPIO0
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