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Merge branch 'bugfix/fix_16mbit_psram_id_read_error' into 'master'

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psram: fix 16mbit psram id read error

See merge request espressif/esp-idf!9083
This commit is contained in:
Angus Gratton 2020-06-19 11:49:26 +08:00
commit 91d8c26349
2 changed files with 15 additions and 2 deletions
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6
components/esp32/spiram_psram.c
View file

@ -900,8 +900,14 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad
bootloader_common_vddsdio_configure();
// GPIO related settings
psram_gpio_config(&psram_io, mode);
/* 16Mbit psram ID read error
* workaround: Issue a pre-condition of dummy read id, then Read ID command
*/
psram_read_id(&s_psram_id);
psram_read_id(&s_psram_id);
if (!PSRAM_IS_VALID(s_psram_id)) {
ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x", (uint32_t)s_psram_id);
return ESP_FAIL;
}

9
components/esp32s2/spiram_psram.c
View file

@ -47,6 +47,8 @@
#if CONFIG_SPIRAM
#include "soc/rtc.h"
static const char* TAG = "psram";
//Commands for PSRAM chip
#define PSRAM_READ 0x03
#define PSRAM_FAST_READ 0x0B
@ -150,7 +152,6 @@ typedef struct {
.psram_spihd_sd2_io = PSRAM_SPIHD_SD2_IO, \
}
//static const char* TAG = "psram";
typedef enum {
PSRAM_SPI_1 = 0x1,
/* PSRAM_SPI_2, */
@ -431,8 +432,14 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad
/* SPI1: set cs timing(hold time) in order to send commands on SPI1 */
psram_set_clk_mode(_SPI_FLASH_PORT, PSRAM_CLK_MODE_A1C);
psram_set_spi1_cmd_cs_timing(PSRAM_CLK_MODE_A1C);
/* 16Mbit psram ID read error
* workaround: Issue a pre-condition of dummy read id, then Read ID command
*/
psram_read_id(&s_psram_id);
psram_read_id(&s_psram_id);
if (!PSRAM_IS_VALID(s_psram_id)) {
ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x", s_psram_id);
return ESP_FAIL;
}