Merge branch 'bugfix/fix_16mbit_psram_id_read_error' into 'master'
psram: fix 16mbit psram id read error See merge request espressif/esp-idf!9083
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commit
91d8c26349
2 changed files with 15 additions and 2 deletions
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@ -900,8 +900,14 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad
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bootloader_common_vddsdio_configure();
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// GPIO related settings
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psram_gpio_config(&psram_io, mode);
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/* 16Mbit psram ID read error
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* workaround: Issue a pre-condition of dummy read id, then Read ID command
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*/
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psram_read_id(&s_psram_id);
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psram_read_id(&s_psram_id);
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if (!PSRAM_IS_VALID(s_psram_id)) {
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ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x", (uint32_t)s_psram_id);
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return ESP_FAIL;
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}
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@ -47,6 +47,8 @@
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#if CONFIG_SPIRAM
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#include "soc/rtc.h"
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static const char* TAG = "psram";
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//Commands for PSRAM chip
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#define PSRAM_READ 0x03
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#define PSRAM_FAST_READ 0x0B
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@ -150,7 +152,6 @@ typedef struct {
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.psram_spihd_sd2_io = PSRAM_SPIHD_SD2_IO, \
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}
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//static const char* TAG = "psram";
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typedef enum {
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PSRAM_SPI_1 = 0x1,
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/* PSRAM_SPI_2, */
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@ -431,8 +432,14 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad
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/* SPI1: set cs timing(hold time) in order to send commands on SPI1 */
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psram_set_clk_mode(_SPI_FLASH_PORT, PSRAM_CLK_MODE_A1C);
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psram_set_spi1_cmd_cs_timing(PSRAM_CLK_MODE_A1C);
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psram_read_id(&s_psram_id);
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/* 16Mbit psram ID read error
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* workaround: Issue a pre-condition of dummy read id, then Read ID command
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*/
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psram_read_id(&s_psram_id);
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psram_read_id(&s_psram_id);
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if (!PSRAM_IS_VALID(s_psram_id)) {
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ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x", s_psram_id);
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return ESP_FAIL;
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}
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