Crash_Override/OVMS3-idf
1
0
Fork 0
Code Issues Pull requests Projects Releases Wiki Activity

Merge branch 'test/fix_psram_readid_redundant' into 'master'

Browse source 
spiram: fix the read id failure

See merge request espressif/esp-idf!9275
This commit is contained in:
Michael (XIAO Xufeng) 2020-06-24 00:34:59 +08:00
commit 91310381d5
2 changed files with 28 additions and 22 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

25
components/esp32/spiram_psram.c
View file

@ -397,11 +397,9 @@ static void psram_disable_qio_mode(psram_spi_num_t spi_num)
psram_cmd_end(spi_num); psram_cmd_end(spi_num);
} }
//read psram id //read psram id, should issue `psram_disable_qio_mode` before calling this
static void psram_read_id(uint64_t* dev_id) static void psram_read_id(psram_spi_num_t spi_num, uint64_t* dev_id)
{ {
psram_spi_num_t spi_num = PSRAM_SPI_1;
psram_disable_qio_mode(spi_num);
uint32_t dummy_bits = 0 + extra_dummy; uint32_t dummy_bits = 0 + extra_dummy;
uint32_t psram_id[2] = {0}; uint32_t psram_id[2] = {0};
psram_cmd_t ps_cmd; psram_cmd_t ps_cmd;
@ -901,14 +899,19 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad
// GPIO related settings // GPIO related settings
psram_gpio_config(&psram_io, mode); psram_gpio_config(&psram_io, mode);
/* 16Mbit psram ID read error psram_spi_num_t spi_num = PSRAM_SPI_1;
* workaround: Issue a pre-condition of dummy read id, then Read ID command psram_disable_qio_mode(spi_num);
*/ psram_read_id(spi_num, &s_psram_id);
psram_read_id(&s_psram_id);
psram_read_id(&s_psram_id);
if (!PSRAM_IS_VALID(s_psram_id)) { if (!PSRAM_IS_VALID(s_psram_id)) {
ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x", (uint32_t)s_psram_id); /* 16Mbit psram ID read error workaround:
return ESP_FAIL; * treat the first read id as a dummy one as the pre-condition,
* Send Read ID command again
*/
psram_read_id(spi_num, &s_psram_id);
if (!PSRAM_IS_VALID(s_psram_id)) {
ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x", (uint32_t)s_psram_id);
return ESP_FAIL;
}
} }
if (psram_is_32mbit_ver0()) { if (psram_is_32mbit_ver0()) {

25
components/esp32s2/spiram_psram.c
View file

@ -306,11 +306,9 @@ bool psram_support_wrap_size(uint32_t wrap_size)
} }
//read psram id //read psram id, should issue `psram_disable_qio_mode` before calling this
static void psram_read_id(uint32_t* dev_id) static void psram_read_id(int spi_num, uint32_t* dev_id)
{ {
int spi_num = PSRAM_SPI_1;
psram_disable_qio_mode(spi_num);
psram_exec_cmd(spi_num, PSRAM_CMD_SPI, psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
PSRAM_DEVICE_ID, 8, /* command and command bit len*/ PSRAM_DEVICE_ID, 8, /* command and command bit len*/
0, 24, /* address and address bit len*/ 0, 24, /* address and address bit len*/
@ -433,14 +431,19 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad
psram_set_clk_mode(_SPI_FLASH_PORT, PSRAM_CLK_MODE_A1C); psram_set_clk_mode(_SPI_FLASH_PORT, PSRAM_CLK_MODE_A1C);
psram_set_spi1_cmd_cs_timing(PSRAM_CLK_MODE_A1C); psram_set_spi1_cmd_cs_timing(PSRAM_CLK_MODE_A1C);
/* 16Mbit psram ID read error int spi_num = PSRAM_SPI_1;
* workaround: Issue a pre-condition of dummy read id, then Read ID command psram_disable_qio_mode(spi_num);
*/ psram_read_id(spi_num, &s_psram_id);
psram_read_id(&s_psram_id);
psram_read_id(&s_psram_id);
if (!PSRAM_IS_VALID(s_psram_id)) { if (!PSRAM_IS_VALID(s_psram_id)) {
ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x", s_psram_id); /* 16Mbit psram ID read error workaround:
return ESP_FAIL; * treat the first read id as a dummy one as the pre-condition,
* Send Read ID command again
*/
psram_read_id(spi_num, &s_psram_id);
if (!PSRAM_IS_VALID(s_psram_id)) {
ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x", s_psram_id);
return ESP_FAIL;
}
} }
psram_clk_mode_t clk_mode = PSRAM_CLK_MODE_MAX; psram_clk_mode_t clk_mode = PSRAM_CLK_MODE_MAX;