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rmt: add HAL layer

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This commit is contained in:
morris 2019-11-19 16:10:02 +08:00
parent bcf1f992ff
commit 8fd8695ea1
14 changed files with 2375 additions and 1414 deletions
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283
components/driver/include/driver/rmt.h
View file

@ -1,9 +1,9 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
@ -12,98 +12,38 @@
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _DRIVER_RMT_CTRL_H_
#define _DRIVER_RMT_CTRL_H_
#include "esp_err.h"
#include "soc/rmt_periph.h"
#include "freertos/FreeRTOS.h"
#include "freertos/semphr.h"
#include "freertos/xtensa_api.h"
#include "freertos/ringbuf.h"
#include "driver/gpio.h"
#include "driver/periph_ctrl.h"
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define RMT_MEM_BLOCK_BYTE_NUM (256)
#define RMT_MEM_ITEM_NUM (RMT_MEM_BLOCK_BYTE_NUM/4)
typedef enum {
RMT_CHANNEL_0 = 0, /*!< RMT Channel 0 */
RMT_CHANNEL_1, /*!< RMT Channel 1 */
RMT_CHANNEL_2, /*!< RMT Channel 2 */
RMT_CHANNEL_3, /*!< RMT Channel 3 */
//ESP32-S2 only have 4 channel
#ifdef CONFIG_IDF_TARGET_ESP32
RMT_CHANNEL_4, /*!< RMT Channel 4 */
RMT_CHANNEL_5, /*!< RMT Channel 5 */
RMT_CHANNEL_6, /*!< RMT Channel 6 */
RMT_CHANNEL_7, /*!< RMT Channel 7 */
#endif
RMT_CHANNEL_MAX
} rmt_channel_t;
typedef enum {
RMT_MEM_OWNER_TX = 0, /*!< RMT TX mode, RMT transmitter owns the memory block*/
RMT_MEM_OWNER_RX = 1, /*!< RMT RX mode, RMT receiver owns the memory block*/
RMT_MEM_OWNER_MAX,
}rmt_mem_owner_t;
typedef enum {
RMT_BASECLK_REF = 0, /*!< RMT source clock system reference tick, 1MHz by default (not supported in this version) */
RMT_BASECLK_APB, /*!< RMT source clock is APB CLK, 80Mhz by default */
RMT_BASECLK_MAX,
} rmt_source_clk_t;
typedef enum {
RMT_DATA_MODE_FIFO = 0, /*<! RMT memory access in FIFO mode */
RMT_DATA_MODE_MEM = 1, /*<! RMT memory access in memory mode */
RMT_DATA_MODE_MAX,
} rmt_data_mode_t;
typedef enum {
RMT_MODE_TX = 0, /*!< RMT TX mode */
RMT_MODE_RX, /*!< RMT RX mode */
RMT_MODE_MAX
} rmt_mode_t;
typedef enum {
RMT_IDLE_LEVEL_LOW = 0, /*!< RMT TX idle level: low Level */
RMT_IDLE_LEVEL_HIGH, /*!< RMT TX idle level: high Level */
RMT_IDLE_LEVEL_MAX,
} rmt_idle_level_t;
typedef enum {
RMT_CARRIER_LEVEL_LOW = 0, /*!< RMT carrier wave is modulated for low Level output */
RMT_CARRIER_LEVEL_HIGH, /*!< RMT carrier wave is modulated for high Level output */
RMT_CARRIER_LEVEL_MAX
} rmt_carrier_level_t;
typedef enum {
RMT_CHANNEL_UNINIT = 0, /*!< RMT channel uninitialized */
RMT_CHANNEL_IDLE = 1, /*!< RMT channel status idle */
RMT_CHANNEL_BUSY = 2, /*!< RMT channel status busy */
} rmt_channel_status_t;
#include <stdbool.h>
#include <stdint.h>
#include "esp_err.h"
#include "driver/gpio.h"
#include "freertos/FreeRTOS.h"
#include "freertos/ringbuf.h"
#include "soc/rmt_caps.h"
#include "soc/rmt_struct.h"
#include "hal/rmt_types.h"
/**
* @brief Data struct of RMT channel status
* @brief Define memory space of each RMT channel (in words = 4 bytes)
*
*/
typedef struct {
rmt_channel_status_t status[RMT_CHANNEL_MAX]; /*!< Store the current status of each channel */
} rmt_channel_status_result_t;
#define RMT_MEM_ITEM_NUM RMT_CHANNEL_MEM_WORDS
/**
* @brief Data struct of RMT TX configure parameters
*/
typedef struct {
bool loop_en; /*!< Enable sending RMT items in a loop */
uint32_t carrier_freq_hz; /*!< RMT carrier frequency */
uint8_t carrier_duty_percent; /*!< RMT carrier duty (%) */
rmt_carrier_level_t carrier_level; /*!< Level of the RMT output, when the carrier is applied */
bool carrier_en; /*!< RMT carrier enable */
rmt_idle_level_t idle_level; /*!< RMT idle level */
uint8_t carrier_duty_percent; /*!< RMT carrier duty (%) */
bool carrier_en; /*!< RMT carrier enable */
bool loop_en; /*!< Enable sending RMT items in a loop */
bool idle_output_en; /*!< RMT idle level output enable */
} rmt_tx_config_t;
@ -111,9 +51,9 @@ typedef struct {
* @brief Data struct of RMT RX configure parameters
*/
typedef struct {
bool filter_en; /*!< RMT receiver filter enable */
uint8_t filter_ticks_thresh; /*!< RMT filter tick number */
uint16_t idle_threshold; /*!< RMT RX idle threshold */
uint8_t filter_ticks_thresh; /*!< RMT filter tick number */
bool filter_en; /*!< RMT receiver filter enable */
} rmt_rx_config_t;
/**
@ -122,8 +62,8 @@ typedef struct {
typedef struct {
rmt_mode_t rmt_mode; /*!< RMT mode: transmitter or receiver */
rmt_channel_t channel; /*!< RMT channel */
uint8_t clk_div; /*!< RMT channel counter divider */
gpio_num_t gpio_num; /*!< RMT GPIO number */
uint8_t clk_div; /*!< RMT channel counter divider */
uint8_t mem_block_num; /*!< RMT memory block number */
union {
rmt_tx_config_t tx_config; /*!< RMT TX parameter */
@ -131,8 +71,56 @@ typedef struct {
};
} rmt_config_t;
/**
* @brief Default configuration for Tx channel
*
*/
#define RMT_DEFAULT_CONFIG_TX(gpio, channel_id) \
{ \
.rmt_mode = RMT_MODE_TX, \
.channel = channel_id, \
.gpio_num = gpio, \
.clk_div = 80, \
.mem_block_num = 1, \
.tx_config = { \
.carrier_freq_hz = 38000, \
.carrier_level = RMT_CARRIER_LEVEL_HIGH, \
.idle_level = RMT_IDLE_LEVEL_LOW, \
.carrier_duty_percent = 33, \
.carrier_en = false, \
.loop_en = false, \
.idle_output_en = true, \
} \
}
/**
* @brief Default configuration for RX channel
*
*/
#define RMT_DEFAULT_CONFIG_RX(gpio, channel_id) \
{ \
.rmt_mode = RMT_MODE_RX, \
.channel = channel_id, \
.gpio_num = gpio, \
.clk_div = 80, \
.mem_block_num = 1, \
.rx_config = { \
.idle_threshold = 12000, \
.filter_ticks_thresh = 100, \
.filter_en = true, \
} \
}
/**
* @brief RMT interrupt handle
*
*/
typedef intr_handle_t rmt_isr_handle_t;
/**
* @brief Type of RMT Tx End callback function
*
*/
typedef void (*rmt_tx_end_fn_t)(rmt_channel_t channel, void *arg);
/**
@ -154,8 +142,9 @@ typedef struct {
* @param wanted_num The number of rmt format data that wanted to get.
* @param[out] translated_size The size of the raw data that has been converted to rmt format,
* it should return 0 if no data is converted in user callback.
* @param[out] item_num The number of the rmt format data that actually converted to, it can be less than wanted_num if there is not enough raw data,
* but cannot exceed wanted_num. it should return 0 if no data was converted.
* @param[out] item_num The number of the rmt format data that actually converted to,
* it can be less than wanted_num if there is not enough raw data, but cannot exceed wanted_num.
* it should return 0 if no data was converted.
*
* @note
* In fact, item_num should be a multiple of translated_size, e.g. :
@ -167,7 +156,7 @@ typedef void (*sample_to_rmt_t)(const void* src, rmt_item32_t* dest, size_t src_
/**
* @brief Set RMT clock divider, channel clock is divided from source clock.
*
* @param channel RMT channel (0-7)
* @param channel RMT channel
* @param div_cnt RMT counter clock divider
*
* @return
@ -179,7 +168,7 @@ esp_err_t rmt_set_clk_div(rmt_channel_t channel, uint8_t div_cnt);
/**
* @brief Get RMT clock divider, channel clock is divided from source clock.
*
* @param channel RMT channel (0-7)
* @param channel RMT channel
* @param div_cnt pointer to accept RMT counter divider
*
* @return
@ -195,7 +184,7 @@ esp_err_t rmt_get_clk_div(rmt_channel_t channel, uint8_t* div_cnt);
* for longer than idle_thres channel clock cycles,
* the receive process is finished.
*
* @param channel RMT channel (0-7)
* @param channel RMT channel
* @param thresh RMT RX idle threshold
*
* @return
@ -211,7 +200,7 @@ esp_err_t rmt_set_rx_idle_thresh(rmt_channel_t channel, uint16_t thresh);
* for longer than idle_thres channel clock cycles,
* the receive process is finished.
*
* @param channel RMT channel (0-7)
* @param channel RMT channel
* @param thresh pointer to accept RMT RX idle threshold value
*
* @return
@ -238,7 +227,7 @@ esp_err_t rmt_get_rx_idle_thresh(rmt_channel_t channel, uint16_t *thresh);
* block of the next channel.
* Channel 0 can use at most 8 blocks of memory, accordingly channel 7 can only use one memory block.
*
* @param channel RMT channel (0-7)
* @param channel RMT channel
* @param rmt_mem_num RMT RX memory block number, one block has 64 * 32 bits.
*
* @return
@ -250,7 +239,7 @@ esp_err_t rmt_set_mem_block_num(rmt_channel_t channel, uint8_t rmt_mem_num);
/**
* @brief Get RMT memory block number
*
* @param channel RMT channel (0-7)
* @param channel RMT channel
* @param rmt_mem_num Pointer to accept RMT RX memory block number
*
* @return
@ -265,11 +254,11 @@ esp_err_t rmt_get_mem_block_num(rmt_channel_t channel, uint8_t* rmt_mem_num);
* Set different values for carrier_high and carrier_low to set different frequency of carrier.
* The unit of carrier_high/low is the source clock tick, not the divided channel counter clock.
*
* @param channel RMT channel (0-7)
* @param channel RMT channel
* @param carrier_en Whether to enable output carrier.
* @param high_level High level duration of carrier
* @param low_level Low level duration of carrier.
* @param carrier_level Configure the way carrier wave is modulated for channel 0-7.
* @param carrier_level Configure the way carrier wave is modulated for channel.
* - 1'b1:transmit on low output level
* - 1'b0:transmit on high output level
*
@ -284,7 +273,7 @@ esp_err_t rmt_set_tx_carrier(rmt_channel_t channel, bool carrier_en, uint16_t hi
*
* Reduce power consumed by memory. 1:memory is in low power state.
*
* @param channel RMT channel (0-7)
* @param channel RMT channel
* @param pd_en RMT memory low power enable.
*
* @return
@ -296,7 +285,7 @@ esp_err_t rmt_set_mem_pd(rmt_channel_t channel, bool pd_en);
/**
* @brief Get RMT memory low power mode.
*
* @param channel RMT channel (0-7)
* @param channel RMT channel
* @param pd_en Pointer to accept RMT memory low power mode.
*
* @return
@ -308,7 +297,7 @@ esp_err_t rmt_get_mem_pd(rmt_channel_t channel, bool* pd_en);
/**
* @brief Set RMT start sending data from memory.
*
* @param channel RMT channel (0-7)
* @param channel RMT channel
* @param tx_idx_rst Set true to reset memory index for TX.
* Otherwise, transmitter will continue sending from the last index in memory.
*
@ -321,7 +310,7 @@ esp_err_t rmt_tx_start(rmt_channel_t channel, bool tx_idx_rst);
/**
* @brief Set RMT stop sending.
*
* @param channel RMT channel (0-7)
* @param channel RMT channel
*
* @return
* - ESP_ERR_INVALID_ARG Parameter error
@ -332,7 +321,7 @@ esp_err_t rmt_tx_stop(rmt_channel_t channel);
/**
* @brief Set RMT start receiving data.
*
* @param channel RMT channel (0-7)
* @param channel RMT channel
* @param rx_idx_rst Set true to reset memory index for receiver.
* Otherwise, receiver will continue receiving data to the last index in memory.
*
@ -345,7 +334,7 @@ esp_err_t rmt_rx_start(rmt_channel_t channel, bool rx_idx_rst);
/**
* @brief Set RMT stop receiving data.
*
* @param channel RMT channel (0-7)
* @param channel RMT channel
*
* @return
* - ESP_ERR_INVALID_ARG Parameter error
@ -356,7 +345,7 @@ esp_err_t rmt_rx_stop(rmt_channel_t channel);
/**
* @brief Reset RMT TX/RX memory index.
*
* @param channel RMT channel (0-7)
* @param channel RMT channel
*
* @return
* - ESP_ERR_INVALID_ARG Parameter error
@ -367,7 +356,7 @@ esp_err_t rmt_memory_rw_rst(rmt_channel_t channel);
/**
* @brief Set RMT memory owner.
*
* @param channel RMT channel (0-7)
* @param channel RMT channel
* @param owner To set when the transmitter or receiver can process the memory of channel.
*
* @return
@ -379,7 +368,7 @@ esp_err_t rmt_set_memory_owner(rmt_channel_t channel, rmt_mem_owner_t owner);
/**
* @brief Get RMT memory owner.
*
* @param channel RMT channel (0-7)
* @param channel RMT channel
* @param owner Pointer to get memory owner.
*
* @return
@ -391,10 +380,10 @@ esp_err_t rmt_get_memory_owner(rmt_channel_t channel, rmt_mem_owner_t* owner);
/**
* @brief Set RMT tx loop mode.
*
* @param channel RMT channel (0-7)
* @param channel RMT channel
* @param loop_en Enable RMT transmitter loop sending mode.
* If set true, transmitter will continue sending from the first data
* to the last data in channel 0-7 over and over again in a loop.
* to the last data in channel over and over again in a loop.
*
* @return
* - ESP_ERR_INVALID_ARG Parameter error
@ -405,7 +394,7 @@ esp_err_t rmt_set_tx_loop_mode(rmt_channel_t channel, bool loop_en);
/**
* @brief Get RMT tx loop mode.
*
* @param channel RMT channel (0-7)
* @param channel RMT channel
* @param loop_en Pointer to accept RMT transmitter loop sending mode.
*
* @return
@ -417,10 +406,10 @@ esp_err_t rmt_get_tx_loop_mode(rmt_channel_t channel, bool* loop_en);
/**
* @brief Set RMT RX filter.
*
* In receive mode, channel 0-7 will ignore input pulse when the pulse width is smaller than threshold.
* In receive mode, channel will ignore input pulse when the pulse width is smaller than threshold.
* Counted in source clock, not divided counter clock.
*
* @param channel RMT channel (0-7)
* @param channel RMT channel
* @param rx_filter_en To enable RMT receiver filter.
* @param thresh Threshold of pulse width for receiver.
*
@ -437,7 +426,7 @@ esp_err_t rmt_set_rx_filter(rmt_channel_t channel, bool rx_filter_en, uint8_t th
* 1. APB clock which is 80Mhz
* 2. REF tick clock, which would be 1Mhz (not supported in this version).
*
* @param channel RMT channel (0-7)
* @param channel RMT channel
* @param base_clk To choose source clock for RMT module.
*
* @return
@ -453,7 +442,7 @@ esp_err_t rmt_set_source_clk(rmt_channel_t channel, rmt_source_clk_t base_clk);
* 1. APB clock which is 80Mhz
* 2. REF tick clock, which would be 1Mhz (not supported in this version).
*
* @param channel RMT channel (0-7)
* @param channel RMT channel
* @param src_clk Pointer to accept source clock for RMT module.
*
* @return
@ -465,9 +454,9 @@ esp_err_t rmt_get_source_clk(rmt_channel_t channel, rmt_source_clk_t* src_clk);
/**
* @brief Set RMT idle output level for transmitter
*
* @param channel RMT channel (0-7)
* @param channel RMT channel
* @param idle_out_en To enable idle level output.
* @param level To set the output signal's level for channel 0-7 in idle state.
* @param level To set the output signal's level for channel in idle state.
*
* @return
* - ESP_ERR_INVALID_ARG Parameter error
@ -478,7 +467,7 @@ esp_err_t rmt_set_idle_level(rmt_channel_t channel, bool idle_out_en, rmt_idle_l
/**
* @brief Get RMT idle output level for transmitter
*
* @param channel RMT channel (0-7)
* @param channel RMT channel
* @param idle_out_en Pointer to accept value of enable idle.
* @param level Pointer to accept value of output signal's level in idle state for specified channel.
*
@ -491,7 +480,7 @@ esp_err_t rmt_get_idle_level(rmt_channel_t channel, bool* idle_out_en, rmt_idle_
/**
* @brief Get RMT status
*
* @param channel RMT channel (0-7)
* @param channel RMT channel
* @param status Pointer to accept channel status.
* Please refer to RMT_CHnSTATUS_REG(n=0~7) in `rmt_reg.h` for more details of each field.
*
@ -520,7 +509,7 @@ void rmt_clr_intr_enable_mask(uint32_t mask);
/**
* @brief Set RMT RX interrupt enable
*
* @param channel RMT channel (0 - 7)
* @param channel RMT channel
* @param en enable or disable RX interrupt.
*
* @return
@ -532,7 +521,7 @@ esp_err_t rmt_set_rx_intr_en(rmt_channel_t channel, bool en);
/**
* @brief Set RMT RX error interrupt enable
*
* @param channel RMT channel (0 - 7)
* @param channel RMT channel
* @param en enable or disable RX err interrupt.
*
* @return
@ -544,7 +533,7 @@ esp_err_t rmt_set_err_intr_en(rmt_channel_t channel, bool en);
/**
* @brief Set RMT TX interrupt enable
*
* @param channel RMT channel (0 - 7)
* @param channel RMT channel
* @param en enable or disable TX interrupt.
*
* @return
@ -558,7 +547,7 @@ esp_err_t rmt_set_tx_intr_en(rmt_channel_t channel, bool en);
*
* An interrupt will be triggered when the number of transmitted items reaches the threshold value
*
* @param channel RMT channel (0 - 7)
* @param channel RMT channel
* @param en enable or disable TX event interrupt.
* @param evt_thresh RMT event interrupt threshold value
*
@ -571,7 +560,7 @@ esp_err_t rmt_set_tx_thr_intr_en(rmt_channel_t channel, bool en, uint16_t evt_th
/**
* @brief Set RMT pin
*
* @param channel RMT channel (0 - 7)
* @param channel RMT channel
* @param mode TX or RX mode for RMT
* @param gpio_num GPIO number to transmit or receive the signal.
*
@ -627,7 +616,7 @@ esp_err_t rmt_isr_deregister(rmt_isr_handle_t handle);
/**
* @brief Fill memory data of channel with given RMT items.
*
* @param channel RMT channel (0 - 7)
* @param channel RMT channel
* @param item Pointer of items.
* @param item_num RMT sending items number.
* @param mem_offset Index offset of memory.
@ -641,7 +630,7 @@ esp_err_t rmt_fill_tx_items(rmt_channel_t channel, const rmt_item32_t* item, uin
/**
* @brief Initialize RMT driver
*
* @param channel RMT channel (0 - 7)
* @param channel RMT channel
* @param rx_buf_size Size of RMT RX ringbuffer. Can be 0 if the RX ringbuffer is not used.
* @param intr_alloc_flags Flags for the RMT driver interrupt handler. Pass 0 for default flags. See esp_intr_alloc.h for details.
* If ESP_INTR_FLAG_IRAM is used, please do not use the memory allocated from psram when calling rmt_write_items.
@ -657,7 +646,7 @@ esp_err_t rmt_driver_install(rmt_channel_t channel, size_t rx_buf_size, int intr
/**
* @brief Uninstall RMT driver.
*
* @param channel RMT channel (0 - 7)
* @param channel RMT channel
*
* @return
* - ESP_ERR_INVALID_ARG Parameter error
@ -678,12 +667,24 @@ esp_err_t rmt_driver_uninstall(rmt_channel_t channel);
*/
esp_err_t rmt_get_channel_status(rmt_channel_status_result_t *channel_status);
/**
* @brief Get speed of channel's internal counter clock.
*
* @param channel RMT channel
* @param[out] clock_hz counter clock speed, in hz
*
* @return
* - ESP_ERR_INVALID_ARG Parameter is NULL
* - ESP_OK Success
*/
esp_err_t rmt_get_counter_clock(rmt_channel_t channel, uint32_t *clock_hz);
/**
* @brief RMT send waveform from rmt_item array.
*
* This API allows user to send waveform with any length.
*
* @param channel RMT channel (0 - 7)
* @param channel RMT channel
* @param rmt_item head point of RMT items array.
* If ESP_INTR_FLAG_IRAM is used, please do not use the memory allocated from psram when calling rmt_write_items.
* @param item_num RMT data item number.
@ -709,7 +710,7 @@ esp_err_t rmt_write_items(rmt_channel_t channel, const rmt_item32_t* rmt_item, i
/**
* @brief Wait RMT TX finished.
*
* @param channel RMT channel (0 - 7)
* @param channel RMT channel
* @param wait_time Maximum time in ticks to wait for transmission to be complete. If set 0, return immediately with ESP_ERR_TIMEOUT if TX is busy (polling).
*
* @return
@ -725,7 +726,7 @@ esp_err_t rmt_wait_tx_done(rmt_channel_t channel, TickType_t wait_time);
*
* Users can get the RMT RX ringbuffer handle, and process the RX data.
*
* @param channel RMT channel (0 - 7)
* @param channel RMT channel
* @param buf_handle Pointer to buffer handle to accept RX ringbuffer handle.
*
* @return
@ -739,7 +740,7 @@ esp_err_t rmt_get_ringbuf_handle(rmt_channel_t channel, RingbufHandle_t* buf_han
* The callback will convert the raw data that needs to be sent to rmt format.
* If a channel is initialized more than once, tha user callback will be replaced by the later.
*
* @param channel RMT channel (0 - 7).
* @param channel RMT channel .
* @param fn Point to the data conversion function.
*
* @return
@ -752,7 +753,7 @@ esp_err_t rmt_translator_init(rmt_channel_t channel, sample_to_rmt_t fn);
* @brief Translate uint8_t type of data into rmt format and send it out.
* Requires rmt_translator_init to init the translator first.
*
* @param channel RMT channel (0 - 7).
* @param channel RMT channel .
* @param src Pointer to the raw data.
* @param src_size The size of the raw data.
* @param wait_tx_done Set true to wait all data send done.
@ -777,40 +778,6 @@ esp_err_t rmt_write_sample(rmt_channel_t channel, const uint8_t *src, size_t src
*/
rmt_tx_end_callback_t rmt_register_tx_end_callback(rmt_tx_end_fn_t function, void *arg);
/*
* ----------------EXAMPLE OF RMT INTERRUPT ------------------
* @code{c}
*
* rmt_isr_register(rmt_isr, NULL, 0); //hook the ISR handler for RMT interrupt
* @endcode
* @note
* 0. If you have called rmt_driver_install, you don't need to set ISR handler any more.
*
* ----------------EXAMPLE OF INTERRUPT HANDLER ---------------
* @code{c}
* #include "esp_attr.h"
* void IRAM_ATTR rmt_isr_handler(void* arg)
* {
* //read RMT interrupt status.
* uint32_t intr_st = RMT.int_st.val;
*
* //you will find which channels have triggered an interrupt here,
* //then, you can post some event to RTOS queue to process the event.
* //later we will add a queue in the driver code.
*
* //clear RMT interrupt status.
* RMT.int_clr.val = intr_st;
* }
* @endcode
*
*--------------------------END OF EXAMPLE --------------------------
*/
#ifdef __cplusplus
}
#endif
#endif /* _DRIVER_RMT_CTRL_H_ */

569
components/driver/rmt.c
View file

@ -3,7 +3,7 @@
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
@ -11,26 +11,26 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <esp_types.h>
#include <string.h>
#include <stdlib.h>
#include "freertos/FreeRTOS.h"
#include "freertos/semphr.h"
#include "freertos/xtensa_api.h"
#include "freertos/ringbuf.h"
#include <string.h>
#include <sys/lock.h>
#include "esp_intr_alloc.h"
#include "esp_log.h"
#include "esp_err.h"
#include "soc/gpio_periph.h"
#include "driver/gpio.h"
#include "driver/periph_ctrl.h"
#include "driver/rmt.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
#include "freertos/ringbuf.h"
#include "soc/soc_memory_layout.h"
#include <sys/lock.h>
#include "hal/rmt_hal.h"
#include "hal/rmt_ll.h"
#define RMT_SOUCCE_CLK_APB (APB_CLK_FREQ) /*!< RMT source clock is APB_CLK */
#define RMT_SOURCE_CLK_REF (1 * 1000000) /*!< not used yet */
#define RMT_SOURCE_CLK(select) ((select == RMT_BASECLK_REF) ? (RMT_SOURCE_CLK_REF) : (RMT_SOUCCE_CLK_APB)) /*! RMT source clock frequency */
#define RMT_SOURCE_CLK(select) ((select == RMT_BASECLK_REF) ? (RMT_SOURCE_CLK_REF) : (RMT_SOUCCE_CLK_APB))
#define RMT_CHANNEL_ERROR_STR "RMT CHANNEL ERR"
#define RMT_ADDR_ERROR_STR "RMT ADDRESS ERR"
@ -50,22 +50,26 @@
#define RMT_PARAM_ERR_STR "RMT param error"
static const char *RMT_TAG = "rmt";
static uint8_t s_rmt_driver_channels; // Bitmask (bits 0-7) of installed drivers' channels
static rmt_isr_handle_t s_rmt_driver_intr_handle;
#define RMT_CHECK(a, str, ret_val) \
if (!(a)) { \
if (!(a)) \
{ \
ESP_LOGE(RMT_TAG, "%s(%d): %s", __FUNCTION__, __LINE__, str); \
return (ret_val); \
}
static uint8_t s_rmt_driver_channels; // Bitmask of installed drivers' channels
// Spinlock for protecting concurrent register-level access only
static portMUX_TYPE rmt_spinlock = portMUX_INITIALIZER_UNLOCKED;
#define RMT_ENTER_CRITICAL() portENTER_CRITICAL_SAFE(&rmt_spinlock)
#define RMT_EXIT_CRITICAL() portEXIT_CRITICAL_SAFE(&rmt_spinlock)
// Mutex lock for protecting concurrent register/unregister of RMT channels' ISR
static _lock_t rmt_driver_isr_lock;
static rmt_isr_handle_t s_rmt_driver_intr_handle;
typedef struct {
rmt_hal_context_t hal;
size_t tx_offset;
size_t tx_len_rem;
size_t tx_sub_len;
@ -90,24 +94,12 @@ rmt_obj_t* p_rmt_obj[RMT_CHANNEL_MAX] = {0};
// Event called when transmission is ended
static rmt_tx_end_callback_t rmt_tx_end_callback;
static void rmt_set_tx_wrap_en(bool en)
{
portENTER_CRITICAL(&rmt_spinlock);
RMT.apb_conf.mem_tx_wrap_en = en;
portEXIT_CRITICAL(&rmt_spinlock);
}
static void rmt_set_data_mode(rmt_data_mode_t data_mode)
{
portENTER_CRITICAL(&rmt_spinlock);
RMT.apb_conf.fifo_mask = data_mode;
portEXIT_CRITICAL(&rmt_spinlock);
}
esp_err_t rmt_set_clk_div(rmt_channel_t channel, uint8_t div_cnt)
{
RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
RMT.conf_ch[channel].conf0.div_cnt = div_cnt;
RMT_ENTER_CRITICAL();
rmt_ll_set_counter_clock_div(p_rmt_obj[channel]->hal.regs, channel, div_cnt);
RMT_EXIT_CRITICAL();
return ESP_OK;
}
@ -115,14 +107,18 @@ esp_err_t rmt_get_clk_div(rmt_channel_t channel, uint8_t* div_cnt)
{
RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
RMT_CHECK(div_cnt != NULL, RMT_ADDR_ERROR_STR, ESP_ERR_INVALID_ARG);
*div_cnt = RMT.conf_ch[channel].conf0.div_cnt;
RMT_ENTER_CRITICAL();
*div_cnt = (uint8_t)rmt_ll_get_counter_clock_div(p_rmt_obj[channel]->hal.regs, channel);
RMT_EXIT_CRITICAL();
return ESP_OK;
}
esp_err_t rmt_set_rx_idle_thresh(rmt_channel_t channel, uint16_t thresh)
{
RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
RMT.conf_ch[channel].conf0.idle_thres = thresh;
RMT_ENTER_CRITICAL();
rmt_ll_set_rx_idle_thres(p_rmt_obj[channel]->hal.regs, channel, thresh);
RMT_EXIT_CRITICAL();
return ESP_OK;
}
@ -130,7 +126,9 @@ esp_err_t rmt_get_rx_idle_thresh(rmt_channel_t channel, uint16_t *thresh)
{
RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
RMT_CHECK(thresh != NULL, RMT_ADDR_ERROR_STR, ESP_ERR_INVALID_ARG);
*thresh = RMT.conf_ch[channel].conf0.idle_thres;
RMT_ENTER_CRITICAL();
*thresh = (uint16_t)rmt_ll_get_rx_idle_thres(p_rmt_obj[channel]->hal.regs, channel);
RMT_EXIT_CRITICAL();
return ESP_OK;
}
@ -138,7 +136,9 @@ esp_err_t rmt_set_mem_block_num(rmt_channel_t channel, uint8_t rmt_mem_num)
{
RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
RMT_CHECK(rmt_mem_num <= RMT_CHANNEL_MAX - channel, RMT_MEM_CNT_ERROR_STR, ESP_ERR_INVALID_ARG);
RMT.conf_ch[channel].conf0.mem_size = rmt_mem_num;
RMT_ENTER_CRITICAL();
rmt_ll_set_mem_blocks(p_rmt_obj[channel]->hal.regs, channel, rmt_mem_num);
RMT_EXIT_CRITICAL();
return ESP_OK;
}
@ -146,7 +146,9 @@ esp_err_t rmt_get_mem_block_num(rmt_channel_t channel, uint8_t* rmt_mem_num)
{
RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
RMT_CHECK(rmt_mem_num != NULL, RMT_ADDR_ERROR_STR, ESP_ERR_INVALID_ARG);
*rmt_mem_num = RMT.conf_ch[channel].conf0.mem_size;
RMT_ENTER_CRITICAL();
*rmt_mem_num = (uint8_t)rmt_ll_get_mem_blocks(p_rmt_obj[channel]->hal.regs, channel);
RMT_EXIT_CRITICAL();
return ESP_OK;
}
@ -155,86 +157,88 @@ esp_err_t rmt_set_tx_carrier(rmt_channel_t channel, bool carrier_en, uint16_t hi
{
RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
RMT_CHECK(carrier_level < RMT_CARRIER_LEVEL_MAX, RMT_CARRIER_ERROR_STR, ESP_ERR_INVALID_ARG);
RMT.carrier_duty_ch[channel].high = high_level;
RMT.carrier_duty_ch[channel].low = low_level;
RMT.conf_ch[channel].conf0.carrier_out_lv = carrier_level;
RMT.conf_ch[channel].conf0.carrier_en = carrier_en;
RMT_ENTER_CRITICAL();
rmt_ll_set_carrier_high_low_ticks(p_rmt_obj[channel]->hal.regs, channel, high_level, low_level);
rmt_ll_set_carrier_to_level(p_rmt_obj[channel]->hal.regs, channel, carrier_level);
rmt_ll_enable_tx_carrier(p_rmt_obj[channel]->hal.regs, channel, carrier_en);
RMT_EXIT_CRITICAL();
return ESP_OK;
}
esp_err_t rmt_set_mem_pd(rmt_channel_t channel, bool pd_en)
{
RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
RMT.conf_ch[channel].conf0.mem_pd = pd_en;
RMT_ENTER_CRITICAL();
rmt_ll_power_down_mem(p_rmt_obj[channel]->hal.regs, channel, pd_en);
RMT_EXIT_CRITICAL();
return ESP_OK;
}
esp_err_t rmt_get_mem_pd(rmt_channel_t channel, bool *pd_en)
{
RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
*pd_en = (bool) RMT.conf_ch[channel].conf0.mem_pd;
RMT_ENTER_CRITICAL();
*pd_en = rmt_ll_is_mem_power_down(p_rmt_obj[channel]->hal.regs, channel);
RMT_EXIT_CRITICAL();
return ESP_OK;
}
esp_err_t rmt_tx_start(rmt_channel_t channel, bool tx_idx_rst)
{
RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
portENTER_CRITICAL(&rmt_spinlock);
RMT_ENTER_CRITICAL();
if (tx_idx_rst) {
RMT.conf_ch[channel].conf1.mem_rd_rst = 1;
rmt_ll_reset_tx_pointer(p_rmt_obj[channel]->hal.regs, channel);
}
RMT.conf_ch[channel].conf1.mem_owner = RMT_MEM_OWNER_TX;
RMT.conf_ch[channel].conf1.tx_start = 1;
portEXIT_CRITICAL(&rmt_spinlock);
rmt_ll_clear_tx_end_interrupt(p_rmt_obj[channel]->hal.regs, channel);
rmt_ll_enable_tx_end_interrupt(p_rmt_obj[channel]->hal.regs, channel, true);
rmt_ll_start_tx(p_rmt_obj[channel]->hal.regs, channel);
RMT_EXIT_CRITICAL();
return ESP_OK;
}
esp_err_t rmt_tx_stop(rmt_channel_t channel)
{
RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
portENTER_CRITICAL(&rmt_spinlock);
#ifdef CONFIG_IDF_TARGET_ESP32
RMTMEM.chan[channel].data32[0].val = 0;
RMT.conf_ch[channel].conf1.tx_start = 0;
#elif defined CONFIG_IDF_TARGET_ESP32S2BETA
RMT.conf_ch[channel].conf1.tx_stop = 1;
#endif
RMT.conf_ch[channel].conf1.mem_rd_rst = 1;
RMT.conf_ch[channel].conf1.mem_rd_rst = 0;
portEXIT_CRITICAL(&rmt_spinlock);
RMT_ENTER_CRITICAL();
rmt_ll_stop_tx(p_rmt_obj[channel]->hal.regs, channel);
rmt_ll_reset_tx_pointer(p_rmt_obj[channel]->hal.regs, channel);
RMT_EXIT_CRITICAL();
return ESP_OK;
}
esp_err_t rmt_rx_start(rmt_channel_t channel, bool rx_idx_rst)
{
RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
portENTER_CRITICAL(&rmt_spinlock);
RMT_ENTER_CRITICAL();
rmt_ll_enable_rx(p_rmt_obj[channel]->hal.regs, channel, false);
if (rx_idx_rst) {
RMT.conf_ch[channel].conf1.mem_wr_rst = 1;
rmt_ll_reset_rx_pointer(p_rmt_obj[channel]->hal.regs, channel);
}
RMT.conf_ch[channel].conf1.rx_en = 0;
RMT.conf_ch[channel].conf1.mem_owner = RMT_MEM_OWNER_RX;
RMT.conf_ch[channel].conf1.rx_en = 1;
portEXIT_CRITICAL(&rmt_spinlock);
rmt_ll_clear_rx_end_interrupt(p_rmt_obj[channel]->hal.regs, channel);
rmt_ll_enable_rx_end_interrupt(p_rmt_obj[channel]->hal.regs, channel, true);
rmt_ll_enable_rx(p_rmt_obj[channel]->hal.regs, channel, true);
RMT_EXIT_CRITICAL();
return ESP_OK;
}
esp_err_t rmt_rx_stop(rmt_channel_t channel)
{
RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
portENTER_CRITICAL(&rmt_spinlock);
RMT.conf_ch[channel].conf1.rx_en = 0;
portEXIT_CRITICAL(&rmt_spinlock);
RMT_ENTER_CRITICAL();
rmt_ll_enable_rx(p_rmt_obj[channel]->hal.regs, channel, false);
rmt_ll_enable_rx_end_interrupt(p_rmt_obj[channel]->hal.regs, channel, false);
RMT_EXIT_CRITICAL();
return ESP_OK;
}
esp_err_t rmt_memory_rw_rst(rmt_channel_t channel)
{
RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
portENTER_CRITICAL(&rmt_spinlock);
RMT.conf_ch[channel].conf1.mem_rd_rst = 1;
RMT.conf_ch[channel].conf1.mem_wr_rst = 1;
portEXIT_CRITICAL(&rmt_spinlock);
RMT_ENTER_CRITICAL();
rmt_ll_reset_tx_pointer(p_rmt_obj[channel]->hal.regs, channel);
rmt_ll_reset_rx_pointer(p_rmt_obj[channel]->hal.regs, channel);
RMT_EXIT_CRITICAL();
return ESP_OK;
}
@ -242,9 +246,9 @@ esp_err_t rmt_set_memory_owner(rmt_channel_t channel, rmt_mem_owner_t owner)
{
RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
RMT_CHECK(owner < RMT_MEM_OWNER_MAX, RMT_MEM_OWNER_ERROR_STR, ESP_ERR_INVALID_ARG);
portENTER_CRITICAL(&rmt_spinlock);
RMT.conf_ch[channel].conf1.mem_owner = owner;
portEXIT_CRITICAL(&rmt_spinlock);
RMT_ENTER_CRITICAL();
rmt_ll_set_mem_owner(p_rmt_obj[channel]->hal.regs, channel, owner);
RMT_EXIT_CRITICAL();
return ESP_OK;
}
@ -252,33 +256,37 @@ esp_err_t rmt_get_memory_owner(rmt_channel_t channel, rmt_mem_owner_t* owner)
{
RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
RMT_CHECK(owner != NULL, RMT_MEM_OWNER_ERROR_STR, ESP_ERR_INVALID_ARG);
*owner = (rmt_mem_owner_t) RMT.conf_ch[channel].conf1.mem_owner;
RMT_ENTER_CRITICAL();
*owner = (rmt_mem_owner_t)rmt_ll_get_mem_owner(p_rmt_obj[channel]->hal.regs, channel);
RMT_EXIT_CRITICAL();
return ESP_OK;
}
esp_err_t rmt_set_tx_loop_mode(rmt_channel_t channel, bool loop_en)
{
RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
portENTER_CRITICAL(&rmt_spinlock);
RMT.conf_ch[channel].conf1.tx_conti_mode = loop_en;
portEXIT_CRITICAL(&rmt_spinlock);
RMT_ENTER_CRITICAL();
rmt_ll_enable_tx_cyclic(p_rmt_obj[channel]->hal.regs, channel, loop_en);
RMT_EXIT_CRITICAL();
return ESP_OK;
}
esp_err_t rmt_get_tx_loop_mode(rmt_channel_t channel, bool *loop_en)
{
RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
*loop_en = (bool) RMT.conf_ch[channel].conf1.tx_conti_mode;
RMT_ENTER_CRITICAL();
*loop_en = rmt_ll_is_tx_cyclic_enabled(p_rmt_obj[channel]->hal.regs, channel);
RMT_EXIT_CRITICAL();
return ESP_OK;
}
esp_err_t rmt_set_rx_filter(rmt_channel_t channel, bool rx_filter_en, uint8_t thresh)
{
RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
portENTER_CRITICAL(&rmt_spinlock);
RMT.conf_ch[channel].conf1.rx_filter_en = rx_filter_en;
RMT.conf_ch[channel].conf1.rx_filter_thres = thresh;
portEXIT_CRITICAL(&rmt_spinlock);
RMT_ENTER_CRITICAL();
rmt_ll_enable_rx_filter(p_rmt_obj[channel]->hal.regs, channel, rx_filter_en);
rmt_ll_set_rx_filter_thres(p_rmt_obj[channel]->hal.regs, channel, thresh);
RMT_EXIT_CRITICAL();
return ESP_OK;
}
@ -286,16 +294,18 @@ esp_err_t rmt_set_source_clk(rmt_channel_t channel, rmt_source_clk_t base_clk)
{
RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
RMT_CHECK(base_clk < RMT_BASECLK_MAX, RMT_BASECLK_ERROR_STR, ESP_ERR_INVALID_ARG);
portENTER_CRITICAL(&rmt_spinlock);
RMT.conf_ch[channel].conf1.ref_always_on = base_clk;
portEXIT_CRITICAL(&rmt_spinlock);
RMT_ENTER_CRITICAL();
rmt_ll_set_counter_clock_src(p_rmt_obj[channel]->hal.regs, channel, base_clk);
RMT_EXIT_CRITICAL();
return ESP_OK;
}
esp_err_t rmt_get_source_clk(rmt_channel_t channel, rmt_source_clk_t *src_clk)
{
RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
*src_clk = (rmt_source_clk_t) (RMT.conf_ch[channel].conf1.ref_always_on);
RMT_ENTER_CRITICAL();
*src_clk = (rmt_source_clk_t)rmt_ll_get_counter_clock_src(p_rmt_obj[channel]->hal.regs, channel);
RMT_EXIT_CRITICAL();
return ESP_OK;
}
@ -303,81 +313,70 @@ esp_err_t rmt_set_idle_level(rmt_channel_t channel, bool idle_out_en, rmt_idle_l
{
RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
RMT_CHECK(level < RMT_IDLE_LEVEL_MAX, "RMT IDLE LEVEL ERR", ESP_ERR_INVALID_ARG);
portENTER_CRITICAL(&rmt_spinlock);
RMT.conf_ch[channel].conf1.idle_out_en = idle_out_en;
RMT.conf_ch[channel].conf1.idle_out_lv = level;
portEXIT_CRITICAL(&rmt_spinlock);
RMT_ENTER_CRITICAL();
rmt_ll_enable_tx_idle(p_rmt_obj[channel]->hal.regs, channel, idle_out_en);
rmt_ll_set_tx_idle_level(p_rmt_obj[channel]->hal.regs, channel, level);
RMT_EXIT_CRITICAL();
return ESP_OK;
}
esp_err_t rmt_get_idle_level(rmt_channel_t channel, bool *idle_out_en, rmt_idle_level_t *level)
{
RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
*idle_out_en = (bool) (RMT.conf_ch[channel].conf1.idle_out_en);
*level = (rmt_idle_level_t) (RMT.conf_ch[channel].conf1.idle_out_lv);
RMT_ENTER_CRITICAL();
*idle_out_en = rmt_ll_is_tx_idle_enabled(p_rmt_obj[channel]->hal.regs, channel);
*level = rmt_ll_get_tx_idle_level(p_rmt_obj[channel]->hal.regs, channel);
RMT_EXIT_CRITICAL();
return ESP_OK;
}
esp_err_t rmt_get_status(rmt_channel_t channel, uint32_t *status)
{
RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
#ifdef CONFIG_IDF_TARGET_ESP32
*status = RMT.status_ch[channel];
#elif defined CONFIG_IDF_TARGET_ESP32S2BETA
*status = RMT.status_ch[channel].val;
#endif
RMT_ENTER_CRITICAL();
*status = rmt_ll_get_channel_status(p_rmt_obj[channel]->hal.regs, channel);
RMT_EXIT_CRITICAL();
return ESP_OK;
}
rmt_data_mode_t rmt_get_data_mode(void)
{
return (rmt_data_mode_t) (RMT.apb_conf.fifo_mask);
}
void rmt_set_intr_enable_mask(uint32_t mask)
{
portENTER_CRITICAL(&rmt_spinlock);
RMT.int_ena.val |= mask;
portEXIT_CRITICAL(&rmt_spinlock);
RMT_ENTER_CRITICAL();
rmt_ll_set_intr_enable_mask(mask);
RMT_EXIT_CRITICAL();
}
void rmt_clr_intr_enable_mask(uint32_t mask)
{
portENTER_CRITICAL(&rmt_spinlock);
RMT.int_ena.val &= (~mask);
portEXIT_CRITICAL(&rmt_spinlock);
RMT_ENTER_CRITICAL();
rmt_ll_clr_intr_enable_mask(mask);
RMT_EXIT_CRITICAL();
}
esp_err_t rmt_set_rx_intr_en(rmt_channel_t channel, bool en)
{
RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
if(en) {
rmt_set_intr_enable_mask(BIT(channel * 3 + 1));
} else {
rmt_clr_intr_enable_mask(BIT(channel * 3 + 1));
}
RMT_ENTER_CRITICAL();
rmt_ll_enable_rx_end_interrupt(p_rmt_obj[channel]->hal.regs, channel, en);
RMT_EXIT_CRITICAL();
return ESP_OK;
}
esp_err_t rmt_set_err_intr_en(rmt_channel_t channel, bool en)
{
RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
if(en) {
rmt_set_intr_enable_mask(BIT(channel * 3 + 2));
} else {
rmt_clr_intr_enable_mask(BIT(channel * 3 + 2));
}
RMT_ENTER_CRITICAL();
rmt_ll_enable_err_interrupt(p_rmt_obj[channel]->hal.regs, channel, en);
RMT_EXIT_CRITICAL();
return ESP_OK;
}
esp_err_t rmt_set_tx_intr_en(rmt_channel_t channel, bool en)
{
RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
if(en) {
rmt_set_intr_enable_mask(BIT(channel * 3));
} else {
rmt_clr_intr_enable_mask(BIT(channel * 3));
}
RMT_ENTER_CRITICAL();
rmt_ll_enable_tx_end_interrupt(p_rmt_obj[channel]->hal.regs, channel, en);
RMT_EXIT_CRITICAL();
return ESP_OK;
}
@ -386,19 +385,15 @@ esp_err_t rmt_set_tx_thr_intr_en(rmt_channel_t channel, bool en, uint16_t evt_th
RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
if (en) {
RMT_CHECK(evt_thresh <= 256, "RMT EVT THRESH ERR", ESP_ERR_INVALID_ARG);
portENTER_CRITICAL(&rmt_spinlock);
RMT.tx_lim_ch[channel].limit = evt_thresh;
portEXIT_CRITICAL(&rmt_spinlock);
rmt_set_tx_wrap_en(true);
#ifdef CONFIG_IDF_TARGET_ESP32
rmt_set_intr_enable_mask(BIT(channel + 24));
RMT_ENTER_CRITICAL();
rmt_ll_set_tx_limit(p_rmt_obj[channel]->hal.regs, channel, evt_thresh);
rmt_ll_enable_tx_pingpong(p_rmt_obj[channel]->hal.regs, true);
rmt_ll_enable_tx_thres_interrupt(p_rmt_obj[channel]->hal.regs, channel, true);
RMT_EXIT_CRITICAL();
} else {
rmt_clr_intr_enable_mask(BIT(channel + 24));
#elif defined CONFIG_IDF_TARGET_ESP32S2BETA
rmt_set_intr_enable_mask(BIT(channel + 12));
} else {
rmt_clr_intr_enable_mask(BIT(channel + 12));
#endif
RMT_ENTER_CRITICAL();
rmt_ll_enable_tx_thres_interrupt(p_rmt_obj[channel]->hal.regs, channel, false);
RMT_EXIT_CRITICAL();
}
return ESP_OK;
}
@ -407,7 +402,8 @@ esp_err_t rmt_set_pin(rmt_channel_t channel, rmt_mode_t mode, gpio_num_t gpio_nu
{
RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
RMT_CHECK(mode < RMT_MODE_MAX, RMT_MODE_ERROR_STR, ESP_ERR_INVALID_ARG);
RMT_CHECK(((GPIO_IS_VALID_GPIO(gpio_num) && (mode == RMT_MODE_RX)) || (GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) && (mode == RMT_MODE_TX))),
RMT_CHECK(((GPIO_IS_VALID_GPIO(gpio_num) && (mode == RMT_MODE_RX)) ||
(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) && (mode == RMT_MODE_TX))),
RMT_GPIO_ERROR_STR, ESP_ERR_INVALID_ARG);
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO);
@ -421,111 +417,108 @@ esp_err_t rmt_set_pin(rmt_channel_t channel, rmt_mode_t mode, gpio_num_t gpio_nu
return ESP_OK;
}
esp_err_t rmt_config(const rmt_config_t* rmt_param)
static esp_err_t rmt_internal_config(rmt_dev_t *dev, const rmt_config_t *rmt_param)
{
uint8_t mode = rmt_param->rmt_mode;
uint8_t channel = rmt_param->channel;
uint8_t gpio_num = rmt_param->gpio_num;
uint8_t mem_cnt = rmt_param->mem_block_num;
int clk_div = rmt_param->clk_div;
uint8_t clk_div = rmt_param->clk_div;
uint32_t carrier_freq_hz = rmt_param->tx_config.carrier_freq_hz;
bool carrier_en = rmt_param->tx_config.carrier_en;
RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
RMT_CHECK(GPIO_IS_VALID_GPIO(gpio_num), RMT_GPIO_ERROR_STR, ESP_ERR_INVALID_ARG);
RMT_CHECK((mem_cnt + channel <= 8 && mem_cnt > 0), RMT_MEM_CNT_ERROR_STR, ESP_ERR_INVALID_ARG);
RMT_CHECK((clk_div > 0), RMT_CLK_DIV_ERROR_STR, ESP_ERR_INVALID_ARG);
if (mode == RMT_MODE_TX) {
RMT_CHECK((!carrier_en || carrier_freq_hz > 0), "RMT carrier frequency can't be zero", ESP_ERR_INVALID_ARG);
}
static bool rmt_enable = false;
if (rmt_enable == false) {
periph_module_reset(PERIPH_RMT_MODULE);
rmt_enable = true;
}
periph_module_enable(PERIPH_RMT_MODULE);
RMT_ENTER_CRITICAL();
rmt_ll_set_counter_clock_div(dev, channel, clk_div);
rmt_ll_enable_mem_access(dev, true);
rmt_ll_reset_tx_pointer(dev, channel);
rmt_ll_reset_rx_pointer(dev, channel);
rmt_ll_set_counter_clock_src(dev, channel, RMT_BASECLK_APB); // only support APB clock for now
rmt_ll_set_mem_blocks(dev, channel, mem_cnt);
rmt_ll_set_mem_owner(dev, channel, RMT_MEM_OWNER_HW);
RMT_EXIT_CRITICAL();
RMT.conf_ch[channel].conf0.div_cnt = clk_div;
/*Visit data use memory not FIFO*/
rmt_set_data_mode(RMT_DATA_MODE_MEM);
/*Reset tx/rx memory index */
portENTER_CRITICAL(&rmt_spinlock);
RMT.conf_ch[channel].conf1.mem_rd_rst = 1;
RMT.conf_ch[channel].conf1.mem_wr_rst = 1;
portEXIT_CRITICAL(&rmt_spinlock);
uint32_t rmt_source_clk_hz = RMT_SOURCE_CLK(RMT_BASECLK_APB);
if (mode == RMT_MODE_TX) {
uint32_t rmt_source_clk_hz = 0;
uint16_t carrier_duty_percent = rmt_param->tx_config.carrier_duty_percent;
uint8_t carrier_level = rmt_param->tx_config.carrier_level;
uint8_t idle_level = rmt_param->tx_config.idle_level;
portENTER_CRITICAL(&rmt_spinlock);
RMT.conf_ch[channel].conf1.tx_conti_mode = rmt_param->tx_config.loop_en;
/*Memory set block number*/
RMT.conf_ch[channel].conf0.mem_size = mem_cnt;
RMT.conf_ch[channel].conf1.mem_owner = RMT_MEM_OWNER_TX;
/*We use APB clock in this version, which is 80Mhz, later we will release system reference clock*/
RMT.conf_ch[channel].conf1.ref_always_on = RMT_BASECLK_APB;
rmt_source_clk_hz = RMT_SOURCE_CLK(RMT_BASECLK_APB);
RMT_ENTER_CRITICAL();
rmt_ll_enable_tx_cyclic(dev, channel, rmt_param->tx_config.loop_en);
/*Set idle level */
RMT.conf_ch[channel].conf1.idle_out_en = rmt_param->tx_config.idle_output_en;
RMT.conf_ch[channel].conf1.idle_out_lv = idle_level;
rmt_ll_enable_tx_idle(dev, channel, rmt_param->tx_config.idle_output_en);
rmt_ll_set_tx_idle_level(dev, channel, idle_level);
/*Set carrier*/
RMT.conf_ch[channel].conf0.carrier_en = carrier_en;
rmt_ll_enable_tx_carrier(dev, channel, carrier_en);
if (carrier_en) {
uint32_t duty_div, duty_h, duty_l;
duty_div = rmt_source_clk_hz / carrier_freq_hz;
duty_h = duty_div * carrier_duty_percent / 100;
duty_l = duty_div - duty_h;
RMT.conf_ch[channel].conf0.carrier_out_lv = carrier_level;
RMT.carrier_duty_ch[channel].high = duty_h;
RMT.carrier_duty_ch[channel].low = duty_l;
rmt_ll_set_carrier_to_level(dev, channel, carrier_level);
rmt_ll_set_carrier_high_low_ticks(dev, channel, duty_h, duty_l);
} else {
RMT.conf_ch[channel].conf0.carrier_out_lv = 0;
RMT.carrier_duty_ch[channel].high = 0;
RMT.carrier_duty_ch[channel].low = 0;
rmt_ll_set_carrier_to_level(dev, channel, 0);
rmt_ll_set_carrier_high_low_ticks(dev, channel, 0, 0);
}
portEXIT_CRITICAL(&rmt_spinlock);
RMT_EXIT_CRITICAL();
ESP_LOGD(RMT_TAG, "Rmt Tx Channel %u|Gpio %u|Sclk_Hz %u|Div %u|Carrier_Hz %u|Duty %u",
channel, gpio_num, rmt_source_clk_hz, clk_div, carrier_freq_hz, carrier_duty_percent);
}
else if(RMT_MODE_RX == mode) {
} else if (RMT_MODE_RX == mode) {
uint8_t filter_cnt = rmt_param->rx_config.filter_ticks_thresh;
uint16_t threshold = rmt_param->rx_config.idle_threshold;
portENTER_CRITICAL(&rmt_spinlock);
/*clock init*/
RMT.conf_ch[channel].conf1.ref_always_on = RMT_BASECLK_APB;
uint32_t rmt_source_clk_hz = RMT_SOURCE_CLK(RMT_BASECLK_APB);
/*memory set block number and owner*/
RMT.conf_ch[channel].conf0.mem_size = mem_cnt;
RMT.conf_ch[channel].conf1.mem_owner = RMT_MEM_OWNER_RX;
RMT_ENTER_CRITICAL();
/*Set idle threshold*/
RMT.conf_ch[channel].conf0.idle_thres = threshold;
rmt_ll_set_rx_idle_thres(dev, channel, threshold);
/* Set RX filter */
RMT.conf_ch[channel].conf1.rx_filter_thres = filter_cnt;
RMT.conf_ch[channel].conf1.rx_filter_en = rmt_param->rx_config.filter_en;
portEXIT_CRITICAL(&rmt_spinlock);
rmt_ll_set_rx_filter_thres(dev, channel, filter_cnt);
rmt_ll_enable_rx_filter(dev, channel, rmt_param->rx_config.filter_en);
RMT_EXIT_CRITICAL();
ESP_LOGD(RMT_TAG, "Rmt Rx Channel %u|Gpio %u|Sclk_Hz %u|Div %u|Thresold %u|Filter %u",
channel, gpio_num, rmt_source_clk_hz, clk_div, threshold, filter_cnt);
}
rmt_set_pin(channel, mode, gpio_num);
return ESP_OK;
}
static void IRAM_ATTR rmt_fill_memory(rmt_channel_t channel, const rmt_item32_t* item, uint16_t item_num, uint16_t mem_offset)
esp_err_t rmt_config(const rmt_config_t *rmt_param)
{
portENTER_CRITICAL_SAFE(&rmt_spinlock);
RMT.apb_conf.fifo_mask = RMT_DATA_MODE_MEM;
portEXIT_CRITICAL_SAFE(&rmt_spinlock);
int i;
for(i = 0; i < item_num; i++) {
RMTMEM.chan[channel].data32[i + mem_offset].val = item[i].val;
// reset the RMT module at the first time initialize RMT driver
static bool rmt_module_enabled = false;
if (rmt_module_enabled == false) {
periph_module_reset(PERIPH_RMT_MODULE);
rmt_module_enabled = true;
}
periph_module_enable(PERIPH_RMT_MODULE);
RMT_CHECK(rmt_set_pin(rmt_param->channel, rmt_param->rmt_mode, rmt_param->gpio_num) == ESP_OK,
"set gpio for RMT driver failed", ESP_ERR_INVALID_ARG);
RMT_CHECK(rmt_internal_config(&RMT, rmt_param) == ESP_OK,
"initialize RMT driver failed", ESP_ERR_INVALID_ARG);
return ESP_OK;
}
static void IRAM_ATTR rmt_fill_memory(rmt_channel_t channel, const rmt_item32_t *item,
uint16_t item_num, uint16_t mem_offset)
{
RMT_ENTER_CRITICAL();
rmt_ll_set_mem_owner(p_rmt_obj[channel]->hal.regs, channel, RMT_MEM_OWNER_SW);
rmt_ll_write_memory(p_rmt_obj[channel]->hal.mem, channel, item, item_num, mem_offset);
rmt_ll_set_mem_owner(p_rmt_obj[channel]->hal.regs, channel, RMT_MEM_OWNER_HW);
RMT_EXIT_CRITICAL();
}
esp_err_t rmt_fill_tx_items(rmt_channel_t channel, const rmt_item32_t *item, uint16_t item_num, uint16_t mem_offset)
@ -535,7 +528,7 @@ esp_err_t rmt_fill_tx_items(rmt_channel_t channel, const rmt_item32_t* item, uin
RMT_CHECK((item_num > 0), RMT_DRIVER_LENGTH_ERROR_STR, ESP_ERR_INVALID_ARG);
/*Each block has 64 x 32 bits of data*/
uint8_t mem_cnt = RMT.conf_ch[channel].conf0.mem_size;
uint8_t mem_cnt = rmt_ll_get_mem_blocks(p_rmt_obj[channel]->hal.regs, channel);
RMT_CHECK((mem_cnt * RMT_MEM_ITEM_NUM >= item_num), RMT_WR_MEM_OVF_ERROR_STR, ESP_ERR_INVALID_ARG);
rmt_fill_memory(channel, item, item_num, mem_offset);
return ESP_OK;
@ -549,7 +542,6 @@ esp_err_t rmt_isr_register(void (*fn)(void*), void * arg, int intr_alloc_flags,
return esp_intr_alloc(ETS_RMT_INTR_SOURCE, intr_alloc_flags, fn, arg, handle);
}
esp_err_t rmt_isr_deregister(rmt_isr_handle_t handle)
{
return esp_intr_free(handle);
@ -557,9 +549,9 @@ esp_err_t rmt_isr_deregister(rmt_isr_handle_t handle)
static int IRAM_ATTR rmt_get_mem_len(rmt_channel_t channel)
{
int block_num = RMT.conf_ch[channel].conf0.mem_size;
int block_num = rmt_ll_get_mem_blocks(p_rmt_obj[channel]->hal.regs, channel);
int item_block_len = block_num * RMT_MEM_ITEM_NUM;
volatile rmt_item32_t* data = RMTMEM.chan[channel].data32;
volatile rmt_item32_t *data = (rmt_item32_t *)RMTMEM.chan[channel].data32;
int idx;
for (idx = 0; idx < item_block_len; idx++) {
if (data[idx].duration0 == 0) {
@ -573,30 +565,21 @@ static int IRAM_ATTR rmt_get_mem_len(rmt_channel_t channel)
static void IRAM_ATTR rmt_driver_isr_default(void *arg)
{
const uint32_t intr_st = RMT.int_st.val;
uint32_t status = intr_st;
uint8_t channel;
portBASE_TYPE HPTaskAwoken = 0;
uint32_t status = 0;
rmt_item32_t volatile *addr = NULL;
uint8_t channel = 0;
rmt_hal_context_t *hal = (rmt_hal_context_t *)arg;
portBASE_TYPE HPTaskAwoken = pdFALSE;
// Tx end interrupt
status = rmt_ll_get_tx_end_interrupt_status(hal->regs);
while (status) {
int i = __builtin_ffs(status) - 1;
status &= ~(1 << i);
#ifdef CONFIG_IDF_TARGET_ESP32
if(i < 24) {
#elif defined CONFIG_IDF_TARGET_ESP32S2BETA
if(i >= 15) {
} else if(i < 12) {
#endif
channel = i / 3;
channel = __builtin_ffs(status) - 1;
status &= ~(1 << channel);
rmt_obj_t *p_rmt = p_rmt_obj[channel];
if(NULL == p_rmt) {
continue;
}
switch(i % 3) {
//TX END
case 0:
if (p_rmt) {
xSemaphoreGiveFromISR(p_rmt->tx_sem, &HPTaskAwoken);
RMT.conf_ch[channel].conf1.mem_rd_rst = 1;
RMT.conf_ch[channel].conf1.mem_rd_rst = 0;
rmt_ll_reset_tx_pointer(p_rmt_obj[channel]->hal.regs, channel);
p_rmt->tx_data = NULL;
p_rmt->tx_len_rem = 0;
p_rmt->tx_offset = 0;
@ -606,48 +589,17 @@ static void IRAM_ATTR rmt_driver_isr_default(void* arg)
if (rmt_tx_end_callback.function != NULL) {
rmt_tx_end_callback.function(channel, rmt_tx_end_callback.arg);
}
break;
//RX_END
case 1:
RMT.conf_ch[channel].conf1.rx_en = 0;
int item_len = rmt_get_mem_len(channel);
//change memory owner to protect data.
RMT.conf_ch[channel].conf1.mem_owner = RMT_MEM_OWNER_TX;
if(p_rmt->rx_buf) {
BaseType_t res = xRingbufferSendFromISR(p_rmt->rx_buf, (void*) RMTMEM.chan[channel].data32, item_len * 4, &HPTaskAwoken);
if(res == pdFALSE) {
ESP_EARLY_LOGE(RMT_TAG, "RMT RX BUFFER FULL");
} else {
}
rmt_ll_clear_tx_end_interrupt(hal->regs, channel);
}
}
} else {
ESP_EARLY_LOGE(RMT_TAG, "RMT RX BUFFER ERROR\n");
}
RMT.conf_ch[channel].conf1.mem_wr_rst = 1;
RMT.conf_ch[channel].conf1.mem_owner = RMT_MEM_OWNER_RX;
RMT.conf_ch[channel].conf1.rx_en = 1;
break;
//ERR
case 2:
ESP_EARLY_LOGE(RMT_TAG, "RMT[%d] ERR", channel);
ESP_EARLY_LOGE(RMT_TAG, "status: 0x%08x", RMT.status_ch[channel]);
RMT.int_ena.val &= (~(BIT(i)));
break;
default:
break;
}
#ifdef CONFIG_IDF_TARGET_ESP32
} else {
channel = i - 24;
#elif defined CONFIG_IDF_TARGET_ESP32S2BETA
} else if(i >= 12 && i < 16) {
channel = i - 12;
#endif
// Tx thres interrupt
status = rmt_ll_get_tx_thres_interrupt_status(hal->regs);
while (status) {
channel = __builtin_ffs(status) - 1;
status &= ~(1 << channel);
rmt_obj_t *p_rmt = p_rmt_obj[channel];
if(p_rmt->tx_data == NULL) {
//skip
} else {
if (p_rmt) {
if (p_rmt->translator) {
if (p_rmt->sample_size_remain > 0) {
size_t translated_size = 0;
@ -656,8 +608,7 @@ static void IRAM_ATTR rmt_driver_isr_default(void* arg)
p_rmt->sample_size_remain,
p_rmt->tx_sub_len,
&translated_size,
&p_rmt->tx_len_rem
);
&p_rmt->tx_len_rem);
p_rmt->sample_size_remain -= translated_size;
p_rmt->sample_cur += translated_size;
p_rmt->tx_data = p_rmt->tx_buf;
@ -673,10 +624,12 @@ static void IRAM_ATTR rmt_driver_isr_default(void* arg)
p_rmt->tx_data += p_rmt->tx_sub_len;
p_rmt->tx_len_rem -= p_rmt->tx_sub_len;
} else if (len_rem == 0) {
RMTMEM.chan[channel].data32[p_rmt->tx_offset].val = 0;
rmt_item32_t stop_data = {0};
rmt_ll_write_memory(p_rmt_obj[channel]->hal.mem, channel, &stop_data, 1, p_rmt->tx_offset);
} else {
rmt_fill_memory(channel, pdata, len_rem, p_rmt->tx_offset);
RMTMEM.chan[channel].data32[p_rmt->tx_offset + len_rem].val = 0;
rmt_item32_t stop_data = {0};
rmt_ll_write_memory(p_rmt_obj[channel]->hal.mem, channel, &stop_data, 1, p_rmt->tx_offset + len_rem);
p_rmt->tx_data += len_rem;
p_rmt->tx_len_rem -= len_rem;
}
@ -686,9 +639,48 @@ static void IRAM_ATTR rmt_driver_isr_default(void* arg)
p_rmt->tx_offset = 0;
}
}
rmt_ll_clear_tx_thres_interrupt(hal->regs, channel);
}
// Rx end interrupt
status = rmt_ll_get_rx_end_interrupt_status(hal->regs);
while (status) {
channel = __builtin_ffs(status) - 1;
status &= ~(1 << channel);
rmt_obj_t *p_rmt = p_rmt_obj[channel];
if (p_rmt) {
rmt_ll_enable_rx(p_rmt_obj[channel]->hal.regs, channel, false);
int item_len = rmt_get_mem_len(channel);
rmt_ll_set_mem_owner(p_rmt_obj[channel]->hal.regs, channel, RMT_MEM_OWNER_SW);
if (p_rmt->rx_buf) {
addr = RMTMEM.chan[channel].data32;
BaseType_t res = xRingbufferSendFromISR(p_rmt->rx_buf, (void *)addr, item_len * 4, &HPTaskAwoken);
if (res == pdFALSE) {
ESP_EARLY_LOGE(RMT_TAG, "RMT RX BUFFER FULL");
}
RMT.int_clr.val = intr_st;
} else {
ESP_EARLY_LOGE(RMT_TAG, "RMT RX BUFFER ERROR");
}
rmt_ll_reset_rx_pointer(p_rmt_obj[channel]->hal.regs, channel);
rmt_ll_set_mem_owner(p_rmt_obj[channel]->hal.regs, channel, RMT_MEM_OWNER_HW);
rmt_ll_enable_rx(p_rmt_obj[channel]->hal.regs, channel, true);
}
rmt_ll_clear_rx_end_interrupt(hal->regs, channel);
}
// Err interrupt
status = rmt_ll_get_err_interrupt_status(hal->regs);
while (status) {
channel = __builtin_ffs(status) - 1;
status &= ~(1 << channel);
rmt_obj_t *p_rmt = p_rmt_obj[channel];
if (p_rmt) {
ESP_EARLY_LOGD(RMT_TAG, "RMT[%d] ERR", channel);
ESP_EARLY_LOGD(RMT_TAG, "status: 0x%08x", rmt_ll_get_channel_status(p_rmt_obj[channel]->hal.regs, channel));
}
rmt_ll_clear_err_interrupt(hal->regs, channel);
}
if (HPTaskAwoken == pdTRUE) {
portYIELD_FROM_ISR();
}
@ -714,7 +706,8 @@ esp_err_t rmt_driver_uninstall(rmt_channel_t channel)
_lock_acquire_recursive(&rmt_driver_isr_lock);
s_rmt_driver_channels &= ~BIT(channel);
if (s_rmt_driver_channels == 0) { // all channels have driver disabled
if (s_rmt_driver_channels == 0) {
// all channels have driver disabled
err = rmt_isr_deregister(s_rmt_driver_intr_handle);
s_rmt_driver_intr_handle = NULL;
}
@ -749,7 +742,8 @@ esp_err_t rmt_driver_uninstall(rmt_channel_t channel)
esp_err_t rmt_driver_install(rmt_channel_t channel, size_t rx_buf_size, int intr_alloc_flags)
{
RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
RMT_CHECK((s_rmt_driver_channels & BIT(channel)) == 0, "RMT driver already installed for channel", ESP_ERR_INVALID_STATE);
RMT_CHECK((s_rmt_driver_channels & BIT(channel)) == 0,
"RMT driver already installed for channel", ESP_ERR_INVALID_STATE);
esp_err_t err = ESP_OK;
@ -774,6 +768,9 @@ esp_err_t rmt_driver_install(rmt_channel_t channel, size_t rx_buf_size, int intr
}
memset(p_rmt_obj[channel], 0, sizeof(rmt_obj_t));
rmt_hal_init(&p_rmt_obj[channel]->hal);
rmt_hal_channel_reset(&p_rmt_obj[channel]->hal, channel);
p_rmt_obj[channel]->tx_len_rem = 0;
p_rmt_obj[channel]->tx_data = NULL;
p_rmt_obj[channel]->channel = channel;
@ -797,20 +794,17 @@ esp_err_t rmt_driver_install(rmt_channel_t channel, size_t rx_buf_size, int intr
}
if (p_rmt_obj[channel]->rx_buf == NULL && rx_buf_size > 0) {
p_rmt_obj[channel]->rx_buf = xRingbufferCreate(rx_buf_size, RINGBUF_TYPE_NOSPLIT);
rmt_set_rx_intr_en(channel, 1);
rmt_set_err_intr_en(channel, 1);
}
rmt_set_err_intr_en(channel, 1);
_lock_acquire_recursive(&rmt_driver_isr_lock);
if(s_rmt_driver_channels == 0) { // first RMT channel using driver
err = rmt_isr_register(rmt_driver_isr_default, NULL, intr_alloc_flags, &s_rmt_driver_intr_handle);
if (s_rmt_driver_channels == 0) {
// first RMT channel using driver
err = rmt_isr_register(rmt_driver_isr_default, &p_rmt_obj[channel]->hal, intr_alloc_flags, &s_rmt_driver_intr_handle);
}
if (err == ESP_OK) {
s_rmt_driver_channels |= BIT(channel);
rmt_set_tx_intr_en(channel, 1);
}
_lock_release_recursive(&rmt_driver_isr_lock);
return err;
@ -831,7 +825,7 @@ esp_err_t rmt_write_items(rmt_channel_t channel, const rmt_item32_t* rmt_item, i
}
#endif
rmt_obj_t *p_rmt = p_rmt_obj[channel];
int block_num = RMT.conf_ch[channel].conf0.mem_size;
int block_num = rmt_ll_get_mem_blocks(p_rmt_obj[channel]->hal.regs, channel);
int item_block_len = block_num * RMT_MEM_ITEM_NUM;
int item_sub_len = block_num * RMT_MEM_ITEM_NUM / 2;
int len_rem = item_num;
@ -848,7 +842,8 @@ esp_err_t rmt_write_items(rmt_channel_t channel, const rmt_item32_t* rmt_item, i
p_rmt->tx_sub_len = item_sub_len;
} else {
rmt_fill_memory(channel, rmt_item, len_rem, 0);
RMTMEM.chan[channel].data32[len_rem].val = 0;
rmt_item32_t stop_data = {0};
rmt_ll_write_memory(p_rmt_obj[channel]->hal.mem, channel, &stop_data, 1, len_rem);
p_rmt->tx_len_rem = 0;
}
rmt_tx_start(channel, true);
@ -868,9 +863,9 @@ esp_err_t rmt_wait_tx_done(rmt_channel_t channel, TickType_t wait_time)
p_rmt_obj[channel]->wait_done = false;
xSemaphoreGive(p_rmt_obj[channel]->tx_sem);
return ESP_OK;
}
else {
if (wait_time != 0) { // Don't emit error message if just polling.
} else {
if (wait_time != 0) {
// Don't emit error message if just polling.
ESP_LOGE(RMT_TAG, "Timeout on wait_tx_done");
}
return ESP_ERR_TIMEOUT;
@ -899,7 +894,8 @@ esp_err_t rmt_translator_init(rmt_channel_t channel, sample_to_rmt_t fn)
RMT_CHECK(fn != NULL, RMT_TRANSLATOR_NULL_STR, ESP_ERR_INVALID_ARG);
RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
RMT_CHECK(p_rmt_obj[channel] != NULL, RMT_DRIVER_ERROR_STR, ESP_FAIL);
const uint32_t block_size = RMT.conf_ch[channel].conf0.mem_size * RMT_MEM_ITEM_NUM * sizeof(rmt_item32_t);
const uint32_t block_size = rmt_ll_get_mem_blocks(p_rmt_obj[channel]->hal.regs, channel) *
RMT_MEM_ITEM_NUM * sizeof(rmt_item32_t);
if (p_rmt_obj[channel]->tx_buf == NULL) {
#if !CONFIG_SPIRAM_USE_MALLOC
p_rmt_obj[channel]->tx_buf = (rmt_item32_t *)malloc(block_size);
@ -938,7 +934,7 @@ esp_err_t rmt_write_sample(rmt_channel_t channel, const uint8_t *src, size_t src
size_t item_num = 0;
size_t translated_size = 0;
rmt_obj_t *p_rmt = p_rmt_obj[channel];
const uint32_t item_block_len = RMT.conf_ch[channel].conf0.mem_size * RMT_MEM_ITEM_NUM;
const uint32_t item_block_len = rmt_ll_get_mem_blocks(p_rmt_obj[channel]->hal.regs, channel) * RMT_MEM_ITEM_NUM;
const uint32_t item_sub_len = item_block_len / 2;
xSemaphoreTake(p_rmt->tx_sem, portMAX_DELAY);
p_rmt->sample_to_rmt((void *)src, p_rmt->tx_buf, src_size, item_block_len, &translated_size, &item_num);
@ -952,7 +948,8 @@ esp_err_t rmt_write_sample(rmt_channel_t channel, const uint8_t *src, size_t src
p_rmt->tx_sub_len = item_sub_len;
p_rmt->translator = true;
} else {
RMTMEM.chan[channel].data32[item_num].val = 0;
rmt_item32_t stop_data = {0};
rmt_ll_write_memory(p_rmt_obj[channel]->hal.mem, channel, &stop_data, 1, item_num);
p_rmt->tx_len_rem = 0;
p_rmt->sample_cur = NULL;
p_rmt->translator = false;
@ -984,3 +981,13 @@ esp_err_t rmt_get_channel_status(rmt_channel_status_result_t *channel_status)
}
return ESP_OK;
}
esp_err_t rmt_get_counter_clock(rmt_channel_t channel, uint32_t *clock_hz)
{
RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
RMT_CHECK(clock_hz, "parameter clock_hz can't be null", ESP_ERR_INVALID_ARG);
RMT_ENTER_CRITICAL();
*clock_hz = rmt_hal_get_counter_clock(&p_rmt_obj[channel]->hal, channel, RMT_SOURCE_CLK(RMT_BASECLK_APB));
RMT_EXIT_CRITICAL();
return ESP_OK;
}

274
components/driver/test/esp32/test_rmt.c
View file

@ -1,22 +1,24 @@
/**
* please connect GPIO18 to GPIO19
* @brief To run this unit test, MAKE SURE GPIO18(TX) is connected to GPIO19(RX)!
*
*/
#include "stdio.h"
#include <stdio.h>
#include <string.h>
#include "driver/rmt.h"
#include "sdkconfig.h"
#include "unity.h"
#include "test_utils.h"
#include "driver/rmt.h"
#include "driver/periph_ctrl.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/queue.h"
#include "freertos/semphr.h"
#include "esp_err.h"
#include "esp_log.h"
#include "driver/periph_ctrl.h"
#include "soc/soc.h"
#include "soc/rmt_periph.h"
static const char* TAG = "RMT";
static const char *TAG = "RMT.test";
#define RMT_RX_ACTIVE_LEVEL 1 /*!< Data bit is active high for self test mode */
#define RMT_TX_CARRIER_EN 0 /*!< Disable carrier for self test mode */
@ -26,8 +28,9 @@ static const char* TAG = "RMT";
#define RMT_RX_CHANNEL 0 /*!< RMT channel for receiver */
#define RMT_RX_GPIO_NUM 19 /*!< GPIO number for receiver */
#define RMT_CLK_DIV 100 /*!< RMT counter clock divider */
#define RMT_TICK_10_US (80000000/RMT_CLK_DIV/100000) /*!< RMT counter value for 10 us.(Source clock is APB clock) */
#define RMT_TICK_10_US (APB_CLK_FREQ / RMT_CLK_DIV / 100000) /*!< RMT counter value for 10 us */
// NEC protocol related parameters
#define HEADER_HIGH_US 9000 /*!< NEC protocol header: positive 9ms */
#define HEADER_LOW_US 4500 /*!< NEC protocol header: negative 4.5ms*/
#define BIT_ONE_HIGH_US 560 /*!< NEC protocol data bit 1: positive 0.56ms */
@ -35,11 +38,11 @@ static const char* TAG = "RMT";
#define BIT_ZERO_HIGH_US 560 /*!< NEC protocol data bit 0: positive 0.56ms */
#define BIT_ZERO_LOW_US (1120 - BIT_ZERO_HIGH_US) /*!< NEC protocol data bit 0: negative 0.56ms */
#define BIT_END 560 /*!< NEC protocol end: positive 0.56ms */
#define BIT_MARGIN 20 /*!< NEC parse margin time */
#define BIT_MARGIN 160 /*!< NEC parse margin time */
#define ITEM_DURATION(d) ((d & 0x7fff) * 10 / RMT_TICK_10_US) /*!< Parse duration time from memory register value */
#define DATA_ITEM_NUM 34 /*!< NEC code item number: header + 32bit data + end */
#define RMT_TX_DATA_NUM 100 /*!< NEC tx test data number */
#define RMT_TX_DATA_NUM 50 /*!< NEC tx test data number */
#define RMT_ITEM32_TIMEOUT_US 9500 /*!< RMT receiver timeout value(us) */
/**
@ -90,8 +93,8 @@ static void fill_item_end(rmt_item32_t* item)
*/
static inline bool check_in_range(int duration_ticks, int target_us, int margin_us)
{
if(( ITEM_DURATION(duration_ticks) < (target_us + margin_us))
&& ( ITEM_DURATION(duration_ticks) > (target_us - margin_us))) {
if ((ITEM_DURATION(duration_ticks) < (target_us + margin_us)) &&
(ITEM_DURATION(duration_ticks) > (target_us - margin_us))) {
return true;
} else {
return false;
@ -103,9 +106,9 @@ static inline bool check_in_range(int duration_ticks, int target_us, int margin_
*/
static bool header_if(rmt_item32_t *item)
{
if((item->level0 == RMT_RX_ACTIVE_LEVEL && item->level1 != RMT_RX_ACTIVE_LEVEL)
&& check_in_range(item->duration0, HEADER_HIGH_US, BIT_MARGIN)
&& check_in_range(item->duration1, HEADER_LOW_US, BIT_MARGIN)) {
if ((item->level0 == RMT_RX_ACTIVE_LEVEL && item->level1 != RMT_RX_ACTIVE_LEVEL) &&
check_in_range(item->duration0, HEADER_HIGH_US, BIT_MARGIN) &&
check_in_range(item->duration1, HEADER_LOW_US, BIT_MARGIN)) {
return true;
}
return false;
@ -116,9 +119,9 @@ static bool header_if(rmt_item32_t* item)
*/
static bool bit_one_if(rmt_item32_t *item)
{
if((item->level0 == RMT_RX_ACTIVE_LEVEL && item->level1 != RMT_RX_ACTIVE_LEVEL)
&& check_in_range(item->duration0, BIT_ONE_HIGH_US, BIT_MARGIN)
&& check_in_range(item->duration1, BIT_ONE_LOW_US, BIT_MARGIN)) {
if ((item->level0 == RMT_RX_ACTIVE_LEVEL && item->level1 != RMT_RX_ACTIVE_LEVEL) &&
check_in_range(item->duration0, BIT_ONE_HIGH_US, BIT_MARGIN) &&
check_in_range(item->duration1, BIT_ONE_LOW_US, BIT_MARGIN)) {
return true;
}
return false;
@ -129,15 +132,14 @@ static bool bit_one_if(rmt_item32_t* item)
*/
static bool bit_zero_if(rmt_item32_t *item)
{
if((item->level0 == RMT_RX_ACTIVE_LEVEL && item->level1 != RMT_RX_ACTIVE_LEVEL)
&& check_in_range(item->duration0, BIT_ZERO_HIGH_US, BIT_MARGIN)
&& check_in_range(item->duration1, BIT_ZERO_LOW_US, BIT_MARGIN)) {
if ((item->level0 == RMT_RX_ACTIVE_LEVEL && item->level1 != RMT_RX_ACTIVE_LEVEL) &&
check_in_range(item->duration0, BIT_ZERO_HIGH_US, BIT_MARGIN) &&
check_in_range(item->duration1, BIT_ZERO_LOW_US, BIT_MARGIN)) {
return true;
}
return false;
}
/**
* @brief Parse NEC 32 bit waveform to address and command.
*/
@ -220,7 +222,6 @@ static void set_tx_data(int tx_channel, uint16_t cmd, uint16_t addr, int item_nu
{
while (1) {
int i = build_items(tx_channel, item + offset, item_num - offset, ((~addr) << 8) | addr, cmd);
printf("cmd :%d\n", cmd);
if (i < 0) {
break;
}
@ -244,7 +245,7 @@ static int get_rx_data(RingbufHandle_t rb)
int res = parse_items(rx_item + rx_offset, rx_size / 4 - rx_offset, &rmt_addr, &rmt_cmd);
if (res > 0) {
rx_offset += res + 1;
ESP_LOGI(TAG, "RMT RCV --- addr: 0x%04x cmd: 0x%04x", rmt_addr, rmt_cmd);
ESP_LOGI(TAG, "receive cmd %d from addr %d", rmt_cmd, rmt_addr & 0xFF);
TEST_ASSERT(rmt_cmd == tmp);
tmp++;
} else {
@ -376,12 +377,12 @@ TEST_CASE("RMT init config", "[rmt][test_env=UT_T1_RMT]")
TEST_CASE("RMT init set function", "[rmt][test_env=UT_T1_RMT]")
{
rmt_channel_t channel = 7;
TEST_ESP_OK(rmt_driver_install(channel, 0, 0));
TEST_ESP_OK(rmt_set_pin(channel, RMT_MODE_RX, RMT_RX_GPIO_NUM));
TEST_ESP_OK(rmt_set_clk_div(channel, RMT_CLK_DIV * 2));
TEST_ESP_OK(rmt_set_mem_block_num(channel, 1));
TEST_ESP_OK(rmt_set_rx_filter(channel, 1, 100));
TEST_ESP_OK(rmt_set_rx_idle_thresh(channel, RMT_ITEM32_TIMEOUT_US / 10 * (RMT_TICK_10_US) * 2));
TEST_ESP_OK(rmt_driver_install(channel, 0, 0));
TEST_ESP_OK(rmt_driver_uninstall(channel));
}
@ -405,8 +406,8 @@ TEST_CASE("RMT clock devider, clock source set(logic analyzer)", "[rmt][ignore]"
rmt_tx.rmt_mode = RMT_MODE_TX;
TEST_ESP_OK(rmt_config(&rmt_tx));
TEST_ESP_OK(rmt_get_clk_div(RMT_TX_CHANNEL, &div_cnt));
TEST_ESP_OK(rmt_driver_install(rmt_tx.channel, 0, 0));
TEST_ESP_OK(rmt_get_clk_div(RMT_TX_CHANNEL, &div_cnt));
TEST_ASSERT_EQUAL_UINT8(div_cnt, RMT_CLK_DIV);
vTaskDelay(1000 / portTICK_PERIOD_MS);
@ -435,14 +436,11 @@ TEST_CASE("RMT rx set and get properties", "[rmt][test_env=UT_T1_RMT]")
TEST_ESP_OK(rmt_get_clk_div(channel, &div_cnt));
TEST_ESP_OK(rmt_get_mem_block_num(channel, &memNum));
TEST_ESP_OK(rmt_get_rx_idle_thresh(channel, &idleThreshold));
TEST_ESP_OK(rmt_get_memory_owner(channel, &owner));
TEST_ASSERT_EQUAL_UINT8(div_cnt, RMT_CLK_DIV);
TEST_ASSERT_EQUAL_UINT8(memNum, 1);
TEST_ASSERT_EQUAL_UINT16(idleThreshold, RMT_ITEM32_TIMEOUT_US / 10 * (RMT_TICK_10_US));
TEST_ASSERT_EQUAL_INT(owner, RMT_MEM_OWNER_RX);
//eRR
TEST_ESP_OK(rmt_set_pin(channel, RMT_MODE_RX, 22));
TEST_ESP_OK(rmt_set_clk_div(channel, RMT_CLK_DIV * 2));
TEST_ESP_OK(rmt_set_mem_block_num(channel, 2));
@ -475,12 +473,10 @@ TEST_CASE("RMT tx set and get properties", "[rmt][test_env=UT_T1_RMT]")
TEST_ESP_OK(rmt_get_clk_div(channel, &div_cnt));
TEST_ESP_OK(rmt_get_mem_block_num(channel, &memNum));
TEST_ESP_OK(rmt_get_tx_loop_mode(channel, &loop_en));
TEST_ESP_OK(rmt_get_memory_owner(channel, &owner));
TEST_ASSERT_EQUAL_INT8(loop_en, 0);
TEST_ASSERT_EQUAL_UINT8(div_cnt, RMT_CLK_DIV);
TEST_ASSERT_EQUAL_UINT8(memNum, 1);
TEST_ASSERT_EQUAL_INT(owner, RMT_MEM_OWNER_TX);
//reset by "set"
TEST_ESP_OK(rmt_set_pin(channel, RMT_MODE_TX, RMT_TX_GPIO_NUM));
@ -501,13 +497,13 @@ TEST_CASE("RMT tx set and get properties", "[rmt][test_env=UT_T1_RMT]")
TEST_ASSERT_EQUAL_UINT8(memNum, 2);
TEST_ASSERT_EQUAL_INT(owner, RMT_MEM_OWNER_TX);
rmt_item32_t items[1];
items[0].duration0 = 300 / 10 * RMT_TICK_10_US; //300us
items[0].level0 = 1;
items[0].duration1 = 0;
items[0].level1 = 0;
rmt_item32_t item;
item.duration0 = 300 / 10 * RMT_TICK_10_US; //300us
item.level0 = 1;
item.duration1 = 0;
item.level1 = 0;
for (int i = 0; i < 100; i++) {
TEST_ESP_OK(rmt_write_items(RMT_TX_CHANNEL, items,
TEST_ESP_OK(rmt_write_items(RMT_TX_CHANNEL, &item,
1, /* Number of items */
1 /* wait till done */));
vTaskDelay(10 / portTICK_PERIOD_MS); //every 10ms to write the item
@ -515,6 +511,44 @@ TEST_CASE("RMT tx set and get properties", "[rmt][test_env=UT_T1_RMT]")
TEST_ESP_OK(rmt_driver_uninstall(channel));
}
TEST_CASE("RMT use multi channel", "[rmt][test_env=UT_T1_RMT]")
{
rmt_tx_config_t tx_cfg = {
.loop_en = true, // set it as true
.carrier_duty_percent = 50,
.carrier_freq_hz = 38000,
.carrier_level = 1,
.carrier_en = RMT_TX_CARRIER_EN,
.idle_level = 0,
.idle_output_en = true,
};
rmt_config_t rmt_tx1 = {
.channel = RMT_TX_CHANNEL,
.gpio_num = RMT_TX_GPIO_NUM,
.mem_block_num = 4,
.clk_div = RMT_CLK_DIV,
.tx_config = tx_cfg,
.rmt_mode = 0,
};
rmt_config(&rmt_tx1);
rmt_driver_install(rmt_tx1.channel, 0, 0);
rmt_config_t rmt_tx2 = rmt_tx1;
rmt_tx2.channel = 2;
rmt_config(&rmt_tx2);
rmt_driver_install(rmt_tx2.channel, 0, 0);
rmt_config_t rmt_tx3 = rmt_tx1;
rmt_tx3.channel = 7;
rmt_tx3.mem_block_num = 1;
rmt_config(&rmt_tx3);
rmt_driver_install(rmt_tx3.channel, 0, 0);
TEST_ESP_OK(rmt_driver_uninstall(RMT_TX_CHANNEL));
TEST_ESP_OK(rmt_driver_uninstall(2));
TEST_ESP_OK(rmt_driver_uninstall(7));
}
TEST_CASE("RMT memory test", "[rmt][test_env=UT_T1_RMT]")
{
rmt_config_t rmt_rx;
@ -580,131 +614,92 @@ TEST_CASE("RMT send waveform(logic analyzer)", "[rmt][test_env=UT_T1_RMT][ignore
TEST_CASE("RMT basic TX and RX", "[rmt][test_env=UT_T1_RMT]")
{
tx_init();
int tx_channel = RMT_TX_CHANNEL;
uint16_t cmd = 0x0;
uint16_t addr = 0x11;
int tx_num = RMT_TX_DATA_NUM;
ESP_LOGI(TAG, "RMT TX DATA");
size_t size = (sizeof(rmt_item32_t) * DATA_ITEM_NUM * tx_num);
rmt_item32_t* item = (rmt_item32_t*) malloc(size);
int item_num = DATA_ITEM_NUM * tx_num;
memset((void*) item, 0, size);
int offset = 0;
int rx_channel = RMT_RX_CHANNEL;
rx_init();
RingbufHandle_t rb = NULL;
rmt_get_ringbuf_handle(rx_channel, &rb);
rmt_rx_start(rx_channel, 1);
// send data
set_tx_data(tx_channel, cmd, addr, item_num, item, offset);
rmt_write_items(tx_channel, item, item_num, 1);
free(item);
// receive data
uint16_t tmp = get_rx_data(rb);
TEST_ASSERT(tmp == 100);
TEST_ESP_OK(rmt_driver_uninstall(RMT_TX_CHANNEL));
TEST_ESP_OK(rmt_driver_uninstall(RMT_RX_CHANNEL));
}
rmt_get_ringbuf_handle(RMT_RX_CHANNEL, &rb);
rmt_rx_start(RMT_RX_CHANNEL, 1);
ESP_LOGI(TAG, "Star receiving RMT data...");
TEST_CASE("RMT TX write item not wait", "[rmt][test_env=UT_T1_RMT]")
{
tx_init();
int tx_channel = RMT_TX_CHANNEL;
uint16_t cmd = 0x0;
uint16_t addr = 0x11;
int tx_num = RMT_TX_DATA_NUM;
ESP_LOGI(TAG, "RMT TX DATA");
size_t size = (sizeof(rmt_item32_t) * DATA_ITEM_NUM * tx_num);
rmt_item32_t* item = (rmt_item32_t*) malloc(size);
int item_num = DATA_ITEM_NUM * tx_num;
memset((void*) item, 0, size);
int offset = 0;
int num_items = DATA_ITEM_NUM * RMT_TX_DATA_NUM;
rmt_item32_t *items = calloc(num_items + 1, sizeof(rmt_item32_t));
int rx_channel = RMT_RX_CHANNEL;
rx_init();
RingbufHandle_t rb = NULL;
rmt_get_ringbuf_handle(rx_channel, &rb);
rmt_rx_start(rx_channel, 1);
vTaskDelay(pdMS_TO_TICKS(2000));
ESP_LOGI(TAG, "Sending RMT data...");
// send data
set_tx_data(tx_channel, cmd, addr, item_num, item, offset);
rmt_write_items(tx_channel, item, item_num, 0);
free(item);
set_tx_data(RMT_TX_CHANNEL, cmd, addr, num_items, items, 0);
// wait until tx done
rmt_write_items(RMT_TX_CHANNEL, items, num_items, 1);
free(items);
// receive data
uint16_t tmp = get_rx_data(rb);
TEST_ASSERT(tmp < 100);
TEST_ASSERT(tmp == RMT_TX_DATA_NUM);
TEST_ESP_OK(rmt_driver_uninstall(RMT_TX_CHANNEL));
TEST_ESP_OK(rmt_driver_uninstall(RMT_RX_CHANNEL));
}
TEST_CASE("RMT TX write item wait some ticks", "[rmt][test_env=UT_T1_RMT]")
{
tx_init();
int tx_channel = RMT_TX_CHANNEL;
uint16_t cmd = 0x0;
uint16_t addr = 0x11;
int tx_num = RMT_TX_DATA_NUM;
ESP_LOGI(TAG, "RMT TX DATA");
size_t size = (sizeof(rmt_item32_t) * DATA_ITEM_NUM * tx_num);
rmt_item32_t* item = (rmt_item32_t*) malloc(size);
int item_num = DATA_ITEM_NUM * tx_num;
memset((void*) item, 0, size);
int offset = 0;
int rx_channel = RMT_RX_CHANNEL;
rx_init();
RingbufHandle_t rb = NULL;
rmt_get_ringbuf_handle(rx_channel, &rb);
rmt_rx_start(rx_channel, 1);
rmt_get_ringbuf_handle(RMT_RX_CHANNEL, &rb);
rmt_rx_start(RMT_RX_CHANNEL, 1);
ESP_LOGI(TAG, "Star receiving RMT data...");
tx_init();
uint16_t cmd = 0x0;
uint16_t addr = 0x11;
int num_items = DATA_ITEM_NUM * RMT_TX_DATA_NUM;
rmt_item32_t *items = calloc(num_items + 1, sizeof(rmt_item32_t));
vTaskDelay(pdMS_TO_TICKS(2000));
ESP_LOGI(TAG, "Sending RMT data...");
// send data
set_tx_data(tx_channel, cmd, addr, item_num, item, offset);
rmt_write_items(tx_channel, item, item_num, 0);
rmt_wait_tx_done(tx_channel, portMAX_DELAY);
free(item);
set_tx_data(RMT_TX_CHANNEL, cmd, addr, num_items, items, 0);
rmt_write_items(RMT_TX_CHANNEL, items, num_items, 0);
rmt_wait_tx_done(RMT_TX_CHANNEL, portMAX_DELAY);
free(items);
// receive data
uint16_t tmp = get_rx_data(rb);
TEST_ASSERT(tmp == 100);
TEST_ASSERT(tmp == RMT_TX_DATA_NUM);
TEST_ESP_OK(rmt_driver_uninstall(RMT_TX_CHANNEL));
TEST_ESP_OK(rmt_driver_uninstall(RMT_RX_CHANNEL));
}
TEST_CASE("RMT TX stop test", "[rmt][test_env=UT_T1_RMT]")
{
int rx_channel = RMT_RX_CHANNEL;
rx_init();
RingbufHandle_t rb = NULL;
rmt_get_ringbuf_handle(rx_channel, &rb);
rmt_rx_start(rx_channel, 1);
rmt_get_ringbuf_handle(RMT_RX_CHANNEL, &rb);
rmt_rx_start(RMT_RX_CHANNEL, 1);
ESP_LOGI(TAG, "Star receiving RMT data...");
vTaskDelay(10);
tx_init();
int tx_channel = RMT_TX_CHANNEL;
int tx_num = RMT_TX_DATA_NUM;
ESP_LOGI(TAG, "RMT TX DATA");
size_t size = (sizeof(rmt_item32_t) * DATA_ITEM_NUM * tx_num);
rmt_item32_t* item = (rmt_item32_t*) malloc(size);
int item_num = DATA_ITEM_NUM * tx_num;
memset((void*) item, 0, size);
int offset = 0;
uint16_t cmd = 0x0;
uint16_t addr = 0x11;
int num_items = DATA_ITEM_NUM * RMT_TX_DATA_NUM;
rmt_item32_t *items = calloc(num_items + 1, sizeof(rmt_item32_t));
vTaskDelay(pdMS_TO_TICKS(2000));
ESP_LOGI(TAG, "Sending RMT data...");
// send data
set_tx_data(tx_channel, cmd, addr, item_num, item, offset);
rmt_write_items(tx_channel, item, item_num, 0);
set_tx_data(RMT_TX_CHANNEL, cmd, addr, num_items, items, 0);
rmt_write_items(RMT_TX_CHANNEL, items, num_items, 0);
vTaskDelay(1000 / portTICK_PERIOD_MS);
rmt_tx_stop(tx_channel);
free(item);
rmt_tx_stop(RMT_TX_CHANNEL);
free(items);
// receive data
uint16_t tmp = get_rx_data(rb);
TEST_ASSERT(tmp < 100);
TEST_ASSERT(tmp < RMT_TX_DATA_NUM);
TEST_ESP_OK(rmt_driver_uninstall(RMT_TX_CHANNEL));
TEST_ESP_OK(rmt_driver_uninstall(RMT_RX_CHANNEL));
@ -761,47 +756,8 @@ TEST_CASE("RMT loop_en test", "[rmt][test_env=UT_T1_RMT][ignore]")
// receive data
uint16_t tmp = get_rx_data(rb);
TEST_ASSERT(tmp < 100);
TEST_ASSERT(tmp < RMT_TX_DATA_NUM);
TEST_ESP_OK(rmt_driver_uninstall(RMT_TX_CHANNEL));
TEST_ESP_OK(rmt_driver_uninstall(RMT_RX_CHANNEL));
}
TEST_CASE("RMT use multi channel", "[rmt][test_env=UT_T1_RMT]")
{
rmt_tx_config_t tx_cfg = {
.loop_en = true, // set it as true
.carrier_duty_percent = 50,
.carrier_freq_hz = 38000,
.carrier_level = 1,
.carrier_en = RMT_TX_CARRIER_EN,
.idle_level = 0,
.idle_output_en = true,
};
rmt_config_t rmt_tx1 = {
.channel = RMT_TX_CHANNEL,
.gpio_num = RMT_TX_GPIO_NUM,
.mem_block_num = 4,
.clk_div = RMT_CLK_DIV,
.tx_config = tx_cfg,
.rmt_mode = 0,
};
rmt_config(&rmt_tx1);
rmt_driver_install(rmt_tx1.channel, 0, 0);
rmt_config_t rmt_tx2 = rmt_tx1;
rmt_tx2.channel = 2;
rmt_config(&rmt_tx2);
rmt_driver_install(rmt_tx2.channel, 0, 0);
rmt_config_t rmt_tx3 = rmt_tx1;
rmt_tx3.channel = 7;
rmt_tx3.mem_block_num = 1;
rmt_config(&rmt_tx3);
rmt_driver_install(rmt_tx3.channel, 0, 0);
TEST_ESP_OK(rmt_driver_uninstall(RMT_TX_CHANNEL));
TEST_ESP_OK(rmt_driver_uninstall(2));
TEST_ESP_OK(rmt_driver_uninstall(7));
}

1
components/soc/CMakeLists.txt
View file

@ -12,6 +12,7 @@ list(APPEND include_dirs include)
list(APPEND srcs
"src/memory_layout_utils.c"
"src/lldesc.c"
"src/hal/rmt_hal.c"
"src/hal/spi_hal.c"
"src/hal/spi_hal_iram.c"
"src/hal/spi_slave_hal.c"

297
components/soc/esp32/include/hal/rmt_ll.h Normal file
View file

@ -0,0 +1,297 @@
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <stdbool.h>
#include "soc/rmt_struct.h"
#include "soc/rmt_caps.h"
static inline void rmt_ll_reset_counter_clock_div(rmt_dev_t *dev, uint32_t channel)
{
dev->conf_ch[channel].conf1.ref_cnt_rst = 1;
dev->conf_ch[channel].conf1.ref_cnt_rst = 0;
}
static inline void rmt_ll_reset_tx_pointer(rmt_dev_t *dev, uint32_t channel)
{
dev->conf_ch[channel].conf1.mem_rd_rst = 1;
dev->conf_ch[channel].conf1.mem_rd_rst = 0;
}
static inline void rmt_ll_reset_rx_pointer(rmt_dev_t *dev, uint32_t channel)
{
dev->conf_ch[channel].conf1.mem_wr_rst = 1;
dev->conf_ch[channel].conf1.mem_wr_rst = 0;
}
static inline void rmt_ll_start_tx(rmt_dev_t *dev, uint32_t channel)
{
dev->conf_ch[channel].conf1.tx_start = 1;
}
static inline void rmt_ll_stop_tx(rmt_dev_t *dev, uint32_t channel)
{
RMTMEM.chan[channel].data32[0].val = 0;
dev->conf_ch[channel].conf1.tx_start = 0;
dev->conf_ch[channel].conf1.mem_rd_rst = 1;
dev->conf_ch[channel].conf1.mem_rd_rst = 0;
}
static inline void rmt_ll_enable_rx(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf_ch[channel].conf1.rx_en = enable;
}
static inline void rmt_ll_power_down_mem(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf_ch[channel].conf0.mem_pd = enable;
}
static inline bool rmt_ll_is_mem_power_down(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf0.mem_pd;
}
static inline void rmt_ll_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num)
{
dev->conf_ch[channel].conf0.mem_size = block_num;
}
static inline uint32_t rmt_ll_get_mem_blocks(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf0.mem_size;
}
static inline void rmt_ll_set_counter_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div)
{
dev->conf_ch[channel].conf0.div_cnt = div;
}
static inline uint32_t rmt_ll_get_counter_clock_div(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf0.div_cnt;
}
static inline void rmt_ll_enable_tx_pingpong(rmt_dev_t *dev, bool enable)
{
dev->apb_conf.mem_tx_wrap_en = enable;
}
static inline void rmt_ll_enable_mem_access(rmt_dev_t *dev, bool enable)
{
dev->apb_conf.fifo_mask = enable;
}
static inline void rmt_ll_set_rx_idle_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres)
{
dev->conf_ch[channel].conf0.idle_thres = thres;
}
static inline uint32_t rmt_ll_get_rx_idle_thres(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf0.idle_thres;
}
static inline void rmt_ll_set_mem_owner(rmt_dev_t *dev, uint32_t channel, uint8_t owner)
{
dev->conf_ch[channel].conf1.mem_owner = owner;
}
static inline uint32_t rmt_ll_get_mem_owner(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf1.mem_owner;
}
static inline void rmt_ll_enable_tx_cyclic(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf_ch[channel].conf1.tx_conti_mode = enable;
}
static inline bool rmt_ll_is_tx_cyclic_enabled(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf1.tx_conti_mode;
}
static inline void rmt_ll_enable_rx_filter(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf_ch[channel].conf1.rx_filter_en = enable;
}
static inline void rmt_ll_set_rx_filter_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres)
{
dev->conf_ch[channel].conf1.rx_filter_thres = thres;
}
static inline void rmt_ll_set_counter_clock_src(rmt_dev_t *dev, uint32_t channel, uint8_t src)
{
dev->conf_ch[channel].conf1.ref_always_on = src;
}
static inline uint32_t rmt_ll_get_counter_clock_src(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf1.ref_always_on;
}
static inline void rmt_ll_enable_tx_idle(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf_ch[channel].conf1.idle_out_en = enable;
}
static inline bool rmt_ll_is_tx_idle_enabled(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf1.idle_out_en;
}
static inline void rmt_ll_set_tx_idle_level(rmt_dev_t *dev, uint32_t channel, uint8_t level)
{
dev->conf_ch[channel].conf1.idle_out_lv = level;
}
static inline uint32_t rmt_ll_get_tx_idle_level(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf1.idle_out_lv;
}
static inline uint32_t rmt_ll_get_channel_status(rmt_dev_t *dev, uint32_t channel)
{
return dev->status_ch[channel];
}
static inline void rmt_ll_set_tx_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit)
{
dev->tx_lim_ch[channel].limit = limit;
}
static inline void rmt_ll_enable_tx_end_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->int_ena.val &= ~(1 << (channel * 3));
dev->int_ena.val |= (enable << (channel * 3));
}
static inline void rmt_ll_enable_rx_end_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->int_ena.val &= ~(1 << (channel * 3 + 1));
dev->int_ena.val |= (enable << (channel * 3 + 1));
}
static inline void rmt_ll_enable_err_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->int_ena.val &= ~(1 << (channel * 3 + 2));
dev->int_ena.val |= (enable << (channel * 3 + 2));
}
static inline void rmt_ll_enable_tx_thres_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->int_ena.val &= ~(1 << (channel + 24));
dev->int_ena.val |= (enable << (channel + 24));
}
static inline void rmt_ll_clear_tx_end_interrupt(rmt_dev_t *dev, uint32_t channel)
{
dev->int_clr.val = (1 << (channel * 3));
}
static inline void rmt_ll_clear_rx_end_interrupt(rmt_dev_t *dev, uint32_t channel)
{
dev->int_clr.val = (1 << (channel * 3 + 1));
}
static inline void rmt_ll_clear_err_interrupt(rmt_dev_t *dev, uint32_t channel)
{
dev->int_clr.val = (1 << (channel * 3 + 2));
}
static inline void rmt_ll_clear_tx_thres_interrupt(rmt_dev_t *dev, uint32_t channel)
{
dev->int_clr.val = (1 << (channel + 24));
}
static inline uint32_t rmt_ll_get_tx_end_interrupt_status(rmt_dev_t *dev)
{
uint32_t status = dev->int_st.val;
return ((status & 0x01) >> 0) | ((status & 0x08) >> 2) | ((status & 0x40) >> 4) | ((status & 0x200) >> 6) |
((status & 0x1000) >> 8) | ((status & 0x8000) >> 10) | ((status & 40000) >> 12) | ((status & 0x200000) >> 14);
}
static inline uint32_t rmt_ll_get_rx_end_interrupt_status(rmt_dev_t *dev)
{
uint32_t status = dev->int_st.val;
return ((status & 0x02) >> 1) | ((status & 0x10) >> 3) | ((status & 0x80) >> 5) | ((status & 0x400) >> 7) |
((status & 0x2000) >> 9) | ((status & 0x10000) >> 11) | ((status & 80000) >> 13) | ((status & 0x400000) >> 15);
}
static inline uint32_t rmt_ll_get_err_interrupt_status(rmt_dev_t *dev)
{
uint32_t status = dev->int_st.val;
return ((status & 0x04) >> 2) | ((status & 0x20) >> 4) | ((status & 0x100) >> 6) | ((status & 0x800) >> 8) |
((status & 0x4000) >> 10) | ((status & 0x20000) >> 12) | ((status & 100000) >> 14) | ((status & 0x800000) >> 16);
}
static inline uint32_t rmt_ll_get_tx_thres_interrupt_status(rmt_dev_t *dev)
{
uint32_t status = dev->int_st.val;
return (status & 0xFF000000) >> 24;
}
static inline void rmt_ll_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks)
{
dev->carrier_duty_ch[channel].high = high_ticks;
dev->carrier_duty_ch[channel].low = low_ticks;
}
static inline void rmt_ll_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks)
{
*high_ticks = dev->carrier_duty_ch[channel].high;
*low_ticks = dev->carrier_duty_ch[channel].low;
}
static inline void rmt_ll_enable_tx_carrier(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf_ch[channel].conf0.carrier_en = enable;
}
static inline void rmt_ll_set_carrier_to_level(rmt_dev_t *dev, uint32_t channel, uint8_t level)
{
dev->conf_ch[channel].conf0.carrier_out_lv = level;
}
static inline void rmt_ll_write_memory(rmt_mem_t *mem, uint32_t channel, const rmt_item32_t *data, uint32_t length, uint32_t off)
{
length = (off + length) > RMT_CHANNEL_MEM_WORDS ? (RMT_CHANNEL_MEM_WORDS - off) : length;
for (uint32_t i = 0; i < length; i++) {
mem->chan[channel].data32[i + off].val = data[i].val;
}
}
/************************************************************************************************
* Following Low Level APIs only used for backward compatible, will be deprecated in the future!
***********************************************************************************************/
static inline void rmt_ll_set_intr_enable_mask(uint32_t mask)
{
RMT.int_ena.val |= mask;
}
static inline void rmt_ll_clr_intr_enable_mask(uint32_t mask)
{
RMT.int_ena.val &= (~mask);
}
#ifdef __cplusplus
}
#endif

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// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#define RMT_CHANNEL_MEM_WORDS (64) /*!< Each channel owns 64 words memory */
/**
* @brief RMT channel ID
*
*/
typedef enum {
RMT_CHANNEL_0, /*!< RMT channel number 0 */
RMT_CHANNEL_1, /*!< RMT channel number 1 */
RMT_CHANNEL_2, /*!< RMT channel number 2 */
RMT_CHANNEL_3, /*!< RMT channel number 3 */
RMT_CHANNEL_4, /*!< RMT channel number 4 */
RMT_CHANNEL_5, /*!< RMT channel number 5 */
RMT_CHANNEL_6, /*!< RMT channel number 6 */
RMT_CHANNEL_7, /*!< RMT channel number 7 */
RMT_CHANNEL_MAX /*!< Number of RMT channels */
} rmt_channel_id_t;
#ifdef __cplusplus
}
#endif

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// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <stdbool.h>
#include "soc/rmt_struct.h"
#include "soc/rmt_caps.h"
static inline void rmt_ll_reset_counter_clock_div(rmt_dev_t *dev, uint32_t channel)
{
}
static inline void rmt_ll_reset_tx_pointer(rmt_dev_t *dev, uint32_t channel)
{
dev->conf_ch[channel].conf1.mem_rd_rst = 1;
dev->conf_ch[channel].conf1.mem_rd_rst = 0;
}
static inline void rmt_ll_reset_rx_pointer(rmt_dev_t *dev, uint32_t channel)
{
dev->conf_ch[channel].conf1.mem_wr_rst = 1;
dev->conf_ch[channel].conf1.mem_wr_rst = 0;
}
static inline void rmt_ll_start_tx(rmt_dev_t *dev, uint32_t channel)
{
dev->conf_ch[channel].conf1.tx_start = 1;
}
static inline void rmt_ll_stop_tx(rmt_dev_t *dev, uint32_t channel)
{
dev->conf_ch[channel].conf1.tx_stop = 1;
}
static inline void rmt_ll_enable_rx(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf_ch[channel].conf1.rx_en = enable;
}
static inline void rmt_ll_power_down_mem(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf_ch[channel].conf0.mem_pd = enable;
}
static inline bool rmt_ll_is_mem_power_down(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf0.mem_pd;
}
static inline void rmt_ll_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num)
{
dev->conf_ch[channel].conf0.mem_size = block_num;
}
static inline uint32_t rmt_ll_get_mem_blocks(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf0.mem_size;
}
static inline void rmt_ll_set_counter_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div)
{
dev->conf_ch[channel].conf0.div_cnt = div;
}
static inline uint32_t rmt_ll_get_counter_clock_div(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf0.div_cnt;
}
static inline void rmt_ll_enable_tx_pingpong(rmt_dev_t *dev, bool enable)
{
dev->apb_conf.mem_tx_wrap_en = enable;
}
static inline void rmt_ll_enable_mem_access(rmt_dev_t *dev, bool enable)
{
dev->apb_conf.fifo_mask = enable;
}
static inline void rmt_ll_set_rx_idle_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres)
{
dev->conf_ch[channel].conf0.idle_thres = thres;
}
static inline uint32_t rmt_ll_get_rx_idle_thres(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf0.idle_thres;
}
static inline void rmt_ll_set_mem_owner(rmt_dev_t *dev, uint32_t channel, uint8_t owner)
{
dev->conf_ch[channel].conf1.mem_owner = owner;
}
static inline uint32_t rmt_ll_get_mem_owner(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf1.mem_owner;
}
static inline void rmt_ll_enable_tx_cyclic(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf_ch[channel].conf1.tx_conti_mode = enable;
}
static inline bool rmt_ll_is_tx_cyclic_enabled(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf1.tx_conti_mode;
}
static inline void rmt_ll_enable_rx_filter(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf_ch[channel].conf1.rx_filter_en = enable;
}
static inline void rmt_ll_set_rx_filter_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres)
{
dev->conf_ch[channel].conf1.rx_filter_thres = thres;
}
static inline void rmt_ll_set_counter_clock_src(rmt_dev_t *dev, uint32_t channel, uint8_t src)
{
dev->conf_ch[channel].conf1.ref_always_on = src;
}
static inline uint32_t rmt_ll_get_counter_clock_src(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf1.ref_always_on;
}
static inline void rmt_ll_enable_tx_idle(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf_ch[channel].conf1.idle_out_en = enable;
}
static inline bool rmt_ll_is_tx_idle_enabled(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf1.idle_out_en;
}
static inline void rmt_ll_set_tx_idle_level(rmt_dev_t *dev, uint32_t channel, uint8_t level)
{
dev->conf_ch[channel].conf1.idle_out_lv = level;
}
static inline uint32_t rmt_ll_get_tx_idle_level(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf1.idle_out_lv;
}
static inline uint32_t rmt_ll_get_channel_status(rmt_dev_t *dev, uint32_t channel)
{
return dev->status_ch[channel].val;
}
static inline void rmt_ll_set_tx_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit)
{
dev->tx_lim_ch[channel].limit = limit;
}
static inline void rmt_ll_enable_tx_end_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->int_ena.val &= ~(1 << (channel * 3));
dev->int_ena.val |= (enable << (channel * 3));
}
static inline void rmt_ll_enable_rx_end_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->int_ena.val &= ~(1 << (channel * 3 + 1));
dev->int_ena.val |= (enable << (channel * 3 + 1));
}
static inline void rmt_ll_enable_err_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->int_ena.val &= ~(1 << (channel * 3 + 2));
dev->int_ena.val |= (enable << (channel * 3 + 2));
}
static inline void rmt_ll_enable_tx_thres_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->int_ena.val &= ~(1 << (channel + 12));
dev->int_ena.val |= (enable << (channel + 12));
}
static inline void rmt_ll_clear_tx_end_interrupt(rmt_dev_t *dev, uint32_t channel)
{
dev->int_clr.val = (1 << (channel * 3));
}
static inline void rmt_ll_clear_rx_end_interrupt(rmt_dev_t *dev, uint32_t channel)
{
dev->int_clr.val = (1 << (channel * 3 + 1));
}
static inline void rmt_ll_clear_err_interrupt(rmt_dev_t *dev, uint32_t channel)
{
dev->int_clr.val = (1 << (channel * 3 + 2));
}
static inline void rmt_ll_clear_tx_thres_interrupt(rmt_dev_t *dev, uint32_t channel)
{
dev->int_clr.val = (1 << (channel + 12));
}
static inline uint32_t rmt_ll_get_tx_end_interrupt_status(rmt_dev_t *dev)
{
uint32_t status = dev->int_st.val;
return ((status & 0x01) >> 0) | ((status & 0x08) >> 2) | ((status & 0x40) >> 4) | ((status & 0x200) >> 6);
}
static inline uint32_t rmt_ll_get_rx_end_interrupt_status(rmt_dev_t *dev)
{
uint32_t status = dev->int_st.val;
return ((status & 0x02) >> 1) | ((status & 0x10) >> 3) | ((status & 0x80) >> 5) | ((status & 0x400) >> 7);
}
static inline uint32_t rmt_ll_get_err_interrupt_status(rmt_dev_t *dev)
{
uint32_t status = dev->int_st.val;
return ((status & 0x04) >> 2) | ((status & 0x20) >> 4) | ((status & 0x100) >> 6) | ((status & 0x800) >> 8);;
}
static inline uint32_t rmt_ll_get_tx_thres_interrupt_status(rmt_dev_t *dev)
{
uint32_t status = dev->int_st.val;
return (status & 0xF000) >> 12;
}
static inline void rmt_ll_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks)
{
dev->carrier_duty_ch[channel].high = high_ticks;
dev->carrier_duty_ch[channel].low = low_ticks;
}
static inline void rmt_ll_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks)
{
*high_ticks = dev->carrier_duty_ch[channel].high;
*low_ticks = dev->carrier_duty_ch[channel].low;
}
static inline void rmt_ll_enable_tx_carrier(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf_ch[channel].conf0.carrier_en = enable;
}
static inline void rmt_ll_set_carrier_to_level(rmt_dev_t *dev, uint32_t channel, uint8_t level)
{
dev->conf_ch[channel].conf0.carrier_out_lv = level;
}
static inline void rmt_ll_write_memory(rmt_mem_t *mem, uint32_t channel, const rmt_item32_t *data, uint32_t length, uint32_t off)
{
length = (off + length) > RMT_CHANNEL_MEM_WORDS ? (RMT_CHANNEL_MEM_WORDS - off) : length;
for (uint32_t i = 0; i < length; i++) {
mem->chan[channel].data32[i + off].val = data[i].val;
}
}
/************************************************************************************************
* Following Low Level APIs only used for backward compatible, will be deprecated in the future!
***********************************************************************************************/
static inline void rmt_ll_set_intr_enable_mask(uint32_t mask)
{
RMT.int_ena.val |= mask;
}
static inline void rmt_ll_clr_intr_enable_mask(uint32_t mask)
{
RMT.int_ena.val &= (~mask);
}
#ifdef __cplusplus
}
#endif

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// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#define RMT_CHANNEL_MEM_WORDS (64) /*!< Each channel owns 64 words memory */
/**
* @brief RMT channel ID
*
*/
typedef enum {
RMT_CHANNEL_0, /*!< RMT channel number 0 */
RMT_CHANNEL_1, /*!< RMT channel number 1 */
RMT_CHANNEL_2, /*!< RMT channel number 2 */
RMT_CHANNEL_3, /*!< RMT channel number 3 */
RMT_CHANNEL_MAX /*!< Number of RMT channels */
} rmt_channel_id_t;
#ifdef __cplusplus
}
#endif

3
components/soc/esp32s2beta/include/soc/rmt_struct.h
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@ -13,6 +13,9 @@
// limitations under the License.
#ifndef _SOC_RMT_STRUCT_H_
#define _SOC_RMT_STRUCT_H_
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif

142
components/soc/include/hal/rmt_hal.h Normal file
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@ -0,0 +1,142 @@
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include "soc/rmt_struct.h"
#include "soc/rmt_caps.h"
/**
* @brief HAL context type of RMT driver
*
*/
typedef struct {
rmt_dev_t *regs; /*!< RMT Register base address */
rmt_mem_t *mem; /*!< RMT Memory base address */
} rmt_hal_context_t;
#define RMT_MEM_OWNER_SW (0) /*!< RMT Memory ownership belongs to software side */
#define RMT_MEM_OWNER_HW (1) /*!< RMT Memory ownership belongs to hardware side */
/**
* @brief Initialize the RMT HAL driver
*
* @param hal: RMT HAL context
*/
void rmt_hal_init(rmt_hal_context_t *hal);
/**
* @brief Reset RMT HAL driver
*
* @param hal: RMT HAL context
*/
void rmt_hal_reset(rmt_hal_context_t *hal);
/**
* @brief Reset RMT Channel specific HAL driver
*
* @param hal: RMT HAL context
* @param channel: RMT channel number
*/
void rmt_hal_channel_reset(rmt_hal_context_t *hal, uint32_t channel);
/**
* @brief Set counter clock for RMT channel
*
* @param hal: RMT HAL context
* @param channel: RMT channel number
* @param base_clk_hz: base clock for RMT internal channel (counter clock will divide from it)
* @param counter_clk_hz: target counter clock
*/
void rmt_hal_set_counter_clock(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz, uint32_t counter_clk_hz);
/**
* @brief Get counter clock for RMT channel
*
* @param hal: RMT HAL context
* @param channel: RMT channel number
* @param base_clk_hz: base clock for RMT internal channel (counter clock will divide from it)
* @return counter clock in Hz
*/
uint32_t rmt_hal_get_counter_clock(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz);
/**
* @brief Set carrier clock for RMT channel
*
* @param hal: RMT HAL context
* @param channel: RMT channel number
* @param base_clk_hz: base clock for RMT carrier generation (carrier clock will divide from it)
* @param carrier_clk_hz: target carrier clock
* @param carrier_clk_duty: duty ratio of carrier clock
*/
void rmt_hal_set_carrier_clock(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz, uint32_t carrier_clk_hz, float carrier_clk_duty);
/**
* @brief Get carrier clock for RMT channel
*
* @param hal: RMT HAL context
* @param channel: RMT channel number
* @param base_clk_hz: base clock for RMT carrier generation
* @param carrier_clk_hz: target carrier clock
* @param carrier_clk_duty: duty ratio of carrier clock
*/
void rmt_hal_get_carrier_clock(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz, uint32_t *carrier_clk_hz, float *carrier_clk_duty);
/**
* @brief Set filter threshold for RMT Receive channel
*
* @param hal: RMT HAL context
* @param channel: RMT channel number
* @param base_clk_hz: base clock for RMT receive filter
* @param thres_us: threshold of RMT receive filter, in us
*/
void rmt_hal_set_rx_filter_thres(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz, uint32_t thres_us);
/**
* @brief Set idle threshold for RMT Receive channel
*
* @param hal: RMT HAL context
* @param channel: RMT channel number
* @param base_clk_hz: base clock for RMT receive channel
* @param thres_us: IDLE threshold for RMT receive channel
*/
void rmt_hal_set_rx_idle_thres(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz, uint32_t thres_us);
/**
* @brief Receive a frame from RMT channel
*
* @param hal: RMT HAL context
* @param channel: RMT channel number
* @param buf: buffer to store received RMT frame
* @return number of items that get received
*/
uint32_t rmt_hal_receive(rmt_hal_context_t *hal, uint32_t channel, rmt_item32_t *buf);
/**
* @brief Transmit a from by RMT
*
* @param hal: RMT HAL context
* @param channel: RMT channel number
* @param src: RMT items to transmit
* @param length: length of RMT items to transmit
* @param offset: offset of RMT internal memory to store the items
*/
void rmt_hal_transmit(rmt_hal_context_t *hal, uint32_t channel, const rmt_item32_t *src, uint32_t length, uint32_t offset);
#ifdef __cplusplus
}
#endif

108
components/soc/include/hal/rmt_types.h Normal file
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@ -0,0 +1,108 @@
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief RMT Channel Type
*
*/
typedef rmt_channel_id_t rmt_channel_t;
/**
* @brief RMT Internal Memory Owner
*
*/
typedef enum {
RMT_MEM_OWNER_TX, /*!< RMT RX mode, RMT transmitter owns the memory block*/
RMT_MEM_OWNER_RX, /*!< RMT RX mode, RMT receiver owns the memory block*/
RMT_MEM_OWNER_MAX,
} rmt_mem_owner_t;
/**
* @brief Clock Source of RMT Channel
*
*/
typedef enum {
RMT_BASECLK_REF, /*!< RMT source clock system reference tick, 1MHz by default (not supported in this version) */
RMT_BASECLK_APB, /*!< RMT source clock is APB CLK, 80Mhz by default */
RMT_BASECLK_MAX,
} rmt_source_clk_t;
/**
* @brief RMT Data Mode
*
* @note We highly recommended to use MEM mode not FIFO mode since there will be some gotcha in FIFO mode.
*
*/
typedef enum {
RMT_DATA_MODE_FIFO, /*<! RMT memory access in FIFO mode */
RMT_DATA_MODE_MEM, /*<! RMT memory access in memory mode */
RMT_DATA_MODE_MAX,
} rmt_data_mode_t;
/**
* @brief RMT Channel Working Mode (TX or RX)
*
*/
typedef enum {
RMT_MODE_TX, /*!< RMT TX mode */
RMT_MODE_RX, /*!< RMT RX mode */
RMT_MODE_MAX
} rmt_mode_t;
/**
* @brief RMT Idle Level
*
*/
typedef enum {
RMT_IDLE_LEVEL_LOW, /*!< RMT TX idle level: low Level */
RMT_IDLE_LEVEL_HIGH, /*!< RMT TX idle level: high Level */
RMT_IDLE_LEVEL_MAX,
} rmt_idle_level_t;
/**
* @brief RMT Carrier Level
*
*/
typedef enum {
RMT_CARRIER_LEVEL_LOW, /*!< RMT carrier wave is modulated for low Level output */
RMT_CARRIER_LEVEL_HIGH, /*!< RMT carrier wave is modulated for high Level output */
RMT_CARRIER_LEVEL_MAX
} rmt_carrier_level_t;
/**
* @brief RMT Channel Status
*
*/
typedef enum {
RMT_CHANNEL_UNINIT, /*!< RMT channel uninitialized */
RMT_CHANNEL_IDLE, /*!< RMT channel status idle */
RMT_CHANNEL_BUSY, /*!< RMT channel status busy */
} rmt_channel_status_t;
/**
* @brief Data struct of RMT channel status
*/
typedef struct {
rmt_channel_status_t status[RMT_CHANNEL_MAX]; /*!< Store the current status of each channel */
} rmt_channel_status_result_t;
#ifdef __cplusplus
}
#endif

106
components/soc/src/hal/rmt_hal.c Normal file
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@ -0,0 +1,106 @@
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "hal/rmt_hal.h"
#include "hal/rmt_ll.h"
void rmt_hal_init(rmt_hal_context_t *hal)
{
hal->regs = &RMT;
hal->mem = &RMTMEM;
}
void rmt_hal_reset(rmt_hal_context_t *hal)
{
}
void rmt_hal_channel_reset(rmt_hal_context_t *hal, uint32_t channel)
{
rmt_ll_reset_tx_pointer(hal->regs, channel);
rmt_ll_reset_rx_pointer(hal->regs, channel);
rmt_ll_enable_err_interrupt(hal->regs, channel, false);
rmt_ll_enable_tx_end_interrupt(hal->regs, channel, false);
rmt_ll_enable_tx_thres_interrupt(hal->regs, channel, false);
rmt_ll_enable_rx_end_interrupt(hal->regs, channel, false);
rmt_ll_clear_err_interrupt(hal->regs, channel);
rmt_ll_clear_tx_end_interrupt(hal->regs, channel);
rmt_ll_clear_tx_thres_interrupt(hal->regs, channel);
rmt_ll_clear_rx_end_interrupt(hal->regs, channel);
}
void rmt_hal_set_counter_clock(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz, uint32_t counter_clk_hz)
{
rmt_ll_reset_counter_clock_div(hal->regs, channel);
uint32_t counter_div = (base_clk_hz + counter_clk_hz / 2) / counter_clk_hz;
rmt_ll_set_counter_clock_div(hal->regs, channel, counter_div);
}
uint32_t rmt_hal_get_counter_clock(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz)
{
return base_clk_hz / rmt_ll_get_counter_clock_div(hal->regs, channel);
}
void rmt_hal_set_carrier_clock(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz, uint32_t carrier_clk_hz, float carrier_clk_duty)
{
uint32_t carrier_div = (base_clk_hz + carrier_clk_hz / 2) / carrier_clk_hz;
uint32_t div_high = (uint32_t)(carrier_div * carrier_clk_duty);
uint32_t div_low = carrier_div - div_high;
rmt_ll_set_carrier_high_low_ticks(hal->regs, channel, div_high, div_low);
}
void rmt_hal_get_carrier_clock(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz, uint32_t *carrier_clk_hz, float *carrier_clk_duty)
{
uint32_t div_high = 0;
uint32_t div_low = 0;
rmt_ll_get_carrier_high_low_ticks(hal->regs, channel, &div_high, &div_low);
*carrier_clk_hz = base_clk_hz / (div_high + div_low);
*carrier_clk_duty = (float)div_high / (div_high + div_low);
}
void rmt_hal_set_rx_filter_thres(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz, uint32_t thres_us)
{
uint32_t thres = (uint32_t)(base_clk_hz / 1e6 * thres_us);
rmt_ll_set_rx_filter_thres(hal->regs, channel, thres);
}
void rmt_hal_set_rx_idle_thres(rmt_hal_context_t *hal, uint32_t channel, uint32_t base_clk_hz, uint32_t thres_us)
{
uint32_t thres = (uint32_t)(base_clk_hz / 1e6 * thres_us);
rmt_ll_set_rx_idle_thres(hal->regs, channel, thres);
}
uint32_t rmt_hal_receive(rmt_hal_context_t *hal, uint32_t channel, rmt_item32_t *buf)
{
uint32_t len = 0;
rmt_ll_set_mem_owner(hal->regs, channel, RMT_MEM_OWNER_SW);
for (len = 0; len < RMT_CHANNEL_MEM_WORDS; len++) {
buf[len].val = hal->mem->chan[channel].data32[len].val;
if (!(buf[len].val & 0x7FFF)) {
break;
} else if (!(buf[len].val & 0x7FFF0000)) {
len++;
break;
}
}
rmt_ll_set_mem_owner(hal->regs, channel, RMT_MEM_OWNER_HW);
rmt_ll_reset_rx_pointer(hal->regs, channel);
return len;
}
void rmt_hal_transmit(rmt_hal_context_t *hal, uint32_t channel, const rmt_item32_t *src, uint32_t length, uint32_t offset)
{
rmt_ll_set_mem_owner(hal->regs, channel, RMT_MEM_OWNER_SW);
rmt_ll_write_memory(hal->mem, channel, src, length, offset);
rmt_ll_set_mem_owner(hal->regs, channel, RMT_MEM_OWNER_HW);
}

1
docs/Doxyfile
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@ -103,6 +103,7 @@ INPUT = \
../../components/driver/include/driver/touch_pad.h \
../../components/driver/include/driver/uart.h \
../../components/esp_adc_cal/include/esp_adc_cal.h \
../../components/soc/include/hal/rmt_types.h \
../../components/soc/include/hal/spi_types.h \
../../components/soc/include/hal/pcnt_types.h \
../../components/soc/esp32/include/soc/adc_channel.h \

11
docs/en/api-reference/peripherals/rmt.rst
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@ -153,7 +153,7 @@ Now, depending on how the channel is configured, we are ready to either `Transmi
Transmit Data
-------------
Before being able to transmit some RMT pulses, we need to define the pulse pattern. The minimum pattern recognized by the RMT controller, later called an 'item', is provided in a structure :cpp:type:`rmt_item32_t`, see :component_file:`soc/esp32/include/soc/rmt_struct.h`. Each item consists of two pairs of two values. The first value in a pair describes the signal duration in ticks and is 15 bits long, the second provides the signal level (high or low) and is contained in a single bit. A block of couple of items and the structure of an item is presented below.
Before being able to transmit some RMT pulses, we need to define the pulse pattern. The minimum pattern recognized by the RMT controller, later called an 'item', is provided in a structure :cpp:type:`rmt_item32_t`, see :component_file:`soc/esp32/include/soc/rmt_caps.h`. Each item consists of two pairs of two values. The first value in a pair describes the signal duration in ticks and is 15 bits long, the second provides the signal level (high or low) and is contained in a single bit. A block of couple of items and the structure of an item is presented below.
.. packetdiag::
:caption: Structure of RMT items (L - signal level)
@ -176,7 +176,7 @@ Before being able to transmit some RMT pulses, we need to define the pulse patte
127: L
}
For a simple example how to define a block of items see :example:`peripherals/rmt_tx`.
For a simple example how to define a block of items see :example:`peripherals/rmt/morse_code`.
The items are provided to the RMT controller by calling function :cpp:func:`rmt_write_items`. This function also automatically triggers start of transmission. It may be called to wait for transmission completion or exit just after transmission start. In such case you can wait for the transmission end by calling :cpp:func:`rmt_wait_tx_done`. This function does not limit the number of data items to transmit. It is using an interrupt to successively copy the new data chunks to RMT's internal memory as previously provided data are sent out.
@ -188,7 +188,7 @@ Receive Data
Before starting the receiver we need some storage for incoming items. The RMT controller has 512 x 32-bits of internal RAM shared between all eight channels. In typical scenarios it is not enough as an ultimate storage for all incoming (and outgoing) items. Therefore this API supports retrieval of incoming items on the fly to save them in a ring buffer of a size defined by the user. The size is provided when calling :cpp:func:`rmt_driver_install` discussed above. To get a handle to this buffer call :cpp:func:`rmt_get_ringbuf_handle`.
With the above steps complete we can start the receiver by calling :cpp:func:`rmt_rx_start` and then move to checking what's inside the buffer. To do so, you can use common FreeRTOS functions that interact with the ring buffer. Please see an example how to do it in :example:`peripherals/rmt_nec_tx_rx`.
With the above steps complete we can start the receiver by calling :cpp:func:`rmt_rx_start` and then move to checking what's inside the buffer. To do so, you can use common FreeRTOS functions that interact with the ring buffer. Please see an example how to do it in :example:`peripherals/rmt/ir_protocols`.
To stop the receiver, call :cpp:func:`rmt_rx_stop`.
@ -256,8 +256,9 @@ If the RMT driver has been installed with :cpp:func:`rmt_driver_install` for som
Application Examples
--------------------
* A simple RMT TX example: :example:`peripherals/rmt_tx`.
* NEC remote control TX and RX example: :example:`peripherals/rmt_nec_tx_rx`.
* A simple RMT TX example: :example:`peripherals/rmt/morse_code`.
* Another RMT TX example, specific to drive a common RGB LED strip: :example:`peripherals/rmt/led_strip`.
* NEC remote control TX and RX example: :example:`peripherals/rmt/ir_protocols`.
API Reference