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panic: prevent INT WDT from re-triggering in OCD mode

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When INT WDT fires, panicHandler is invoked. In OCD mode, panicHandler
sets a breakpoint on the PC from the exception frame and returns.
However in case of INT WDT, interrupt flag is still set in TIMERG1
peripheral, which causes INT WDT to trigger again. This causes an
endless stream of "Core  0 panic'ed (Interrupt wdt timeout on CPU1)"
messages. OpenOCD also gets terribly confused at this point.

Disable watchdogs when exiting panic handler in OCD mode.
Clear TIMERG1 WDT interrupt flag to prevent re-entry into panic handler.
This commit is contained in:
Ivan Grokhotkov 2018-01-09 01:46:24 +08:00
parent 0cd97cecb2
commit 8e8cb1a139
1 changed files with 6 additions and 0 deletions
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6
components/esp32/panic.c
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@ -165,6 +165,7 @@ static const char *edesc[] = {
#define NUM_EDESCS (sizeof(edesc) / sizeof(char *)) #define NUM_EDESCS (sizeof(edesc) / sizeof(char *))
static void commonErrorHandler(XtExcFrame *frame); static void commonErrorHandler(XtExcFrame *frame);
static inline void disableAllWdts();
//The fact that we've panic'ed probably means the other CPU is now running wild, possibly //The fact that we've panic'ed probably means the other CPU is now running wild, possibly
//messing up the serial output, so we stall it here. //messing up the serial output, so we stall it here.
@ -257,6 +258,11 @@ void panicHandler(XtExcFrame *frame)
} }
if (esp_cpu_in_ocd_debug_mode()) { if (esp_cpu_in_ocd_debug_mode()) {
disableAllWdts();
if (frame->exccause == PANIC_RSN_INTWDT_CPU0 ||
frame->exccause == PANIC_RSN_INTWDT_CPU1) {
TIMERG1.int_clr_timers.wdt = 1;
}
#if CONFIG_ESP32_APPTRACE_ENABLE #if CONFIG_ESP32_APPTRACE_ENABLE
#if CONFIG_SYSVIEW_ENABLE #if CONFIG_SYSVIEW_ENABLE
SEGGER_RTT_ESP32_FlushNoLock(CONFIG_ESP32_APPTRACE_POSTMORTEM_FLUSH_TRAX_THRESH, APPTRACE_ONPANIC_HOST_FLUSH_TMO); SEGGER_RTT_ESP32_FlushNoLock(CONFIG_ESP32_APPTRACE_POSTMORTEM_FLUSH_TRAX_THRESH, APPTRACE_ONPANIC_HOST_FLUSH_TMO);