diff --git a/components/bootloader_support/src/bootloader_clock.c b/components/bootloader_support/src/bootloader_clock.c index 059ea3623..217a2c018 100644 --- a/components/bootloader_support/src/bootloader_clock.c +++ b/components/bootloader_support/src/bootloader_clock.c @@ -48,7 +48,7 @@ void bootloader_clock_configure() clk_cfg.xtal_freq = CONFIG_ESP32_XTAL_FREQ; clk_cfg.cpu_freq_mhz = cpu_freq_mhz; #elif CONFIG_IDF_TARGET_ESP32S2BETA - clk_cfg.xtal_freq = CONFIG_ESP32_XTAL_FREQ; + clk_cfg.xtal_freq = CONFIG_ESP32S2_XTAL_FREQ; clk_cfg.cpu_freq = RTC_CPU_FREQ_80M; #endif clk_cfg.slow_freq = rtc_clk_slow_freq_get(); diff --git a/components/bootloader_support/src/bootloader_init.c b/components/bootloader_support/src/bootloader_init.c index 99a6011e7..ecbb5053b 100644 --- a/components/bootloader_support/src/bootloader_init.c +++ b/components/bootloader_support/src/bootloader_init.c @@ -172,12 +172,14 @@ static esp_err_t bootloader_main() } flash_gpio_configure(&fhdr); +#ifdef CONFIG_IDF_TARGET_ESP32 int rated_freq = bootloader_clock_get_rated_freq_mhz(); if (rated_freq < CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ) { ESP_LOGE(TAG, "Chip CPU frequency rated for %dMHz, configured for %dMHz. Modify CPU frequency in menuconfig", rated_freq, CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ); return ESP_FAIL; } +#endif bootloader_clock_configure(); uart_console_configure(); @@ -675,7 +677,7 @@ void __assert_func(const char *file, int line, const char *func, const char *exp void abort() { -#if !CONFIG_ESP32_PANIC_SILENT_REBOOT +#if !(CONFIG_ESP32_PANIC_SILENT_REBOOT || CONFIG_ESP32S2_PANIC_SILENT_REBOOT) ets_printf("abort() was called at PC 0x%08x\r\n", (intptr_t)__builtin_return_address(0) - 3); #endif if (esp_cpu_in_ocd_debug_mode()) { diff --git a/components/esp32/Kconfig b/components/esp32/Kconfig index ad7f228d9..522f8f574 100644 --- a/components/esp32/Kconfig +++ b/components/esp32/Kconfig @@ -1,4 +1,8 @@ menu "ESP32-specific" + # TODO: this component simply shouldn't be included + # in the build at the CMake level, but this is currently + # not working so we just hide all items here + visible if CONFIG_IDF_TARGET_ESP32 choice ESP32_DEFAULT_CPU_FREQ_MHZ prompt "CPU frequency" @@ -446,8 +450,6 @@ menu "ESP32-specific" e.g. GCOV data dump. config ESP32_BROWNOUT_DET - #The brownout detector code is disabled (by making it depend on a nonexisting symbol) because the current - #revision of ESP32 silicon has a bug in the brown-out detector, rendering it unusable for resetting the CPU. bool "Hardware brownout detect & reset" default y help diff --git a/components/esp32s2beta/Kconfig b/components/esp32s2beta/Kconfig index a55e23fd5..ea42e5998 100644 --- a/components/esp32s2beta/Kconfig +++ b/components/esp32s2beta/Kconfig @@ -1,117 +1,117 @@ menu "ESP32S2-specific" - choice ESP32_DEFAULT_CPU_FREQ_MHZ + choice ESP32S2_DEFAULT_CPU_FREQ_MHZ prompt "CPU frequency" - default ESP32_DEFAULT_CPU_FREQ_160 + default ESP32S2_DEFAULT_CPU_FREQ_160 help CPU frequency to be set on application startup. - config ESP32_DEFAULT_CPU_FREQ_80 + config ESP32S2_DEFAULT_CPU_FREQ_80 bool "80 MHz" - config ESP32_DEFAULT_CPU_FREQ_160 + config ESP32S2_DEFAULT_CPU_FREQ_160 bool "160 MHz" - config ESP32_DEFAULT_CPU_FREQ_240 + config ESP32S2_DEFAULT_CPU_FREQ_240 bool "240 MHz" endchoice - config ESP32_DEFAULT_CPU_FREQ_MHZ + config ESP32S2_DEFAULT_CPU_FREQ_MHZ int - default 80 if ESP32_DEFAULT_CPU_FREQ_80 - default 160 if ESP32_DEFAULT_CPU_FREQ_160 - default 240 if ESP32_DEFAULT_CPU_FREQ_240 + default 80 if ESP32S2_DEFAULT_CPU_FREQ_80 + default 160 if ESP32S2_DEFAULT_CPU_FREQ_160 + default 240 if ESP32S2_DEFAULT_CPU_FREQ_240 menu "Cache config" - choice INSTRUCTION_CACHE_SIZE + choice ESP32S2_INSTRUCTION_CACHE_SIZE prompt "Instruction cache size" - default INSTRUCTION_CACHE_8KB + default ESP32S2_INSTRUCTION_CACHE_8KB help Instruction cache size to be set on application startup. If you use 8KB instruction cache rather than 16KB instruction cache, the other 8KB will be added to the heap. - config INSTRUCTION_CACHE_8KB + config ESP32S2_INSTRUCTION_CACHE_8KB bool "8KB" - config INSTRUCTION_CACHE_16KB + config ESP32S2_INSTRUCTION_CACHE_16KB bool "16KB" endchoice - choice INSTRUCTION_CACHE_ASSOCIATED_WAYS + choice ESP32S2_INSTRUCTION_CACHE_ASSOCIATED_WAYS prompt "Instruction cache associated ways" - default INSTRUCTION_CACHE_8WAYS + default ESP32S2_INSTRUCTION_CACHE_8WAYS help Instruction cache associated ways to be set on application startup. - config INSTRUCTION_CACHE_4WAYS + config ESP32S2_INSTRUCTION_CACHE_4WAYS bool "4 ways" - config INSTRUCTION_CACHE_8WAYS + config ESP32S2_INSTRUCTION_CACHE_8WAYS bool "8 ways" endchoice - choice INSTRUCTION_CACHE_LINE_SIZE + choice ESP32S2_INSTRUCTION_CACHE_LINE_SIZE prompt "Instruction cache line size" - default INSTRUCTION_CACHE_LINE_32B + default ESP32S2_INSTRUCTION_CACHE_LINE_32B help Instruction cache line size to be set on application startup. - config INSTRUCTION_CACHE_LINE_16B + config ESP32S2_INSTRUCTION_CACHE_LINE_16B bool "16 Bytes" - config INSTRUCTION_CACHE_LINE_32B + config ESP32S2_INSTRUCTION_CACHE_LINE_32B bool "32 Bytes" - config INSTRUCTION_CACHE_LINE_64B + config ESP32S2_INSTRUCTION_CACHE_LINE_64B bool "64 Bytes" endchoice - choice DATA_CACHE_SIZE + choice ESP32S2_DATA_CACHE_SIZE prompt "Data cache size" - default DATA_CACHE_8KB + default ESP32S2_DATA_CACHE_8KB help Data cache size to be set on application startup. If you use 8KB data cache rather than 16KB data cache, the other 8KB will be added to the heap. - config DATA_CACHE_0KB - depends on !SPIRAM_SUPPORT + config ESP32S2_DATA_CACHE_0KB + depends on !ESP32S2_SPIRAM_SUPPORT bool "0KB" - config DATA_CACHE_8KB + config ESP32S2_DATA_CACHE_8KB bool "8KB" - config DATA_CACHE_16KB + config ESP32S2_DATA_CACHE_16KB bool "16KB" endchoice - choice DATA_CACHE_ASSOCIATED_WAYS + choice ESP32S2_DATA_CACHE_ASSOCIATED_WAYS prompt "Data cache associated ways" - default DATA_CACHE_8WAYS + default ESP32S2_DATA_CACHE_8WAYS help Data cache associated ways to be set on application startup. - config DATA_CACHE_4WAYS + config ESP32S2_DATA_CACHE_4WAYS bool "4 ways" - config DATA_CACHE_8WAYS + config ESP32S2_DATA_CACHE_8WAYS bool "8 ways" endchoice - choice DATA_CACHE_LINE_SIZE + choice ESP32S2_DATA_CACHE_LINE_SIZE prompt "Data cache line size" - default DATA_CACHE_LINE_32B + default ESP32S2_DATA_CACHE_LINE_32B help Data cache line size to be set on application startup. - config DATA_CACHE_LINE_16B + config ESP32S2_DATA_CACHE_LINE_16B bool "16 Bytes" - config DATA_CACHE_LINE_32B + config ESP32S2_DATA_CACHE_LINE_32B bool "32 Bytes" - config DATA_CACHE_LINE_64B + config ESP32S2_DATA_CACHE_LINE_64B bool "64 Bytes" endchoice - config RODATA_USE_DATA_CACHE - depends on DATA_CACHE_8KB || DATA_CACHE_16KB + config ESP32S2_RODATA_USE_DATA_CACHE + depends on ESP32S2_DATA_CACHE_8KB || ESP32S2_DATA_CACHE_16KB bool "Use data cache rather than instruction cache to access read only data" default "n" help If enabled, CPU will access rodata through data cache, which will reduce the overload of instruction cache, however will increase the overload of data cache. - config ENABLE_INSTRUCTION_CACHE_WRAP + config ESP32S2_INSTRUCTION_CACHE_WRAP bool "Enable instruction cache wrap" default "n" help @@ -119,7 +119,7 @@ menu "ESP32S2-specific" The wrap length equals to INSTRUCTION_CACHE_LINE_SIZE. However, it depends on complex conditions. - config ENABLE_DATA_CACHE_WRAP + config ESP32S2_DATA_CACHE_WRAP bool "Enable data cache wrap" default "n" help @@ -127,9 +127,9 @@ menu "ESP32S2-specific" The wrap length equals to DATA_CACHE_LINE_SIZE. However, it depends on complex conditions. - endmenu + endmenu # Cache config - config SPIRAM_SUPPORT + config ESP32S2_SPIRAM_SUPPORT bool "Support for external, SPI-connected RAM" default "n" help @@ -137,7 +137,7 @@ menu "ESP32S2-specific" main SPI flash chip. menu "SPI RAM config" - depends on SPIRAM_SUPPORT + depends on ESP32S2_SPIRAM_SUPPORT config SPIRAM_BOOT_INIT bool "Initialize SPI RAM when booting the ESP32" @@ -195,21 +195,21 @@ menu "ESP32S2-specific" default 8388608 if SPIRAM_TYPE_ESPPSRAM64 default 0 - config INSTRUCTION_USE_SPIRAM + config SPIRAM_FETCH_INSTRUCTIONS bool "Cache fetch instructions from SPI RAM" default n help If enabled, instruction in flash will be copied into SPIRAM. If you also enable RODATA_USE_SPIRAM option, you can run the instruction when you are erasing or programming the flash. - config RODATA_USE_SPIRAM + config SPIRAM_RODATA bool "Cache load read only data from SPI RAM" default n help If enabled, radata in flash will be copied into SPIRAM. If you also enable INSTRUCTION_USE_SPIRAM option, you can run the instruction when you erasing or programming the flash. - config USE_AHB_DBUS3_ACCESS_SPIRAM + config SPIRAM_USE_AHB_DBUS3 bool "Enable AHB DBUS3 to access SPIRAM" default n help @@ -315,86 +315,30 @@ menu "ESP32S2-specific" endmenu - config MEMMAP_TRACEMEM + config ESP32S2_MEMMAP_TRACEMEM bool default "n" - config MEMMAP_TRACEMEM_TWOBANKS - bool - default "n" - - config ESP32_TRAX + config ESP32S2_TRAX bool "Use TRAX tracing feature" default "n" - select MEMMAP_TRACEMEM + select ESP32S2_MEMMAP_TRACEMEM help - The ESP32 contains a feature which allows you to trace the execution path the processor + The ESP32S2 contains a feature which allows you to trace the execution path the processor has taken through the program. This is stored in a chunk of 32K (16K for single-processor) of memory that can't be used for general purposes anymore. Disable this if you do not know what this is. - config ESP32_TRAX_TWOBANKS - bool "Reserve memory for tracing both pro as well as app cpu execution" - default "n" - depends on ESP32_TRAX && !FREERTOS_UNICORE - select MEMMAP_TRACEMEM_TWOBANKS - help - The ESP32 contains a feature which allows you to trace the execution path the processor - has taken through the program. This is stored in a chunk of 32K (16K for single-processor) - of memory that can't be used for general purposes anymore. Disable this if you do not know - what this is. - - # Memory to reverse for trace, used in linker script - config TRACEMEM_RESERVE_DRAM + # Memory to reverse for trace, used in linker script + config ESP32S2_TRACEMEM_RESERVE_DRAM hex - default 0x8000 if MEMMAP_TRACEMEM && MEMMAP_TRACEMEM_TWOBANKS - default 0x4000 if MEMMAP_TRACEMEM && !MEMMAP_TRACEMEM_TWOBANKS + default 0x4000 if ESP32S2_MEMMAP_TRACEMEM default 0x0 - choice ESP32_COREDUMP_TO_FLASH_OR_UART - prompt "Core dump destination" - default ESP32_ENABLE_COREDUMP_TO_NONE - help - Select place to store core dump: flash, uart or none (to disable core dumps generation). - If core dump is configured to be stored in flash and custom partition table is used add - corresponding entry to your CSV. For examples, please see predefined partition table CSV descriptions - in the components/partition_table directory. - - config ESP32_ENABLE_COREDUMP_TO_FLASH - bool "Flash" - select ESP32_ENABLE_COREDUMP - config ESP32_ENABLE_COREDUMP_TO_UART - bool "UART" - select ESP32_ENABLE_COREDUMP - config ESP32_ENABLE_COREDUMP_TO_NONE - bool "None" - endchoice - - config ESP32_ENABLE_COREDUMP - bool - default F - help - Enables/disable core dump module. - - config ESP32_CORE_DUMP_UART_DELAY - int "Core dump print to UART delay" - depends on ESP32_ENABLE_COREDUMP_TO_UART - default 0 - help - Config delay (in ms) before printing core dump to UART. - Delay can be interrupted by pressing Enter key. - - config ESP32_CORE_DUMP_LOG_LEVEL - int "Core dump module logging level" - depends on ESP32_ENABLE_COREDUMP - default 1 - help - Config core dump module logging level (0-5). - - choice NUMBER_OF_UNIVERSAL_MAC_ADDRESS + choice ESP32S2_UNIVERSAL_MAC_ADDRESSES bool "Number of universally administered (by IEEE) MAC address" - default FOUR_UNIVERSAL_MAC_ADDRESS + default ESP32S2_UNIVERSAL_MAC_ADDRESSES_FOUR help Configure the number of universally administered (by IEEE) MAC addresses. During initialisation, MAC addresses for each network interface are generated or derived from a @@ -411,338 +355,68 @@ menu "ESP32S2-specific" a custom universal MAC address range, the correct setting will depend on the allocation of MAC addresses in this range (either 2 or 4 per device.) - config TWO_UNIVERSAL_MAC_ADDRESS + config ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO bool "Two" - config FOUR_UNIVERSAL_MAC_ADDRESS + config ESP32S2_UNIVERSAL_MAC_ADDRESSES_FOUR bool "Four" endchoice - config NUMBER_OF_UNIVERSAL_MAC_ADDRESS + config ESP32S2_UNIVERSAL_MAC_ADDRESSES int - default 2 if TWO_UNIVERSAL_MAC_ADDRESS - default 4 if FOUR_UNIVERSAL_MAC_ADDRESS + default 2 if ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO + default 4 if ESP32S2_UNIVERSAL_MAC_ADDRESSES_FOUR - config SYSTEM_EVENT_QUEUE_SIZE - int "System event queue size" - default 32 - help - Config system event queue size in different application. - - config SYSTEM_EVENT_TASK_STACK_SIZE - int "Event loop task stack size" - default 2304 - help - Config system event task stack size in different application. - - config MAIN_TASK_STACK_SIZE - int "Main task stack size" - default 3584 - help - Configure the "main task" stack size. This is the stack of the task - which calls app_main(). If app_main() returns then this task is deleted - and its stack memory is freed. - - config IPC_TASK_STACK_SIZE - int "Inter-Processor Call (IPC) task stack size" - default 1024 - range 512 65536 if !ESP32_APPTRACE_ENABLE - range 2048 65536 if ESP32_APPTRACE_ENABLE - help - Configure the IPC tasks stack size. One IPC task runs on each core - (in dual core mode), and allows for cross-core function calls. - - See IPC documentation for more details. - - The default stack size should be enough for most common use cases. - It can be shrunk if you are sure that you do not use any custom - IPC functionality. - - config TIMER_TASK_STACK_SIZE - int "High-resolution timer task stack size" - default 3584 - range 2048 65536 - help - Configure the stack size of esp_timer/ets_timer task. This task is used - to dispatch callbacks of timers created using ets_timer and esp_timer - APIs. If you are seing stack overflow errors in timer task, increase - this value. - - Note that this is not the same as FreeRTOS timer task. To configure - FreeRTOS timer task size, see "FreeRTOS timer task stack size" option - in "FreeRTOS" menu. - - choice NEWLIB_STDOUT_LINE_ENDING - prompt "Line ending for UART output" - default NEWLIB_STDOUT_LINE_ENDING_CRLF - help - This option allows configuring the desired line endings sent to UART - when a newline ('\n', LF) appears on stdout. - Three options are possible: - - CRLF: whenever LF is encountered, prepend it with CR - - LF: no modification is applied, stdout is sent as is - - CR: each occurence of LF is replaced with CR - - This option doesn't affect behavior of the UART driver (drivers/uart.h). - - config NEWLIB_STDOUT_LINE_ENDING_CRLF - bool "CRLF" - config NEWLIB_STDOUT_LINE_ENDING_LF - bool "LF" - config NEWLIB_STDOUT_LINE_ENDING_CR - bool "CR" - endchoice - - choice NEWLIB_STDIN_LINE_ENDING - prompt "Line ending for UART input" - default NEWLIB_STDIN_LINE_ENDING_CR - help - This option allows configuring which input sequence on UART produces - a newline ('\n', LF) on stdin. - Three options are possible: - - CRLF: CRLF is converted to LF - - LF: no modification is applied, input is sent to stdin as is - - CR: each occurence of CR is replaced with LF - - This option doesn't affect behavior of the UART driver (drivers/uart.h). - - config NEWLIB_STDIN_LINE_ENDING_CRLF - bool "CRLF" - config NEWLIB_STDIN_LINE_ENDING_LF - bool "LF" - config NEWLIB_STDIN_LINE_ENDING_CR - bool "CR" - endchoice - - config NEWLIB_NANO_FORMAT - bool "Enable 'nano' formatting options for printf/scanf family" - default n - help - ESP32 ROM contains parts of newlib C library, including printf/scanf family - of functions. These functions have been compiled with so-called "nano" - formatting option. This option doesn't support 64-bit integer formats and C99 - features, such as positional arguments. - - For more details about "nano" formatting option, please see newlib readme file, - search for '--enable-newlib-nano-formatted-io': - https://sourceware.org/newlib/README - - If this option is enabled, build system will use functions available in - ROM, reducing the application binary size. Functions available in ROM run - faster than functions which run from flash. Functions available in ROM can - also run when flash instruction cache is disabled. - - If you need 64-bit integer formatting support or C99 features, keep this - option disabled. - - choice CONSOLE_UART - prompt "UART for console output" - default CONSOLE_UART_DEFAULT - help - Select whether to use UART for console output (through stdout and stderr). - - - Default is to use UART0 on pins GPIO1(TX) and GPIO3(RX). - - If "Custom" is selected, UART0 or UART1 can be chosen, - and any pins can be selected. - - If "None" is selected, there will be no console output on any UART, except - for initial output from ROM bootloader. This output can be further suppressed by - bootstrapping GPIO13 pin to low logic level. - - config CONSOLE_UART_DEFAULT - bool "Default: UART0, TX=GPIO1, RX=GPIO3" - config CONSOLE_UART_CUSTOM - bool "Custom" - config CONSOLE_UART_NONE - bool "None" - endchoice - - choice CONSOLE_UART_NUM - prompt "UART peripheral to use for console output (0-1)" - depends on CONSOLE_UART_CUSTOM - default CONSOLE_UART_CUSTOM_NUM_0 - help - Due of a ROM bug, UART2 is not supported for console output - via ets_printf. - - config CONSOLE_UART_CUSTOM_NUM_0 - bool "UART0" - config CONSOLE_UART_CUSTOM_NUM_1 - bool "UART1" - endchoice - - config CONSOLE_UART_NUM - int - default 0 if CONSOLE_UART_DEFAULT || CONSOLE_UART_NONE - default 0 if CONSOLE_UART_CUSTOM_NUM_0 - default 1 if CONSOLE_UART_CUSTOM_NUM_1 - - config CONSOLE_UART_TX_GPIO - int "UART TX on GPIO#" - depends on CONSOLE_UART_CUSTOM - range 0 33 - default 19 - - config CONSOLE_UART_RX_GPIO - int "UART RX on GPIO#" - depends on CONSOLE_UART_CUSTOM - range 0 39 - default 21 - - config CONSOLE_UART_BAUDRATE - int "UART console baud rate" - depends on !CONSOLE_UART_NONE - default 115200 - range 1200 4000000 - - config ULP_COPROC_ENABLED - bool "Enable Ultra Low Power (ULP) Coprocessor" - default "n" - help - Set to 'y' if you plan to load a firmware for the coprocessor. - - If this option is enabled, further coprocessor configuration will appear in the Components menu. - - config ULP_COPROC_RESERVE_MEM - int - prompt "RTC slow memory reserved for coprocessor" if ULP_COPROC_ENABLED - default 512 if ULP_COPROC_ENABLED - range 32 8192 if ULP_COPROC_ENABLED - default 0 if !ULP_COPROC_ENABLED - range 0 0 if !ULP_COPROC_ENABLED - help - Bytes of memory to reserve for ULP coprocessor firmware & data. - - Data is reserved at the beginning of RTC slow memory. - - choice ESP32_PANIC + choice ESP32S2__PANIC prompt "Panic handler behaviour" - default ESP32_PANIC_PRINT_REBOOT + default ESP32S2_PANIC_PRINT_REBOOT help If FreeRTOS detects unexpected behaviour or an unhandled exception, the panic handler is invoked. Configure the panic handlers action here. - config ESP32_PANIC_PRINT_HALT + config ESP32S2_PANIC_PRINT_HALT bool "Print registers and halt" help Outputs the relevant registers over the serial port and halt the processor. Needs a manual reset to restart. - config ESP32_PANIC_PRINT_REBOOT + config ESP32S2_PANIC_PRINT_REBOOT bool "Print registers and reboot" help Outputs the relevant registers over the serial port and immediately reset the processor. - config ESP32_PANIC_SILENT_REBOOT + config ESP32S2_PANIC_SILENT_REBOOT bool "Silent reboot" help Just resets the processor without outputting anything - config ESP32_PANIC_GDBSTUB + config ESP32S2_PANIC_GDBSTUB bool "Invoke GDBStub" help Invoke gdbstub on the serial port, allowing for gdb to attach to it to do a postmortem of the crash. endchoice - config ESP32_DEBUG_OCDAWARE + config ESP32S2_DEBUG_OCDAWARE bool "Make exception and panic handlers JTAG/OCD aware" default y help The FreeRTOS panic and unhandled exception handers can detect a JTAG OCD debugger and instead of panicking, have the debugger stop on the offending instruction. - config ESP32_DEBUG_STUBS_ENABLE + config ESP32S2_DEBUG_STUBS_ENABLE bool "OpenOCD debug stubs" default OPTIMIZATION_LEVEL_DEBUG - depends on !ESP32_TRAX + depends on !ESP32S2_TRAX help Debug stubs are used by OpenOCD to execute pre-compiled onboard code which does some useful debugging, e.g. GCOV data dump. - config INT_WDT - bool "Interrupt watchdog" - default y - help - This watchdog timer can detect if the FreeRTOS tick interrupt has not been called for a certain time, - either because a task turned off interrupts and did not turn them on for a long time, or because an - interrupt handler did not return. It will try to invoke the panic handler first and failing that - reset the SoC. - - config INT_WDT_TIMEOUT_MS - int "Interrupt watchdog timeout (ms)" - depends on INT_WDT - default 300 if !SPIRAM_SUPPORT - default 800 if SPIRAM_SUPPORT - range 10 10000 - help - The timeout of the watchdog, in miliseconds. Make this higher than the FreeRTOS tick rate. - - config INT_WDT_CHECK_CPU1 - bool "Also watch CPU1 tick interrupt" - depends on INT_WDT && !FREERTOS_UNICORE - default y - help - Also detect if interrupts on CPU 1 are disabled for too long. - - config TASK_WDT - bool "Initialize Task Watchdog Timer on startup" - default y - help - The Task Watchdog Timer can be used to make sure individual tasks are still - running. Enabling this option will cause the Task Watchdog Timer to be - initialized automatically at startup. The Task Watchdog timer can be - initialized after startup as well (see Task Watchdog Timer API Reference) - - config TASK_WDT_PANIC - bool "Invoke panic handler on Task Watchdog timeout" - depends on TASK_WDT - default n - help - If this option is enabled, the Task Watchdog Timer will be configured to - trigger the panic handler when it times out. This can also be configured - at run time (see Task Watchdog Timer API Reference) - - config TASK_WDT_TIMEOUT_S - int "Task Watchdog timeout period (seconds)" - depends on TASK_WDT - range 1 60 - default 5 - help - Timeout period configuration for the Task Watchdog Timer in seconds. - This is also configurable at run time (see Task Watchdog Timer API Reference) - - config TASK_WDT_CHECK_IDLE_TASK_CPU0 - bool "Watch CPU0 Idle Task" - depends on TASK_WDT - default y - help - If this option is enabled, the Task Watchdog Timer will watch the CPU0 - Idle Task. Having the Task Watchdog watch the Idle Task allows for detection - of CPU starvation as the Idle Task not being called is usually a symptom of - CPU starvation. Starvation of the Idle Task is detrimental as FreeRTOS household - tasks depend on the Idle Task getting some runtime every now and then. - - config TASK_WDT_CHECK_IDLE_TASK_CPU1 - bool "Watch CPU1 Idle Task" - depends on TASK_WDT && !FREERTOS_UNICORE - default y - help - If this option is enabled, the Task Wtachdog Timer will wach the CPU1 - Idle Task. - - config BROWNOUT_DET - #The brownout detector code is disabled (by making it depend on a nonexisting symbol) because the current - #revision of ESP32 silicon has a bug in the brown-out detector, rendering it unusable for resetting the CPU. + config ESP32S2_BROWNOUT_DET bool "Hardware brownout detect & reset" default y help - The ESP32 has a built-in brownout detector which can detect if the voltage is lower than + The ESP32S2 has a built-in brownout detector which can detect if the voltage is lower than a specific value. If this happens, it will reset the chip in order to prevent unintended behaviour. @@ -757,43 +431,43 @@ menu "ESP32S2-specific" #The voltage levels here are estimates, more work needs to be done to figure out the exact voltages #of the brownout threshold levels. - config BROWNOUT_DET_LVL_SEL_0 + config ESP32S2_BROWNOUT_DET_LVL_SEL_0 bool "2.43V +/- 0.05" - config BROWNOUT_DET_LVL_SEL_1 + config ESP32S2_BROWNOUT_DET_LVL_SEL_1 bool "2.48V +/- 0.05" - config BROWNOUT_DET_LVL_SEL_2 + config ESP32S2_BROWNOUT_DET_LVL_SEL_2 bool "2.58V +/- 0.05" - config BROWNOUT_DET_LVL_SEL_3 + config ESP32S2_BROWNOUT_DET_LVL_SEL_3 bool "2.62V +/- 0.05" - config BROWNOUT_DET_LVL_SEL_4 + config ESP32S2_BROWNOUT_DET_LVL_SEL_4 bool "2.67V +/- 0.05" - config BROWNOUT_DET_LVL_SEL_5 + config ESP32S2_BROWNOUT_DET_LVL_SEL_5 bool "2.70V +/- 0.05" - config BROWNOUT_DET_LVL_SEL_6 + config ESP32S2_BROWNOUT_DET_LVL_SEL_6 bool "2.77V +/- 0.05" - config BROWNOUT_DET_LVL_SEL_7 + config ESP32S2_BROWNOUT_DET_LVL_SEL_7 bool "2.80V +/- 0.05" endchoice - config BROWNOUT_DET_LVL + config ESP32S2_BROWNOUT_DET_LVL int - default 0 if BROWNOUT_DET_LVL_SEL_0 - default 1 if BROWNOUT_DET_LVL_SEL_1 - default 2 if BROWNOUT_DET_LVL_SEL_2 - default 3 if BROWNOUT_DET_LVL_SEL_3 - default 4 if BROWNOUT_DET_LVL_SEL_4 - default 5 if BROWNOUT_DET_LVL_SEL_5 - default 6 if BROWNOUT_DET_LVL_SEL_6 - default 7 if BROWNOUT_DET_LVL_SEL_7 + default 0 if ESP32S2_BROWNOUT_DET_LVL_SEL_0 + default 1 if ESP32S2_BROWNOUT_DET_LVL_SEL_1 + default 2 if ESP32S2_BROWNOUT_DET_LVL_SEL_2 + default 3 if ESP32S2_BROWNOUT_DET_LVL_SEL_3 + default 4 if ESP32S2_BROWNOUT_DET_LVL_SEL_4 + default 5 if ESP32S2_BROWNOUT_DET_LVL_SEL_5 + default 6 if ESP32S2_BROWNOUT_DET_LVL_SEL_6 + default 7 if ESP32S2_BROWNOUT_DET_LVL_SEL_7 # Note about the use of "FRC1" name: currently FRC1 timer is not used for # high resolution timekeeping anymore. Instead the esp_timer API, implemented # using FRC2 timer, is used. # FRC1 name in the option name is kept for compatibility. - choice ESP32_TIME_SYSCALL + choice ESP32S2__TIME_SYSCALL prompt "Timers used for gettimeofday function" - default ESP32_TIME_SYSCALL_USE_RTC_FRC1 + default ESP32S2_TIME_SYSCALL_USE_RTC_FRC1 help This setting defines which hardware timers are used to implement 'gettimeofday' and 'time' functions in C library. @@ -813,32 +487,32 @@ menu "ESP32S2-specific" - When RTC is used for timekeeping, two RTC_STORE registers are used to keep time in deep sleep mode. - config ESP32_TIME_SYSCALL_USE_RTC_FRC1 + config ESP32S2_TIME_SYSCALL_USE_RTC_FRC1 bool "RTC and high-resolution timer" - config ESP32_TIME_SYSCALL_USE_RTC + config ESP32S2_TIME_SYSCALL_USE_RTC bool "RTC" - config ESP32_TIME_SYSCALL_USE_FRC1 + config ESP32S2_TIME_SYSCALL_USE_FRC1 bool "High-resolution timer" - config ESP32_TIME_SYSCALL_USE_NONE + config ESP32S2_TIME_SYSCALL_USE_NONE bool "None" endchoice - choice ESP32_RTC_CLOCK_SOURCE + choice ESP32S2_RTC_CLK_SRC prompt "RTC clock source" - default ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC + default ESP32S2_RTC_CLK_SRC_INT_RC help Choose which clock is used as RTC clock source. - config ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC + config ESP32S2_RTC_CLK_SRC_INT_RC bool "Internal 150kHz RC oscillator" - config ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL + config ESP32S2_RTC_CLK_SRC_EXT_CRYS bool "External 32kHz crystal" endchoice - config ESP32_RTC_CLK_CAL_CYCLES + config ESP32S2__RTC_CLK_CAL_CYCLES int "Number of cycles for RTC_SLOW_CLK calibration" - default 3000 if ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL - default 1024 if ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC + default 3000 if ESP32S2_RTC_CLK_SRC_EXT_CRYS + default 1024 if ESP32S2_RTC_CLK_SRC_INT_RC range 0 125000 help When the startup code initializes RTC_SLOW_CLK, it can perform @@ -856,44 +530,9 @@ menu "ESP32S2-specific" In case more value will help improve the definition of the launch of the crystal. If the crystal could not start, it will be switched to internal RC. - config ESP32_RTC_XTAL_BOOTSTRAP_CYCLES - int "Bootstrap cycles for external 32kHz crystal" - depends on ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL - default 5 - range 0 32768 - help - To reduce the startup time of an external RTC crystal, - we bootstrap it with a 32kHz square wave for a fixed number of cycles. - Setting 0 will disable bootstrapping (if disabled, the crystal may take - longer to start up or fail to oscillate under some conditions). - - If this value is too high, a faulty crystal may initially start and then fail. - If this value is too low, an otherwise good crystal may not start. - - To accurately determine if the crystal has started, - set a larger "Number of cycles for RTC_SLOW_CLK calibration" (about 3000). - - config ESP32_DEEP_SLEEP_WAKEUP_DELAY - int "Extra delay in deep sleep wake stub (in us)" - default 2000 - range 0 5000 - help - When ESP32 exits deep sleep, the CPU and the flash chip are powered on - at the same time. CPU will run deep sleep stub first, and then - proceed to load code from flash. Some flash chips need sufficient - time to pass between power on and first read operation. By default, - without any extra delay, this time is approximately 900us, although - some flash chip types need more than that. - - By default extra delay is set to 2000us. When optimizing startup time - for applications which require it, this value may be reduced. - - If you are seeing "flash read err, 1000" message printed to the - console after deep sleep reset, try increasing this value. - - choice ESP32_XTAL_FREQ_SEL + choice ESP32S2_XTAL_FREQ_SEL prompt "Main XTAL frequency" - default ESP32_XTAL_FREQ_40 + default ESP32S2_XTAL_FREQ_40 help ESP32 currently supports the following XTAL frequencies: @@ -906,22 +545,22 @@ menu "ESP32S2-specific" to use automatic XTAL frequency detection in applications which need to work at high ambient temperatures and use high-temperature qualified chips and modules. - config ESP32_XTAL_FREQ_40 + config ESP32S2_XTAL_FREQ_40 bool "40 MHz" - config ESP32_XTAL_FREQ_26 + config ESP32S2_XTAL_FREQ_26 bool "26 MHz" - config ESP32_XTAL_FREQ_AUTO + config ESP32S2_XTAL_FREQ_AUTO bool "Autodetect" endchoice # Keep these values in sync with rtc_xtal_freq_t enum in soc/rtc.h - config ESP32_XTAL_FREQ + config ESP32S2_XTAL_FREQ int - default 0 if ESP32_XTAL_FREQ_AUTO - default 40 if ESP32_XTAL_FREQ_40 - default 26 if ESP32_XTAL_FREQ_26 + default 0 if ESP32S2_XTAL_FREQ_AUTO + default 40 if ESP32S2_XTAL_FREQ_40 + default 26 if ESP32S2_XTAL_FREQ_26 - config DISABLE_BASIC_ROM_CONSOLE + config ESP32S2_DISABLE_BASIC_ROM_CONSOLE bool "Permanently disable BASIC ROM Console" default n help @@ -933,7 +572,7 @@ menu "ESP32S2-specific" (Enabling secure boot also disables the BASIC ROM Console by default.) - config NO_BLOBS + config ESP32S2_NO_BLOBS bool "No Binary Blobs" depends on !BT_ENABLED default n @@ -941,43 +580,6 @@ menu "ESP32S2-specific" If enabled, this disables the linking of binary libraries in the application build. Note that after enabling this Wi-Fi/Bluetooth will not work. - config ESP_TIMER_PROFILING - bool "Enable esp_timer profiling features" - default n - help - If enabled, esp_timer_dump will dump information such as number of times - the timer was started, number of times the timer has triggered, and the - total time it took for the callback to run. - This option has some effect on timer performance and the amount of memory - used for timer storage, and should only be used for debugging/testing - purposes. - - config COMPATIBLE_PRE_V2_1_BOOTLOADERS - bool "App compatible with bootloaders before IDF v2.1" - default n - help - Bootloaders before IDF v2.1 did less initialisation of the - system clock. This setting needs to be enabled to build an app - which can be booted by these older bootloaders. - - If this setting is enabled, the app can be booted by any bootloader - from IDF v1.0 up to the current version. - - If this setting is disabled, the app can only be booted by bootloaders - from IDF v2.1 or newer. - - Enabling this setting adds approximately 1KB to the app's IRAM usage. - - config ESP_ERR_TO_NAME_LOOKUP - bool "Enable lookup of error code strings" - default "y" - help - Functions esp_err_to_name() and esp_err_to_name_r() return string - representations of error codes from a pre-generated lookup table. - This option can be used to turn off the use of the look-up table in - order to save memory but this comes at the price of sacrificing - distinguishable (meaningful) output string representations. - endmenu # ESP32S2-Specific menu "Power Management" @@ -998,14 +600,14 @@ menu "Power Management" default n help If enabled, startup code configures dynamic frequency scaling. - Max CPU frequency is set to CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ setting, + Max CPU frequency is set to CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ setting, min frequency is set to XTAL frequency. If disabled, DFS will not be active until the application configures it using esp_pm_configure function. config PM_USE_RTC_TIMER_REF bool "Use RTC timer to prevent time drift (EXPERIMENTAL)" - depends on PM_ENABLE && (ESP32_TIME_SYSCALL_USE_RTC || ESP32_TIME_SYSCALL_USE_RTC_FRC1) + depends on PM_ENABLE && (ESP32S2_TIME_SYSCALL_USE_RTC || ESP32S2_TIME_SYSCALL_USE_RTC_FRC1) default n help When APB clock frequency changes, high-resolution timer (esp_timer) diff --git a/components/esp32s2beta/brownout.c b/components/esp32s2beta/brownout.c index a48dd4b8e..9d46e177e 100644 --- a/components/esp32s2beta/brownout.c +++ b/components/esp32s2beta/brownout.c @@ -25,11 +25,11 @@ #include "driver/rtc_cntl.h" #include "freertos/FreeRTOS.h" -#ifdef CONFIG_BROWNOUT_DET_LVL -#define BROWNOUT_DET_LVL CONFIG_BROWNOUT_DET_LVL +#ifdef CONFIG_ESP32S2_BROWNOUT_DET_LVL +#define BROWNOUT_DET_LVL CONFIG_ESP32S2_BROWNOUT_DET_LVL #else #define BROWNOUT_DET_LVL 0 -#endif //CONFIG_BROWNOUT_DET_LVL +#endif //CONFIG_ESP32S2_BROWNOUT_DET_LVL static void rtc_brownout_isr_handler() { diff --git a/components/esp32s2beta/clk.c b/components/esp32s2beta/clk.c index 0966a4630..eecbe0ddf 100644 --- a/components/esp32s2beta/clk.c +++ b/components/esp32s2beta/clk.c @@ -39,7 +39,7 @@ * Larger values increase startup delay. Smaller values may cause false positive * detection (i.e. oscillator runs for a few cycles and then stops). */ -#define SLOW_CLK_CAL_CYCLES CONFIG_ESP32_RTC_CLK_CAL_CYCLES +#define SLOW_CLK_CAL_CYCLES CONFIG_ESP32S2_RTC_CLK_CAL_CYCLES #define MHZ (1000000) @@ -59,30 +59,17 @@ void esp_clk_init(void) rtc_config_t cfg = RTC_CONFIG_DEFAULT(); rtc_init(cfg); -#ifdef CONFIG_COMPATIBLE_PRE_V2_1_BOOTLOADERS - /* Check the bootloader set the XTAL frequency. - - Bootloaders pre-v2.1 don't do this. - */ - rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get(); - if (xtal_freq == RTC_XTAL_FREQ_AUTO) { - ESP_EARLY_LOGW(TAG, "RTC domain not initialised by bootloader"); - bootloader_clock_configure(); - } -#else - /* If this assertion fails, either upgrade the bootloader or enable CONFIG_COMPATIBLE_PRE_V2_1_BOOTLOADERS */ assert(rtc_clk_xtal_freq_get() != RTC_XTAL_FREQ_AUTO); -#endif rtc_clk_fast_freq_set(RTC_FAST_FREQ_8M); -#ifdef CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL +#ifdef CONFIG_ESP32S2_RTC_CLK_SRC_EXT_CRYS select_rtc_slow_clk(RTC_SLOW_FREQ_32K_XTAL); #else select_rtc_slow_clk(RTC_SLOW_FREQ_RTC); #endif - uint32_t freq_mhz = CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ; + uint32_t freq_mhz = CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ; rtc_cpu_freq_t freq = RTC_CPU_FREQ_80M; switch(freq_mhz) { case 240: @@ -108,7 +95,7 @@ void esp_clk_init(void) rtc_clk_cpu_freq_set(freq); // Re calculate the ccount to make time calculation correct. - uint32_t freq_after = CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ; + uint32_t freq_after = CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ; XTHAL_SET_CCOUNT( XTHAL_GET_CCOUNT() * freq_after / freq_before ); } diff --git a/components/esp32s2beta/cpu_start.c b/components/esp32s2beta/cpu_start.c index ff787b4f9..53b61cdda 100644 --- a/components/esp32s2beta/cpu_start.c +++ b/components/esp32s2beta/cpu_start.c @@ -156,14 +156,14 @@ extern void esp_config_instruction_cache_mode(void); esp_config_instruction_cache_mode(); /* copy MMU table from ICache to DCache, so we can use DCache to access rodata later. */ -#if CONFIG_RODATA_USE_DATA_CACHE +#if CONFIG_ESP32S2_RODATA_USE_DATA_CACHE MMU_Drom0_I2D_Copy(); #endif /* If we need use SPIRAM, we should use data cache, or if we want to access rodata, we also should use data cache. Configure the mode of data : cache size, cache associated ways, cache line size. Enable data cache, so if we don't use SPIRAM, it just works. */ -#if CONFIG_SPIRAM_BOOT_INIT || CONFIG_RODATA_USE_DATA_CACHE +#if CONFIG_SPIRAM_BOOT_INIT || CONFIG_ESP32S2_RODATA_USE_DATA_CACHE extern void esp_config_data_cache_mode(void); esp_config_data_cache_mode(); Cache_Enable_DCache(0); @@ -186,7 +186,7 @@ extern void esp_config_data_cache_mode(void); #endif /* Start to use data cache to access rodata. */ -#if CONFIG_RODATA_USE_DATA_CACHE +#if CONFIG_ESP32S2_RODATA_USE_DATA_CACHE extern void esp_switch_rodata_to_dcache(void); esp_switch_rodata_to_dcache(); #endif @@ -229,21 +229,21 @@ extern void esp_switch_rodata_to_dcache(void); } #endif -#if CONFIG_INSTRUCTION_USE_SPIRAM +#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS extern void esp_spiram_enable_instruction_access(void); esp_spiram_enable_instruction_access(); #endif -#if CONFIG_RODATA_USE_SPIRAM +#if SPIRAM_RODATA extern void esp_spiram_enable_rodata_access(void); esp_spiram_enable_rodata_access(); #endif -#if CONFIG_ENABLE_INSTRUCTION_CACHE_WRAP || CONFIG_ENABLE_DATA_CACHE_WRAP +#if CONFIG_ESP32S2_INSTRUCTION_CACHE_WRAP || CONFIG_ESP32S2_DATA_CACHE_WRAP uint32_t icache_wrap_enable = 0,dcache_wrap_enable = 0; -#if CONFIG_ENABLE_INSTRUCTION_CACHE_WRAP +#if CONFIG_ESP32S2_INSTRUCTION_CACHE_WRAP icache_wrap_enable = 1; #endif -#if CONFIG_ENABLE_DATA_CACHE_WRAP +#if CONFIG_ESP32S2_DATA_CACHE_WRAP dcache_wrap_enable = 1; #endif extern void esp_enable_cache_wrap(uint32_t icache_wrap_enable, uint32_t dcache_wrap_enable); @@ -334,12 +334,8 @@ void start_cpu0_default(void) } //Enable trace memory and immediately start trace. -#if CONFIG_ESP32_TRAX -#if CONFIG_ESP32_TRAX_TWOBANKS - trax_enable(TRAX_ENA_PRO_APP); -#else +#if CONFIG_ESP32S2_TRAX trax_enable(TRAX_ENA_PRO); -#endif trax_start_trace(TRAX_DOWNCOUNT_WORDS); #endif esp_clk_init(); @@ -357,10 +353,10 @@ void start_cpu0_default(void) uart_div_modify(CONFIG_CONSOLE_UART_NUM, (uart_clk_freq << 4) / CONFIG_CONSOLE_UART_BAUDRATE); #endif // CONFIG_CONSOLE_UART_NONE -#if CONFIG_BROWNOUT_DET +#if CONFIG_ESP32S2_BROWNOUT_DET esp_brownout_init(); #endif -#if CONFIG_DISABLE_BASIC_ROM_CONSOLE +#if CONFIG_ESP32S2_DISABLE_BASIC_ROM_CONSOLE esp_efuse_disable_basic_rom_console(); #endif rtc_gpio_force_hold_dis_all(); @@ -385,14 +381,14 @@ void start_cpu0_default(void) #if CONFIG_SYSVIEW_ENABLE SEGGER_SYSVIEW_Conf(); #endif -#if CONFIG_ESP32_DEBUG_STUBS_ENABLE +#if CONFIG_ESP32S2_DEBUG_STUBS_ENABLE esp_dbg_stubs_init(); #endif err = esp_pthread_init(); assert(err == ESP_OK && "Failed to init pthread module!"); do_global_ctors(); -#if CONFIG_INT_WDT +#if CONFIG_ESP_INT_WDT //esp_int_wdt_init(); //Initialize the interrupt watch dog for CPU0. //esp_int_wdt_cpu_init(); @@ -409,7 +405,7 @@ void start_cpu0_default(void) esp_pm_impl_init(); #ifdef CONFIG_PM_DFS_INIT_AUTO rtc_cpu_freq_t max_freq; - rtc_clk_cpu_freq_from_mhz(CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ, &max_freq); + rtc_clk_cpu_freq_from_mhz(CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ, &max_freq); esp_pm_config_esp32_t cfg = { .max_cpu_freq = max_freq, .min_cpu_freq = RTC_CPU_FREQ_XTAL @@ -464,13 +460,13 @@ void start_cpu1_default(void) #ifdef CONFIG_COMPILER_CXX_EXCEPTIONS size_t __cxx_eh_arena_size_get() { - return CONFIG_CXX_EXCEPTIONS_EMG_POOL_SIZE; + return CONFIG_COMPILER_CXX_EXCEPTIONS_EMG_POOL_SIZE; } #endif static void do_global_ctors(void) { -#ifdef CONFIG_CXX_EXCEPTIONS +#ifdef CONFIG_COMPILER_CXX_EXCEPTIONS static struct object ob; __register_frame_info( __eh_frame, &ob ); #endif @@ -496,26 +492,19 @@ static void main_task(void* args) heap_caps_enable_nonos_stack_heaps(); //Initialize task wdt if configured to do so -#ifdef CONFIG_TASK_WDT_PANIC - //ESP_ERROR_CHECK(esp_task_wdt_init(CONFIG_TASK_WDT_TIMEOUT_S, true)) -#elif CONFIG_TASK_WDT - //ESP_ERROR_CHECK(esp_task_wdt_init(CONFIG_TASK_WDT_TIMEOUT_S, false)) +#ifdef CONFIG_ESP_TASK_WDT_PANIC + //ESP_ERROR_CHECK(esp_task_wdt_init(CONFIG_ESP_TASK_WDT_TIMEOUT_S, true)) +#elif CONFIG_ESP_TASK_WDT + //ESP_ERROR_CHECK(esp_task_wdt_init(CONFIG_ESP_TASK_WDT_TIMEOUT_S, false)) #endif //Add IDLE 0 to task wdt -#if 0 -#ifdef CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0 +#if 0 // TODO: re-enable task WDT +#ifdef CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0 TaskHandle_t idle_0 = xTaskGetIdleTaskHandleForCPU(0); if(idle_0 != NULL){ ESP_ERROR_CHECK(esp_task_wdt_add(idle_0)) } -#endif - //Add IDLE 1 to task wdt -#ifdef CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1 - TaskHandle_t idle_1 = xTaskGetIdleTaskHandleForCPU(1); - if(idle_1 != NULL){ - ESP_ERROR_CHECK(esp_task_wdt_add(idle_1)) - } #endif #endif diff --git a/components/esp32s2beta/int_wdt.c b/components/esp32s2beta/int_wdt.c index 34a10d66c..e1c13300e 100644 --- a/components/esp32s2beta/int_wdt.c +++ b/components/esp32s2beta/int_wdt.c @@ -32,14 +32,14 @@ #include "driver/periph_ctrl.h" #include "esp_int_wdt.h" -#if CONFIG_INT_WDT +#if CONFIG_ESP_INT_WDT #define WDT_INT_NUM 24 //Take care: the tick hook can also be called before esp_int_wdt_init() is called. -#if CONFIG_INT_WDT_CHECK_CPU1 +#if CONFIG_ESP_INT_WDT_CHECK_CPU1 //Not static; the ISR assembly checks this. bool int_wdt_app_cpu_ticked=false; @@ -50,8 +50,8 @@ static void IRAM_ATTR tick_hook(void) { //Only feed wdt if app cpu also ticked. if (int_wdt_app_cpu_ticked) { TIMERG1.wdt_wprotect=TIMG_WDT_WKEY_VALUE; - TIMERG1.wdt_config2=CONFIG_INT_WDT_TIMEOUT_MS*2; //Set timeout before interrupt - TIMERG1.wdt_config3=CONFIG_INT_WDT_TIMEOUT_MS*4; //Set timeout before reset + TIMERG1.wdt_config2=CONFIG_ESP_INT_WDT_TIMEOUT_MS*2; //Set timeout before interrupt + TIMERG1.wdt_config3=CONFIG_ESP_INT_WDT_TIMEOUT_MS*4; //Set timeout before reset TIMERG1.wdt_feed=1; TIMERG1.wdt_wprotect=0; int_wdt_app_cpu_ticked=false; @@ -62,8 +62,8 @@ static void IRAM_ATTR tick_hook(void) { static void IRAM_ATTR tick_hook(void) { if (xPortGetCoreID()!=0) return; TIMERG1.wdt_wprotect=TIMG_WDT_WKEY_VALUE; - TIMERG1.wdt_config2=CONFIG_INT_WDT_TIMEOUT_MS*2; //Set timeout before interrupt - TIMERG1.wdt_config3=CONFIG_INT_WDT_TIMEOUT_MS*4; //Set timeout before reset + TIMERG1.wdt_config2=CONFIG_ESP_INT_WDT_TIMEOUT_MS*2; //Set timeout before interrupt + TIMERG1.wdt_config3=CONFIG_ESP_INT_WDT_TIMEOUT_MS*4; //Set timeout before reset TIMERG1.wdt_feed=1; TIMERG1.wdt_wprotect=0; } diff --git a/components/esp32s2beta/panic.c b/components/esp32s2beta/panic.c index 3109faf11..7b0d3a86f 100644 --- a/components/esp32s2beta/panic.c +++ b/components/esp32s2beta/panic.c @@ -62,7 +62,7 @@ Note: The linker script will put everything in this file in IRAM/DRAM, so it also works with flash cache disabled. */ -#if !CONFIG_ESP32_PANIC_SILENT_REBOOT +#if !CONFIG_ESP32S2_PANIC_SILENT_REBOOT //printf may be broken, so we fix our own printing fns... static void panicPutChar(char c) { @@ -145,7 +145,7 @@ static __attribute__((noreturn)) inline void invoke_abort() void abort() { -#if !CONFIG_ESP32_PANIC_SILENT_REBOOT +#if !CONFIG_ESP32S2_PANIC_SILENT_REBOOT ets_printf("abort() was called at PC 0x%08x on core %d\r\n", (intptr_t)__builtin_return_address(0) - 3, xPortGetCoreID()); #endif invoke_abort(); @@ -557,7 +557,7 @@ static __attribute__((noreturn)) void commonErrorHandler(XtExcFrame *frame) reconfigureAllWdts(); #endif -#if CONFIG_ESP32_PANIC_GDBSTUB +#if CONFIG_ESP32S2_PANIC_GDBSTUB disableAllWdts(); esp_panic_wdt_stop(); panicPutStr("Entering gdb stub now.\r\n"); @@ -593,8 +593,8 @@ static __attribute__((noreturn)) void commonErrorHandler(XtExcFrame *frame) disableAllWdts(); panicPutStr("CPU halted.\r\n"); while (1); -#endif /* CONFIG_ESP32_PANIC_PRINT_REBOOT || CONFIG_ESP32_PANIC_SILENT_REBOOT */ -#endif /* CONFIG_ESP32_PANIC_GDBSTUB */ +#endif /* CONFIG_ESP32S2_PANIC_PRINT_REBOOT || CONFIG_ESP32S2_PANIC_SILENT_REBOOT */ +#endif /* CONFIG_ESP32S2_PANIC_GDBSTUB */ } diff --git a/components/esp32s2beta/pm_esp32s2beta.c b/components/esp32s2beta/pm_esp32s2beta.c index 3b14d1a41..3646e24ff 100644 --- a/components/esp32s2beta/pm_esp32s2beta.c +++ b/components/esp32s2beta/pm_esp32s2beta.c @@ -582,7 +582,7 @@ void esp_pm_impl_init() * This will be modified later by a call to esp_pm_configure. */ rtc_cpu_freq_t default_freq; - if (!rtc_clk_cpu_freq_from_mhz(CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ, &default_freq)) { + if (!rtc_clk_cpu_freq_from_mhz(CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ, &default_freq)) { assert(false && "unsupported frequency"); } for (size_t i = 0; i < PM_MODE_COUNT; ++i) { diff --git a/components/esp32s2beta/sleep_modes.c b/components/esp32s2beta/sleep_modes.c index 7fd84d918..7bc6835f6 100644 --- a/components/esp32s2beta/sleep_modes.c +++ b/components/esp32s2beta/sleep_modes.c @@ -47,13 +47,13 @@ // Extra time it takes to enter and exit light sleep and deep sleep // For deep sleep, this is until the wake stub runs (not the app). -#ifdef CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL -#define LIGHT_SLEEP_TIME_OVERHEAD_US (650 + 30 * 240 / CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ) -#define DEEP_SLEEP_TIME_OVERHEAD_US (650 + 100 * 240 / CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ) +#ifdef CONFIG_ESP32S2_RTC_CLK_SRC_EXT_CRYS +#define LIGHT_SLEEP_TIME_OVERHEAD_US (650 + 30 * 240 / CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ) +#define DEEP_SLEEP_TIME_OVERHEAD_US (650 + 100 * 240 / CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ) #else -#define LIGHT_SLEEP_TIME_OVERHEAD_US (250 + 30 * 240 / CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ) -#define DEEP_SLEEP_TIME_OVERHEAD_US (250 + 100 * 240 / CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ) -#endif // CONFIG_ESP32_RTC_CLOCK_SOURCE +#define LIGHT_SLEEP_TIME_OVERHEAD_US (250 + 30 * 240 / CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ) +#define DEEP_SLEEP_TIME_OVERHEAD_US (250 + 100 * 240 / CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ) +#endif // CONFIG_ESP32S2_RTC_CLK_SRC_EXT_CRYS // Minimal amount of time we can sleep for #define LIGHT_SLEEP_MIN_TIME_US 200 @@ -123,15 +123,6 @@ void RTC_IRAM_ATTR esp_default_wake_deep_sleep(void) { /* Clear MMU for CPU 0 */ _DPORT_REG_SET_BIT(DPORT_PRO_CACHE_IA_INT_EN_REG, DPORT_PRO_CACHE_INT_CLR); _DPORT_REG_SET_BIT(DPORT_PRO_CACHE_IA_INT_EN_REG, DPORT_PRO_CACHE_DBG_EN); - -#if CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY > 0 - // ROM code has not started yet, so we need to set delay factor - // used by ets_delay_us first. - ets_update_cpu_frequency(ets_get_xtal_freq() / 1000000); - // This delay is configured in menuconfig, it can be used to give - // the flash chip some time to become ready. - ets_delay_us(CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY); -#endif } void __attribute__((weak, alias("esp_default_wake_deep_sleep"))) esp_wake_deep_sleep(void); @@ -299,10 +290,9 @@ esp_err_t esp_light_sleep_start() // Decide if VDD_SDIO needs to be powered down; // If it needs to be powered down, adjust sleep time. - const uint32_t flash_enable_time_us = VDD_SDIO_POWERUP_TO_FLASH_READ_US - + CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY; + const uint32_t flash_enable_time_us = VDD_SDIO_POWERUP_TO_FLASH_READ_US; -#ifndef CONFIG_SPIRAM_SUPPORT +#ifndef CONFIG_ESP32S2_SPIRAM_SUPPORT const uint32_t vddsdio_pd_sleep_duration = MAX(FLASH_PD_MIN_SLEEP_TIME_US, flash_enable_time_us + LIGHT_SLEEP_TIME_OVERHEAD_US + LIGHT_SLEEP_MIN_TIME_US); @@ -310,7 +300,7 @@ esp_err_t esp_light_sleep_start() pd_flags |= RTC_SLEEP_PD_VDDSDIO; s_config.sleep_time_adjustment += flash_enable_time_us; } -#endif //CONFIG_SPIRAM_SUPPORT +#endif //CONFIG_ESP32S2_SPIRAM_SUPPORT rtc_vddsdio_config_t vddsdio_config = rtc_vddsdio_get_config(); @@ -370,11 +360,6 @@ esp_err_t esp_sleep_disable_wakeup_source(esp_sleep_source_t source) else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_TOUCHPAD, RTC_TOUCH_TRIG_EN)) { s_config.wakeup_triggers &= ~RTC_TOUCH_TRIG_EN; } -#ifdef CONFIG_ULP_COPROC_ENABLED - else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_ULP, RTC_ULP_TRIG_EN)) { - s_config.wakeup_triggers &= ~RTC_ULP_TRIG_EN; - } -#endif else { ESP_LOGE(TAG, "Incorrect wakeup source (%d) to disable.", (int) source); return ESP_ERR_INVALID_STATE; @@ -384,16 +369,7 @@ esp_err_t esp_sleep_disable_wakeup_source(esp_sleep_source_t source) esp_err_t esp_sleep_enable_ulp_wakeup() { -#ifdef CONFIG_ULP_COPROC_ENABLED - if(s_config.wakeup_triggers & RTC_EXT0_TRIG_EN) { - ESP_LOGE(TAG, "Conflicting wake-up trigger: ext0"); - return ESP_ERR_INVALID_STATE; - } - s_config.wakeup_triggers |= RTC_ULP_TRIG_EN; - return ESP_OK; -#else - return ESP_ERR_INVALID_STATE; -#endif + return ESP_ERR_NOT_SUPPORTED; } esp_err_t esp_sleep_enable_timer_wakeup(uint64_t time_in_us) diff --git a/components/esp32s2beta/spiram.c b/components/esp32s2beta/spiram.c index 3d421d04d..3ecc4ea39 100644 --- a/components/esp32s2beta/spiram.c +++ b/components/esp32s2beta/spiram.c @@ -37,7 +37,7 @@ we add more types of external RAM memory, this can be made into a more intellige #if CONFIG_FREERTOS_UNICORE #define PSRAM_MODE PSRAM_VADDR_MODE_NORMAL #else -#if CONFIG_MEMMAP_SPIRAM_CACHE_EVENODD +#if 0 /* TODO: no even/odd mode for ESP32S2 PSRAM? */ #define PSRAM_MODE PSRAM_VADDR_MODE_EVENODD #else #define PSRAM_MODE PSRAM_VADDR_MODE_LOWHIGH @@ -147,7 +147,7 @@ void IRAM_ATTR esp_spiram_init_cache() REG_SET_BIT(DPORT_CACHE_SOURCE_1_REG, DPORT_PRO_CACHE_D_SOURCE_PRO_DPORT | DPORT_PRO_CACHE_D_SOURCE_PRO_DRAM0); REG_CLR_BIT(DPORT_PRO_DCACHE_CTRL1_REG, DPORT_PRO_DCACHE_MASK_DRAM1 | DPORT_PRO_DCACHE_MASK_DRAM0 | DPORT_PRO_DCACHE_MASK_DPORT); #else -#if CONFIG_USE_AHB_DBUS3_ACCESS_SPIRAM +#if CONFIG_SPIRAM_USE_AHB_DBUS3 #if CONFIG_SPIRAM_SIZE <= DRAM0_DRAM1_DPORT_DBUS3_CACHE_SIZE /* cache size <= 14MB + 576KB, map DRAM0, DRAM1, DPORT bus, as well as data bus3 */ Cache_Dbus_MMU_Set(DPORT_MMU_ACCESS_SPIRAM, SPIRAM_MID_SIZE_MAP_VADDR, SPIRAM_MID_SIZE_MAP_PADDR, 64, SPIRAM_MID_SIZE_MAP_SIZE >> 16, 0); @@ -266,7 +266,7 @@ esp_err_t esp_spiram_add_to_heapalloc() /* cache size <= 10MB + 576KB, map DRAM0, DRAM1, DPORT bus */ return heap_caps_add_region((intptr_t)SPIRAM_SMALL_SIZE_MAP_VADDR + size_for_flash, (intptr_t)SPIRAM_SMALL_SIZE_MAP_VADDR + SPIRAM_SMALL_SIZE_MAP_SIZE -1); #else -#if CONFIG_USE_AHB_DBUS3_ACCESS_SPIRAM +#if CONFIG_SPIRAM_USE_AHB_DBUS3 #if CONFIG_SPIRAM_SIZE <= DRAM0_DRAM1_DPORT_DBUS3_CACHE_SIZE /* cache size <= 14MB + 576KB, map DRAM0, DRAM1, DPORT bus, as well as data bus3 */ if (size_for_flash <= SPIRAM_MID_SIZE_MAP_SIZE) { diff --git a/components/esp_wifi/CMakeLists.txt b/components/esp_wifi/CMakeLists.txt index 5c9fbf2be..37a3016e2 100644 --- a/components/esp_wifi/CMakeLists.txt +++ b/components/esp_wifi/CMakeLists.txt @@ -11,14 +11,19 @@ set(COMPONENT_PRIV_INCLUDEDIRS) set(COMPONENT_REQUIRES wpa_supplicant smartconfig_ack) set(COMPONENT_PRIV_REQUIRES "nvs_flash") -if(NOT CONFIG_ESP32_NO_BLOBS) +set(link_binary_libs 1) +if (CONFIG_ESP32_NO_BLOBS OR CONFIG_ESP32S2_NO_BLOBS) + set(link_binary_libs 0) +endif() + +if(link_binary_libs) set(COMPONENT_ADD_LDFRAGMENTS "linker.lf") endif() register_component() target_link_libraries(${COMPONENT_LIB} "-L ${CMAKE_CURRENT_SOURCE_DIR}/lib_${IDF_TARGET}") -if(NOT CONFIG_ESP32_NO_BLOBS) +if(link_binary_libs) set(blobs coexist core espnow mesh net80211 phy pp rtc smartconfig wpa2 wpa wps) foreach(blob ${blobs}) add_library(${blob} STATIC IMPORTED)