Crash_Override/OVMS3-idf
1
0
Fork 0
Code Issues Pull requests Projects Releases Wiki Activity

Merge branch 'refactor/common_rom_gpio_apis' into 'master'

Browse source 
esp_rom: extract common GPIO apis into esp_rom_gpio.h

See merge request espressif/esp-idf!9248
This commit is contained in:
Ivan Grokhotkov 2020-07-07 17:28:39 +08:00
commit 8cd1f99ace
89 changed files with 440 additions and 595 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
components/app_update/test/test_switch_ota.c
View file

@ -279,7 +279,7 @@ static void set_output_pin(uint32_t num_pin)
TEST_ESP_OK(gpio_hold_dis(num_pin));
gpio_config_t io_conf;
io_conf.intr_type = GPIO_PIN_INTR_DISABLE;
io_conf.intr_type = GPIO_INTR_DISABLE;
io_conf.mode = GPIO_MODE_OUTPUT;
io_conf.pin_bit_mask = (1ULL << num_pin);
io_conf.pull_down_en = 0;

12
components/bootloader_support/src/bootloader_common.c
View file

@ -19,19 +19,19 @@
#include "esp_log.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/spi_flash.h"
#include "esp32/rom/gpio.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/spi_flash.h"
#include "esp32s2/rom/ets_sys.h"
#include "esp32s2/rom/gpio.h"
#endif
#include "esp_rom_crc.h"
#include "esp_rom_gpio.h"
#include "esp_flash_partitions.h"
#include "bootloader_flash.h"
#include "bootloader_common.h"
#include "soc/gpio_periph.h"
#include "soc/rtc.h"
#include "soc/efuse_reg.h"
#include "hal/gpio_ll.h"
#include "esp_image_format.h"
#include "bootloader_sha.h"
#include "sys/param.h"
@ -57,17 +57,17 @@ bool bootloader_common_ota_select_valid(const esp_ota_select_entry_t *s)
esp_comm_gpio_hold_t bootloader_common_check_long_hold_gpio(uint32_t num_pin, uint32_t delay_sec)
{
gpio_pad_select_gpio(num_pin);
esp_rom_gpio_pad_select_gpio(num_pin);
if (GPIO_PIN_MUX_REG[num_pin]) {
PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[num_pin]);
}
gpio_pad_pullup(num_pin);
esp_rom_gpio_pad_pullup_only(num_pin);
uint32_t tm_start = esp_log_early_timestamp();
if (GPIO_INPUT_GET(num_pin) == 1) {
if (gpio_ll_get_level(&GPIO, num_pin) == 1) {
return GPIO_NOT_HOLD;
}
do {
if (GPIO_INPUT_GET(num_pin) != 0) {
if (gpio_ll_get_level(&GPIO, num_pin) != 0) {
return GPIO_SHORT_HOLD;
}
} while (delay_sec > ((esp_log_early_timestamp() - tm_start) / 1000L));

9
components/bootloader_support/src/bootloader_console.c
View file

@ -24,14 +24,13 @@
#ifdef CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/ets_sys.h"
#include "esp32/rom/uart.h"
#include "esp32/rom/gpio.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/ets_sys.h"
#include "esp32s2/rom/uart.h"
#include "esp32s2/rom/gpio.h"
#include "esp32s2/rom/usb/cdc_acm.h"
#include "esp32s2/rom/usb/usb_common.h"
#endif
#include "esp_rom_gpio.h"
#ifdef CONFIG_ESP_CONSOLE_UART_NONE
void bootloader_console_init(void)
@ -70,9 +69,9 @@ void bootloader_console_init(void)
const uint32_t tx_idx = uart_periph_signal[uart_num].tx_sig;
const uint32_t rx_idx = uart_periph_signal[uart_num].rx_sig;
PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[uart_rx_gpio]);
gpio_pad_pullup(uart_rx_gpio);
gpio_matrix_out(uart_tx_gpio, tx_idx, 0, 0);
gpio_matrix_in(uart_rx_gpio, rx_idx, 0);
esp_rom_gpio_pad_pullup_only(uart_rx_gpio);
esp_rom_gpio_connect_out_signal(uart_tx_gpio, tx_idx, 0, 0);
esp_rom_gpio_connect_in_signal(uart_rx_gpio, rx_idx, 0);
// Enable the peripheral
periph_ll_enable_clk_clear_rst(PERIPH_UART0_MODULE + uart_num);
}

20
components/bootloader_support/src/bootloader_flash_config_esp32.c
View file

@ -17,7 +17,7 @@
#include "sdkconfig.h"
#include "esp_err.h"
#include "esp_log.h"
#include "esp32/rom/gpio.h"
#include "esp_rom_gpio.h"
#include "esp32/rom/spi_flash.h"
#include "esp32/rom/efuse.h"
#include "soc/gpio_periph.h"
@ -93,15 +93,15 @@ void IRAM_ATTR bootloader_flash_gpio_config(const esp_image_header_t* pfhdr)
} else {
const uint32_t spiconfig = ets_efuse_get_spiconfig();
if (spiconfig == EFUSE_SPICONFIG_SPI_DEFAULTS) {
gpio_matrix_out(SPI_IOMUX_PIN_NUM_CS, SPICS0_OUT_IDX, 0, 0);
gpio_matrix_out(SPI_IOMUX_PIN_NUM_MISO, SPIQ_OUT_IDX, 0, 0);
gpio_matrix_in(SPI_IOMUX_PIN_NUM_MISO, SPIQ_IN_IDX, 0);
gpio_matrix_out(SPI_IOMUX_PIN_NUM_MOSI, SPID_OUT_IDX, 0, 0);
gpio_matrix_in(SPI_IOMUX_PIN_NUM_MOSI, SPID_IN_IDX, 0);
gpio_matrix_out(SPI_IOMUX_PIN_NUM_WP, SPIWP_OUT_IDX, 0, 0);
gpio_matrix_in(SPI_IOMUX_PIN_NUM_WP, SPIWP_IN_IDX, 0);
gpio_matrix_out(SPI_IOMUX_PIN_NUM_HD, SPIHD_OUT_IDX, 0, 0);
gpio_matrix_in(SPI_IOMUX_PIN_NUM_HD, SPIHD_IN_IDX, 0);
esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_CS, SPICS0_OUT_IDX, 0, 0);
esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_MISO, SPIQ_OUT_IDX, 0, 0);
esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_MISO, SPIQ_IN_IDX, 0);
esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_MOSI, SPID_OUT_IDX, 0, 0);
esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_MOSI, SPID_IN_IDX, 0);
esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_WP, SPIWP_OUT_IDX, 0, 0);
esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_WP, SPIWP_IN_IDX, 0);
esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_HD, SPIHD_OUT_IDX, 0, 0);
esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_HD, SPIHD_IN_IDX, 0);
//select pin function gpio
PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA0_U, PIN_FUNC_GPIO);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA1_U, PIN_FUNC_GPIO);

2
components/bootloader_support/src/bootloader_flash_config_esp32s2.c
View file

@ -17,10 +17,8 @@
#include "sdkconfig.h"
#include "esp_err.h"
#include "esp_log.h"
#include "esp32s2/rom/gpio.h"
#include "esp32s2/rom/spi_flash.h"
#include "esp32s2/rom/efuse.h"
#include "soc/gpio_periph.h"
#include "soc/efuse_reg.h"
#include "soc/spi_reg.h"
#include "soc/spi_mem_reg.h"

2
components/bootloader_support/src/bootloader_utility.c
View file

@ -26,7 +26,6 @@
#include "esp32/rom/spi_flash.h"
#include "esp32/rom/rtc.h"
#include "esp32/rom/uart.h"
#include "esp32/rom/gpio.h"
#include "esp32/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/cache.h"
@ -35,7 +34,6 @@
#include "esp32s2/rom/spi_flash.h"
#include "esp32s2/rom/rtc.h"
#include "esp32s2/rom/uart.h"
#include "esp32s2/rom/gpio.h"
#include "esp32s2/rom/secure_boot.h"
#include "soc/extmem_reg.h"
#include "soc/cache_memory.h"

20
components/bootloader_support/src/esp32/bootloader_esp32.c
View file

@ -37,7 +37,7 @@
#include "esp32/rom/cache.h"
#include "esp32/rom/efuse.h"
#include "esp32/rom/ets_sys.h"
#include "esp32/rom/gpio.h"
#include "esp_rom_gpio.h"
#include "esp32/rom/spi_flash.h"
#include "esp32/rom/rtc.h"
#include "esp32/rom/uart.h"
@ -74,15 +74,15 @@ void bootloader_configure_spi_pins(int drv)
} else {
const uint32_t spiconfig = ets_efuse_get_spiconfig();
if (spiconfig == EFUSE_SPICONFIG_SPI_DEFAULTS) {
gpio_matrix_out(FLASH_CS_IO, SPICS0_OUT_IDX, 0, 0);
gpio_matrix_out(FLASH_SPIQ_IO, SPIQ_OUT_IDX, 0, 0);
gpio_matrix_in(FLASH_SPIQ_IO, SPIQ_IN_IDX, 0);
gpio_matrix_out(FLASH_SPID_IO, SPID_OUT_IDX, 0, 0);
gpio_matrix_in(FLASH_SPID_IO, SPID_IN_IDX, 0);
gpio_matrix_out(FLASH_SPIWP_IO, SPIWP_OUT_IDX, 0, 0);
gpio_matrix_in(FLASH_SPIWP_IO, SPIWP_IN_IDX, 0);
gpio_matrix_out(FLASH_SPIHD_IO, SPIHD_OUT_IDX, 0, 0);
gpio_matrix_in(FLASH_SPIHD_IO, SPIHD_IN_IDX, 0);
esp_rom_gpio_connect_out_signal(FLASH_CS_IO, SPICS0_OUT_IDX, 0, 0);
esp_rom_gpio_connect_out_signal(FLASH_SPIQ_IO, SPIQ_OUT_IDX, 0, 0);
esp_rom_gpio_connect_in_signal(FLASH_SPIQ_IO, SPIQ_IN_IDX, 0);
esp_rom_gpio_connect_out_signal(FLASH_SPID_IO, SPID_OUT_IDX, 0, 0);
esp_rom_gpio_connect_in_signal(FLASH_SPID_IO, SPID_IN_IDX, 0);
esp_rom_gpio_connect_out_signal(FLASH_SPIWP_IO, SPIWP_OUT_IDX, 0, 0);
esp_rom_gpio_connect_in_signal(FLASH_SPIWP_IO, SPIWP_IN_IDX, 0);
esp_rom_gpio_connect_out_signal(FLASH_SPIHD_IO, SPIHD_OUT_IDX, 0, 0);
esp_rom_gpio_connect_in_signal(FLASH_SPIHD_IO, SPIHD_IN_IDX, 0);
//select pin function gpio
PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA0_U, PIN_FUNC_GPIO);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA1_U, PIN_FUNC_GPIO);

14
components/bootloader_support/src/esp32s2/bootloader_esp32s2.c
View file

@ -19,7 +19,7 @@
#include "soc/gpio_sig_map.h"
#include "soc/io_mux_reg.h"
#include "esp32s2/rom/efuse.h"
#include "esp32s2/rom/gpio.h"
#include "esp_rom_gpio.h"
#include "esp32s2/rom/spi_flash.h"
#include "bootloader_init.h"
@ -66,15 +66,15 @@ void bootloader_configure_spi_pins(int drv)
hd_gpio_num = (spiconfig >> 24) & 0x3f;
wp_gpio_num = wp_pin;
}
gpio_pad_set_drv(clk_gpio_num, drv);
gpio_pad_set_drv(q_gpio_num, drv);
gpio_pad_set_drv(d_gpio_num, drv);
gpio_pad_set_drv(cs0_gpio_num, drv);
esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv);
if (hd_gpio_num <= MAX_PAD_GPIO_NUM) {
gpio_pad_set_drv(hd_gpio_num, drv);
esp_rom_gpio_pad_set_drv(hd_gpio_num, drv);
}
if (wp_gpio_num <= MAX_PAD_GPIO_NUM) {
gpio_pad_set_drv(wp_gpio_num, drv);
esp_rom_gpio_pad_set_drv(wp_gpio_num, drv);
}
}

3
components/driver/gpio.c
View file

@ -28,6 +28,7 @@
#include "soc/gpio_periph.h"
#include "esp_log.h"
#include "hal/gpio_hal.h"
#include "esp_rom_gpio.h"
static const char *GPIO_TAG = "gpio";
#define GPIO_CHECK(a, str, ret_val) \
@ -192,7 +193,7 @@ static esp_err_t gpio_output_enable(gpio_num_t gpio_num)
{
GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO output gpio_num error", ESP_ERR_INVALID_ARG);
gpio_hal_output_enable(gpio_context.gpio_hal, gpio_num);
gpio_matrix_out(gpio_num, SIG_GPIO_OUT_IDX, false, false);
esp_rom_gpio_connect_out_signal(gpio_num, SIG_GPIO_OUT_IDX, false, false);
return ESP_OK;
}

9
components/driver/i2c.c
View file

@ -30,6 +30,7 @@
#include "soc/i2c_periph.h"
#include "driver/i2c.h"
#include "driver/periph_ctrl.h"
#include "esp_rom_gpio.h"
static const char *I2C_TAG = "i2c";
#define I2C_CHECK(a, str, ret) if(!(a)) { \
@ -788,15 +789,15 @@ esp_err_t i2c_set_pin(i2c_port_t i2c_num, int sda_io_num, int scl_io_num, bool s
} else {
gpio_set_pull_mode(sda_io_num, GPIO_FLOATING);
}
gpio_matrix_out(sda_io_num, sda_out_sig, 0, 0);
gpio_matrix_in(sda_io_num, sda_in_sig, 0);
esp_rom_gpio_connect_out_signal(sda_io_num, sda_out_sig, 0, 0);
esp_rom_gpio_connect_in_signal(sda_io_num, sda_in_sig, 0);
}
if (scl_io_num >= 0) {
gpio_set_level(scl_io_num, I2C_IO_INIT_LEVEL);
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[scl_io_num], PIN_FUNC_GPIO);
gpio_set_direction(scl_io_num, GPIO_MODE_INPUT_OUTPUT_OD);
gpio_matrix_out(scl_io_num, scl_out_sig, 0, 0);
gpio_matrix_in(scl_io_num, scl_in_sig, 0);
esp_rom_gpio_connect_out_signal(scl_io_num, scl_out_sig, 0, 0);
esp_rom_gpio_connect_in_signal(scl_io_num, scl_in_sig, 0);
if (scl_pullup_en == GPIO_PULLUP_ENABLE) {
gpio_set_pull_mode(scl_io_num, GPIO_PULLUP_ONLY);
} else {

7
components/driver/i2s.c
View file

@ -22,7 +22,7 @@
#include "freertos/xtensa_api.h"
#include "freertos/semphr.h"
#include "esp32/rom/lldesc.h"
#include "soc/lldesc.h"
#include "driver/gpio.h"
#include "driver/i2s.h"
@ -38,6 +38,7 @@
#include "esp_log.h"
#include "esp_pm.h"
#include "esp_efuse.h"
#include "esp_rom_gpio.h"
static const char* I2S_TAG = "I2S";
@ -121,7 +122,7 @@ static inline void gpio_matrix_out_check(uint32_t gpio, uint32_t signal_idx, boo
if (gpio != -1) {
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio], PIN_FUNC_GPIO);
gpio_set_direction(gpio, GPIO_MODE_DEF_OUTPUT);
gpio_matrix_out(gpio, signal_idx, out_inv, oen_inv);
esp_rom_gpio_connect_out_signal(gpio, signal_idx, out_inv, oen_inv);
}
}
@ -131,7 +132,7 @@ static inline void gpio_matrix_in_check(uint32_t gpio, uint32_t signal_idx, bool
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio], PIN_FUNC_GPIO);
//Set direction, for some GPIOs, the input function are not enabled as default.
gpio_set_direction(gpio, GPIO_MODE_DEF_INPUT);
gpio_matrix_in(gpio, signal_idx, inv);
esp_rom_gpio_connect_in_signal(gpio, signal_idx, inv);
}
}

4
components/driver/include/driver/gpio.h
View file

@ -22,6 +22,10 @@
#include "soc/gpio_periph.h"
#include "hal/gpio_types.h"
// |================================= WARNING ====================================================== |
// | Including ROM header file in a PUBLIC API file will be REMOVED in the next major release (5.x). |
// | User should include "esp_rom_gpio.h" in their code if they have to use those ROM API. |
// |================================================================================================ |
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/gpio.h"
#elif CONFIG_IDF_TARGET_ESP32S2

5
components/driver/ledc.c
View file

@ -22,6 +22,7 @@
#include "soc/rtc.h"
#include "hal/ledc_hal.h"
#include "driver/ledc.h"
#include "esp_rom_gpio.h"
static const char* LEDC_TAG = "ledc";
@ -361,7 +362,7 @@ esp_err_t ledc_set_pin(int gpio_num, ledc_mode_t speed_mode, ledc_channel_t ledc
LEDC_ARG_CHECK(speed_mode < LEDC_SPEED_MODE_MAX, "speed_mode");
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO);
gpio_set_direction(gpio_num, GPIO_MODE_OUTPUT);
gpio_matrix_out(gpio_num, ledc_periph_signal[speed_mode].sig_out0_idx + ledc_channel, 0, 0);
esp_rom_gpio_connect_out_signal(gpio_num, ledc_periph_signal[speed_mode].sig_out0_idx + ledc_channel, 0, 0);
return ESP_OK;
}
@ -403,7 +404,7 @@ esp_err_t ledc_channel_config(const ledc_channel_config_t* ledc_conf)
/*set LEDC signal in gpio matrix*/
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO);
gpio_set_direction(gpio_num, GPIO_MODE_OUTPUT);
gpio_matrix_out(gpio_num, ledc_periph_signal[speed_mode].sig_out0_idx + ledc_channel, 0, 0);
esp_rom_gpio_connect_out_signal(gpio_num, ledc_periph_signal[speed_mode].sig_out0_idx + ledc_channel, 0, 0);
return ret;
}

12
components/driver/mcpwm.c
View file

@ -24,7 +24,7 @@
#include "driver/periph_ctrl.h"
#include "sdkconfig.h"
#include "hal/mcpwm_hal.h"
#include "esp_rom_gpio.h"
typedef struct {
mcpwm_hal_context_t hal;
@ -115,22 +115,22 @@ esp_err_t mcpwm_gpio_init(mcpwm_unit_t mcpwm_num, mcpwm_io_signals_t io_signal,
if (mcpwm_gpio_sig) {
MCPWM_CHECK((GPIO_IS_VALID_OUTPUT_GPIO(gpio_num)), MCPWM_GPIO_ERROR, ESP_ERR_INVALID_ARG);
gpio_set_direction(gpio_num, GPIO_MODE_OUTPUT);
gpio_matrix_out(gpio_num, PWM0_OUT0A_IDX + io_signal, 0, 0);
esp_rom_gpio_connect_out_signal(gpio_num, PWM0_OUT0A_IDX + io_signal, 0, 0);
} else {
gpio_set_direction(gpio_num, GPIO_MODE_INPUT);
gpio_matrix_in(gpio_num, PWM0_SYNC0_IN_IDX + io_signal - OFFSET_FOR_GPIO_IDX_1, 0);
esp_rom_gpio_connect_in_signal(gpio_num, PWM0_SYNC0_IN_IDX + io_signal - OFFSET_FOR_GPIO_IDX_1, 0);
}
} else { //MCPWM_UNIT_1
if (mcpwm_gpio_sig) {
MCPWM_CHECK((GPIO_IS_VALID_OUTPUT_GPIO(gpio_num)), MCPWM_GPIO_ERROR, ESP_ERR_INVALID_ARG);
gpio_set_direction(gpio_num, GPIO_MODE_OUTPUT);
gpio_matrix_out(gpio_num, PWM1_OUT0A_IDX + io_signal, 0, 0);
esp_rom_gpio_connect_out_signal(gpio_num, PWM1_OUT0A_IDX + io_signal, 0, 0);
} else if (io_signal >= MCPWM_SYNC_0 && io_signal <= MCPWM_FAULT_2) {
gpio_set_direction(gpio_num, GPIO_MODE_INPUT);
gpio_matrix_in(gpio_num, PWM1_SYNC0_IN_IDX + io_signal - OFFSET_FOR_GPIO_IDX_1, 0);
esp_rom_gpio_connect_in_signal(gpio_num, PWM1_SYNC0_IN_IDX + io_signal - OFFSET_FOR_GPIO_IDX_1, 0);
} else {
gpio_set_direction(gpio_num, GPIO_MODE_INPUT);
gpio_matrix_in(gpio_num, PWM1_SYNC0_IN_IDX + io_signal - OFFSET_FOR_GPIO_IDX_2, 0);
esp_rom_gpio_connect_in_signal(gpio_num, PWM1_SYNC0_IN_IDX + io_signal - OFFSET_FOR_GPIO_IDX_2, 0);
}
}
return ESP_OK;

5
components/driver/pcnt.c
View file

@ -20,6 +20,7 @@
#include "driver/periph_ctrl.h"
#include "hal/pcnt_hal.h"
#include "soc/pcnt_caps.h"
#include "esp_rom_gpio.h"
#define PCNT_CHANNEL_ERR_STR "PCNT CHANNEL ERROR"
#define PCNT_UNIT_ERR_STR "PCNT UNIT ERROR"
@ -98,14 +99,14 @@ static inline esp_err_t _pcnt_set_pin(pcnt_port_t pcnt_port, pcnt_unit_t unit, p
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[pulse_io], PIN_FUNC_GPIO);
gpio_set_direction(pulse_io, GPIO_MODE_INPUT);
gpio_set_pull_mode(pulse_io, GPIO_PULLUP_ONLY);
gpio_matrix_in(pulse_io, input_sig_index, 0);
esp_rom_gpio_connect_in_signal(pulse_io, input_sig_index, 0);
}
if (ctrl_io >= 0) {
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[ctrl_io], PIN_FUNC_GPIO);
gpio_set_direction(ctrl_io, GPIO_MODE_INPUT);
gpio_set_pull_mode(ctrl_io, GPIO_PULLUP_ONLY);
gpio_matrix_in(ctrl_io, ctrl_sig_index, 0);
esp_rom_gpio_connect_in_signal(ctrl_io, ctrl_sig_index, 0);
}
return ESP_OK;

5
components/driver/rmt.c
View file

@ -26,6 +26,7 @@
#include "soc/soc_memory_layout.h"
#include "hal/rmt_hal.h"
#include "hal/rmt_ll.h"
#include "esp_rom_gpio.h"
#define RMT_CHANNEL_ERROR_STR "RMT CHANNEL ERR"
#define RMT_ADDR_ERROR_STR "RMT ADDRESS ERR"
@ -486,10 +487,10 @@ esp_err_t rmt_set_pin(rmt_channel_t channel, rmt_mode_t mode, gpio_num_t gpio_nu
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO);
if (mode == RMT_MODE_TX) {
gpio_set_direction(gpio_num, GPIO_MODE_OUTPUT);
gpio_matrix_out(gpio_num, RMT_SIG_OUT0_IDX + channel, 0, 0);
esp_rom_gpio_connect_out_signal(gpio_num, RMT_SIG_OUT0_IDX + channel, 0, 0);
} else {
gpio_set_direction(gpio_num, GPIO_MODE_INPUT);
gpio_matrix_in(gpio_num, RMT_SIG_IN0_IDX + channel, 0);
esp_rom_gpio_connect_in_signal(gpio_num, RMT_SIG_IN0_IDX + channel, 0);
}
return ESP_OK;
}

17
components/driver/sdmmc_host.c
View file

@ -18,7 +18,8 @@
#include "esp_log.h"
#include "esp_intr_alloc.h"
#include "soc/gpio_periph.h"
#include "esp32/rom/gpio.h"
#include "soc/gpio_caps.h"
#include "esp_rom_gpio.h"
#include "driver/gpio.h"
#include "driver/sdmmc_host.h"
#include "driver/periph_ctrl.h"
@ -362,35 +363,35 @@ esp_err_t sdmmc_host_init_slot(int slot, const sdmmc_slot_config_t* slot_config)
// SDIO slave interrupt is edge sensitive to ~(int_n | card_int | card_detect)
// set this and card_detect to high to enable sdio interrupt
gpio_matrix_in(GPIO_FUNC_IN_HIGH, pslot->card_int, false);
esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ONE_INPUT, pslot->card_int, false);
// Set up Card Detect input
int matrix_in_cd;
if (gpio_cd != SDMMC_SLOT_NO_CD) {
ESP_LOGD(TAG, "using GPIO%d as CD pin", gpio_cd);
gpio_pad_select_gpio(gpio_cd);
esp_rom_gpio_pad_select_gpio(gpio_cd);
gpio_set_direction(gpio_cd, GPIO_MODE_INPUT);
matrix_in_cd = gpio_cd;
} else {
// if not set, default to CD low (card present)
matrix_in_cd = GPIO_FUNC_IN_LOW;
matrix_in_cd = GPIO_MATRIX_CONST_ZERO_INPUT;
}
gpio_matrix_in(matrix_in_cd, pslot->card_detect, false);
esp_rom_gpio_connect_in_signal(matrix_in_cd, pslot->card_detect, false);
// Set up Write Protect input
int matrix_in_wp;
if (gpio_wp != SDMMC_SLOT_NO_WP) {
ESP_LOGD(TAG, "using GPIO%d as WP pin", gpio_wp);
gpio_pad_select_gpio(gpio_wp);
esp_rom_gpio_pad_select_gpio(gpio_wp);
gpio_set_direction(gpio_wp, GPIO_MODE_INPUT);
matrix_in_wp = gpio_wp;
} else {
// if not set, default to WP high (not write protected)
matrix_in_wp = GPIO_FUNC_IN_HIGH;
matrix_in_wp = GPIO_MATRIX_CONST_ONE_INPUT;
}
// WP signal is normally active low, but hardware expects
// an active-high signal, so invert it in GPIO matrix
gpio_matrix_in(matrix_in_wp, pslot->write_protect, true);
esp_rom_gpio_connect_in_signal(matrix_in_wp, pslot->write_protect, true);
// By default, set probing frequency (400kHz) and 1-bit bus
esp_err_t ret = sdmmc_host_set_card_clk(slot, 400);

6
components/driver/sdspi_host.c
View file

@ -252,7 +252,7 @@ static esp_err_t deinit_slot(slot_info_t *slot)
gpio_config_t config = {
.pin_bit_mask = pin_bit_mask,
.mode = GPIO_MODE_INPUT,
.intr_type = GPIO_PIN_INTR_DISABLE,
.intr_type = GPIO_INTR_DISABLE,
};
gpio_config(&config);
@ -334,7 +334,7 @@ esp_err_t sdspi_host_init_device(const sdspi_device_config_t* slot_config, sdspi
// Configure CS pin
gpio_config_t io_conf = {
.intr_type = GPIO_PIN_INTR_DISABLE,
.intr_type = GPIO_INTR_DISABLE,
.mode = GPIO_MODE_OUTPUT,
.pin_bit_mask = 1ULL << slot_config->gpio_cs,
};
@ -348,7 +348,7 @@ esp_err_t sdspi_host_init_device(const sdspi_device_config_t* slot_config, sdspi
// Configure CD and WP pins
io_conf = (gpio_config_t) {
.intr_type = GPIO_PIN_INTR_DISABLE,
.intr_type = GPIO_INTR_DISABLE,
.mode = GPIO_MODE_INPUT,
.pin_bit_mask = 0,
.pull_up_en = true

3
components/driver/sigmadelta.c
View file

@ -17,6 +17,7 @@
#include "driver/sigmadelta.h"
#include "esp_heap_caps.h"
#include "hal/sigmadelta_hal.h"
#include "esp_rom_gpio.h"
static const char *TAG = "SIGMADELTA";
@ -58,7 +59,7 @@ static inline esp_err_t _sigmadelta_set_pin(sigmadelta_port_t sigmadelta_port, s
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO);
gpio_set_direction(gpio_num, GPIO_MODE_OUTPUT);
gpio_matrix_out(gpio_num, GPIO_SD0_OUT_IDX + channel, 0, 0);
esp_rom_gpio_connect_out_signal(gpio_num, GPIO_SD0_OUT_IDX + channel, 0, 0);
return ESP_OK;
}

25
components/driver/spi_common.c
View file

@ -30,6 +30,7 @@
#include "driver/spi_common_internal.h"
#include "stdatomic.h"
#include "hal/spi_hal.h"
#include "esp_rom_gpio.h"
static const char *SPI_TAG = "spi";
@ -315,11 +316,11 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf
if (bus_config->mosi_io_num >= 0) {
if (mosi_need_output || (temp_flag&SPICOMMON_BUSFLAG_DUAL)) {
gpio_set_direction(bus_config->mosi_io_num, GPIO_MODE_INPUT_OUTPUT);
gpio_matrix_out(bus_config->mosi_io_num, spi_periph_signal[host].spid_out, false, false);
esp_rom_gpio_connect_out_signal(bus_config->mosi_io_num, spi_periph_signal[host].spid_out, false, false);
} else {
gpio_set_direction(bus_config->mosi_io_num, GPIO_MODE_INPUT);
}
gpio_matrix_in(bus_config->mosi_io_num, spi_periph_signal[host].spid_in, false);
esp_rom_gpio_connect_in_signal(bus_config->mosi_io_num, spi_periph_signal[host].spid_in, false);
#if CONFIG_IDF_TARGET_ESP32S2
PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[bus_config->mosi_io_num]);
#endif
@ -328,11 +329,11 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf
if (bus_config->miso_io_num >= 0) {
if (miso_need_output || (temp_flag&SPICOMMON_BUSFLAG_DUAL)) {
gpio_set_direction(bus_config->miso_io_num, GPIO_MODE_INPUT_OUTPUT);
gpio_matrix_out(bus_config->miso_io_num, spi_periph_signal[host].spiq_out, false, false);
esp_rom_gpio_connect_out_signal(bus_config->miso_io_num, spi_periph_signal[host].spiq_out, false, false);
} else {
gpio_set_direction(bus_config->miso_io_num, GPIO_MODE_INPUT);
}
gpio_matrix_in(bus_config->miso_io_num, spi_periph_signal[host].spiq_in, false);
esp_rom_gpio_connect_in_signal(bus_config->miso_io_num, spi_periph_signal[host].spiq_in, false);
#if CONFIG_IDF_TARGET_ESP32S2
PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[bus_config->miso_io_num]);
#endif
@ -340,8 +341,8 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf
}
if (bus_config->quadwp_io_num >= 0) {
gpio_set_direction(bus_config->quadwp_io_num, GPIO_MODE_INPUT_OUTPUT);
gpio_matrix_out(bus_config->quadwp_io_num, spi_periph_signal[host].spiwp_out, false, false);
gpio_matrix_in(bus_config->quadwp_io_num, spi_periph_signal[host].spiwp_in, false);
esp_rom_gpio_connect_out_signal(bus_config->quadwp_io_num, spi_periph_signal[host].spiwp_out, false, false);
esp_rom_gpio_connect_in_signal(bus_config->quadwp_io_num, spi_periph_signal[host].spiwp_in, false);
#if CONFIG_IDF_TARGET_ESP32S2
PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[bus_config->quadwp_io_num]);
#endif
@ -349,8 +350,8 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf
}
if (bus_config->quadhd_io_num >= 0) {
gpio_set_direction(bus_config->quadhd_io_num, GPIO_MODE_INPUT_OUTPUT);
gpio_matrix_out(bus_config->quadhd_io_num, spi_periph_signal[host].spihd_out, false, false);
gpio_matrix_in(bus_config->quadhd_io_num, spi_periph_signal[host].spihd_in, false);
esp_rom_gpio_connect_out_signal(bus_config->quadhd_io_num, spi_periph_signal[host].spihd_out, false, false);
esp_rom_gpio_connect_in_signal(bus_config->quadhd_io_num, spi_periph_signal[host].spihd_in, false);
#if CONFIG_IDF_TARGET_ESP32S2
PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[bus_config->quadhd_io_num]);
#endif
@ -359,11 +360,11 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf
if (bus_config->sclk_io_num >= 0) {
if (sclk_need_output) {
gpio_set_direction(bus_config->sclk_io_num, GPIO_MODE_INPUT_OUTPUT);
gpio_matrix_out(bus_config->sclk_io_num, spi_periph_signal[host].spiclk_out, false, false);
esp_rom_gpio_connect_out_signal(bus_config->sclk_io_num, spi_periph_signal[host].spiclk_out, false, false);
} else {
gpio_set_direction(bus_config->sclk_io_num, GPIO_MODE_INPUT);
}
gpio_matrix_in(bus_config->sclk_io_num, spi_periph_signal[host].spiclk_in, false);
esp_rom_gpio_connect_in_signal(bus_config->sclk_io_num, spi_periph_signal[host].spiclk_in, false);
#if CONFIG_IDF_TARGET_ESP32S2
PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[bus_config->sclk_io_num]);
#endif
@ -410,11 +411,11 @@ void spicommon_cs_initialize(spi_host_device_t host, int cs_io_num, int cs_num,
//Use GPIO matrix
if (GPIO_IS_VALID_OUTPUT_GPIO(cs_io_num)) {
gpio_set_direction(cs_io_num, GPIO_MODE_INPUT_OUTPUT);
gpio_matrix_out(cs_io_num, spi_periph_signal[host].spics_out[cs_num], false, false);
esp_rom_gpio_connect_out_signal(cs_io_num, spi_periph_signal[host].spics_out[cs_num], false, false);
} else {
gpio_set_direction(cs_io_num, GPIO_MODE_INPUT);
}
if (cs_num == 0) gpio_matrix_in(cs_io_num, spi_periph_signal[host].spics_in, false);
if (cs_num == 0) esp_rom_gpio_connect_in_signal(cs_io_num, spi_periph_signal[host].spics_in, false);
PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[cs_io_num]);
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[cs_io_num], FUNC_GPIO);
}

6
components/driver/spi_slave.c
View file

@ -20,6 +20,7 @@
#include "driver/spi_common_internal.h"
#include "driver/spi_slave.h"
#include "soc/spi_periph.h"
#include "soc/gpio_caps.h"
#include "esp_types.h"
#include "esp_attr.h"
#include "esp_intr_alloc.h"
@ -33,6 +34,7 @@
#include "soc/soc_memory_layout.h"
#include "driver/gpio.h"
#include "esp_heap_caps.h"
#include "esp_rom_gpio.h"
static const char *SPI_TAG = "spi_slave";
#define SPI_CHECK(a, str, ret_val) \
@ -90,7 +92,7 @@ static inline bool bus_is_iomux(spi_slave_t *host)
static void freeze_cs(spi_slave_t *host)
{
gpio_matrix_in(GPIO_FUNC_IN_HIGH, spi_periph_signal[host->id].spics_in, false);
esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ONE_INPUT, spi_periph_signal[host->id].spics_in, false);
}
// Use this function instead of cs_initial to avoid overwrite the output config
@ -100,7 +102,7 @@ static inline void restore_cs(spi_slave_t *host)
if (bus_is_iomux(host)) {
gpio_iomux_in(host->cfg.spics_io_num, spi_periph_signal[host->id].spics_in);
} else {
gpio_matrix_in(host->cfg.spics_io_num, spi_periph_signal[host->id].spics_in, false);
esp_rom_gpio_connect_in_signal(host->cfg.spics_io_num, spi_periph_signal[host->id].spics_in, false);
}
}

6
components/driver/test/test_gpio.c
View file

@ -56,7 +56,7 @@ static gpio_config_t init_io(gpio_num_t num)
{
TEST_ASSERT(num < TEST_GPIO_OUTPUT_MAX);
gpio_config_t io_conf;
io_conf.intr_type = GPIO_PIN_INTR_DISABLE;
io_conf.intr_type = GPIO_INTR_DISABLE;
io_conf.mode = GPIO_MODE_OUTPUT;
io_conf.pin_bit_mask = (1ULL << num);
io_conf.pull_down_en = 0;
@ -156,7 +156,7 @@ TEST_CASE("GPIO config parameters test", "[gpio]")
//error param test
//ESP32 test 41 bit, ESP32-S2 test 48 bit
gpio_config_t io_config;
io_config.intr_type = GPIO_PIN_INTR_DISABLE;
io_config.intr_type = GPIO_INTR_DISABLE;
io_config.pin_bit_mask = ((uint64_t)1<<(GPIO_NUM_MAX+1));
TEST_ASSERT(gpio_config(&io_config) == ESP_ERR_INVALID_ARG);
@ -379,7 +379,7 @@ TEST_CASE("GPIO enable and disable interrupt test", "[gpio][test_env=UT_T1_GPIO]
TEST_CASE("GPIO set gpio output level test", "[gpio][ignore]")
{
gpio_config_t io_conf;
io_conf.intr_type = GPIO_PIN_INTR_DISABLE;
io_conf.intr_type = GPIO_INTR_DISABLE;
io_conf.mode = GPIO_MODE_OUTPUT;
io_conf.pin_bit_mask = (1<<TEST_GPIO_EXT_OUT_IO);
io_conf.pull_down_en = 0;

5
components/driver/test/test_i2c.c
View file

@ -17,6 +17,7 @@
#include "driver/pcnt.h"
#include "soc/uart_struct.h"
#include "driver/periph_ctrl.h"
#include "esp_rom_gpio.h"
#define DATA_LENGTH 512 /*!<Data buffer length for test buffer*/
@ -628,8 +629,8 @@ static void uart_aut_baud_det_init(int rxd_io_num)
{
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[rxd_io_num], PIN_FUNC_GPIO);
gpio_set_direction(rxd_io_num, GPIO_MODE_INPUT_OUTPUT);
gpio_matrix_out(rxd_io_num, I2CEXT1_SCL_OUT_IDX, 0, 0);
gpio_matrix_in(rxd_io_num, U1RXD_IN_IDX, 0);
esp_rom_gpio_connect_out_signal(rxd_io_num, I2CEXT1_SCL_OUT_IDX, 0, 0);
esp_rom_gpio_connect_in_signal(rxd_io_num, U1RXD_IN_IDX, 0);
periph_module_enable(PERIPH_UART1_MODULE);
UART1.int_ena.val = 0;
UART1.int_clr.val = ~0;

29
components/driver/test/test_i2s.c
View file

@ -13,6 +13,7 @@
#include "driver/gpio.h"
#include "unity.h"
#include "math.h"
#include "esp_rom_gpio.h"
#define SAMPLE_RATE (36000)
#define SAMPLE_BITS (16)
@ -52,32 +53,32 @@ static void i2s_test_io_config(int mode)
switch (mode) {
#if SOC_I2S_NUM > 1
case I2S_TEST_MODE_SLAVE_TO_MAXTER: {
gpio_matrix_out(MASTER_BCK_IO, I2S0I_BCK_OUT_IDX, 0, 0);
gpio_matrix_in(MASTER_BCK_IO, I2S1O_BCK_IN_IDX, 0);
esp_rom_gpio_connect_out_signal(MASTER_BCK_IO, I2S0I_BCK_OUT_IDX, 0, 0);
esp_rom_gpio_connect_in_signal(MASTER_BCK_IO, I2S1O_BCK_IN_IDX, 0);
gpio_matrix_out(MASTER_WS_IO, I2S0I_WS_OUT_IDX, 0, 0);
gpio_matrix_in(MASTER_WS_IO, I2S1O_WS_IN_IDX, 0);
esp_rom_gpio_connect_out_signal(MASTER_WS_IO, I2S0I_WS_OUT_IDX, 0, 0);
esp_rom_gpio_connect_in_signal(MASTER_WS_IO, I2S1O_WS_IN_IDX, 0);
gpio_matrix_out(DATA_OUT_IO, I2S1O_DATA_OUT23_IDX, 0, 0);
gpio_matrix_in(DATA_OUT_IO, I2S0I_DATA_IN15_IDX, 0);
esp_rom_gpio_connect_out_signal(DATA_OUT_IO, I2S1O_DATA_OUT23_IDX, 0, 0);
esp_rom_gpio_connect_in_signal(DATA_OUT_IO, I2S0I_DATA_IN15_IDX, 0);
}
break;
case I2S_TEST_MODE_MASTER_TO_SLAVE: {
gpio_matrix_out(MASTER_BCK_IO, I2S0O_BCK_OUT_IDX, 0, 0);
gpio_matrix_in(MASTER_BCK_IO, I2S1I_BCK_IN_IDX, 0);
esp_rom_gpio_connect_out_signal(MASTER_BCK_IO, I2S0O_BCK_OUT_IDX, 0, 0);
esp_rom_gpio_connect_in_signal(MASTER_BCK_IO, I2S1I_BCK_IN_IDX, 0);
gpio_matrix_out(MASTER_WS_IO, I2S0O_WS_OUT_IDX, 0, 0);
gpio_matrix_in(MASTER_WS_IO, I2S1I_WS_IN_IDX, 0);
esp_rom_gpio_connect_out_signal(MASTER_WS_IO, I2S0O_WS_OUT_IDX, 0, 0);
esp_rom_gpio_connect_in_signal(MASTER_WS_IO, I2S1I_WS_IN_IDX, 0);
gpio_matrix_out(DATA_OUT_IO, I2S0O_DATA_OUT23_IDX, 0, 0);
gpio_matrix_in(DATA_OUT_IO, I2S1I_DATA_IN15_IDX, 0);
esp_rom_gpio_connect_out_signal(DATA_OUT_IO, I2S0O_DATA_OUT23_IDX, 0, 0);
esp_rom_gpio_connect_in_signal(DATA_OUT_IO, I2S1I_DATA_IN15_IDX, 0);
}
break;
#endif
case I2S_TEST_MODE_LOOPBACK: {
gpio_matrix_out(DATA_OUT_IO, I2S0O_DATA_OUT23_IDX, 0, 0);
gpio_matrix_in(DATA_OUT_IO, I2S0I_DATA_IN15_IDX, 0);
esp_rom_gpio_connect_out_signal(DATA_OUT_IO, I2S0O_DATA_OUT23_IDX, 0, 0);
esp_rom_gpio_connect_in_signal(DATA_OUT_IO, I2S0I_DATA_IN15_IDX, 0);
}
break;

8
components/driver/test/test_pcnt.c
View file

@ -21,7 +21,9 @@
#include "esp_attr.h"
#include "esp_log.h"
#include "soc/gpio_periph.h"
#include "soc/gpio_caps.h"
#include "unity.h"
#include "esp_rom_gpio.h"
#define PULSE_IO 21
#define PCNT_INPUT_IO 4
@ -49,9 +51,9 @@ static void pcnt_test_io_config(int ctrl_level)
{
// Connect internal signals using IO matrix.
gpio_set_direction(PULSE_IO, GPIO_MODE_INPUT_OUTPUT);
gpio_matrix_out(PULSE_IO, LEDC_LS_SIG_OUT1_IDX, 0, 0); // LEDC_TIMER_1, LEDC_LOW_SPEED_MODE
gpio_matrix_in(PULSE_IO, PCNT_SIG_CH0_IN0_IDX, 0); // PCNT_UNIT_0, PCNT_CHANNEL_0
gpio_matrix_in(ctrl_level ? GPIO_FUNC_IN_HIGH: GPIO_FUNC_IN_LOW, PCNT_CTRL_CH0_IN0_IDX, 0); // PCNT_UNIT_0, PCNT_CHANNEL_0
esp_rom_gpio_connect_out_signal(PULSE_IO, LEDC_LS_SIG_OUT1_IDX, 0, 0); // LEDC_TIMER_1, LEDC_LOW_SPEED_MODE
esp_rom_gpio_connect_in_signal(PULSE_IO, PCNT_SIG_CH0_IN0_IDX, 0); // PCNT_UNIT_0, PCNT_CHANNEL_0
esp_rom_gpio_connect_in_signal(ctrl_level ? GPIO_MATRIX_CONST_ONE_INPUT: GPIO_MATRIX_CONST_ZERO_INPUT, PCNT_CTRL_CH0_IN0_IDX, 0); // PCNT_UNIT_0, PCNT_CHANNEL_0
}
/* use LEDC to produce pulse for PCNT

5
components/driver/test/test_rmt.c
View file

@ -10,6 +10,7 @@
#include "ir_tools.h"
#include "unity.h"
#include "test_utils.h"
#include "esp_rom_gpio.h"
// CI ONLY: Don't connect any other signals to this GPIO
#define RMT_DATA_IO (12) // bind signal RMT_SIG_OUT0_IDX and RMT_SIG_IN0_IDX on the same GPIO
@ -61,8 +62,8 @@ static void rmt_setup_testbench(int tx_channel, int rx_channel, uint32_t flags)
// Routing internal signals by IO Matrix (bind rmt tx and rx signal on the same GPIO)
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[RMT_DATA_IO], PIN_FUNC_GPIO);
TEST_ESP_OK(gpio_set_direction(RMT_DATA_IO, GPIO_MODE_INPUT_OUTPUT));
gpio_matrix_out(RMT_DATA_IO, RMT_SIG_OUT0_IDX + tx_channel, 0, 0);
gpio_matrix_in(RMT_DATA_IO, RMT_SIG_IN0_IDX + rx_channel, 0);
esp_rom_gpio_connect_out_signal(RMT_DATA_IO, RMT_SIG_OUT0_IDX + tx_channel, 0, 0);
esp_rom_gpio_connect_in_signal(RMT_DATA_IO, RMT_SIG_IN0_IDX + rx_channel, 0);
// install driver
if (tx_channel >= 0) {

5
components/driver/test/test_spi_slave.c
View file

@ -10,6 +10,7 @@
#include "esp_log.h"
#include "sdkconfig.h"
#include "test/test_common_spi.h"
#include "esp_rom_gpio.h"
#ifndef CONFIG_SPIRAM
//This test should be removed once the timing test is merged.
@ -20,8 +21,8 @@
static inline void int_connect( uint32_t gpio, uint32_t sigo, uint32_t sigi )
{
gpio_matrix_out( gpio, sigo, false, false );
gpio_matrix_in( gpio, sigi, false );
esp_rom_gpio_connect_out_signal( gpio, sigo, false, false );
esp_rom_gpio_connect_in_signal( gpio, sigi, false );
}
static void master_init_nodma( spi_device_handle_t* spi)

17
components/driver/twai.c
View file

@ -28,6 +28,7 @@
#include "driver/twai.h"
#include "soc/twai_periph.h"
#include "hal/twai_hal.h"
#include "esp_rom_gpio.h"
/* ---------------------------- Definitions --------------------------------- */
//Internal Macros
@ -302,27 +303,27 @@ static void twai_configure_gpio(gpio_num_t tx, gpio_num_t rx, gpio_num_t clkout,
{
//Set TX pin
gpio_set_pull_mode(tx, GPIO_FLOATING);
gpio_matrix_out(tx, TWAI_TX_IDX, false, false);
gpio_pad_select_gpio(tx);
esp_rom_gpio_connect_out_signal(tx, TWAI_TX_IDX, false, false);
esp_rom_gpio_pad_select_gpio(tx);
//Set RX pin
gpio_set_pull_mode(rx, GPIO_FLOATING);
gpio_matrix_in(rx, TWAI_RX_IDX, false);
gpio_pad_select_gpio(rx);
esp_rom_gpio_connect_in_signal(rx, TWAI_RX_IDX, false);
esp_rom_gpio_pad_select_gpio(rx);
gpio_set_direction(rx, GPIO_MODE_INPUT);
//Configure output clock pin (Optional)
if (clkout >= 0 && clkout < GPIO_NUM_MAX) {
gpio_set_pull_mode(clkout, GPIO_FLOATING);
gpio_matrix_out(clkout, TWAI_CLKOUT_IDX, false, false);
gpio_pad_select_gpio(clkout);
esp_rom_gpio_connect_out_signal(clkout, TWAI_CLKOUT_IDX, false, false);
esp_rom_gpio_pad_select_gpio(clkout);
}
//Configure bus status pin (Optional)
if (bus_status >= 0 && bus_status < GPIO_NUM_MAX) {
gpio_set_pull_mode(bus_status, GPIO_FLOATING);
gpio_matrix_out(bus_status, TWAI_BUS_OFF_ON_IDX, false, false);
gpio_pad_select_gpio(bus_status);
esp_rom_gpio_connect_out_signal(bus_status, TWAI_BUS_OFF_ON_IDX, false, false);
esp_rom_gpio_pad_select_gpio(bus_status);
}
}

9
components/driver/uart.c
View file

@ -29,6 +29,7 @@
#include "driver/uart_select.h"
#include "driver/periph_ctrl.h"
#include "sdkconfig.h"
#include "esp_rom_gpio.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/clk.h"
@ -564,24 +565,24 @@ esp_err_t uart_set_pin(uart_port_t uart_num, int tx_io_num, int rx_io_num, int r
if(tx_io_num >= 0) {
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[tx_io_num], PIN_FUNC_GPIO);
gpio_set_level(tx_io_num, 1);
gpio_matrix_out(tx_io_num, uart_periph_signal[uart_num].tx_sig, 0, 0);
esp_rom_gpio_connect_out_signal(tx_io_num, uart_periph_signal[uart_num].tx_sig, 0, 0);
}
if(rx_io_num >= 0) {
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[rx_io_num], PIN_FUNC_GPIO);
gpio_set_pull_mode(rx_io_num, GPIO_PULLUP_ONLY);
gpio_set_direction(rx_io_num, GPIO_MODE_INPUT);
gpio_matrix_in(rx_io_num, uart_periph_signal[uart_num].rx_sig, 0);
esp_rom_gpio_connect_in_signal(rx_io_num, uart_periph_signal[uart_num].rx_sig, 0);
}
if(rts_io_num >= 0) {
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[rts_io_num], PIN_FUNC_GPIO);
gpio_set_direction(rts_io_num, GPIO_MODE_OUTPUT);
gpio_matrix_out(rts_io_num, uart_periph_signal[uart_num].rts_sig, 0, 0);
esp_rom_gpio_connect_out_signal(rts_io_num, uart_periph_signal[uart_num].rts_sig, 0, 0);
}
if(cts_io_num >= 0) {
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[cts_io_num], PIN_FUNC_GPIO);
gpio_set_pull_mode(cts_io_num, GPIO_PULLUP_ONLY);
gpio_set_direction(cts_io_num, GPIO_MODE_INPUT);
gpio_matrix_in(cts_io_num, uart_periph_signal[uart_num].cts_sig, 0);
esp_rom_gpio_connect_in_signal(cts_io_num, uart_periph_signal[uart_num].cts_sig, 0);
}
return ESP_OK;
}

65
components/esp32/spiram_psram.c
View file

@ -24,9 +24,7 @@
#include "esp_types.h"
#include "esp_log.h"
#include "spiram_psram.h"
#include "esp32/rom/ets_sys.h"
#include "esp32/rom/spi_flash.h"
#include "esp32/rom/gpio.h"
#include "esp32/rom/cache.h"
#include "esp32/rom/efuse.h"
#include "soc/dport_reg.h"
@ -36,6 +34,7 @@
#include "driver/spi_common_internal.h"
#include "driver/periph_ctrl.h"
#include "bootloader_common.h"
#include "esp_rom_gpio.h"
#if CONFIG_SPIRAM
#include "soc/rtc.h"
@ -557,12 +556,12 @@ static esp_err_t IRAM_ATTR psram_2t_mode_enable(psram_spi_num_t spi_num)
// send 128 cycles clock
// send 1 bit high levle in ninth clock from the back to PSRAM SIO1
GPIO_OUTPUT_SET(D0WD_PSRAM_CS_IO, 1);
gpio_matrix_out(D0WD_PSRAM_CS_IO, SIG_GPIO_OUT_IDX, 0, 0);
esp_rom_gpio_connect_out_signal(D0WD_PSRAM_CS_IO, SIG_GPIO_OUT_IDX, 0, 0);
gpio_matrix_out(PSRAM_SPID_SD1_IO, SPIQ_OUT_IDX, 0, 0);
gpio_matrix_in(PSRAM_SPID_SD1_IO, SPIQ_IN_IDX, 0);
gpio_matrix_out(PSRAM_SPIQ_SD0_IO, SPID_OUT_IDX, 0, 0);
gpio_matrix_in(PSRAM_SPIQ_SD0_IO, SPID_IN_IDX, 0);
esp_rom_gpio_connect_out_signal(PSRAM_SPID_SD1_IO, SPIQ_OUT_IDX, 0, 0);
esp_rom_gpio_connect_in_signal(PSRAM_SPID_SD1_IO, SPIQ_IN_IDX, 0);
esp_rom_gpio_connect_out_signal(PSRAM_SPIQ_SD0_IO, SPID_OUT_IDX, 0, 0);
esp_rom_gpio_connect_in_signal(PSRAM_SPIQ_SD0_IO, SPID_IN_IDX, 0);
uint32_t w_data_2t[4] = {0x0, 0x0, 0x0, 0x00010000};
@ -576,12 +575,12 @@ static esp_err_t IRAM_ATTR psram_2t_mode_enable(psram_spi_num_t spi_num)
psram_cmd_recv_start(spi_num, NULL, 0, PSRAM_CMD_SPI);
psram_cmd_end(spi_num);
gpio_matrix_out(PSRAM_SPIQ_SD0_IO, SPIQ_OUT_IDX, 0, 0);
gpio_matrix_in(PSRAM_SPIQ_SD0_IO, SPIQ_IN_IDX, 0);
gpio_matrix_out(PSRAM_SPID_SD1_IO, SPID_OUT_IDX, 0, 0);
gpio_matrix_in(PSRAM_SPID_SD1_IO, SPID_IN_IDX, 0);
esp_rom_gpio_connect_out_signal(PSRAM_SPIQ_SD0_IO, SPIQ_OUT_IDX, 0, 0);
esp_rom_gpio_connect_in_signal(PSRAM_SPIQ_SD0_IO, SPIQ_IN_IDX, 0);
esp_rom_gpio_connect_out_signal(PSRAM_SPID_SD1_IO, SPID_OUT_IDX, 0, 0);
esp_rom_gpio_connect_in_signal(PSRAM_SPID_SD1_IO, SPID_IN_IDX, 0);
gpio_matrix_out(D0WD_PSRAM_CS_IO, SPICS1_OUT_IDX, 0, 0);
esp_rom_gpio_connect_out_signal(D0WD_PSRAM_CS_IO, SPICS1_OUT_IDX, 0, 0);
// setp4: send cmd 0x5f
// send one more bit clock after send cmd
@ -733,16 +732,16 @@ static void IRAM_ATTR psram_gpio_config(psram_io_t *psram_io, psram_cache_mode_t
// In bootloader, all the signals are already configured,
// We keep the following code in case the bootloader is some older version.
gpio_matrix_out(psram_io->flash_cs_io, SPICS0_OUT_IDX, 0, 0);
gpio_matrix_out(psram_io->psram_cs_io, SPICS1_OUT_IDX, 0, 0);
gpio_matrix_out(psram_io->psram_spiq_sd0_io, SPIQ_OUT_IDX, 0, 0);
gpio_matrix_in(psram_io->psram_spiq_sd0_io, SPIQ_IN_IDX, 0);
gpio_matrix_out(psram_io->psram_spid_sd1_io, SPID_OUT_IDX, 0, 0);
gpio_matrix_in(psram_io->psram_spid_sd1_io, SPID_IN_IDX, 0);
gpio_matrix_out(psram_io->psram_spiwp_sd3_io, SPIWP_OUT_IDX, 0, 0);
gpio_matrix_in(psram_io->psram_spiwp_sd3_io, SPIWP_IN_IDX, 0);
gpio_matrix_out(psram_io->psram_spihd_sd2_io, SPIHD_OUT_IDX, 0, 0);
gpio_matrix_in(psram_io->psram_spihd_sd2_io, SPIHD_IN_IDX, 0);
esp_rom_gpio_connect_out_signal(psram_io->flash_cs_io, SPICS0_OUT_IDX, 0, 0);
esp_rom_gpio_connect_out_signal(psram_io->psram_cs_io, SPICS1_OUT_IDX, 0, 0);
esp_rom_gpio_connect_out_signal(psram_io->psram_spiq_sd0_io, SPIQ_OUT_IDX, 0, 0);
esp_rom_gpio_connect_in_signal(psram_io->psram_spiq_sd0_io, SPIQ_IN_IDX, 0);
esp_rom_gpio_connect_out_signal(psram_io->psram_spid_sd1_io, SPID_OUT_IDX, 0, 0);
esp_rom_gpio_connect_in_signal(psram_io->psram_spid_sd1_io, SPID_IN_IDX, 0);
esp_rom_gpio_connect_out_signal(psram_io->psram_spiwp_sd3_io, SPIWP_OUT_IDX, 0, 0);
esp_rom_gpio_connect_in_signal(psram_io->psram_spiwp_sd3_io, SPIWP_IN_IDX, 0);
esp_rom_gpio_connect_out_signal(psram_io->psram_spihd_sd2_io, SPIHD_OUT_IDX, 0, 0);
esp_rom_gpio_connect_in_signal(psram_io->psram_spihd_sd2_io, SPIHD_IN_IDX, 0);
//select pin function gpio
if ((psram_io->flash_clk_io == SPI_IOMUX_PIN_NUM_CLK) && (psram_io->flash_clk_io != psram_io->psram_clk_io)) {
@ -871,7 +870,7 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad
switch (mode) {
case PSRAM_CACHE_F80M_S80M:
gpio_matrix_out(psram_io.psram_clk_io, SPICLK_OUT_IDX, 0, 0);
esp_rom_gpio_connect_out_signal(psram_io.psram_clk_io, SPICLK_OUT_IDX, 0, 0);
break;
case PSRAM_CACHE_F80M_S40M:
case PSRAM_CACHE_F40M_S40M:
@ -883,13 +882,13 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad
silicon) as a temporary pad for this. So the signal path is:
SPI CLK --> GPIO28 --> signal224(in then out) --> internal GPIO29 --> signal225(in then out) --> GPIO17(PSRAM CLK)
*/
gpio_matrix_out(PSRAM_INTERNAL_IO_28, SPICLK_OUT_IDX, 0, 0);
gpio_matrix_in(PSRAM_INTERNAL_IO_28, SIG_IN_FUNC224_IDX, 0);
gpio_matrix_out(PSRAM_INTERNAL_IO_29, SIG_IN_FUNC224_IDX, 0, 0);
gpio_matrix_in(PSRAM_INTERNAL_IO_29, SIG_IN_FUNC225_IDX, 0);
gpio_matrix_out(psram_io.psram_clk_io, SIG_IN_FUNC225_IDX, 0, 0);
esp_rom_gpio_connect_out_signal(PSRAM_INTERNAL_IO_28, SPICLK_OUT_IDX, 0, 0);
esp_rom_gpio_connect_in_signal(PSRAM_INTERNAL_IO_28, SIG_IN_FUNC224_IDX, 0);
esp_rom_gpio_connect_out_signal(PSRAM_INTERNAL_IO_29, SIG_IN_FUNC224_IDX, 0, 0);
esp_rom_gpio_connect_in_signal(PSRAM_INTERNAL_IO_29, SIG_IN_FUNC225_IDX, 0);
esp_rom_gpio_connect_out_signal(psram_io.psram_clk_io, SIG_IN_FUNC225_IDX, 0, 0);
} else {
gpio_matrix_out(psram_io.psram_clk_io, SPICLK_OUT_IDX, 0, 0);
esp_rom_gpio_connect_out_signal(psram_io.psram_clk_io, SPICLK_OUT_IDX, 0, 0);
}
break;
}
@ -930,7 +929,7 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad
if (!r) {
return ESP_ERR_INVALID_STATE;
}
gpio_matrix_out(psram_io.psram_clk_io, PSRAM_CLK_SIGNAL, 0, 0);
esp_rom_gpio_connect_out_signal(psram_io.psram_clk_io, PSRAM_CLK_SIGNAL, 0, 0);
//use spi3 clock,but use spi1 data/cs wires
//We get a solid 80MHz clock from SPI3 by setting it up, starting a transaction, waiting until it
//is in progress, then cutting the clock (but not the reset!) to that peripheral.
@ -949,9 +948,9 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad
} else {
// For other psram, we don't need any extra clock cycles after cs get back to high level
s_clk_mode = PSRAM_CLK_MODE_NORM;
gpio_matrix_out(PSRAM_INTERNAL_IO_28, SIG_GPIO_OUT_IDX, 0, 0);
gpio_matrix_out(PSRAM_INTERNAL_IO_29, SIG_GPIO_OUT_IDX, 0, 0);
gpio_matrix_out(psram_io.psram_clk_io, SPICLK_OUT_IDX, 0, 0);
esp_rom_gpio_connect_out_signal(PSRAM_INTERNAL_IO_28, SIG_GPIO_OUT_IDX, 0, 0);
esp_rom_gpio_connect_out_signal(PSRAM_INTERNAL_IO_29, SIG_GPIO_OUT_IDX, 0, 0);
esp_rom_gpio_connect_out_signal(psram_io.psram_clk_io, SPICLK_OUT_IDX, 0, 0);
}
// Update cs timing according to psram driving method.

2
components/esp32/test/test_ahb_arb.c
View file

@ -2,9 +2,7 @@
#include <esp_types.h>
#include <stdio.h>
#include <stdlib.h>
#include "esp32/rom/ets_sys.h"
#include "esp32/rom/lldesc.h"
#include "esp32/rom/gpio.h"
#include "driver/periph_ctrl.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"

2
components/esp32/test/test_unal_dma.c
View file

@ -3,9 +3,7 @@
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "esp32/rom/ets_sys.h"
#include "esp32/rom/lldesc.h"
#include "esp32/rom/gpio.h"
#include "driver/periph_ctrl.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"

2
components/esp32s2/spiram_psram.c
View file

@ -27,7 +27,6 @@
#include "esp32s2/rom/ets_sys.h"
#include "esp32s2/rom/spi_flash.h"
#include "esp32s2/rom/opi_flash.h"
#include "esp32s2/rom/gpio.h"
#include "esp32s2/rom/cache.h"
#include "esp32s2/rom/efuse.h"
#include "soc/dport_reg.h"
@ -35,7 +34,6 @@
#include "soc/spi_caps.h"
#include "soc/io_mux_reg.h"
#include "soc/apb_ctrl_reg.h"
#include "soc/gpio_sig_map.h"
#include "soc/efuse_reg.h"
#include "soc/soc.h"
#include "driver/gpio.h"

3
components/esp_eth/src/esp_eth_mac_dm9051.c
View file

@ -28,6 +28,7 @@
#include "hal/cpu_hal.h"
#include "dm9051.h"
#include "sdkconfig.h"
#include "esp_rom_gpio.h"
static const char *TAG = "emac_dm9051";
#define MAC_CHECK(a, str, goto_tag, ret_value, ...) \
@ -676,7 +677,7 @@ static esp_err_t emac_dm9051_init(esp_eth_mac_t *mac)
esp_err_t ret = ESP_OK;
emac_dm9051_t *emac = __containerof(mac, emac_dm9051_t, parent);
esp_eth_mediator_t *eth = emac->eth;
gpio_pad_select_gpio(emac->int_gpio_num);
esp_rom_gpio_pad_select_gpio(emac->int_gpio_num);
gpio_set_direction(emac->int_gpio_num, GPIO_MODE_INPUT);
gpio_set_pull_mode(emac->int_gpio_num, GPIO_PULLDOWN_ONLY);
gpio_set_intr_type(emac->int_gpio_num, GPIO_INTR_POSEDGE);

7
components/esp_eth/src/esp_eth_mac_esp32.c
View file

@ -30,6 +30,7 @@
#include "hal/emac.h"
#include "soc/soc.h"
#include "sdkconfig.h"
#include "esp_rom_gpio.h"
static const char *TAG = "emac_esp32";
#define MAC_CHECK(a, str, goto_tag, ret_value, ...) \
@ -275,12 +276,12 @@ static void emac_esp32_init_smi_gpio(emac_esp32_t *emac)
{
/* Setup SMI MDC GPIO */
gpio_set_direction(emac->smi_mdc_gpio_num, GPIO_MODE_OUTPUT);
gpio_matrix_out(emac->smi_mdc_gpio_num, EMAC_MDC_O_IDX, false, false);
esp_rom_gpio_connect_out_signal(emac->smi_mdc_gpio_num, EMAC_MDC_O_IDX, false, false);
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[emac->smi_mdc_gpio_num], PIN_FUNC_GPIO);
/* Setup SMI MDIO GPIO */
gpio_set_direction(emac->smi_mdio_gpio_num, GPIO_MODE_INPUT_OUTPUT);
gpio_matrix_out(emac->smi_mdio_gpio_num, EMAC_MDO_O_IDX, false, false);
gpio_matrix_in(emac->smi_mdio_gpio_num, EMAC_MDI_I_IDX, false);
esp_rom_gpio_connect_out_signal(emac->smi_mdio_gpio_num, EMAC_MDO_O_IDX, false, false);
esp_rom_gpio_connect_in_signal(emac->smi_mdio_gpio_num, EMAC_MDI_I_IDX, false);
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[emac->smi_mdio_gpio_num], PIN_FUNC_GPIO);
}

3
components/esp_eth/src/esp_eth_phy_dm9051.c
View file

@ -20,6 +20,7 @@
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "driver/gpio.h"
#include "esp_rom_gpio.h"
static const char *TAG = "dm9051";
#define PHY_CHECK(a, str, goto_tag, ...) \
@ -189,7 +190,7 @@ static esp_err_t dm9051_reset_hw(esp_eth_phy_t *phy)
phy_dm9051_t *dm9051 = __containerof(phy, phy_dm9051_t, parent);
// set reset_gpio_num minus zero can skip hardware reset phy chip
if (dm9051->reset_gpio_num >= 0) {
gpio_pad_select_gpio(dm9051->reset_gpio_num);
esp_rom_gpio_pad_select_gpio(dm9051->reset_gpio_num);
gpio_set_direction(dm9051->reset_gpio_num, GPIO_MODE_OUTPUT);
gpio_set_level(dm9051->reset_gpio_num, 0);
gpio_set_level(dm9051->reset_gpio_num, 1);

3
components/esp_eth/src/esp_eth_phy_dp83848.c
View file

@ -20,6 +20,7 @@
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "driver/gpio.h"
#include "esp_rom_gpio.h"
static const char *TAG = "dp83848";
#define PHY_CHECK(a, str, goto_tag, ...) \
@ -178,7 +179,7 @@ static esp_err_t dp83848_reset_hw(esp_eth_phy_t *phy)
{
phy_dp83848_t *dp83848 = __containerof(phy, phy_dp83848_t, parent);
if (dp83848->reset_gpio_num >= 0) {
gpio_pad_select_gpio(dp83848->reset_gpio_num);
esp_rom_gpio_pad_select_gpio(dp83848->reset_gpio_num);
gpio_set_direction(dp83848->reset_gpio_num, GPIO_MODE_OUTPUT);
gpio_set_level(dp83848->reset_gpio_num, 0);
gpio_set_level(dp83848->reset_gpio_num, 1);

3
components/esp_eth/src/esp_eth_phy_ip101.c
View file

@ -20,6 +20,7 @@
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "driver/gpio.h"
#include "esp_rom_gpio.h"
static const char *TAG = "ip101";
#define PHY_CHECK(a, str, goto_tag, ...) \
@ -218,7 +219,7 @@ static esp_err_t ip101_reset_hw(esp_eth_phy_t *phy)
{
phy_ip101_t *ip101 = __containerof(phy, phy_ip101_t, parent);
if (ip101->reset_gpio_num >= 0) {
gpio_pad_select_gpio(ip101->reset_gpio_num);
esp_rom_gpio_pad_select_gpio(ip101->reset_gpio_num);
gpio_set_direction(ip101->reset_gpio_num, GPIO_MODE_OUTPUT);
gpio_set_level(ip101->reset_gpio_num, 0);
gpio_set_level(ip101->reset_gpio_num, 1);

3
components/esp_eth/src/esp_eth_phy_lan8720.c
View file

@ -20,6 +20,7 @@
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "driver/gpio.h"
#include "esp_rom_gpio.h"
static const char *TAG = "lan8720";
#define PHY_CHECK(a, str, goto_tag, ...) \
@ -263,7 +264,7 @@ static esp_err_t lan8720_reset_hw(esp_eth_phy_t *phy)
{
phy_lan8720_t *lan8720 = __containerof(phy, phy_lan8720_t, parent);
if (lan8720->reset_gpio_num >= 0) {
gpio_pad_select_gpio(lan8720->reset_gpio_num);
esp_rom_gpio_pad_select_gpio(lan8720->reset_gpio_num);
gpio_set_direction(lan8720->reset_gpio_num, GPIO_MODE_OUTPUT);
gpio_set_level(lan8720->reset_gpio_num, 0);
gpio_set_level(lan8720->reset_gpio_num, 1);

3
components/esp_eth/src/esp_eth_phy_rtl8201.c
View file

@ -21,6 +21,7 @@
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "driver/gpio.h"
#include "esp_rom_gpio.h"
static const char *TAG = "rtl8201";
#define PHY_CHECK(a, str, goto_tag, ...) \
@ -172,7 +173,7 @@ static esp_err_t rtl8201_reset_hw(esp_eth_phy_t *phy)
{
phy_rtl8201_t *rtl8201 = __containerof(phy, phy_rtl8201_t, parent);
if (rtl8201->reset_gpio_num >= 0) {
gpio_pad_select_gpio(rtl8201->reset_gpio_num);
esp_rom_gpio_pad_select_gpio(rtl8201->reset_gpio_num);
gpio_set_direction(rtl8201->reset_gpio_num, GPIO_MODE_OUTPUT);
gpio_set_level(rtl8201->reset_gpio_num, 0);
gpio_set_level(rtl8201->reset_gpio_num, 1);

7
components/esp_rom/esp32/ld/esp32.rom.api.ld
View file

@ -8,3 +8,10 @@ PROVIDE ( esp_rom_crc8_le = crc8_le );
PROVIDE ( esp_rom_crc32_be = crc32_be );
PROVIDE ( esp_rom_crc16_be = crc16_be );
PROVIDE ( esp_rom_crc8_be = crc8_be );
PROVIDE ( esp_rom_gpio_pad_select_gpio = gpio_pad_select_gpio );
PROVIDE ( esp_rom_gpio_pad_pullup_only = gpio_pad_pullup );
PROVIDE ( esp_rom_gpio_pad_set_drv = gpio_pad_set_drv );
PROVIDE ( esp_rom_gpio_pad_unhold = gpio_pad_unhold );
PROVIDE ( esp_rom_gpio_connect_in_signal = gpio_matrix_in );
PROVIDE ( esp_rom_gpio_connect_out_signal = gpio_matrix_out );

7
components/esp_rom/esp32s2/ld/esp32s2.rom.api.ld
View file

@ -5,3 +5,10 @@
PROVIDE ( esp_rom_crc32_le = crc32_le );
PROVIDE ( esp_rom_crc16_le = crc16_le );
PROVIDE ( esp_rom_crc8_le = crc8_le );
PROVIDE ( esp_rom_gpio_pad_select_gpio = gpio_pad_select_gpio );
PROVIDE ( esp_rom_gpio_pad_pullup_only = gpio_pad_pullup );
PROVIDE ( esp_rom_gpio_pad_set_drv = gpio_pad_set_drv );
PROVIDE ( esp_rom_gpio_pad_unhold = gpio_pad_unhold );
PROVIDE ( esp_rom_gpio_connect_in_signal = gpio_matrix_in );
PROVIDE ( esp_rom_gpio_connect_out_signal = gpio_matrix_out );

7
components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld
View file

@ -8,3 +8,10 @@ PROVIDE ( esp_rom_crc8_le = crc8_le );
PROVIDE ( esp_rom_crc32_be = crc32_be );
PROVIDE ( esp_rom_crc16_be = crc16_be );
PROVIDE ( esp_rom_crc8_be = crc8_be );
PROVIDE ( esp_rom_gpio_pad_select_gpio = gpio_pad_select_gpio );
PROVIDE ( esp_rom_gpio_pad_pullup_only = gpio_pad_pullup );
PROVIDE ( esp_rom_gpio_pad_set_drv = gpio_pad_set_drv );
PROVIDE ( esp_rom_gpio_pad_unhold = gpio_pad_unhold );
PROVIDE ( esp_rom_gpio_connect_in_signal = gpio_matrix_in );
PROVIDE ( esp_rom_gpio_connect_out_signal = gpio_matrix_out );

87
components/esp_rom/include/esp_rom_gpio.h Normal file
View file

@ -0,0 +1,87 @@
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stdbool.h>
#include "sdkconfig.h"
/**
* @brief Configure IO Pad as General Purpose IO,
* so that it can be connected to internal Matrix,
* then combined with one or more peripheral signals.
*
* @param iopad_num IO Pad number
*/
void esp_rom_gpio_pad_select_gpio(uint32_t iopad_num);
/**
* @brief Enable internal pull up, and disable internal pull down.
*
* @param iopad_num IO Pad number
*/
void esp_rom_gpio_pad_pullup_only(uint32_t iopad_num);
/**
* @brief Unhold the IO Pad.
* @note When the Pad is set to hold, the state is latched at that moment and won't get changed.
*
* @param iopad_num IP Pad number
*/
void esp_rom_gpio_pad_unhold(uint32_t gpio_num);
/**
* @brief Set IO Pad current drive capability.
*
* @param iopad_num IO Pad number
* @param drv Numeric to indicate the capability of current drive
* - 0: 5mA
* - 1: 10mA
* - 2: 20mA
* - 3: 40mA
*/
void esp_rom_gpio_pad_set_drv(uint32_t iopad_num, uint32_t drv);
/**
* @brief Combine a GPIO input with a peripheral signal, which tagged as input attribute.
*
* @note There's no limitation on the number of signals that a GPIO can combine with.
*
* @param gpio_num GPIO number, especially, `GPIO_MATRIX_CONST_ZERO_INPUT` means connect logic 0 to signal
* `GPIO_MATRIX_CONST_ONE_INPUT` means connect logic 1 to signal
* @param signal_idx Peripheral signal index (tagged as input attribute)
* @param inv Whether the GPIO input to be inverted or not
*/
void esp_rom_gpio_connect_in_signal(uint32_t gpio_num, uint32_t signal_idx, bool inv);
/**
* @brief Combine a peripheral signal which tagged as output attribute with a GPIO.
*
* @note There's no limitation on the number of signals that a GPIO can combine with.
*
* @param gpio_num GPIO number
* @param signal_idx Peripheral signal index (tagged as output attribute)
* @param out_inv Whether to signal to be inverted or not
* @param oen_inv Whether the output enable control is inverted or not
*/
void esp_rom_gpio_connect_out_signal(uint32_t gpio_num, uint32_t signal_idx, bool out_inv, bool oen_inv);
#ifdef __cplusplus
}
#endif

11
components/sdmmc/test/test_sd.c
View file

@ -15,6 +15,9 @@
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <sys/time.h>
#include <unistd.h>
#include "unity.h"
#include "driver/gpio.h"
#include "soc/soc_caps.h"
@ -26,9 +29,7 @@
#include "sdmmc_cmd.h"
#include "esp_log.h"
#include "esp_heap_caps.h"
#include <time.h>
#include <sys/time.h>
#include <unistd.h>
#include "esp_rom_gpio.h"
// Can't test eMMC (slot 0) and PSRAM together
#ifndef CONFIG_SPIRAM
@ -448,7 +449,7 @@ __attribute__((unused)) static void test_cd_input(int gpio_cd_num, const sdmmc_h
// SDMMC host should have configured CD as input.
// Enable output as well (not using the driver, to avoid touching input
// enable bits).
gpio_matrix_out(gpio_cd_num, SIG_GPIO_OUT_IDX, false, false);
esp_rom_gpio_connect_out_signal(gpio_cd_num, SIG_GPIO_OUT_IDX, false, false);
REG_WRITE(GPIO_ENABLE_W1TS_REG, BIT(gpio_cd_num));
// Check that card initialization fails if CD is high
@ -513,7 +514,7 @@ __attribute__((unused)) static void test_wp_input(int gpio_wp_num, const sdmmc_h
// SDMMC host should have configured WP as input.
// Enable output as well (not using the driver, to avoid touching input
// enable bits).
gpio_matrix_out(gpio_wp_num, SIG_GPIO_OUT_IDX, false, false);
esp_rom_gpio_connect_out_signal(gpio_wp_num, SIG_GPIO_OUT_IDX, false, false);
REG_WRITE(GPIO_ENABLE_W1TS_REG, BIT(gpio_wp_num));
// Check that the card can be initialized with WP low

3
components/soc/soc/esp32/include/soc/gpio_caps.h
View file

@ -43,6 +43,9 @@ extern "C" {
#define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) ((GPIO_IS_VALID_GPIO(gpio_num)) && (gpio_num < 34)) /*!< Check whether it can be a valid GPIO number of output mode */
#define GPIO_MASK_CONTAIN_INPUT_GPIO(gpio_mask) ((gpio_mask & (GPIO_SEL_34 | GPIO_SEL_35 | GPIO_SEL_36 | GPIO_SEL_37 | GPIO_SEL_38 | GPIO_SEL_39))) /*!< Check whether it contains input io */
#define GPIO_MATRIX_CONST_ONE_INPUT (0x38)
#define GPIO_MATRIX_CONST_ZERO_INPUT (0x30)
#ifdef __cplusplus
}
#endif

3
components/soc/soc/esp32s2/include/soc/gpio_caps.h
View file

@ -40,6 +40,9 @@ extern "C" {
#define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) ((GPIO_IS_VALID_GPIO(gpio_num)) && (gpio_num < 46)) /*!< Check whether it can be a valid GPIO number of output mode */
#define GPIO_MASK_CONTAIN_INPUT_GPIO(gpio_mask) ((gpio_mask & (GPIO_SEL_46))) /*!< Check whether it contains input io */
#define GPIO_MATRIX_CONST_ONE_INPUT (0x38)
#define GPIO_MATRIX_CONST_ZERO_INPUT (0x3C)
#ifdef __cplusplus
}
#endif

12
components/soc/soc/esp32s2/usb_periph.c
View file

@ -12,9 +12,8 @@
// See the License for the specific language governing permissions and
// limitations under the License.
#include "esp32s2/rom/gpio.h"
#include "soc/usb_periph.h"
#include "soc/gpio_caps.h"
const usb_iopin_dsc_t usb_periph_iopins[] = {
{USBPHY_VP_NUM, USB_EXTPHY_VP_IDX, 0, 1},
@ -23,11 +22,10 @@ const usb_iopin_dsc_t usb_periph_iopins[] = {
{USBPHY_OEN_NUM, USB_EXTPHY_OEN_IDX, 1, 1},
{USBPHY_VPO_NUM, USB_EXTPHY_VPO_IDX, 1, 1},
{USBPHY_VMO_NUM, USB_EXTPHY_VMO_IDX, 1, 1},
{GPIO_FUNC_IN_HIGH, USB_OTG_IDDIG_IN_IDX, 0, 0}, //connected connector is mini-B
// {GPIO_FUNC_IN_LOW, USB_OTG_IDDIG_IN_IDX, 0, 0},
{GPIO_MATRIX_CONST_ONE_INPUT, USB_OTG_IDDIG_IN_IDX, 0, 0}, //connected connector is mini-B
//connected connector is mini-B
{GPIO_FUNC_IN_HIGH, USB_SRP_BVALID_IN_IDX, 0, 0}, //HIGH to force USB device mode
{GPIO_FUNC_IN_HIGH, USB_OTG_VBUSVALID_IN_IDX, 0, 0}, //receiving a valid Vbus from host
{GPIO_FUNC_IN_LOW, USB_OTG_AVALID_IN_IDX, 0, 0},
{GPIO_MATRIX_CONST_ONE_INPUT, USB_SRP_BVALID_IN_IDX, 0, 0}, //HIGH to force USB device mode
{GPIO_MATRIX_CONST_ONE_INPUT, USB_OTG_VBUSVALID_IN_IDX, 0, 0}, //receiving a valid Vbus from host
{GPIO_MATRIX_CONST_ZERO_INPUT, USB_OTG_AVALID_IN_IDX, 0, 0},
{-1, -1, 0, 0}
};

25
components/soc/src/esp32/rtc_clk.c
View file

@ -19,13 +19,15 @@
#include "esp32/rom/ets_sys.h"
#include "esp32/rom/rtc.h"
#include "esp32/rom/uart.h"
#include "esp32/rom/gpio.h"
#include "esp_rom_gpio.h"
#include "soc/rtc.h"
#include "soc/rtc_periph.h"
#include "soc/sens_periph.h"
#include "soc/dport_reg.h"
#include "soc/efuse_periph.h"
#include "soc/apb_ctrl_reg.h"
#include "soc/gpio_struct.h"
#include "hal/gpio_ll.h"
#include "i2c_rtc_clk.h"
#include "soc_log.h"
#include "sdkconfig.h"
@ -174,22 +176,27 @@ void rtc_clk_32k_bootstrap(uint32_t cycle)
if (cycle){
const uint32_t pin_32 = 32;
const uint32_t pin_33 = 33;
const uint32_t mask_32 = (1 << (pin_32 - 32));
const uint32_t mask_33 = (1 << (pin_33 - 32));
gpio_pad_select_gpio(pin_32);
gpio_pad_select_gpio(pin_33);
gpio_output_set_high(mask_32, mask_33, mask_32 | mask_33, 0);
esp_rom_gpio_pad_select_gpio(pin_32);
esp_rom_gpio_pad_select_gpio(pin_33);
gpio_ll_output_enable(&GPIO, pin_32);
gpio_ll_output_enable(&GPIO, pin_33);
gpio_ll_set_level(&GPIO, pin_32, 1);
gpio_ll_set_level(&GPIO, pin_33, 0);
const uint32_t delay_us = (1000000 / RTC_SLOW_CLK_FREQ_32K / 2);
while(cycle){
gpio_output_set_high(mask_32, mask_33, mask_32 | mask_33, 0);
gpio_ll_set_level(&GPIO, pin_32, 1);
gpio_ll_set_level(&GPIO, pin_33, 0);
ets_delay_us(delay_us);
gpio_output_set_high(mask_33, mask_32, mask_32 | mask_33, 0);
gpio_ll_set_level(&GPIO, pin_33, 1);
gpio_ll_set_level(&GPIO, pin_32, 0);
ets_delay_us(delay_us);
cycle--;
}
gpio_output_set_high(0, 0, 0, mask_32 | mask_33); // disable pins
// disable pins
gpio_ll_output_disable(&GPIO, pin_32);
gpio_ll_output_disable(&GPIO, pin_33);
}
CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K);

1
components/soc/src/esp32/rtc_clk_init.c
View file

@ -19,7 +19,6 @@
#include "esp32/rom/ets_sys.h"
#include "esp32/rom/rtc.h"
#include "esp32/rom/uart.h"
#include "esp32/rom/gpio.h"
#include "soc/rtc.h"
#include "soc/rtc_periph.h"
#include "soc/sens_periph.h"

40
components/soc/src/esp32/soc_log.h
View file

@ -1,40 +0,0 @@
// Copyright 2016-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
/**
* @file soc_log.h
* @brief SOC library logging functions
*
* To make SOC library compatible with environments which don't use ESP-IDF,
* this header file provides wrappers for logging functions.
*/
#ifdef ESP_PLATFORM
#include "esp_log.h"
#define SOC_LOGE(tag, fmt, ...) ESP_EARLY_LOGE(tag, fmt, ##__VA_ARGS__)
#define SOC_LOGW(tag, fmt, ...) ESP_EARLY_LOGW(tag, fmt, ##__VA_ARGS__)
#define SOC_LOGI(tag, fmt, ...) ESP_EARLY_LOGI(tag, fmt, ##__VA_ARGS__)
#define SOC_LOGD(tag, fmt, ...) ESP_EARLY_LOGD(tag, fmt, ##__VA_ARGS__)
#define SOC_LOGV(tag, fmt, ...) ESP_EARLY_LOGV(tag, fmt, ##__VA_ARGS__)
#else
#include "esp32/rom/ets_sys.h"
#define SOC_LOGE(tag, fmt, ...) ets_printf("%s(err): " fmt, tag, ##__VA_ARGS__)
#define SOC_LOGW(tag, fmt, ...) ets_printf("%s(warn): " fmt, tag, ##__VA_ARGS__)
#define SOC_LOGI(tag, fmt, ...) ets_printf("%s(info): " fmt, tag, ##__VA_ARGS__)
#define SOC_LOGD(tag, fmt, ...) ets_printf("%s(dbg): " fmt, tag, ##__VA_ARGS__)
#define SOC_LOGV(tag, fmt, ...) ets_printf("%s: " fmt, tag, ##__VA_ARGS__)
#endif //ESP_PLATFORM

280
components/soc/src/esp32/test/test_rtc_clk.c
View file

@ -1,280 +0,0 @@
#include <stdio.h>
#include "unity.h"
#include "esp32/rom/ets_sys.h"
#include "esp32/rom/uart.h"
#include "soc/rtc.h"
#include "soc/rtc_periph.h"
#include "soc/sens_periph.h"
#include "soc/gpio_periph.h"
#include "driver/rtc_io.h"
#include "test_utils.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
#include "../esp_clk_internal.h"
#include "esp32/clk.h"
#define CALIBRATE_ONE(cali_clk) calibrate_one(cali_clk, #cali_clk)
static uint32_t calibrate_one(rtc_cal_sel_t cal_clk, const char* name)
{
const uint32_t cal_count = 1000;
const float factor = (1 << 19) * 1000.0f;
uint32_t cali_val;
printf("%s:\n", name);
for (int i = 0; i < 5; ++i) {
printf("calibrate (%d): ", i);
cali_val = rtc_clk_cal(cal_clk, cal_count);
printf("%.3f kHz\n", factor / (float) cali_val);
}
return cali_val;
}
TEST_CASE("RTC_SLOW_CLK sources calibration", "[rtc_clk]")
{
rtc_clk_32k_enable(true);
rtc_clk_8m_enable(true, true);
CALIBRATE_ONE(RTC_CAL_RTC_MUX);
CALIBRATE_ONE(RTC_CAL_8MD256);
uint32_t cal_32k = CALIBRATE_ONE(RTC_CAL_32K_XTAL);
if (cal_32k == 0) {
printf("32K XTAL OSC has not started up");
} else {
printf("switching to RTC_SLOW_FREQ_32K_XTAL: ");
rtc_clk_slow_freq_set(RTC_SLOW_FREQ_32K_XTAL);
printf("done\n");
CALIBRATE_ONE(RTC_CAL_RTC_MUX);
CALIBRATE_ONE(RTC_CAL_8MD256);
CALIBRATE_ONE(RTC_CAL_32K_XTAL);
}
printf("switching to RTC_SLOW_FREQ_8MD256: ");
rtc_clk_slow_freq_set(RTC_SLOW_FREQ_8MD256);
printf("done\n");
CALIBRATE_ONE(RTC_CAL_RTC_MUX);
CALIBRATE_ONE(RTC_CAL_8MD256);
CALIBRATE_ONE(RTC_CAL_32K_XTAL);
}
/* The following two are not unit tests, but are added here to make it easy to
* check the frequency of 150k/32k oscillators. The following two "tests" will
* output either 32k or 150k clock to GPIO25.
*/
static void pull_out_clk(int sel)
{
REG_SET_BIT(RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_MUX_SEL_M);
REG_CLR_BIT(RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_RDE_M | RTC_IO_PDAC1_RUE_M);
REG_SET_FIELD(RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_FUN_SEL, 1);
REG_SET_FIELD(SENS_SAR_DAC_CTRL1_REG, SENS_DEBUG_BIT_SEL, 0);
REG_SET_FIELD(RTC_IO_RTC_DEBUG_SEL_REG, RTC_IO_DEBUG_SEL0, sel);
}
TEST_CASE("Output 150k clock to GPIO25", "[rtc_clk][ignore]")
{
pull_out_clk(RTC_IO_DEBUG_SEL0_150K_OSC);
}
TEST_CASE("Output 32k XTAL clock to GPIO25", "[rtc_clk][ignore]")
{
rtc_clk_32k_enable(true);
pull_out_clk(RTC_IO_DEBUG_SEL0_32K_XTAL);
}
TEST_CASE("Output 8M XTAL clock to GPIO25", "[rtc_clk][ignore]")
{
rtc_clk_8m_enable(true, true);
SET_PERI_REG_MASK(RTC_IO_RTC_DEBUG_SEL_REG, RTC_IO_DEBUG_12M_NO_GATING);
pull_out_clk(RTC_IO_DEBUG_SEL0_8M);
}
static void test_clock_switching(void (*switch_func)(const rtc_cpu_freq_config_t* config))
{
uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
const int test_duration_sec = 10;
ref_clock_init();
uint64_t t_start = ref_clock_get();
rtc_cpu_freq_config_t cur_config;
rtc_clk_cpu_freq_get_config(&cur_config);
rtc_cpu_freq_config_t xtal_config;
rtc_clk_cpu_freq_mhz_to_config((uint32_t) rtc_clk_xtal_freq_get(), &xtal_config);
int count = 0;
while (ref_clock_get() - t_start < test_duration_sec * 1000000) {
switch_func(&xtal_config);
switch_func(&cur_config);
++count;
}
uint64_t t_end = ref_clock_get();
printf("Switch count: %d. Average time to switch PLL -> XTAL -> PLL: %d us\n", count, (int) ((t_end - t_start) / count));
ref_clock_deinit();
}
TEST_CASE("Calculate 8M clock frequency", "[rtc_clk]")
{
// calibrate 8M/256 clock against XTAL, get 8M/256 clock period
uint32_t rtc_8md256_period = rtc_clk_cal(RTC_CAL_8MD256, 100);
uint32_t rtc_fast_freq_hz = 1000000ULL * (1 << RTC_CLK_CAL_FRACT) * 256 / rtc_8md256_period;
printf("RTC_FAST_CLK=%d Hz\n", rtc_fast_freq_hz);
TEST_ASSERT_INT32_WITHIN(500000, RTC_FAST_CLK_FREQ_APPROX, rtc_fast_freq_hz);
}
TEST_CASE("Test switching between PLL and XTAL", "[rtc_clk]")
{
test_clock_switching(rtc_clk_cpu_freq_set_config);
}
TEST_CASE("Test fast switching between PLL and XTAL", "[rtc_clk]")
{
test_clock_switching(rtc_clk_cpu_freq_set_config_fast);
}
#define COUNT_TEST 3
#define TIMEOUT_TEST_MS (5 + CONFIG_ESP32_RTC_CLK_CAL_CYCLES / 16)
void stop_rtc_external_quartz(void){
const uint8_t pin_32 = 32;
const uint8_t pin_33 = 33;
const uint8_t mask_32 = (1 << (pin_32 - 32));
const uint8_t mask_33 = (1 << (pin_33 - 32));
rtc_clk_32k_enable(false);
gpio_pad_select_gpio(pin_32);
gpio_pad_select_gpio(pin_33);
gpio_output_set_high(0, mask_32 | mask_33, mask_32 | mask_33, 0);
ets_delay_us(500000);
gpio_output_set_high(0, 0, 0, mask_32 | mask_33); // disable pins
}
static void start_freq(rtc_slow_freq_t required_src_freq, uint32_t start_delay_ms)
{
int i = 0, fail = 0;
uint32_t start_time;
uint32_t end_time;
rtc_slow_freq_t selected_src_freq;
stop_rtc_external_quartz();
#ifdef CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS
uint32_t bootstrap_cycles = CONFIG_ESP32_RTC_XTAL_BOOTSTRAP_CYCLES;
printf("Test is started. Kconfig settings:\n External 32K crystal is selected,\n Oscillation cycles = %d,\n Calibration cycles = %d.\n",
bootstrap_cycles,
CONFIG_ESP32_RTC_CLK_CAL_CYCLES);
#else
uint32_t bootstrap_cycles = 5;
printf("Test is started. Kconfig settings:\n Internal RC is selected,\n Oscillation cycles = %d,\n Calibration cycles = %d.\n",
bootstrap_cycles,
CONFIG_ESP32_RTC_CLK_CAL_CYCLES);
#endif
if (start_delay_ms == 0 && CONFIG_ESP32_RTC_CLK_CAL_CYCLES < 1500){
start_delay_ms = 50;
printf("Recommended increase Number of cycles for RTC_SLOW_CLK calibration to 3000!\n");
}
while(i < COUNT_TEST){
start_time = xTaskGetTickCount() * (1000 / configTICK_RATE_HZ);
i++;
printf("attempt #%d/%d...", i, COUNT_TEST);
rtc_clk_32k_bootstrap(bootstrap_cycles);
ets_delay_us(start_delay_ms * 1000);
rtc_clk_select_rtc_slow_clk();
selected_src_freq = rtc_clk_slow_freq_get();
end_time = xTaskGetTickCount() * (1000 / configTICK_RATE_HZ);
printf(" [time=%d] ", (end_time - start_time) - start_delay_ms);
if(selected_src_freq != required_src_freq){
printf("FAIL. Time measurement...");
fail = 1;
} else {
printf("PASS. Time measurement...");
}
uint64_t clk_rtc_time;
uint32_t fail_measure = 0;
for (int j = 0; j < 3; ++j) {
clk_rtc_time = esp_clk_rtc_time();
ets_delay_us(1000000);
uint64_t delta = esp_clk_rtc_time() - clk_rtc_time;
if (delta < 900000LL || delta > 1100000){
printf("FAIL");
fail = 1;
fail_measure = 1;
break;
}
}
if(fail_measure == 0) {
printf("PASS");
}
printf(" [calibration val = %d] \n", esp_clk_slowclk_cal_get());
stop_rtc_external_quartz();
ets_delay_us(500000);
}
TEST_ASSERT_MESSAGE(fail == 0, "Test failed");
printf("Test passed successfully\n");
}
TEST_CASE("Test starting external RTC quartz", "[rtc_clk][test_env=UT_T1_32kXTAL]")
{
int i = 0, fail = 0;
uint32_t start_time;
uint32_t end_time;
stop_rtc_external_quartz();
#ifdef CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS
uint32_t bootstrap_cycles = CONFIG_ESP32_RTC_XTAL_BOOTSTRAP_CYCLES;
printf("Test is started. Kconfig settings:\n External 32K crystal is selected,\n Oscillation cycles = %d,\n Calibration cycles = %d.\n",
bootstrap_cycles,
CONFIG_ESP32_RTC_CLK_CAL_CYCLES);
#else
uint32_t bootstrap_cycles = 5;
printf("Test is started. Kconfig settings:\n Internal RC is selected,\n Oscillation cycles = %d,\n Calibration cycles = %d.\n",
bootstrap_cycles,
CONFIG_ESP32_RTC_CLK_CAL_CYCLES);
#endif
if (CONFIG_ESP32_RTC_CLK_CAL_CYCLES < 1500){
printf("Recommended increase Number of cycles for RTC_SLOW_CLK calibration to 3000!\n");
}
while(i < COUNT_TEST){
start_time = xTaskGetTickCount() * (1000 / configTICK_RATE_HZ);
i++;
printf("attempt #%d/%d...", i, COUNT_TEST);
rtc_clk_32k_bootstrap(bootstrap_cycles);
rtc_clk_select_rtc_slow_clk();
end_time = xTaskGetTickCount() * (1000 / configTICK_RATE_HZ);
printf(" [time=%d] ", end_time - start_time);
if((end_time - start_time) > TIMEOUT_TEST_MS){
printf("FAIL\n");
fail = 1;
} else {
printf("PASS\n");
}
stop_rtc_external_quartz();
ets_delay_us(100000);
}
TEST_ASSERT_MESSAGE(fail == 0, "Test failed");
printf("Test passed successfully\n");
}
TEST_CASE("Test starting 'External 32kHz XTAL' on the board with it.", "[rtc_clk][test_env=UT_T1_32kXTAL]")
{
start_freq(RTC_SLOW_FREQ_32K_XTAL, 200);
start_freq(RTC_SLOW_FREQ_32K_XTAL, 0);
}
TEST_CASE("Test starting 'External 32kHz XTAL' on the board without it.", "[rtc_clk][test_env=UT_T1_no32kXTAL]")
{
printf("Tries to start the 'External 32kHz XTAL' on the board without it. "
"Clock switching to 'Internal 150 kHz RC oscillator'.\n");
printf("This test will be successful for boards without an external crystal or non-working crystal. "
"First, there will be an attempt to start from the external crystal after a failure "
"will switch to the internal RC circuit. If the switch to the internal RC circuit "
"was successful then the test succeeded.\n");
start_freq(RTC_SLOW_FREQ_RTC, 200);
start_freq(RTC_SLOW_FREQ_RTC, 0);
}

2
components/soc/src/esp32s2/include/hal/gpio_ll.h
View file

@ -18,7 +18,7 @@
* See readme.md in soc/include/hal/readme.md
******************************************************************************/
// The LL layer for ESP32 GPIO register operations
// The LL layer for ESP32-S2 GPIO register operations
#pragma once

1
components/soc/src/esp32s2/rtc_clk.c
View file

@ -21,7 +21,6 @@
#include "esp32s2/rom/ets_sys.h"
#include "esp32s2/rom/rtc.h"
#include "esp32s2/rom/uart.h"
#include "esp32s2/rom/gpio.h"
#include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/rtc_io_reg.h"

1
components/soc/src/hal/gpio_hal.c
View file

@ -17,7 +17,6 @@
#include "soc/soc.h"
#include "soc/gpio_periph.h"
#include "hal/gpio_hal.h"
#include "esp32/rom/gpio.h"
void gpio_hal_intr_enable_on_core(gpio_hal_context_t *hal, gpio_num_t gpio_num, uint32_t core_id)
{

4
components/soc/test/component.mk
View file

@ -1,6 +1,4 @@
SOC_NAME := $(IDF_TARGET)
COMPONENT_SRCDIRS := $(SOC_NAME)
COMPONENT_SRCDIRS := .
COMPONENT_ADD_LDFLAGS = -Wl,--whole-archive -l$(COMPONENT_NAME) -Wl,--no-whole-archive

17
components/soc/test/test_rtc_clk.c
View file

@ -5,12 +5,13 @@
#include "soc/rtc_periph.h"
#include "soc/sens_periph.h"
#include "soc/gpio_periph.h"
#include "hal/gpio_ll.h"
#include "driver/rtc_io.h"
#include "test_utils.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
#include "esp_rom_gpio.h"
extern void rtc_clk_select_rtc_slow_clk(void);
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
@ -148,16 +149,18 @@ TEST_CASE("Test fast switching between PLL and XTAL", "[rtc_clk]")
void stop_rtc_external_quartz(void){
const uint8_t pin_32 = 32;
const uint8_t pin_33 = 33;
const uint8_t mask_32 = (1 << (pin_32 - 32));
const uint8_t mask_33 = (1 << (pin_33 - 32));
rtc_clk_32k_enable(false);
gpio_pad_select_gpio(pin_32);
gpio_pad_select_gpio(pin_33);
gpio_output_set_high(0, mask_32 | mask_33, mask_32 | mask_33, 0);
esp_rom_gpio_pad_select_gpio(pin_32);
esp_rom_gpio_pad_select_gpio(pin_33);
gpio_ll_output_enable(&GPIO, pin_32);
gpio_ll_output_enable(&GPIO, pin_33);
gpio_ll_set_level(&GPIO, pin_32, 0);
gpio_ll_set_level(&GPIO, pin_33, 0);
ets_delay_us(500000);
gpio_output_set_high(0, 0, 0, mask_32 | mask_33); // disable pins
gpio_ll_output_disable(&GPIO, pin_32);
gpio_ll_output_disable(&GPIO, pin_33);
}
static void start_freq(rtc_slow_freq_t required_src_freq, uint32_t start_delay_ms)

1
components/spi_flash/esp32/spi_flash_rom_patch.c
View file

@ -13,7 +13,6 @@
// limitations under the License.
#include "sdkconfig.h"
#include "esp32/rom/ets_sys.h"
#include "esp32/rom/gpio.h"
#include "esp32/rom/spi_flash.h"
#include "soc/spi_periph.h"

5
components/spi_flash/esp_flash_spi_init.c
View file

@ -18,6 +18,7 @@
#include "esp_flash_spi_init.h"
#include "driver/gpio.h"
#include "esp32/rom/spi_flash.h"
#include "esp_rom_gpio.h"
#include "esp_log.h"
#include "esp_heap_caps.h"
#include "hal/spi_types.h"
@ -100,9 +101,9 @@ static IRAM_ATTR NOINLINE_ATTR void cs_initialize(esp_flash_t *chip, const esp_f
GPIO.enable1_w1ts.data = (0x1 << (cs_io_num - 32));
}
GPIO.pin[cs_io_num].pad_driver = 0;
gpio_matrix_out(cs_io_num, spics_out, false, false);
esp_rom_gpio_connect_out_signal(cs_io_num, spics_out, false, false);
if (cs_id == 0) {
gpio_matrix_in(cs_io_num, spics_in, false);
esp_rom_gpio_connect_in_signal(cs_io_num, spics_in, false);
}
PIN_FUNC_SELECT(iomux_reg, PIN_FUNC_GPIO);
}

3
components/spi_flash/test/test_esp_flash.c
View file

@ -20,6 +20,7 @@
#include "hal/spi_flash_hal.h"
#include "ccomp_timer.h"
#include "esp_rom_gpio.h"
#define FUNC_SPI 1
@ -192,7 +193,7 @@ static void setup_bus(spi_host_device_t host_id)
ESP_LOGI(TAG, "setup flash on SPI1 CS1...\n");
//no need to initialize the bus, however the CLK may need one more output if it's on the usual place of PSRAM
#ifdef EXTRA_SPI1_CLK_IO
gpio_matrix_out(EXTRA_SPI1_CLK_IO, SPICLK_OUT_IDX, 0, 0);
esp_rom_gpio_connect_out_signal(EXTRA_SPI1_CLK_IO, SPICLK_OUT_IDX, 0, 0);
#endif
#if !DISABLED_FOR_TARGETS(ESP32)
} else if (host_id == FSPI_HOST) {

5
components/tinyusb/port/esp32s2/include/device_controller_driver.h
View file

@ -18,15 +18,14 @@
extern "C" {
#endif
#include <stdbool.h>
#include <stdint.h>
// Espressif
#include "driver/periph_ctrl.h"
#include "freertos/xtensa_api.h"
#include "esp_intr_alloc.h"
#include "esp_log.h"
#include "esp32s2/rom/gpio.h"
#include "soc/dport_reg.h"
#include "soc/gpio_sig_map.h"
#include "soc/usb_periph.h"
#include "tusb_config.h"
// TinyUSB

16
components/tinyusb/port/esp32s2/src/tinyusb.c
View file

@ -15,9 +15,11 @@
#include "tinyusb.h"
#include "hal/usb_hal.h"
#include "soc/usb_periph.h"
#include "soc/gpio_periph.h"
#include "hal/gpio_ll.h"
#include "esp_rom_gpio.h"
#include "driver/periph_ctrl.h"
#include "driver/gpio.h"
#include "esp32s2/rom/gpio.h"
static void configure_pins(usb_hal_context_t *usb)
{
@ -25,16 +27,16 @@ static void configure_pins(usb_hal_context_t *usb)
* Introduce additional parameters in usb_hal_context_t when adding support
* for USB Host.
*/
for (const usb_iopin_dsc_t* iopin = usb_periph_iopins; iopin->pin != -1; ++iopin) {
for (const usb_iopin_dsc_t *iopin = usb_periph_iopins; iopin->pin != -1; ++iopin) {
if ((usb->use_external_phy) || (iopin->ext_phy_only == 0)) {
gpio_pad_select_gpio(iopin->pin);
esp_rom_gpio_pad_select_gpio(iopin->pin);
if (iopin->is_output) {
gpio_matrix_out(iopin->pin, iopin->func, false, false);
esp_rom_gpio_connect_out_signal(iopin->pin, iopin->func, false, false);
} else {
gpio_matrix_in(iopin->pin, iopin->func, false);
gpio_pad_input_enable(iopin->pin);
esp_rom_gpio_connect_in_signal(iopin->pin, iopin->func, false);
gpio_ll_input_enable(&GPIO, iopin->pin);
}
gpio_pad_unhold(iopin->pin);
esp_rom_gpio_pad_unhold(iopin->pin);
}
}
if (!usb->use_external_phy) {

8
docs/en/contribute/style-guide.rst
View file

@ -91,10 +91,10 @@ No space is necessary around ``.`` and ``->`` operators.
Sometimes adding horizontal space within a line can help make code more readable. For example, you can add space to align function arguments::
gpio_matrix_in(PIN_CAM_D6, I2S0I_DATA_IN14_IDX, false);
gpio_matrix_in(PIN_CAM_D7, I2S0I_DATA_IN15_IDX, false);
gpio_matrix_in(PIN_CAM_HREF, I2S0I_H_ENABLE_IDX, false);
gpio_matrix_in(PIN_CAM_PCLK, I2S0I_DATA_IN15_IDX, false);
esp_rom_gpio_connect_in_signal(PIN_CAM_D6, I2S0I_DATA_IN14_IDX, false);
esp_rom_gpio_connect_in_signal(PIN_CAM_D7, I2S0I_DATA_IN15_IDX, false);
esp_rom_gpio_connect_in_signal(PIN_CAM_HREF, I2S0I_H_ENABLE_IDX, false);
esp_rom_gpio_connect_in_signal(PIN_CAM_PCLK, I2S0I_DATA_IN15_IDX, false);
Note however that if someone goes to add new line with a longer identifier as first argument (e.g. ``PIN_CAM_VSYNC``), it will not fit. So other lines would have to be realigned, adding meaningless changes to the commit.

15
examples/bluetooth/bluedroid/classic_bt/hfp_ag/main/gpio_pcm_config.c
View file

@ -10,6 +10,7 @@
#include "soc/gpio_reg.h"
#include "soc/gpio_sig_map.h"
#include "gpio_pcm_config.h"
#include "esp_rom_gpio.h"
#define GPIO_OUTPUT_PCM_FSYNC (25)
#define GPIO_OUTPUT_PCM_CLK_OUT (5)
@ -25,7 +26,7 @@ void app_gpio_pcm_io_cfg(void)
gpio_config_t io_conf;
/// configure the PCM output pins
//disable interrupt
io_conf.intr_type = GPIO_PIN_INTR_DISABLE;
io_conf.intr_type = GPIO_INTR_DISABLE;
//set as output mode
io_conf.mode = GPIO_MODE_OUTPUT;
//bit mask of the pins that you want to set,e.g.GPIO18/19
@ -39,7 +40,7 @@ void app_gpio_pcm_io_cfg(void)
/// configure the PCM input pin
//interrupt of rising edge
io_conf.intr_type = GPIO_PIN_INTR_DISABLE;
io_conf.intr_type = GPIO_INTR_DISABLE;
//bit mask of the pins, use GPIO4/5 here
io_conf.pin_bit_mask = GPIO_INPUT_PCM_PIN_SEL;
//set as input mode
@ -51,10 +52,10 @@ void app_gpio_pcm_io_cfg(void)
gpio_config(&io_conf);
/// matrix out | in the internal PCM signals to the GPIOs
gpio_matrix_out(GPIO_OUTPUT_PCM_FSYNC, PCMFSYNC_OUT_IDX, false, false);
gpio_matrix_out(GPIO_OUTPUT_PCM_CLK_OUT, PCMCLK_OUT_IDX, false, false);
gpio_matrix_out(GPIO_OUTPUT_PCM_DOUT, PCMDOUT_IDX, false, false);
gpio_matrix_in(GPIO_INPUT_PCM_DIN, PCMDIN_IDX, false);
esp_rom_gpio_connect_out_signal(GPIO_OUTPUT_PCM_FSYNC, PCMFSYNC_OUT_IDX, false, false);
esp_rom_gpio_connect_out_signal(GPIO_OUTPUT_PCM_CLK_OUT, PCMCLK_OUT_IDX, false, false);
esp_rom_gpio_connect_out_signal(GPIO_OUTPUT_PCM_DOUT, PCMDOUT_IDX, false, false);
esp_rom_gpio_connect_in_signal(GPIO_INPUT_PCM_DIN, PCMDIN_IDX, false);
}
#if ACOUSTIC_ECHO_CANCELLATION_ENABLE
@ -68,7 +69,7 @@ void app_gpio_aec_io_cfg(void)
{
gpio_config_t io_conf;
//disable interrupt
io_conf.intr_type = GPIO_PIN_INTR_DISABLE;
io_conf.intr_type = GPIO_INTR_DISABLE;
//set as output mode
io_conf.mode = GPIO_MODE_OUTPUT;
//bit mask of the pins that you want to set,e.g.GPIO18/19

15
examples/bluetooth/bluedroid/classic_bt/hfp_hf/main/gpio_pcm_config.c
View file

@ -10,6 +10,7 @@
#include "soc/gpio_reg.h"
#include "soc/gpio_sig_map.h"
#include "gpio_pcm_config.h"
#include "esp_rom_gpio.h"
#define GPIO_OUTPUT_PCM_FSYNC (25)
#define GPIO_OUTPUT_PCM_CLK_OUT (5)
@ -25,7 +26,7 @@ void app_gpio_pcm_io_cfg(void)
gpio_config_t io_conf;
/// configure the PCM output pins
//disable interrupt
io_conf.intr_type = GPIO_PIN_INTR_DISABLE;
io_conf.intr_type = GPIO_INTR_DISABLE;
//set as output mode
io_conf.mode = GPIO_MODE_OUTPUT;
//bit mask of the pins that you want to set,e.g.GPIO18/19
@ -39,7 +40,7 @@ void app_gpio_pcm_io_cfg(void)
/// configure the PCM input pin
//interrupt of rising edge
io_conf.intr_type = GPIO_PIN_INTR_DISABLE;
io_conf.intr_type = GPIO_INTR_DISABLE;
//bit mask of the pins, use GPIO4/5 here
io_conf.pin_bit_mask = GPIO_INPUT_PCM_PIN_SEL;
//set as input mode
@ -51,10 +52,10 @@ void app_gpio_pcm_io_cfg(void)
gpio_config(&io_conf);
/// matrix out | in the internal PCM signals to the GPIOs
gpio_matrix_out(GPIO_OUTPUT_PCM_FSYNC, PCMFSYNC_OUT_IDX, false, false);
gpio_matrix_out(GPIO_OUTPUT_PCM_CLK_OUT, PCMCLK_OUT_IDX, false, false);
gpio_matrix_out(GPIO_OUTPUT_PCM_DOUT, PCMDOUT_IDX, false, false);
gpio_matrix_in(GPIO_INPUT_PCM_DIN, PCMDIN_IDX, false);
esp_rom_gpio_connect_out_signal(GPIO_OUTPUT_PCM_FSYNC, PCMFSYNC_OUT_IDX, false, false);
esp_rom_gpio_connect_out_signal(GPIO_OUTPUT_PCM_CLK_OUT, PCMCLK_OUT_IDX, false, false);
esp_rom_gpio_connect_out_signal(GPIO_OUTPUT_PCM_DOUT, PCMDOUT_IDX, false, false);
esp_rom_gpio_connect_in_signal(GPIO_INPUT_PCM_DIN, PCMDIN_IDX, false);
}
#if ACOUSTIC_ECHO_CANCELLATION_ENABLE
@ -68,7 +69,7 @@ void app_gpio_aec_io_cfg(void)
{
gpio_config_t io_conf;
//disable interrupt
io_conf.intr_type = GPIO_PIN_INTR_DISABLE;
io_conf.intr_type = GPIO_INTR_DISABLE;
//set as output mode
io_conf.mode = GPIO_MODE_OUTPUT;
//bit mask of the pins that you want to set,e.g.GPIO18/19

2
examples/bluetooth/esp_ble_mesh/ble_mesh_fast_provision/fast_prov_server/main/board.c
View file

@ -58,7 +58,7 @@ void board_led_operation(uint8_t pin, uint8_t onoff)
static void board_led_init(void)
{
for (int i = 0; i < 3; i++) {
gpio_pad_select_gpio(led_state[i].pin);
gpio_reset_pin(led_state[i].pin);
gpio_set_direction(led_state[i].pin, GPIO_MODE_OUTPUT);
gpio_set_level(led_state[i].pin, LED_OFF);
led_state[i].previous = LED_OFF;

3
examples/bluetooth/esp_ble_mesh/ble_mesh_node/onoff_client/main/board.c
View file

@ -10,6 +10,7 @@
#include <stdio.h>
#include "driver/uart.h"
#include "driver/gpio.h"
#include "esp_log.h"
#include "iot_button.h"
@ -49,7 +50,7 @@ void board_led_operation(uint8_t pin, uint8_t onoff)
static void board_led_init(void)
{
for (int i = 0; i < ARRAY_SIZE(led_state); i++) {
gpio_pad_select_gpio(led_state[i].pin);
gpio_reset_pin(led_state[i].pin);
gpio_set_direction(led_state[i].pin, GPIO_MODE_OUTPUT);
gpio_set_level(led_state[i].pin, LED_OFF);
led_state[i].previous = LED_OFF;

2
examples/bluetooth/esp_ble_mesh/ble_mesh_node/onoff_server/main/board.c
View file

@ -43,7 +43,7 @@ void board_led_operation(uint8_t pin, uint8_t onoff)
static void board_led_init(void)
{
for (int i = 0; i < 3; i++) {
gpio_pad_select_gpio(led_state[i].pin);
gpio_reset_pin(led_state[i].pin);
gpio_set_direction(led_state[i].pin, GPIO_MODE_OUTPUT);
gpio_set_level(led_state[i].pin, LED_OFF);
led_state[i].previous = LED_OFF;

2
examples/bluetooth/esp_ble_mesh/ble_mesh_sensor_model/sensor_server/main/board.c
View file

@ -42,7 +42,7 @@ void board_led_operation(uint8_t pin, uint8_t onoff)
static void board_led_init(void)
{
for (int i = 0; i < 3; i++) {
gpio_pad_select_gpio(led_state[i].pin);
gpio_reset_pin(led_state[i].pin);
gpio_set_direction(led_state[i].pin, GPIO_MODE_OUTPUT);
gpio_set_level(led_state[i].pin, LED_OFF);
led_state[i].previous = LED_OFF;

2
examples/bluetooth/esp_ble_mesh/ble_mesh_vendor_model/vendor_server/main/board.c
View file

@ -42,7 +42,7 @@ void board_led_operation(uint8_t pin, uint8_t onoff)
static void board_led_init(void)
{
for (int i = 0; i < 3; i++) {
gpio_pad_select_gpio(led_state[i].pin);
gpio_reset_pin(led_state[i].pin);
gpio_set_direction(led_state[i].pin, GPIO_MODE_OUTPUT);
gpio_set_level(led_state[i].pin, LED_OFF);
led_state[i].previous = LED_OFF;

2
examples/bluetooth/esp_ble_mesh/ble_mesh_wifi_coexist/main/board.c
View file

@ -58,7 +58,7 @@ void board_led_operation(uint8_t pin, uint8_t onoff)
static void board_led_init(void)
{
for (int i = 0; i < 3; i++) {
gpio_pad_select_gpio(led_state[i].pin);
gpio_reset_pin(led_state[i].pin);
gpio_set_direction(led_state[i].pin, GPIO_MODE_OUTPUT);
gpio_set_level(led_state[i].pin, LED_OFF);
led_state[i].previous = LED_OFF;

2
examples/bluetooth/esp_ble_mesh/ble_mesh_wifi_coexist/tutorial/BLE_Mesh_WiFi_Coexist_Example_Walkthrough.md
View file

@ -102,7 +102,7 @@ This demo calls the `board_init` function to:
```c
for (int i = 0; i < 3; i++) {
gpio_pad_select_gpio(led_state[i].pin);
esp_rom_gpio_pad_select_gpio(led_state[i].pin);
gpio_set_direction(led_state[i].pin, GPIO_MODE_OUTPUT);
gpio_set_level(led_state[i].pin, LED_OFF);
led_state[i].previous = LED_OFF;

2
examples/ethernet/enc28j60/main/esp_eth_mac_enc28j60.c
View file

@ -838,7 +838,7 @@ static esp_err_t emac_enc28j60_init(esp_eth_mac_t *mac)
esp_eth_mediator_t *eth = emac->eth;
/* init gpio used for reporting enc28j60 interrupt */
gpio_pad_select_gpio(emac->int_gpio_num);
gpio_reset_pin(emac->int_gpio_num);
gpio_set_direction(emac->int_gpio_num, GPIO_MODE_INPUT);
gpio_set_pull_mode(emac->int_gpio_num, GPIO_PULLUP_ONLY);
gpio_set_intr_type(emac->int_gpio_num, GPIO_INTR_NEGEDGE);

2
examples/ethernet/enc28j60/main/esp_eth_phy_enc28j60.c
View file

@ -163,7 +163,7 @@ static esp_err_t enc28j60_reset_hw(esp_eth_phy_t *phy)
phy_enc28j60_t *enc28j60 = __containerof(phy, phy_enc28j60_t, parent);
// set reset_gpio_num minus zero can skip hardware reset phy chip
if (enc28j60->reset_gpio_num >= 0) {
gpio_pad_select_gpio(enc28j60->reset_gpio_num);
gpio_reset_pin(enc28j60->reset_gpio_num);
gpio_set_direction(enc28j60->reset_gpio_num, GPIO_MODE_OUTPUT);
gpio_set_level(enc28j60->reset_gpio_num, 0);
gpio_set_level(enc28j60->reset_gpio_num, 1);

2
examples/get-started/blink/main/blink.c
View file

@ -25,7 +25,7 @@ void app_main(void)
Technical Reference for a list of pads and their default
functions.)
*/
gpio_pad_select_gpio(BLINK_GPIO);
gpio_reset_pin(BLINK_GPIO);
/* Set the GPIO as a push/pull output */
gpio_set_direction(BLINK_GPIO, GPIO_MODE_OUTPUT);
while(1) {

2
examples/mesh/ip_internal_network/main/mesh_main.c
View file

@ -61,7 +61,7 @@ void mqtt_app_publish(char* topic, char *publish_string);
static void initialise_button(void)
{
gpio_config_t io_conf = {0};
io_conf.intr_type = GPIO_PIN_INTR_DISABLE;
io_conf.intr_type = GPIO_INTR_DISABLE;
io_conf.pin_bit_mask = BIT64(EXAMPLE_BUTTON_GPIO);
io_conf.mode = GPIO_MODE_INPUT;
io_conf.pull_up_en = 1;

4
examples/peripherals/gpio/main/gpio_example_main.c
View file

@ -61,7 +61,7 @@ void app_main(void)
{
gpio_config_t io_conf;
//disable interrupt
io_conf.intr_type = GPIO_PIN_INTR_DISABLE;
io_conf.intr_type = GPIO_INTR_DISABLE;
//set as output mode
io_conf.mode = GPIO_MODE_OUTPUT;
//bit mask of the pins that you want to set,e.g.GPIO18/19
@ -74,7 +74,7 @@ void app_main(void)
gpio_config(&io_conf);
//interrupt of rising edge
io_conf.intr_type = GPIO_PIN_INTR_POSEDGE;
io_conf.intr_type = GPIO_INTR_POSEDGE;
//bit mask of the pins, use GPIO4/5 here
io_conf.pin_bit_mask = GPIO_INPUT_PIN_SEL;
//set as input mode

4
examples/peripherals/sigmadelta/README.md
View file

@ -58,11 +58,11 @@ Immediately after that the LED should start brightening and dimming.
If you are using [ESP-WROVER-KIT](https://www.espressif.com/en/products/hardware/esp-wrover-kit/overview) then this board has an RGB LED already installed. GPIO4 is driving blue color of the LED. The brightening and dimming effect of the blue LED may not be distinctly visible because red and green LEDs are not actively driven by this example and will slightly lit. To resolve this issue you can switch both diodes off by adding the following code at the end of `sigmadelta_example_init()` function:
```c
gpio_pad_select_gpio(GPIO_NUM_0);
esp_rom_gpio_pad_select_gpio(GPIO_NUM_0);
gpio_set_direction(GPIO_NUM_0, GPIO_MODE_OUTPUT);
gpio_set_level(GPIO_NUM_0, 0);
gpio_pad_select_gpio(GPIO_NUM_2);
esp_rom_gpio_pad_select_gpio(GPIO_NUM_2);
gpio_set_direction(GPIO_NUM_2, GPIO_MODE_OUTPUT);
gpio_set_level(GPIO_NUM_2, 0);
```

4
examples/peripherals/spi_slave/sender/main/app_main.c
View file

@ -119,7 +119,7 @@ void app_main(void)
//GPIO config for the handshake line.
gpio_config_t io_conf={
.intr_type=GPIO_PIN_INTR_POSEDGE,
.intr_type=GPIO_INTR_POSEDGE,
.mode=GPIO_MODE_INPUT,
.pull_up_en=1,
.pin_bit_mask=(1<<GPIO_HANDSHAKE)
@ -137,7 +137,7 @@ void app_main(void)
//Set up handshake line interrupt.
gpio_config(&io_conf);
gpio_install_isr_service(0);
gpio_set_intr_type(GPIO_HANDSHAKE, GPIO_PIN_INTR_POSEDGE);
gpio_set_intr_type(GPIO_HANDSHAKE, GPIO_INTR_POSEDGE);
gpio_isr_handler_add(GPIO_HANDSHAKE, gpio_handshake_isr_handler, NULL);
//Initialize the SPI bus and add the device we want to send stuff to.

5
examples/peripherals/twai/twai_alert_and_recovery/main/twai_alert_and_recovery_example_main.c
View file

@ -27,6 +27,7 @@
#include "esp_log.h"
#include "driver/gpio.h"
#include "driver/twai.h"
#include "esp_rom_gpio.h"
/* --------------------- Definitions and static variables ------------------ */
//Example Configuration
@ -53,10 +54,10 @@ static void invert_tx_bits(bool enable)
{
if (enable) {
//Inverts output of TX to trigger errors
gpio_matrix_out(TX_GPIO_NUM, TWAI_TX_IDX, true, false);
esp_rom_gpio_connect_out_signal(TX_GPIO_NUM, TWAI_TX_IDX, true, false);
} else {
//Returns TX to default settings
gpio_matrix_out(TX_GPIO_NUM, TWAI_TX_IDX, false, false);
esp_rom_gpio_connect_out_signal(TX_GPIO_NUM, TWAI_TX_IDX, false, false);
}
}

2
examples/protocols/mdns/main/mdns_example_main.c
View file

@ -139,7 +139,7 @@ static void query_mdns_host(const char * host_name)
static void initialise_button(void)
{
gpio_config_t io_conf = {0};
io_conf.intr_type = GPIO_PIN_INTR_DISABLE;
io_conf.intr_type = GPIO_INTR_DISABLE;
io_conf.pin_bit_mask = BIT64(EXAMPLE_BUTTON_GPIO);
io_conf.mode = GPIO_MODE_INPUT;
io_conf.pull_up_en = 1;

2
examples/storage/nvs_rw_blob/main/nvs_blob_example_main.c
View file

@ -167,7 +167,7 @@ void app_main(void)
err = save_restart_counter();
if (err != ESP_OK) printf("Error (%s) saving restart counter to NVS!\n", esp_err_to_name(err));
gpio_pad_select_gpio(GPIO_NUM_0);
gpio_reset_pin(GPIO_NUM_0);
gpio_set_direction(GPIO_NUM_0, GPIO_MODE_DEF_INPUT);
/* Read the status of GPIO0. If GPIO0 is LOW for longer than 1000 ms,

2
examples/system/gcov/main/gcov_example_main.c
View file

@ -32,7 +32,7 @@ static void blink_task(void *pvParameter)
Technical Reference for a list of pads and their default
functions.)
*/
gpio_pad_select_gpio(BLINK_GPIO);
gpio_reset_pin(BLINK_GPIO);
/* Set the GPIO as a push/pull output */
gpio_set_direction(BLINK_GPIO, GPIO_MODE_OUTPUT);

2
examples/system/ota/native_ota_example/main/native_ota_example.c
View file

@ -249,7 +249,7 @@ static void ota_example_task(void *pvParameter)
static bool diagnostic(void)
{
gpio_config_t io_conf;
io_conf.intr_type = GPIO_PIN_INTR_DISABLE;
io_conf.intr_type = GPIO_INTR_DISABLE;
io_conf.mode = GPIO_MODE_INPUT;
io_conf.pin_bit_mask = (1ULL << CONFIG_EXAMPLE_GPIO_DIAGNOSTIC);
io_conf.pull_down_en = GPIO_PULLDOWN_DISABLE;

6
tools/ci/check_examples_rom_header.sh
View file

@ -1,14 +1,16 @@
#!/usr/bin/env bash
set -uo pipefail
# Examples shouldn't include rom headers directly
output=$(find ${IDF_PATH}/examples -name "*.[chS]" -o -name "*.cpp" -not -path "**/build/**")
files=$(egrep ".*include.*\<rom\>.*h" ${output} | cut -d ":" -f 1)
files=$(egrep ".*include.*\Wrom\W.*h" ${output} | cut -d ":" -f 1)
found_rom=0
for file in ${files}
do
echo "${file} contains rom headers!"
found_rom=`expr $found_rom + 1`;
((found_rom++))
done
if [ $found_rom -eq 0 ]; then

23
tools/ci/check_rom_apis.sh Executable file
View file

@ -0,0 +1,23 @@
#!/usr/bin/env bash
set -uo pipefail
# ESP-IDF should only use the ROM API that has a prefix "esp_rom_"
cd ${IDF_PATH} # git ls-files operates on working directory only, make sure we're at the top directory
deprecated_rom_apis=$(cat ${IDF_PATH}/components/esp_rom/esp32/ld/esp32.rom.api.ld | grep "esp_rom_" | cut -d "=" -f 2 | cut -d " " -f 2)
files_to_search=$(git ls-files --full-name '*.c')
count=0
for api in $deprecated_rom_apis; do
found_files=$(grep -E "\W+"$api"\W+" $files_to_search)
if [ -n "$found_files" ]; then
echo $found_files
((count++))
fi
done
if [ $count -gt 0 ]; then
echo "ROM APIs used in ESP-IDF should have an esp_rom_ prefix"
echo "Please try to use the APIs listed in esp_rom/include/esp_rom_xxx.h"
exit 1
fi

3
tools/ci/config/pre_check.yml
View file

@ -48,10 +48,11 @@ check_examples_cmake_make:
script:
- tools/ci/check_examples_cmake_make.sh
check_examples_rom_header:
check_rom_api_header:
extends: .check_job_template_with_filter
script:
- tools/ci/check_examples_rom_header.sh
- tools/ci/check_rom_apis.sh
check_python_style:
extends: .python_lint_template

1
tools/ci/executable-list.txt
View file

@ -44,6 +44,7 @@ tools/ci/check_deprecated_kconfigs.py
tools/ci/check_examples_cmake_make.sh
tools/ci/check_examples_rom_header.sh
tools/ci/check_idf_version.sh
tools/ci/check_rom_apis.sh
tools/ci/check_ut_cmake_make.sh
tools/ci/checkout_project_ref.py
tools/ci/deploy_docs.py

10
tools/unit-test-app/components/test_utils/ref_clock.c
View file

@ -41,11 +41,7 @@
#include "esp_intr_alloc.h"
#include "freertos/FreeRTOS.h"
#include "driver/periph_ctrl.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/gpio.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/gpio.h"
#endif
#include "esp_rom_gpio.h"
#include "sdkconfig.h"
/* Select which RMT and PCNT channels, and GPIO to use */
@ -81,7 +77,7 @@ void ref_clock_init()
assert(s_intr_handle == NULL && "already initialized");
// Route RMT output to GPIO matrix
gpio_matrix_out(REF_CLOCK_GPIO, RMT_SIG_OUT0_IDX + REF_CLOCK_RMT_CHANNEL, false, false);
esp_rom_gpio_connect_out_signal(REF_CLOCK_GPIO, RMT_SIG_OUT0_IDX + REF_CLOCK_RMT_CHANNEL, false, false);
// Initialize RMT
periph_module_enable(PERIPH_RMT_MODULE);
@ -106,7 +102,7 @@ void ref_clock_init()
// Route signal to PCNT
int pcnt_sig_idx = get_pcnt_sig();
gpio_matrix_in(REF_CLOCK_GPIO, pcnt_sig_idx, false);
esp_rom_gpio_connect_in_signal(REF_CLOCK_GPIO, pcnt_sig_idx, false);
if (REF_CLOCK_GPIO != 20) {
PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[REF_CLOCK_GPIO]);
} else {