From 8b6c0947c7d2c88660344730b815724821eee50a Mon Sep 17 00:00:00 2001
From: morris <maoshengrong@espressif.com>
Date: Fri, 6 Mar 2020 11:08:10 +0800
Subject: [PATCH] soc: add hal api to set exception vector table base address

---
 components/esp32/cpu_start.c                    | 11 ++++-------
 components/esp32s2/cpu_start.c                  |  6 ++----
 components/soc/include/hal/cpu_hal.h            |  7 +++++++
 components/soc/src/esp32/include/hal/cpu_ll.h   |  5 +++++
 components/soc/src/esp32s2/include/hal/cpu_ll.h |  5 +++++
 components/soc/src/hal/cpu_hal.c                |  7 ++++++-
 6 files changed, 29 insertions(+), 12 deletions(-)

diff --git a/components/esp32/cpu_start.c b/components/esp32/cpu_start.c
index 61060c5f3..6115ec2c7 100644
--- a/components/esp32/cpu_start.c
+++ b/components/esp32/cpu_start.c
@@ -130,10 +130,8 @@ void IRAM_ATTR call_start_cpu0(void)
 
     bootloader_init_mem();
 
-    //Move exception vectors to IRAM
-    asm volatile (\
-                  "wsr    %0, vecbase\n" \
-                  ::"r"(&_init_start));
+    // Move exception vectors to IRAM
+    cpu_hal_set_vecbase(&_init_start);
 
     rst_reas[0] = rtc_get_reset_reason(0);
 
@@ -273,9 +271,8 @@ static void wdt_reset_cpu1_info_enable(void)
 
 void IRAM_ATTR call_start_cpu1(void)
 {
-    asm volatile (\
-                  "wsr    %0, vecbase\n" \
-                  ::"r"(&_init_start));
+    // Move exception vectors to IRAM
+    cpu_hal_set_vecbase(&_init_start);
 
     ets_set_appcpu_boot_addr(0);
 
diff --git a/components/esp32s2/cpu_start.c b/components/esp32s2/cpu_start.c
index ae18101fc..bbd374d18 100644
--- a/components/esp32s2/cpu_start.c
+++ b/components/esp32s2/cpu_start.c
@@ -113,10 +113,8 @@ void IRAM_ATTR call_start_cpu0(void)
 
     bootloader_init_mem();
 
-    //Move exception vectors to IRAM
-    asm volatile (\
-                  "wsr    %0, vecbase\n" \
-                  ::"r"(&_init_start));
+    // Move exception vectors to IRAM
+    cpu_hal_set_vecbase(&_init_start);
 
     rst_reas = rtc_get_reset_reason(0);
 
diff --git a/components/soc/include/hal/cpu_hal.h b/components/soc/include/hal/cpu_hal.h
index adda25de0..7584aa407 100644
--- a/components/soc/include/hal/cpu_hal.h
+++ b/components/soc/include/hal/cpu_hal.h
@@ -109,6 +109,13 @@ void cpu_hal_clear_watchpoint(int id);
 
 #endif // SOC_CPU_WATCHPOINTS_NUM > 0
 
+/**
+ * Set exception vector table base address.
+ *
+ * @param base address to move the exception vector table to
+ */
+void cpu_hal_set_vecbase(const void* base);
+
 #ifdef __cplusplus
 }
 #endif
\ No newline at end of file
diff --git a/components/soc/src/esp32/include/hal/cpu_ll.h b/components/soc/src/esp32/include/hal/cpu_ll.h
index 362de7399..180b615c7 100644
--- a/components/soc/src/esp32/include/hal/cpu_ll.h
+++ b/components/soc/src/esp32/include/hal/cpu_ll.h
@@ -166,6 +166,11 @@ static inline void cpu_ll_break(void)
     __asm__ ("break 0,0");
 }
 
+static inline void cpu_ll_set_vecbase(const void* vecbase)
+{
+    asm volatile ("wsr %0, vecbase" :: "r" (vecbase));
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/soc/src/esp32s2/include/hal/cpu_ll.h b/components/soc/src/esp32s2/include/hal/cpu_ll.h
index a81775965..a0a002a3f 100644
--- a/components/soc/src/esp32s2/include/hal/cpu_ll.h
+++ b/components/soc/src/esp32s2/include/hal/cpu_ll.h
@@ -162,6 +162,11 @@ static inline void cpu_ll_break(void)
     __asm__ ("break 0,0");
 }
 
+static inline void cpu_ll_set_vecbase(const void* vecbase)
+{
+    asm volatile ("wsr %0, vecbase" :: "r" (vecbase));
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/soc/src/hal/cpu_hal.c b/components/soc/src/hal/cpu_hal.c
index 4b2ca22c9..1da4ff29a 100644
--- a/components/soc/src/hal/cpu_hal.c
+++ b/components/soc/src/hal/cpu_hal.c
@@ -54,4 +54,9 @@ void cpu_hal_clear_watchpoint(int id)
 {
     cpu_ll_clear_watchpoint(id);
 }
-#endif // SOC_CPU_WATCHPOINTS_NUM > 0
\ No newline at end of file
+#endif // SOC_CPU_WATCHPOINTS_NUM > 0
+
+void cpu_hal_set_vecbase(const void* base)
+{
+    cpu_ll_set_vecbase(base);
+}