Merge branch 'bugfix/improve_flash_dio_read_timing_v3.1' into 'release/v3.1'
bugfix(flash): fix flash dio read mode configuration error on SPI0 (backport v3.1) See merge request idf/esp-idf!5290
This commit is contained in:
commit
85d00d8daa
4 changed files with 10 additions and 5 deletions
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@ -306,10 +306,11 @@ static void IRAM_ATTR flash_gpio_configure(const esp_image_header_t* pfhdr)
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int drv = 2;
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int drv = 2;
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switch (pfhdr->spi_mode) {
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switch (pfhdr->spi_mode) {
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case ESP_IMAGE_SPI_MODE_QIO:
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case ESP_IMAGE_SPI_MODE_QIO:
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spi_cache_dummy = SPI0_R_DIO_DUMMY_CYCLELEN;
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spi_cache_dummy = SPI0_R_QIO_DUMMY_CYCLELEN;
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break;
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break;
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case ESP_IMAGE_SPI_MODE_DIO:
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case ESP_IMAGE_SPI_MODE_DIO:
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spi_cache_dummy = SPI0_R_DIO_DUMMY_CYCLELEN; //qio 3
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spi_cache_dummy = SPI0_R_DIO_DUMMY_CYCLELEN;
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SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_ADDR_BITLEN_V, SPI0_R_DIO_ADDR_BITSLEN, SPI_USR_ADDR_BITLEN_S);
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break;
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break;
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case ESP_IMAGE_SPI_MODE_QOUT:
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case ESP_IMAGE_SPI_MODE_QOUT:
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case ESP_IMAGE_SPI_MODE_DOUT:
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case ESP_IMAGE_SPI_MODE_DOUT:
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@ -86,7 +86,8 @@ extern "C" {
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#define SPI0_R_QIO_DUMMY_CYCLELEN 3
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#define SPI0_R_QIO_DUMMY_CYCLELEN 3
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#define SPI0_R_QIO_ADDR_BITSLEN 31
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#define SPI0_R_QIO_ADDR_BITSLEN 31
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#define SPI0_R_FAST_DUMMY_CYCLELEN 7
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#define SPI0_R_FAST_DUMMY_CYCLELEN 7
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#define SPI0_R_DIO_DUMMY_CYCLELEN 3
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#define SPI0_R_DIO_DUMMY_CYCLELEN 1
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#define SPI0_R_DIO_ADDR_BITSLEN 27
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#define SPI0_R_FAST_ADDR_BITSLEN 23
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#define SPI0_R_FAST_ADDR_BITSLEN 23
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#define SPI0_R_SIO_ADDR_BITSLEN 23
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#define SPI0_R_SIO_ADDR_BITSLEN 23
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@ -446,9 +446,11 @@ static void IRAM_ATTR psram_gpio_config(psram_cache_mode_t mode)
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{
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{
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int spi_cache_dummy = 0;
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int spi_cache_dummy = 0;
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uint32_t rd_mode_reg = READ_PERI_REG(SPI_CTRL_REG(0));
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uint32_t rd_mode_reg = READ_PERI_REG(SPI_CTRL_REG(0));
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if (rd_mode_reg & (SPI_FREAD_QIO_M | SPI_FREAD_DIO_M)) {
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if (rd_mode_reg & SPI_FREAD_QIO_M) {
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spi_cache_dummy = SPI0_R_QIO_DUMMY_CYCLELEN;
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spi_cache_dummy = SPI0_R_QIO_DUMMY_CYCLELEN;
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} else if (rd_mode_reg & (SPI_FREAD_QUAD_M | SPI_FREAD_DUAL_M)) {
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} else if (rd_mode_reg & SPI_FREAD_DIO_M) {
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spi_cache_dummy = SPI0_R_DIO_DUMMY_CYCLELEN;
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} else if (rd_mode_reg & (SPI_FREAD_QUAD_M | SPI_FREAD_DUAL_M)) {
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spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN;
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spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN;
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} else {
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} else {
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spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN;
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spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN;
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@ -322,6 +322,7 @@ static void spi_cache_mode_switch(uint32_t modebit)
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REG_SET_FIELD(SPI_USER2_REG(0), SPI_USR_COMMAND_VALUE, 0x6B);
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REG_SET_FIELD(SPI_USER2_REG(0), SPI_USR_COMMAND_VALUE, 0x6B);
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REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN, SPI0_R_FAST_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]);
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REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN, SPI0_R_FAST_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]);
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} else if ((modebit & SPI_FREAD_DIO)) {
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} else if ((modebit & SPI_FREAD_DIO)) {
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REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_ADDR_BITLEN, SPI0_R_DIO_ADDR_BITSLEN);
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REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN, SPI0_R_DIO_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]);
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REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN, SPI0_R_DIO_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]);
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REG_SET_FIELD(SPI_USER2_REG(0), SPI_USR_COMMAND_VALUE, 0xBB);
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REG_SET_FIELD(SPI_USER2_REG(0), SPI_USR_COMMAND_VALUE, 0xBB);
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} else if ((modebit & SPI_FREAD_DUAL)) {
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} else if ((modebit & SPI_FREAD_DUAL)) {
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