From dda0208614dc418068779780b5eb1bad57579718 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Thu, 29 Nov 2018 15:15:21 +0800 Subject: [PATCH 1/3] =?UTF-8?q?soc/rtc=5Fclk:=20don=E2=80=99t=20clear=20DP?= =?UTF-8?q?ORT=5FCPUPERIOD=5FSEL=20when=20switching=20to=20XTAL?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is not necessary since RTC_CNTL_SOC_CLK_SEL is set before this. --- components/soc/esp32/rtc_clk.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/components/soc/esp32/rtc_clk.c b/components/soc/esp32/rtc_clk.c index 3156517b9..b88f59bdc 100644 --- a/components/soc/esp32/rtc_clk.c +++ b/components/soc/esp32/rtc_clk.c @@ -398,7 +398,6 @@ void rtc_clk_cpu_freq_to_xtal(int freq, int div) REG_WRITE(APB_CTRL_XTAL_TICK_CONF_REG, freq * MHZ / REF_CLK_FREQ - 1); /* switch clock source */ REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_XTL); - DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, 0); /* clear DPORT_CPUPERIOD_SEL */ rtc_clk_apb_freq_update(freq * MHZ); /* lower the voltage */ if (freq <= 2) { @@ -414,7 +413,6 @@ static void rtc_clk_cpu_freq_to_8m() REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL); REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, 0); REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_8M); - DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, 0); // clear DPORT_CPUPERIOD_SEL rtc_clk_apb_freq_update(RTC_FAST_CLK_FREQ_8M); } From 178e5b25e6b6a254e40cca6b0663c398ab732ca5 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Thu, 29 Nov 2018 15:18:11 +0800 Subject: [PATCH 2/3] bootloader: check previously used clock frequency at run time In the situation when bootloader was compiled for 240MHz, and app was compiled for 160MHz, and the chip is a revision 0 chip, the bootloader will assume that the application has also been running at 240MHz. This will cause the chip to lock up later. Modify this to use a run time check of DPORT_CPUPERIOD_SEL, which indicates which of the PLL frequencies was used. Closes https://github.com/espressif/esp-idf/issues/2731. --- components/bootloader_support/src/bootloader_clock.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/components/bootloader_support/src/bootloader_clock.c b/components/bootloader_support/src/bootloader_clock.c index d5a1e52ab..50c84cfb0 100644 --- a/components/bootloader_support/src/bootloader_clock.c +++ b/components/bootloader_support/src/bootloader_clock.c @@ -31,14 +31,14 @@ void bootloader_clock_configure() /* Set CPU to 80MHz. Keep other clocks unmodified. */ int cpu_freq_mhz = 80; - /* On ESP32 rev 0, switching to 80MHz if clock was previously set to + /* On ESP32 rev 0, switching to 80/160 MHz if clock was previously set to * 240 MHz may cause the chip to lock up (see section 3.5 of the errata - * document). For rev. 0, switch to 240 instead if it was chosen in - * menuconfig. + * document). For rev. 0, switch to 240 instead if it has been enabled + * previously. */ uint32_t chip_ver_reg = REG_READ(EFUSE_BLK0_RDATA3_REG); if ((chip_ver_reg & EFUSE_RD_CHIP_VER_REV1_M) == 0 && - CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ == 240) { + DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL) == 2) { cpu_freq_mhz = 240; } From 8cc6226051c8bd283b1a23489e9f3033b49ac706 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Tue, 26 Feb 2019 17:07:59 +0800 Subject: [PATCH 3/3] soc: define named constants for DPORT_CPUPERIOD_SEL values --- components/bootloader_support/src/bootloader_clock.c | 2 +- components/soc/esp32/include/soc/dport_reg.h | 3 +++ components/soc/esp32/rtc_clk.c | 12 ++++++------ 3 files changed, 10 insertions(+), 7 deletions(-) diff --git a/components/bootloader_support/src/bootloader_clock.c b/components/bootloader_support/src/bootloader_clock.c index 50c84cfb0..24267cc32 100644 --- a/components/bootloader_support/src/bootloader_clock.c +++ b/components/bootloader_support/src/bootloader_clock.c @@ -38,7 +38,7 @@ void bootloader_clock_configure() */ uint32_t chip_ver_reg = REG_READ(EFUSE_BLK0_RDATA3_REG); if ((chip_ver_reg & EFUSE_RD_CHIP_VER_REV1_M) == 0 && - DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL) == 2) { + DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL) == DPORT_CPUPERIOD_SEL_240) { cpu_freq_mhz = 240; } diff --git a/components/soc/esp32/include/soc/dport_reg.h b/components/soc/esp32/include/soc/dport_reg.h index 6c23dfe63..9cc3320b3 100644 --- a/components/soc/esp32/include/soc/dport_reg.h +++ b/components/soc/esp32/include/soc/dport_reg.h @@ -179,6 +179,9 @@ #define DPORT_CPUPERIOD_SEL_M ((DPORT_CPUPERIOD_SEL_V)<<(DPORT_CPUPERIOD_SEL_S)) #define DPORT_CPUPERIOD_SEL_V 0x3 #define DPORT_CPUPERIOD_SEL_S 0 +#define DPORT_CPUPERIOD_SEL_80 0 +#define DPORT_CPUPERIOD_SEL_160 1 +#define DPORT_CPUPERIOD_SEL_240 2 #define DPORT_PRO_CACHE_CTRL_REG (DR_REG_DPORT_BASE + 0x040) /* DPORT_PRO_DRAM_HL : R/W ;bitpos:[16] ;default: 1'b0 ; */ diff --git a/components/soc/esp32/rtc_clk.c b/components/soc/esp32/rtc_clk.c index b88f59bdc..43964448c 100644 --- a/components/soc/esp32/rtc_clk.c +++ b/components/soc/esp32/rtc_clk.c @@ -453,14 +453,14 @@ static void rtc_clk_bbpll_enable() static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz) { int dbias = DIG_DBIAS_80M_160M; - int per_conf = 0; + int per_conf = DPORT_CPUPERIOD_SEL_80; if (cpu_freq_mhz == 80) { /* nothing to do */ } else if (cpu_freq_mhz == 160) { - per_conf = 1; + per_conf = DPORT_CPUPERIOD_SEL_160; } else if (cpu_freq_mhz == 240) { dbias = DIG_DBIAS_240M; - per_conf = 2; + per_conf = DPORT_CPUPERIOD_SEL_240; } else { SOC_LOGE(TAG, "invalid frequency"); abort(); @@ -688,15 +688,15 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t* out_config) case RTC_CNTL_SOC_CLK_SEL_PLL: { source = RTC_CPU_FREQ_SRC_PLL; uint32_t cpuperiod_sel = DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL); - if (cpuperiod_sel == 0) { + if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_80) { source_freq_mhz = RTC_PLL_FREQ_320M; div = 4; freq_mhz = 80; - } else if (cpuperiod_sel == 1) { + } else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_160) { source_freq_mhz = RTC_PLL_FREQ_320M; div = 2; freq_mhz = 160; - } else if (cpuperiod_sel == 2) { + } else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_240) { source_freq_mhz = RTC_PLL_FREQ_480M; div = 2; freq_mhz = 240;