bootloader_support: Fix using shared CLK_EN and RST_EN regs for random
bootloader_random_enable() and bootloader_random_disable() functions can be used in app. This MR added the protection for shared CLK_EN and RST_EN registers.
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2f38a1a362
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807826f796
1 changed files with 17 additions and 1 deletions
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@ -23,6 +23,7 @@
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#ifndef BOOTLOADER_BUILD
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#include "esp_system.h"
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#include "driver/periph_ctrl.h"
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void bootloader_fill_random(void *buffer, size_t length)
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{
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@ -65,7 +66,11 @@ void bootloader_random_enable(void)
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/* Ensure the hardware RNG is enabled following a soft reset. This should always be the case already (this clock is
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never disabled while the CPU is running), this is a "belts and braces" type check.
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*/
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#ifdef BOOTLOADER_BUILD
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DPORT_SET_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_RNG_EN);
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#else
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periph_module_enable(PERIPH_RNG_MODULE);
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#endif // BOOTLOADER_BUILD
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/* Enable SAR ADC in test mode to feed ADC readings of the 1.1V
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reference via I2S into the RNG entropy input.
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@ -77,7 +82,11 @@ void bootloader_random_enable(void)
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SET_PERI_REG_MASK(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_ENT_RTC);
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SET_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_SAR2_EN_TEST);
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#ifdef BOOTLOADER_BUILD
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN);
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#else
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periph_module_enable(PERIPH_I2S0_MODULE);
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#endif // BOOTLOADER_BUILD
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CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_FORCE_START_TOP);
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CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_START_TOP);
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// Test pattern configuration byte 0xAD:
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@ -115,8 +124,11 @@ void bootloader_random_enable(void)
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void bootloader_random_disable(void)
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{
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/* Disable i2s clock */
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#ifdef BOOTLOADER_BUILD
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN);
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#else
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periph_module_disable(PERIPH_I2S0_MODULE);
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#endif // BOOTLOADER_BUILD
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/* Reset some i2s configuration (possibly redundant as we reset entire
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I2S peripheral further down). */
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@ -138,8 +150,12 @@ void bootloader_random_disable(void)
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SET_PERI_REG_BITS(SYSCON_SARADC_FSM_REG, SYSCON_SARADC_START_WAIT, 8, SYSCON_SARADC_START_WAIT_S);
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/* Reset i2s peripheral */
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#ifdef BOOTLOADER_BUILD
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST);
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#else
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periph_module_reset(PERIPH_I2S0_MODULE);
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#endif
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/* Disable pull supply voltage to SAR ADC */
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CLEAR_PERI_REG_MASK(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_ENT_RTC);
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