From 7fe4f987fd9cb37c3a0c12e0642079dc4708d6a4 Mon Sep 17 00:00:00 2001 From: "Michael (XIAO Xufeng)" Date: Wed, 24 Oct 2018 11:17:56 +0800 Subject: [PATCH] sdio_slave: add documentation for the standard init process --- .../peripherals/esp_slave_protocol.rst | 92 +++++++++++++++++-- .../api-reference/peripherals/sdio_slave.rst | 14 ++- 2 files changed, 94 insertions(+), 12 deletions(-) diff --git a/docs/en/api-reference/peripherals/esp_slave_protocol.rst b/docs/en/api-reference/peripherals/esp_slave_protocol.rst index de3c0596e..37fd21912 100644 --- a/docs/en/api-reference/peripherals/esp_slave_protocol.rst +++ b/docs/en/api-reference/peripherals/esp_slave_protocol.rst @@ -1,5 +1,79 @@ +Communication with ESP SDIO Slave +==================================== + +.. _esp_slave_init: + +ESP SDIO slave initialization +------------------------------ + +The host should initialize the ESP32 SDIO slave according to the standard +SDIO initialization process (Sector 3.1.2 of `SDIO Simplified +Specification `_). In this specification +and below, the SDIO slave is also called an (SD)IO card. All the +initialization CMD52 and CMD53 are sent to Func 0 (CIA region). Here is an +brief example on how to do this: + +1. SDIO reset + CMD52 (Write 0x6=0x8) + +2. SD reset + CMD0 + +3. Check whether IO card (optional) + CMD8 + +4. Send SDIO op cond and wait for card ready + CMD5 arg = 0x00000000 + + CMD5 arg = 0x00ff8000 (according to the response above, poll until ready) + + **Example:** + Arg of R4 after first CMD5 (arg=0x00000000) is 0xXXFFFF00. + + Keep sending CMD5 with arg=0x00FFFF00 until the R4 shows card ready (arg bit 31=1). + +5. Set address + CMD3 + +6. Select card + CMD7 (arg address according to CMD3 response) + + **Example:** + Arg of R6 after CMD3 is 0x0001xxxx. + + Arg of CMD7 should be 0x00010000. + +7. Select 4-bit mode (optional) + CMD52 (Write 0x07=0x02) + +8. Enable func1 + CMD52 (Write 0x02=0x02) + +9. Enable SDIO interrupt (required if interrupt line (DAT1) is used) + CMD52 (Write 0x04=0x03) + +10. Set Func0 blocksize (optional, default value is 512 (0x200)) + CMD52/53 (Read 0x10~0x11) + + CMD52/53 (Write 0x10=0x00) + + CMD52/53 (Write 0x11=0x02) + + CMD52/53 (Read 0x10~0x11, read to check the final value) + +11. Set Func1 blocksize (optional, default value is 512 (0x200)) + CMD52/53 (Read 0x110~0x111) + + CMD52/53 (Write 0x110=0x00) + + CMD52/53 (Write 0x111=0x02) + + CMD52/53 (Read 0x110~0x111, read to check the final value) + +.. _esp_slave_protocol_layer: + ESP SDIO slave protocol -======================= +----------------------- The protocol is based on Function 1 access by CMD52 and CMD53, offering 3 services: (1) sending and receiving FIFO, (2) 52 8-bit R/W register shared by host and slave, (3) 8 general purpose interrupt sources from host to slave and 8 in the oppsite direction. @@ -7,10 +81,11 @@ register shared by host and slave, (3) 8 general purpose interrupt sources from The host should access the registers below as described to communicate with slave. Slave register table --------------------- +^^^^^^^^^^^^^^^^^^^^ 32-bit -^^^^^^^ +####### + - 0x044 (TOKEN_RDATA): in which bit 27-16 holds the receiving buffer number. - 0x058 (INT_ST): holds the interrupt source bits from slave to host. - 0x060 (PKT_LEN): holds the accumulated length (by byte) to be sent from slave to host. @@ -18,7 +93,8 @@ Slave register table - 0x0DC (INT_ENA): mask bits for interrupts from slave to host. 8-bit -^^^^^ +##### + Shared general purpose registers: - 0x06C-0x077: R/W registers 0-11 shared by slave and host. @@ -31,7 +107,7 @@ Interrupt Registers: - 0x08D (SLAVE_INT): bits for host to interrupt slave. auto clear. FIFO (sending and receiving) -^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +############################ 0x090 - 0x1F7FF are reserved for FIFOs. @@ -59,7 +135,7 @@ or discard (receiving). supports that) to address 0x1F7F9=0x1F800-**7**. Interrupts ----------- +^^^^^^^^^^ For the host interrupts, the slave raise the interrupt by pulling DAT1 line down at a proper time (level sensitive). The host detect this and read the INT_ST register to see the source. Then the host can clear it by writing the INT_CLR @@ -72,7 +148,7 @@ For the slave interrupts, the host send transfers to write the SLAVE_INT registe the slave hardware and driver will detect it and inform the app. Receiving FIFO --------------- +^^^^^^^^^^^^^^ To write the receiving FIFO in the slave, host should work in the following steps: @@ -86,7 +162,7 @@ To write the receiving FIFO in the slave, host should work in the following step 4. Calculate used buffers, note that non-full buffer at the tail should be seen as one that is used. Sending FIFO ------------- +^^^^^^^^^^^^ To read the sending FIFO in the slave, host should work in the following steps: diff --git a/docs/en/api-reference/peripherals/sdio_slave.rst b/docs/en/api-reference/peripherals/sdio_slave.rst index eb041d424..163cf1168 100644 --- a/docs/en/api-reference/peripherals/sdio_slave.rst +++ b/docs/en/api-reference/peripherals/sdio_slave.rst @@ -89,11 +89,17 @@ The SDIO slave driver uses the following terms: and from slave to host (called host interrupts below). See more in :ref:`interrupts`. - Registers: specific address in Function 1 access by CMD52 or CMD53. -ESP SDIO Slave Protocol -^^^^^^^^^^^^^^^^^^^^^^^ +Communication with ESP SDIO Slave +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -The communication protocol slave used to communicate with the host is ESP32 specific, please refer to -:doc:`esp_slave_protocol`, or example :example:`peripherals/sdio` for designing a host. +The host should initialize the ESP32 SDIO slave according to the standard +SDIO initialization process (Sector 3.1.2 of `SDIO Simplified +Specification `_), which is described +briefly in :ref:`esp_slave_init`. + +However, there's an ESP32-specific upper-level communication protocol upon +the CMD52/CMD53 to Func 1. Please refer to :ref:`esp_slave_protocol_layer`, +or example :example:`peripherals/sdio` when programming your host. .. toctree:: :hidden: