esp32: fix RTC watchdog configuration in esp_restart
RTC watchdog didn’t have any actions configured for any of the stages. This change configures it to use SW_SYSTEM_RESET at stage 0 and a full reset at stage 1. The timeout is now calculated based on RTC_SLOW_CLK frequency.
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cbe23147bf
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780569c04a
2 changed files with 5 additions and 2 deletions
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@ -264,13 +264,15 @@ void IRAM_ATTR esp_restart_noos()
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esp_dport_access_int_deinit();
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// We need to disable TG0/TG1 watchdogs
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// First enable RTC watchdog to be on the safe side
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// First enable RTC watchdog for 1 second
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REG_WRITE(RTC_CNTL_WDTWPROTECT_REG, RTC_CNTL_WDT_WKEY_VALUE);
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REG_WRITE(RTC_CNTL_WDTCONFIG0_REG,
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RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M |
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(RTC_WDT_STG_SEL_RESET_SYSTEM << RTC_CNTL_WDT_STG0_S) |
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(RTC_WDT_STG_SEL_RESET_RTC << RTC_CNTL_WDT_STG1_S) |
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(1 << RTC_CNTL_WDT_SYS_RESET_LENGTH_S) |
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(1 << RTC_CNTL_WDT_CPU_RESET_LENGTH_S) );
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REG_WRITE(RTC_CNTL_WDTCONFIG1_REG, 128000);
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REG_WRITE(RTC_CNTL_WDTCONFIG1_REG, rtc_clk_slow_freq_get_hz() * 1);
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// Disable TG0/TG1 watchdogs
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TIMERG0.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
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@ -1718,6 +1718,7 @@
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#define RTC_WDT_STG_SEL_INT 1
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#define RTC_WDT_STG_SEL_RESET_CPU 2
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#define RTC_WDT_STG_SEL_RESET_SYSTEM 3
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#define RTC_WDT_STG_SEL_RESET_RTC 4
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#define RTC_CNTL_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0x90)
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/* RTC_CNTL_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd128000 ; */
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