test(spi): add test for SPI timing
This commit is contained in:
michael
bot
parent
208d993de1
commit
75cdbcefc7
1 changed files with 347 additions and 11 deletions
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@ -21,6 +21,7 @@
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#include "soc/spi_struct.h"
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#include "esp_heap_caps.h"
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#include "esp_log.h"
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#include "driver/spi_pins.h"
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#include "freertos/ringbuf.h"
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const static char TAG[] = "test_spi";
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@ -41,6 +42,7 @@ const static char TAG[] = "test_spi";
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.pre_cb=NULL, \
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.cs_ena_pretrans = 0,\
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.cs_ena_posttrans = 0,\
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.input_delay_ns = 62.5,\
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}
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//steal register definition from gpio.c
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@ -507,17 +509,6 @@ DRAM_ATTR static uint32_t data_dram[320]={0};
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//force to place in code area.
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static const uint32_t data_drom[320] = {0};
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#define HSPI_NATIVE_PIN_NUM_MISO 12
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#define HSPI_NATIVE_PIN_NUM_MOSI 13
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#define HSPI_NATIVE_PIN_NUM_CLK 14
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#define HSPI_NATIVE_PIN_NUM_CS 15
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#define VSPI_NATIVE_PIN_NUM_MISO 19
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#define VSPI_NATIVE_PIN_NUM_MOSI 23
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#define VSPI_NATIVE_PIN_NUM_CLK 18
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#define VSPI_NATIVE_PIN_NUM_CS 5
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#if 1 //HSPI
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#define PIN_NUM_MISO HSPI_NATIVE_PIN_NUM_MISO
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#define PIN_NUM_MOSI HSPI_NATIVE_PIN_NUM_MOSI
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@ -916,6 +907,351 @@ TEST_CASE("SPI master variable cmd & addr test","[spi]")
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ESP_LOGI(MASTER_TAG, "test passed.");
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}
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/********************************************************************************
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* Test Timing By Internal Connections
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********************************************************************************/
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typedef enum {
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FULL_DUPLEX = 0,
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HALF_DUPLEX_MISO = 1,
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HALF_DUPLEX_MOSI = 2,
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} spi_dup_t;
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static int timing_speed_array[]={/**/
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SPI_MASTER_FREQ_8M ,
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SPI_MASTER_FREQ_9M ,
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SPI_MASTER_FREQ_10M,
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SPI_MASTER_FREQ_11M,
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SPI_MASTER_FREQ_13M,
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SPI_MASTER_FREQ_16M,
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SPI_MASTER_FREQ_20M,
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SPI_MASTER_FREQ_26M,
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SPI_MASTER_FREQ_40M,
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SPI_MASTER_FREQ_80M,
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};
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typedef struct {
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uint8_t master_rxbuf[320];
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spi_transaction_t master_trans[16];
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TaskHandle_t handle_slave;
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spi_slave_task_context_t slave_context;
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slave_txdata_t slave_trans[16];
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} timing_context_t;
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void master_print_data(spi_transaction_t *t, spi_dup_t dup)
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{
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if (t->tx_buffer) {
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ESP_LOG_BUFFER_HEX( "master tx", t->tx_buffer, t->length/8 );
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} else {
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ESP_LOGI( "master tx", "no data" );
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}
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int rxlength;
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if (dup!=HALF_DUPLEX_MISO) {
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rxlength = t->length/8;
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} else {
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rxlength = t->rxlength/8;
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}
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if (t->rx_buffer) {
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ESP_LOG_BUFFER_HEX( "master rx", t->rx_buffer, rxlength );
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} else {
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ESP_LOGI( "master rx", "no data" );
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}
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}
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void slave_print_data(slave_rxdata_t *t)
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{
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int rcv_len = (t->len+7)/8;
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ESP_LOGI(SLAVE_TAG, "trans_len: %d", t->len);
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ESP_LOG_BUFFER_HEX( "slave tx", t->tx_start, rcv_len);
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ESP_LOG_BUFFER_HEX( "slave rx", t->data, rcv_len);
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}
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esp_err_t check_data(spi_transaction_t *t, spi_dup_t dup, slave_rxdata_t *slave_t)
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{
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int length;
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if (dup!=HALF_DUPLEX_MISO) {
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length = t->length;
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} else {
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length = t->rxlength;
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}
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TEST_ASSERT(length!=0);
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//currently the rcv_len can be in range of [t->length-1, t->length+3]
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uint32_t rcv_len = slave_t->len;
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TEST_ASSERT(rcv_len >= length-1 && rcv_len <= length+3);
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//the timing speed is temporarily only for master
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if (dup!=HALF_DUPLEX_MISO) {
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// TEST_ASSERT_EQUAL_HEX8_ARRAY(t->tx_buffer, slave_t->data, (t->length+7)/8);
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}
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if (dup!=HALF_DUPLEX_MOSI) {
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TEST_ASSERT_EQUAL_HEX8_ARRAY(slave_t->tx_start, t->rx_buffer, (length+7)/8);
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}
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return ESP_OK;
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}
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static void timing_init_transactions(spi_dup_t dup, timing_context_t* context)
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{
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spi_transaction_t* trans = context->master_trans;
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uint8_t *rx_buf_ptr = context->master_rxbuf;
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if (dup==HALF_DUPLEX_MISO) {
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for (int i = 0; i < 8; i++ ) {
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trans[i] = (spi_transaction_t) {
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.flags = 0,
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.rxlength = 8*(i*2+1),
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.rx_buffer = rx_buf_ptr,
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};
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rx_buf_ptr += ((context->master_trans[i].rxlength + 31)/8)&(~3);
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}
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} else if (dup==HALF_DUPLEX_MOSI) {
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for (int i = 0; i < 8; i++ ) {
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trans[i] = (spi_transaction_t) {
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.flags = 0,
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.length = 8*(i*2+1),
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.tx_buffer = master_send+i,
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};
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}
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} else {
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for (int i = 0; i < 8; i++ ) {
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trans[i] = (spi_transaction_t) {
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.flags = 0,
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.length = 8*(i*2+1),
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.tx_buffer = master_send+i,
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.rx_buffer = rx_buf_ptr,
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};
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rx_buf_ptr += ((context->master_trans[i].length + 31)/8)&(~3);
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}
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}
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//prepare slave tx data
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for (int i = 0; i < 8; i ++) {
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context->slave_trans[i] = (slave_txdata_t) {
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.start = slave_send + 4*(i%3),
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.len = 256,
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};
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}
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}
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typedef struct {
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const char cfg_name[30];
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/*The test work till the frequency below,
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*set the frequency to higher and remove checks in the driver to know how fast the system can run.
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*/
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int freq_limit;
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spi_dup_t dup;
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bool master_native;
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bool slave_native;
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int slave_tv_ns;
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} test_timing_config_t;
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#define ESP_SPI_SLAVE_TV (12.5*3)
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#define GPIO_DELAY (12.5*2)
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#define SAMPLE_DELAY 12.5
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#define TV_INT_CONNECT_GPIO (ESP_SPI_SLAVE_TV+GPIO_DELAY)
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#define TV_INT_CONNECT (ESP_SPI_SLAVE_TV)
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#define TV_WITH_ESP_SLAVE_GPIO (ESP_SPI_SLAVE_TV+SAMPLE_DELAY+GPIO_DELAY)
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#define TV_WITH_ESP_SLAVE (ESP_SPI_SLAVE_TV+SAMPLE_DELAY)
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//currently ESP32 slave only supports up to 20MHz, but 40MHz on the same board
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#define ESP_SPI_SLAVE_MAX_FREQ SPI_MASTER_FREQ_20M
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#define ESP_SPI_SLAVE_MAX_FREQ_SYNC SPI_MASTER_FREQ_40M
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static test_timing_config_t timing_master_conf_t[] = {/**/
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{ .cfg_name = "FULL_DUP, MASTER NATIVE",
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.freq_limit = SPI_MASTER_FREQ_13M,
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.dup = FULL_DUPLEX,
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.master_native = true,
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.slave_native = false,
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.slave_tv_ns = TV_INT_CONNECT_GPIO,
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},
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{ .cfg_name = "FULL_DUP, SLAVE NATIVE",
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.freq_limit = SPI_MASTER_FREQ_13M,
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.dup = FULL_DUPLEX,
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.master_native = false,
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.slave_native = true,
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.slave_tv_ns = TV_INT_CONNECT,
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},
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{ .cfg_name = "FULL_DUP, BOTH GPIO",
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.freq_limit = SPI_MASTER_FREQ_10M,
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.dup = FULL_DUPLEX,
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.master_native = false,
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.slave_native = false,
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.slave_tv_ns = TV_INT_CONNECT_GPIO,
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},
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{ .cfg_name = "HALF_DUP, MASTER NATIVE",
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.freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC,
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.dup = HALF_DUPLEX_MISO,
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.master_native = true,
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.slave_native = false,
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.slave_tv_ns = TV_INT_CONNECT_GPIO,
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},
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{ .cfg_name = "HALF_DUP, SLAVE NATIVE",
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.freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC,
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.dup = HALF_DUPLEX_MISO,
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.master_native = false,
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.slave_native = true,
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.slave_tv_ns = TV_INT_CONNECT,
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},
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{ .cfg_name = "HALF_DUP, BOTH GPIO",
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.freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC,
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.dup = HALF_DUPLEX_MISO,
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.master_native = false,
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.slave_native = false,
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.slave_tv_ns = TV_INT_CONNECT_GPIO,
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},
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{ .cfg_name = "MOSI_DUP, MASTER NATIVE",
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.freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC,
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.dup = HALF_DUPLEX_MOSI,
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.master_native = true,
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.slave_native = false,
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.slave_tv_ns = TV_INT_CONNECT_GPIO,
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},
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{ .cfg_name = "MOSI_DUP, SLAVE NATIVE",
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.freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC,
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.dup = HALF_DUPLEX_MOSI,
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.master_native = false,
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.slave_native = true,
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.slave_tv_ns = TV_INT_CONNECT,
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},
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{ .cfg_name = "MOSI_DUP, BOTH GPIO",
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.freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC,
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.dup = HALF_DUPLEX_MOSI,
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.master_native = false,
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.slave_native = false,
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.slave_tv_ns = TV_INT_CONNECT_GPIO,
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},
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};
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//this case currently only checks master read
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TEST_CASE("test timing_master","[spi][timeout=120]")
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{
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timing_context_t context;
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//Enable pull-ups on SPI lines so we don't detect rogue pulses when no master is connected.
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//slave_pull_up(&slv_buscfg, slvcfg.spics_io_num);
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context.slave_context = (spi_slave_task_context_t){};
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esp_err_t err = init_slave_context( &context.slave_context );
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TEST_ASSERT( err == ESP_OK );
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xTaskCreate( task_slave, "spi_slave", 4096, &context.slave_context, 0, &context.handle_slave);
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const int test_size = sizeof(timing_master_conf_t)/sizeof(test_timing_config_t);
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for (int i = 0; i < test_size; i++) {
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test_timing_config_t* conf = &timing_master_conf_t[i];
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spi_device_handle_t spi;
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timing_init_transactions(conf->dup, &context);
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ESP_LOGI(MASTER_TAG, "****************** %s ***************", conf->cfg_name);
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for (int j=0; j<sizeof(timing_speed_array)/sizeof(int); j++ ) {
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if (timing_speed_array[j] > conf->freq_limit) break;
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ESP_LOGI(MASTER_TAG, "======> %dk", timing_speed_array[j]/1000);
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//master config
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const int master_mode = 0;
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spi_bus_config_t buscfg=SPI_BUS_TEST_DEFAULT_CONFIG();
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spi_device_interface_config_t devcfg=SPI_DEVICE_TEST_DEFAULT_CONFIG();
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devcfg.mode = master_mode;
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if (conf->dup==HALF_DUPLEX_MISO||conf->dup==HALF_DUPLEX_MOSI) {
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devcfg.cs_ena_pretrans = 20;
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devcfg.flags |= SPI_DEVICE_HALFDUPLEX;
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} else {
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devcfg.cs_ena_pretrans = 1;
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}
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devcfg.cs_ena_posttrans = 20;
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devcfg.input_delay_ns = conf->slave_tv_ns;
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devcfg.clock_speed_hz = timing_speed_array[j];
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//slave config
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int slave_mode = 0;
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spi_slave_interface_config_t slvcfg=SPI_SLAVE_TEST_DEFAULT_CONFIG();
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slvcfg.mode = slave_mode;
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//pin config & initialize
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//we can't have two sets of native pins on the same pins
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assert(!conf->master_native || !conf->slave_native);
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if (conf->slave_native) {
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//only in this case, use VSPI native pins
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buscfg.miso_io_num = VSPI_NATIVE_PIN_NUM_MISO;
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buscfg.mosi_io_num = VSPI_NATIVE_PIN_NUM_MOSI;
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buscfg.sclk_io_num = VSPI_NATIVE_PIN_NUM_CLK;
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devcfg.spics_io_num = VSPI_NATIVE_PIN_NUM_CS;
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slvcfg.spics_io_num = VSPI_NATIVE_PIN_NUM_CS;
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} else {
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buscfg.miso_io_num = HSPI_NATIVE_PIN_NUM_MISO;
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buscfg.mosi_io_num = HSPI_NATIVE_PIN_NUM_MOSI;
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buscfg.sclk_io_num = HSPI_NATIVE_PIN_NUM_CLK;
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devcfg.spics_io_num = HSPI_NATIVE_PIN_NUM_CS;
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slvcfg.spics_io_num = HSPI_NATIVE_PIN_NUM_CS;
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}
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slave_pull_up(&buscfg, slvcfg.spics_io_num);
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//this does nothing, but avoid the driver from using native pins if required
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buscfg.quadhd_io_num = (!conf->master_native && !conf->slave_native? VSPI_NATIVE_PIN_NUM_MISO: -1);
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TEST_ESP_OK(spi_bus_initialize(HSPI_HOST, &buscfg, 0));
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TEST_ESP_OK(spi_bus_add_device(HSPI_HOST, &devcfg, &spi));
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//slave automatically use native pins if pins are on VSPI_* pins
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buscfg.quadhd_io_num = -1;
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TEST_ESP_OK( spi_slave_initialize(VSPI_HOST, &buscfg, &slvcfg, 0) );
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//initialize master and slave on the same pins break some of the output configs, fix them
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if (conf->master_native) {
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gpio_output_sel(buscfg.mosi_io_num, FUNC_SPI, HSPID_OUT_IDX);
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gpio_output_sel(buscfg.miso_io_num, FUNC_GPIO, VSPIQ_OUT_IDX);
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gpio_output_sel(devcfg.spics_io_num, FUNC_SPI, HSPICS0_OUT_IDX);
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gpio_output_sel(buscfg.sclk_io_num, FUNC_SPI, HSPICLK_OUT_IDX);
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} else if (conf->slave_native) {
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gpio_output_sel(buscfg.mosi_io_num, FUNC_GPIO, HSPID_OUT_IDX);
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gpio_output_sel(buscfg.miso_io_num, FUNC_SPI, VSPIQ_OUT_IDX);
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gpio_output_sel(devcfg.spics_io_num, FUNC_GPIO, HSPICS0_OUT_IDX);
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gpio_output_sel(buscfg.sclk_io_num, FUNC_GPIO, HSPICLK_OUT_IDX);
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} else {
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gpio_output_sel(buscfg.mosi_io_num, FUNC_GPIO, HSPID_OUT_IDX);
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gpio_output_sel(buscfg.miso_io_num, FUNC_GPIO, VSPIQ_OUT_IDX);
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gpio_output_sel(devcfg.spics_io_num, FUNC_GPIO, HSPICS0_OUT_IDX);
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gpio_output_sel(buscfg.sclk_io_num, FUNC_GPIO, HSPICLK_OUT_IDX);
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}
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//clear master receive buffer
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memset(context.master_rxbuf, 0x66, sizeof(context.master_rxbuf));
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//prepare slave tx data
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for (int k = 0; k < 8; k ++) xQueueSend( context.slave_context.data_to_send, &context.slave_trans[k], portMAX_DELAY );
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for( int k= 0; k < 8; k ++ ) {
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//wait for both master and slave end
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ESP_LOGI( MASTER_TAG, "=> test%d", k );
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//send master tx data
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vTaskDelay(9);
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spi_transaction_t *t = &context.master_trans[k];
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TEST_ESP_OK (spi_device_transmit( spi, t) );
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master_print_data(t, conf->dup);
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size_t rcv_len;
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slave_rxdata_t *rcv_data = xRingbufferReceive( context.slave_context.data_received, &rcv_len, portMAX_DELAY );
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slave_print_data(rcv_data);
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//check result
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TEST_ESP_OK(check_data(t, conf->dup, rcv_data));
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//clean
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vRingbufferReturnItem(context.slave_context.data_received, rcv_data);
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}
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master_deinit(spi);
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TEST_ASSERT(spi_slave_free(VSPI_HOST) == ESP_OK);
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}
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}
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vTaskDelete( context.handle_slave );
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context.handle_slave = 0;
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deinit_slave_context(&context.slave_context);
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ESP_LOGI(MASTER_TAG, "test passed.");
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}
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/********************************************************************************
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* Test SPI transaction interval
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