diff --git a/components/driver/i2c.c b/components/driver/i2c.c index 96b4737c9..0acc2f983 100644 --- a/components/driver/i2c.c +++ b/components/driver/i2c.c @@ -303,8 +303,13 @@ esp_err_t i2c_driver_install(i2c_port_t i2c_num, i2c_mode_t mode, size_t slv_rx_ i2c_hw_enable(i2c_num); //Disable I2C interrupt. i2c_hal_disable_intr_mask(&(i2c_context[i2c_num].hal), I2C_INTR_MASK); + i2c_hal_clr_intsts_mask(&(i2c_context[i2c_num].hal), I2C_INTR_MASK); //hook isr handler i2c_isr_register(i2c_num, i2c_isr_handler_default, p_i2c_obj[i2c_num], intr_alloc_flags, &p_i2c_obj[i2c_num]->intr_handle); + //Enable I2C slave rx interrupt + if (mode == I2C_MODE_SLAVE) { + i2c_hal_enable_slave_rx_it(&(i2c_context[i2c_num].hal)); + } return ESP_OK; err: @@ -606,7 +611,6 @@ esp_err_t i2c_param_config(i2c_port_t i2c_num, const i2c_config_t *i2c_conf) //set timing for data i2c_hal_set_sda_timing(&(i2c_context[i2c_num].hal), I2C_SLAVE_SDA_SAMPLE_DEFAULT, I2C_SLAVE_SDA_HOLD_DEFAULT); i2c_hal_set_tout(&(i2c_context[i2c_num].hal), I2C_SLAVE_TIMEOUT_DEFAULT); - i2c_hal_enable_slave_tx_it(&(i2c_context[i2c_num].hal)); i2c_hal_enable_slave_rx_it(&(i2c_context[i2c_num].hal)); } else { i2c_hal_master_init(&(i2c_context[i2c_num].hal), i2c_num); @@ -787,22 +791,17 @@ esp_err_t i2c_set_pin(i2c_port_t i2c_num, int sda_io_num, int scl_io_num, bool s gpio_matrix_out(sda_io_num, sda_out_sig, 0, 0); gpio_matrix_in(sda_io_num, sda_in_sig, 0); } - if (scl_io_num >= 0) { gpio_set_level(scl_io_num, I2C_IO_INIT_LEVEL); PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[scl_io_num], PIN_FUNC_GPIO); - if (mode == I2C_MODE_MASTER) { - gpio_set_direction(scl_io_num, GPIO_MODE_INPUT_OUTPUT_OD); - gpio_matrix_out(scl_io_num, scl_out_sig, 0, 0); - } else { - gpio_set_direction(scl_io_num, GPIO_MODE_INPUT); - } + gpio_set_direction(scl_io_num, GPIO_MODE_INPUT_OUTPUT_OD); + gpio_matrix_out(scl_io_num, scl_out_sig, 0, 0); + gpio_matrix_in(scl_io_num, scl_in_sig, 0); if (scl_pullup_en == GPIO_PULLUP_ENABLE) { gpio_set_pull_mode(scl_io_num, GPIO_PULLUP_ONLY); } else { gpio_set_pull_mode(scl_io_num, GPIO_FLOATING); } - gpio_matrix_in(scl_io_num, scl_in_sig, 0); } #if !I2C_SUPPORT_HW_CLR_BUS i2c_context[i2c_num].scl_io_num = scl_io_num; diff --git a/components/soc/soc/esp32s2/include/soc/i2c_caps.h b/components/soc/soc/esp32s2/include/soc/i2c_caps.h index dddb36eea..08f452ee3 100644 --- a/components/soc/soc/esp32s2/include/soc/i2c_caps.h +++ b/components/soc/soc/esp32s2/include/soc/i2c_caps.h @@ -1,4 +1,4 @@ -// Copyright 2010-2019 Espressif Systems (Shanghai) PTE LTD +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -22,7 +22,7 @@ extern "C" { #define SOC_I2C_NUM (2) #define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */ -#define I2C_INTR_MASK (0x3fff) /*!< I2C all interrupt bitmap */ +#define I2C_INTR_MASK (0x1ffff) /*!< I2C all interrupt bitmap */ //ESP32-S2 support hardware FSM reset #define I2C_SUPPORT_HW_FSM_RST (1) diff --git a/components/soc/soc/esp32s2/include/soc/i2c_reg.h b/components/soc/soc/esp32s2/include/soc/i2c_reg.h index b9d56180b..7cdeca652 100644 --- a/components/soc/soc/esp32s2/include/soc/i2c_reg.h +++ b/components/soc/soc/esp32s2/include/soc/i2c_reg.h @@ -1,9 +1,9 @@ -// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at -// + // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software @@ -76,12 +76,12 @@ extern "C" { #define I2C_MS_MODE_M (BIT(4)) #define I2C_MS_MODE_V 0x1 #define I2C_MS_MODE_S 4 -/* I2C_ACK_LEVEL : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/* I2C_RX_FULL_ACK_LEVEL : R/W ;bitpos:[3] ;default: 1'b1 ; */ /*description: */ -#define I2C_ACK_LEVEL (BIT(3)) -#define I2C_ACK_LEVEL_M (BIT(3)) -#define I2C_ACK_LEVEL_V 0x1 -#define I2C_ACK_LEVEL_S 3 +#define I2C_RX_FULL_ACK_LEVEL (BIT(3)) +#define I2C_RX_FULL_ACK_LEVEL_M (BIT(3)) +#define I2C_RX_FULL_ACK_LEVEL_V 0x1 +#define I2C_RX_FULL_ACK_LEVEL_S 3 /* I2C_SAMPLE_SCL_LEVEL : R/W ;bitpos:[2] ;default: 1'b0 ; */ /*description: */ #define I2C_SAMPLE_SCL_LEVEL (BIT(2)) @@ -120,6 +120,12 @@ extern "C" { #define I2C_TXFIFO_CNT_M ((I2C_TXFIFO_CNT_V)<<(I2C_TXFIFO_CNT_S)) #define I2C_TXFIFO_CNT_V 0x3F #define I2C_TXFIFO_CNT_S 18 +/* I2C_STRETCH_CAUSE : RO ;bitpos:[15:14] ;default: 2'b0 ; */ +/*description: */ +#define I2C_STRETCH_CAUSE 0x00000003 +#define I2C_STRETCH_CAUSE_M ((I2C_STRETCH_CAUSE_V)<<(I2C_STRETCH_CAUSE_S)) +#define I2C_STRETCH_CAUSE_V 0x3 +#define I2C_STRETCH_CAUSE_S 14 /* I2C_RXFIFO_CNT : RO ;bitpos:[13:8] ;default: 6'b0 ; */ /*description: */ #define I2C_RXFIFO_CNT 0x0000003F @@ -162,12 +168,12 @@ extern "C" { #define I2C_SLAVE_RW_M (BIT(1)) #define I2C_SLAVE_RW_V 0x1 #define I2C_SLAVE_RW_S 1 -/* I2C_ACK_REC : RO ;bitpos:[0] ;default: 1'b0 ; */ +/* I2C_RESP_REC : RO ;bitpos:[0] ;default: 1'b0 ; */ /*description: */ -#define I2C_ACK_REC (BIT(0)) -#define I2C_ACK_REC_M (BIT(0)) -#define I2C_ACK_REC_V 0x1 -#define I2C_ACK_REC_S 0 +#define I2C_RESP_REC (BIT(0)) +#define I2C_RESP_REC_M (BIT(0)) +#define I2C_RESP_REC_V 0x1 +#define I2C_RESP_REC_S 0 #define I2C_TO_REG(i) (REG_I2C_BASE(i) + 0x000c) /* I2C_TIME_OUT_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ @@ -197,19 +203,13 @@ extern "C" { #define I2C_SLAVE_ADDR_V 0x7FFF #define I2C_SLAVE_ADDR_S 0 -#define I2C_RXFIFO_ST_REG(i) (REG_I2C_BASE(i) + 0x0014) -/* I2C_RXFIFO_INIT_WADDR : RO ;bitpos:[31:27] ;default: 5'b0 ; */ +#define I2C_FIFO_ST_REG(i) (REG_I2C_BASE(i) + 0x0014) +/* I2C_SLAVE_RW_POINT : RO ;bitpos:[29:22] ;default: 8'b0 ; */ /*description: */ -#define I2C_RXFIFO_INIT_WADDR 0x0000001F -#define I2C_RXFIFO_INIT_WADDR_M ((I2C_RXFIFO_INIT_WADDR_V)<<(I2C_RXFIFO_INIT_WADDR_S)) -#define I2C_RXFIFO_INIT_WADDR_V 0x1F -#define I2C_RXFIFO_INIT_WADDR_S 27 -/* I2C_TXFIFO_INIT_RADDR : RO ;bitpos:[26:22] ;default: 5'b0 ; */ -/*description: */ -#define I2C_TXFIFO_INIT_RADDR 0x0000001F -#define I2C_TXFIFO_INIT_RADDR_M ((I2C_TXFIFO_INIT_RADDR_V)<<(I2C_TXFIFO_INIT_RADDR_S)) -#define I2C_TXFIFO_INIT_RADDR_V 0x1F -#define I2C_TXFIFO_INIT_RADDR_S 22 +#define I2C_SLAVE_RW_POINT 0x000000FF +#define I2C_SLAVE_RW_POINT_M ((I2C_SLAVE_RW_POINT_V)<<(I2C_SLAVE_RW_POINT_S)) +#define I2C_SLAVE_RW_POINT_V 0xFF +#define I2C_SLAVE_RW_POINT_S 22 /* I2C_TX_UPDATE : WO ;bitpos:[21] ;default: 1'b0 ; */ /*description: */ #define I2C_TX_UPDATE (BIT(21)) @@ -248,6 +248,12 @@ extern "C" { #define I2C_RXFIFO_START_ADDR_S 0 #define I2C_FIFO_CONF_REG(i) (REG_I2C_BASE(i) + 0x0018) +/* I2C_FIFO_PRT_EN : R/W ;bitpos:[26] ;default: 1'b1 ; */ +/*description: */ +#define I2C_FIFO_PRT_EN (BIT(26)) +#define I2C_FIFO_PRT_EN_M (BIT(26)) +#define I2C_FIFO_PRT_EN_V 0x1 +#define I2C_FIFO_PRT_EN_S 26 /* I2C_NONFIFO_TX_THRES : R/W ;bitpos:[25:20] ;default: 6'h15 ; */ /*description: */ #define I2C_NONFIFO_TX_THRES 0x0000003F @@ -284,20 +290,18 @@ extern "C" { #define I2C_NONFIFO_EN_M (BIT(10)) #define I2C_NONFIFO_EN_V 0x1 #define I2C_NONFIFO_EN_S 10 -/* I2C_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[9:5] ;default: 5'h4 ; */ +/* I2C_TXFIFO_WM_THRHD : R/W ;bitpos:[9:5] ;default: 5'h4 ; */ /*description: */ -#define I2C_TXFIFO_EMPTY_THRHD 0x0000001F -#define I2C_TXFIFO_EMPTY_THRHD_M ((I2C_TXFIFO_EMPTY_THRHD_V)<<(I2C_TXFIFO_EMPTY_THRHD_S)) -#define I2C_TXFIFO_EMPTY_THRHD_V 0x1F -#define I2C_TXFIFO_EMPTY_THRHD_S 5 -/* I2C_RXFIFO_FULL_THRHD : R/W ;bitpos:[4:0] ;default: 5'hb ; */ +#define I2C_TXFIFO_WM_THRHD 0x0000001F +#define I2C_TXFIFO_WM_THRHD_M ((I2C_TXFIFO_WM_THRHD_V)<<(I2C_TXFIFO_WM_THRHD_S)) +#define I2C_TXFIFO_WM_THRHD_V 0x1F +#define I2C_TXFIFO_WM_THRHD_S 5 +/* I2C_RXFIFO_WM_THRHD : R/W ;bitpos:[4:0] ;default: 5'hb ; */ /*description: */ -#define I2C_RXFIFO_FULL_THRHD 0x0000001F -#define I2C_RXFIFO_FULL_THRHD_M ((I2C_RXFIFO_FULL_THRHD_V)<<(I2C_RXFIFO_FULL_THRHD_S)) -#define I2C_RXFIFO_FULL_THRHD_V 0x1F -#define I2C_RXFIFO_FULL_THRHD_S 0 - -#define I2C_DATA_APB_REG(i) (0x60013000 + (i) * 0x14000 + 0x001c) +#define I2C_RXFIFO_WM_THRHD 0x0000001F +#define I2C_RXFIFO_WM_THRHD_M ((I2C_RXFIFO_WM_THRHD_V)<<(I2C_RXFIFO_WM_THRHD_S)) +#define I2C_RXFIFO_WM_THRHD_V 0x1F +#define I2C_RXFIFO_WM_THRHD_S 0 #define I2C_DATA_REG(i) (REG_I2C_BASE(i) + 0x001c) /* I2C_FIFO_RDATA : RO ;bitpos:[7:0] ;default: 8'b0 ; */ @@ -308,6 +312,12 @@ extern "C" { #define I2C_FIFO_RDATA_S 0 #define I2C_INT_RAW_REG(i) (REG_I2C_BASE(i) + 0x0020) +/* I2C_SLAVE_STRETCH_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define I2C_SLAVE_STRETCH_INT_RAW (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_RAW_M (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_RAW_V 0x1 +#define I2C_SLAVE_STRETCH_INT_RAW_S 16 /* I2C_DET_START_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ /*description: */ #define I2C_DET_START_INT_RAW (BIT(15)) @@ -326,24 +336,24 @@ extern "C" { #define I2C_SCL_ST_TO_INT_RAW_M (BIT(13)) #define I2C_SCL_ST_TO_INT_RAW_V 0x1 #define I2C_SCL_ST_TO_INT_RAW_S 13 -/* I2C_TX_SEND_EMPTY_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/* I2C_RXFIFO_UDF_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ /*description: */ -#define I2C_TX_SEND_EMPTY_INT_RAW (BIT(12)) -#define I2C_TX_SEND_EMPTY_INT_RAW_M (BIT(12)) -#define I2C_TX_SEND_EMPTY_INT_RAW_V 0x1 -#define I2C_TX_SEND_EMPTY_INT_RAW_S 12 -/* I2C_RX_REC_FULL_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +#define I2C_RXFIFO_UDF_INT_RAW (BIT(12)) +#define I2C_RXFIFO_UDF_INT_RAW_M (BIT(12)) +#define I2C_RXFIFO_UDF_INT_RAW_V 0x1 +#define I2C_RXFIFO_UDF_INT_RAW_S 12 +/* I2C_TXFIFO_OVF_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ /*description: */ -#define I2C_RX_REC_FULL_INT_RAW (BIT(11)) -#define I2C_RX_REC_FULL_INT_RAW_M (BIT(11)) -#define I2C_RX_REC_FULL_INT_RAW_V 0x1 -#define I2C_RX_REC_FULL_INT_RAW_S 11 -/* I2C_ACK_ERR_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +#define I2C_TXFIFO_OVF_INT_RAW (BIT(11)) +#define I2C_TXFIFO_OVF_INT_RAW_M (BIT(11)) +#define I2C_TXFIFO_OVF_INT_RAW_V 0x1 +#define I2C_TXFIFO_OVF_INT_RAW_S 11 +/* I2C_NACK_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ /*description: */ -#define I2C_ACK_ERR_INT_RAW (BIT(10)) -#define I2C_ACK_ERR_INT_RAW_M (BIT(10)) -#define I2C_ACK_ERR_INT_RAW_V 0x1 -#define I2C_ACK_ERR_INT_RAW_S 10 +#define I2C_NACK_INT_RAW (BIT(10)) +#define I2C_NACK_INT_RAW_M (BIT(10)) +#define I2C_NACK_INT_RAW_V 0x1 +#define I2C_NACK_INT_RAW_S 10 /* I2C_TRANS_START_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ /*description: */ #define I2C_TRANS_START_INT_RAW (BIT(9)) @@ -362,24 +372,24 @@ extern "C" { #define I2C_TRANS_COMPLETE_INT_RAW_M (BIT(7)) #define I2C_TRANS_COMPLETE_INT_RAW_V 0x1 #define I2C_TRANS_COMPLETE_INT_RAW_S 7 -/* I2C_MASTER_TRAN_COMP_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/* I2C_MST_TXFIFO_UDF_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ /*description: */ -#define I2C_MASTER_TRAN_COMP_INT_RAW (BIT(6)) -#define I2C_MASTER_TRAN_COMP_INT_RAW_M (BIT(6)) -#define I2C_MASTER_TRAN_COMP_INT_RAW_V 0x1 -#define I2C_MASTER_TRAN_COMP_INT_RAW_S 6 +#define I2C_MST_TXFIFO_UDF_INT_RAW (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_RAW_M (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_RAW_V 0x1 +#define I2C_MST_TXFIFO_UDF_INT_RAW_S 6 /* I2C_ARBITRATION_LOST_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ /*description: */ #define I2C_ARBITRATION_LOST_INT_RAW (BIT(5)) #define I2C_ARBITRATION_LOST_INT_RAW_M (BIT(5)) #define I2C_ARBITRATION_LOST_INT_RAW_V 0x1 #define I2C_ARBITRATION_LOST_INT_RAW_S 5 -/* I2C_SLAVE_TRAN_COMP_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/* I2C_BYTE_TRANS_DONE_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ /*description: */ -#define I2C_SLAVE_TRAN_COMP_INT_RAW (BIT(4)) -#define I2C_SLAVE_TRAN_COMP_INT_RAW_M (BIT(4)) -#define I2C_SLAVE_TRAN_COMP_INT_RAW_V 0x1 -#define I2C_SLAVE_TRAN_COMP_INT_RAW_S 4 +#define I2C_BYTE_TRANS_DONE_INT_RAW (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_RAW_M (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_RAW_V 0x1 +#define I2C_BYTE_TRANS_DONE_INT_RAW_S 4 /* I2C_END_DETECT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ /*description: */ #define I2C_END_DETECT_INT_RAW (BIT(3)) @@ -392,20 +402,26 @@ extern "C" { #define I2C_RXFIFO_OVF_INT_RAW_M (BIT(2)) #define I2C_RXFIFO_OVF_INT_RAW_V 0x1 #define I2C_RXFIFO_OVF_INT_RAW_S 2 -/* I2C_TXFIFO_EMPTY_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/* I2C_TXFIFO_WM_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ /*description: */ -#define I2C_TXFIFO_EMPTY_INT_RAW (BIT(1)) -#define I2C_TXFIFO_EMPTY_INT_RAW_M (BIT(1)) -#define I2C_TXFIFO_EMPTY_INT_RAW_V 0x1 -#define I2C_TXFIFO_EMPTY_INT_RAW_S 1 -/* I2C_RXFIFO_FULL_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +#define I2C_TXFIFO_WM_INT_RAW (BIT(1)) +#define I2C_TXFIFO_WM_INT_RAW_M (BIT(1)) +#define I2C_TXFIFO_WM_INT_RAW_V 0x1 +#define I2C_TXFIFO_WM_INT_RAW_S 1 +/* I2C_RXFIFO_WM_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ /*description: */ -#define I2C_RXFIFO_FULL_INT_RAW (BIT(0)) -#define I2C_RXFIFO_FULL_INT_RAW_M (BIT(0)) -#define I2C_RXFIFO_FULL_INT_RAW_V 0x1 -#define I2C_RXFIFO_FULL_INT_RAW_S 0 +#define I2C_RXFIFO_WM_INT_RAW (BIT(0)) +#define I2C_RXFIFO_WM_INT_RAW_M (BIT(0)) +#define I2C_RXFIFO_WM_INT_RAW_V 0x1 +#define I2C_RXFIFO_WM_INT_RAW_S 0 #define I2C_INT_CLR_REG(i) (REG_I2C_BASE(i) + 0x0024) +/* I2C_SLAVE_STRETCH_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define I2C_SLAVE_STRETCH_INT_CLR (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_CLR_M (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_CLR_V 0x1 +#define I2C_SLAVE_STRETCH_INT_CLR_S 16 /* I2C_DET_START_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ /*description: */ #define I2C_DET_START_INT_CLR (BIT(15)) @@ -424,24 +440,24 @@ extern "C" { #define I2C_SCL_ST_TO_INT_CLR_M (BIT(13)) #define I2C_SCL_ST_TO_INT_CLR_V 0x1 #define I2C_SCL_ST_TO_INT_CLR_S 13 -/* I2C_TX_SEND_EMPTY_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/* I2C_RXFIFO_UDF_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ /*description: */ -#define I2C_TX_SEND_EMPTY_INT_CLR (BIT(12)) -#define I2C_TX_SEND_EMPTY_INT_CLR_M (BIT(12)) -#define I2C_TX_SEND_EMPTY_INT_CLR_V 0x1 -#define I2C_TX_SEND_EMPTY_INT_CLR_S 12 -/* I2C_RX_REC_FULL_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +#define I2C_RXFIFO_UDF_INT_CLR (BIT(12)) +#define I2C_RXFIFO_UDF_INT_CLR_M (BIT(12)) +#define I2C_RXFIFO_UDF_INT_CLR_V 0x1 +#define I2C_RXFIFO_UDF_INT_CLR_S 12 +/* I2C_TXFIFO_OVF_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ /*description: */ -#define I2C_RX_REC_FULL_INT_CLR (BIT(11)) -#define I2C_RX_REC_FULL_INT_CLR_M (BIT(11)) -#define I2C_RX_REC_FULL_INT_CLR_V 0x1 -#define I2C_RX_REC_FULL_INT_CLR_S 11 -/* I2C_ACK_ERR_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +#define I2C_TXFIFO_OVF_INT_CLR (BIT(11)) +#define I2C_TXFIFO_OVF_INT_CLR_M (BIT(11)) +#define I2C_TXFIFO_OVF_INT_CLR_V 0x1 +#define I2C_TXFIFO_OVF_INT_CLR_S 11 +/* I2C_NACK_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ /*description: */ -#define I2C_ACK_ERR_INT_CLR (BIT(10)) -#define I2C_ACK_ERR_INT_CLR_M (BIT(10)) -#define I2C_ACK_ERR_INT_CLR_V 0x1 -#define I2C_ACK_ERR_INT_CLR_S 10 +#define I2C_NACK_INT_CLR (BIT(10)) +#define I2C_NACK_INT_CLR_M (BIT(10)) +#define I2C_NACK_INT_CLR_V 0x1 +#define I2C_NACK_INT_CLR_S 10 /* I2C_TRANS_START_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ /*description: */ #define I2C_TRANS_START_INT_CLR (BIT(9)) @@ -460,24 +476,24 @@ extern "C" { #define I2C_TRANS_COMPLETE_INT_CLR_M (BIT(7)) #define I2C_TRANS_COMPLETE_INT_CLR_V 0x1 #define I2C_TRANS_COMPLETE_INT_CLR_S 7 -/* I2C_MASTER_TRAN_COMP_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/* I2C_MST_TXFIFO_UDF_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ /*description: */ -#define I2C_MASTER_TRAN_COMP_INT_CLR (BIT(6)) -#define I2C_MASTER_TRAN_COMP_INT_CLR_M (BIT(6)) -#define I2C_MASTER_TRAN_COMP_INT_CLR_V 0x1 -#define I2C_MASTER_TRAN_COMP_INT_CLR_S 6 +#define I2C_MST_TXFIFO_UDF_INT_CLR (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_CLR_M (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_CLR_V 0x1 +#define I2C_MST_TXFIFO_UDF_INT_CLR_S 6 /* I2C_ARBITRATION_LOST_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ /*description: */ #define I2C_ARBITRATION_LOST_INT_CLR (BIT(5)) #define I2C_ARBITRATION_LOST_INT_CLR_M (BIT(5)) #define I2C_ARBITRATION_LOST_INT_CLR_V 0x1 #define I2C_ARBITRATION_LOST_INT_CLR_S 5 -/* I2C_SLAVE_TRAN_COMP_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/* I2C_BYTE_TRANS_DONE_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ /*description: */ -#define I2C_SLAVE_TRAN_COMP_INT_CLR (BIT(4)) -#define I2C_SLAVE_TRAN_COMP_INT_CLR_M (BIT(4)) -#define I2C_SLAVE_TRAN_COMP_INT_CLR_V 0x1 -#define I2C_SLAVE_TRAN_COMP_INT_CLR_S 4 +#define I2C_BYTE_TRANS_DONE_INT_CLR (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_CLR_M (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_CLR_V 0x1 +#define I2C_BYTE_TRANS_DONE_INT_CLR_S 4 /* I2C_END_DETECT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ /*description: */ #define I2C_END_DETECT_INT_CLR (BIT(3)) @@ -490,20 +506,26 @@ extern "C" { #define I2C_RXFIFO_OVF_INT_CLR_M (BIT(2)) #define I2C_RXFIFO_OVF_INT_CLR_V 0x1 #define I2C_RXFIFO_OVF_INT_CLR_S 2 -/* I2C_TXFIFO_EMPTY_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/* I2C_TXFIFO_WM_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ /*description: */ -#define I2C_TXFIFO_EMPTY_INT_CLR (BIT(1)) -#define I2C_TXFIFO_EMPTY_INT_CLR_M (BIT(1)) -#define I2C_TXFIFO_EMPTY_INT_CLR_V 0x1 -#define I2C_TXFIFO_EMPTY_INT_CLR_S 1 -/* I2C_RXFIFO_FULL_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +#define I2C_TXFIFO_WM_INT_CLR (BIT(1)) +#define I2C_TXFIFO_WM_INT_CLR_M (BIT(1)) +#define I2C_TXFIFO_WM_INT_CLR_V 0x1 +#define I2C_TXFIFO_WM_INT_CLR_S 1 +/* I2C_RXFIFO_WM_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ /*description: */ -#define I2C_RXFIFO_FULL_INT_CLR (BIT(0)) -#define I2C_RXFIFO_FULL_INT_CLR_M (BIT(0)) -#define I2C_RXFIFO_FULL_INT_CLR_V 0x1 -#define I2C_RXFIFO_FULL_INT_CLR_S 0 +#define I2C_RXFIFO_WM_INT_CLR (BIT(0)) +#define I2C_RXFIFO_WM_INT_CLR_M (BIT(0)) +#define I2C_RXFIFO_WM_INT_CLR_V 0x1 +#define I2C_RXFIFO_WM_INT_CLR_S 0 #define I2C_INT_ENA_REG(i) (REG_I2C_BASE(i) + 0x0028) +/* I2C_SLAVE_STRETCH_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define I2C_SLAVE_STRETCH_INT_ENA (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_ENA_M (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_ENA_V 0x1 +#define I2C_SLAVE_STRETCH_INT_ENA_S 16 /* I2C_DET_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ /*description: */ #define I2C_DET_START_INT_ENA (BIT(15)) @@ -522,24 +544,24 @@ extern "C" { #define I2C_SCL_ST_TO_INT_ENA_M (BIT(13)) #define I2C_SCL_ST_TO_INT_ENA_V 0x1 #define I2C_SCL_ST_TO_INT_ENA_S 13 -/* I2C_TX_SEND_EMPTY_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/* I2C_RXFIFO_UDF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ /*description: */ -#define I2C_TX_SEND_EMPTY_INT_ENA (BIT(12)) -#define I2C_TX_SEND_EMPTY_INT_ENA_M (BIT(12)) -#define I2C_TX_SEND_EMPTY_INT_ENA_V 0x1 -#define I2C_TX_SEND_EMPTY_INT_ENA_S 12 -/* I2C_RX_REC_FULL_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +#define I2C_RXFIFO_UDF_INT_ENA (BIT(12)) +#define I2C_RXFIFO_UDF_INT_ENA_M (BIT(12)) +#define I2C_RXFIFO_UDF_INT_ENA_V 0x1 +#define I2C_RXFIFO_UDF_INT_ENA_S 12 +/* I2C_TXFIFO_OVF_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ /*description: */ -#define I2C_RX_REC_FULL_INT_ENA (BIT(11)) -#define I2C_RX_REC_FULL_INT_ENA_M (BIT(11)) -#define I2C_RX_REC_FULL_INT_ENA_V 0x1 -#define I2C_RX_REC_FULL_INT_ENA_S 11 -/* I2C_ACK_ERR_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +#define I2C_TXFIFO_OVF_INT_ENA (BIT(11)) +#define I2C_TXFIFO_OVF_INT_ENA_M (BIT(11)) +#define I2C_TXFIFO_OVF_INT_ENA_V 0x1 +#define I2C_TXFIFO_OVF_INT_ENA_S 11 +/* I2C_NACK_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ /*description: */ -#define I2C_ACK_ERR_INT_ENA (BIT(10)) -#define I2C_ACK_ERR_INT_ENA_M (BIT(10)) -#define I2C_ACK_ERR_INT_ENA_V 0x1 -#define I2C_ACK_ERR_INT_ENA_S 10 +#define I2C_NACK_INT_ENA (BIT(10)) +#define I2C_NACK_INT_ENA_M (BIT(10)) +#define I2C_NACK_INT_ENA_V 0x1 +#define I2C_NACK_INT_ENA_S 10 /* I2C_TRANS_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ /*description: */ #define I2C_TRANS_START_INT_ENA (BIT(9)) @@ -558,24 +580,24 @@ extern "C" { #define I2C_TRANS_COMPLETE_INT_ENA_M (BIT(7)) #define I2C_TRANS_COMPLETE_INT_ENA_V 0x1 #define I2C_TRANS_COMPLETE_INT_ENA_S 7 -/* I2C_MASTER_TRAN_COMP_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/* I2C_MST_TXFIFO_UDF_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ /*description: */ -#define I2C_MASTER_TRAN_COMP_INT_ENA (BIT(6)) -#define I2C_MASTER_TRAN_COMP_INT_ENA_M (BIT(6)) -#define I2C_MASTER_TRAN_COMP_INT_ENA_V 0x1 -#define I2C_MASTER_TRAN_COMP_INT_ENA_S 6 +#define I2C_MST_TXFIFO_UDF_INT_ENA (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_ENA_M (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_ENA_V 0x1 +#define I2C_MST_TXFIFO_UDF_INT_ENA_S 6 /* I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ /*description: */ #define I2C_ARBITRATION_LOST_INT_ENA (BIT(5)) #define I2C_ARBITRATION_LOST_INT_ENA_M (BIT(5)) #define I2C_ARBITRATION_LOST_INT_ENA_V 0x1 #define I2C_ARBITRATION_LOST_INT_ENA_S 5 -/* I2C_SLAVE_TRAN_COMP_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/* I2C_BYTE_TRANS_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ /*description: */ -#define I2C_SLAVE_TRAN_COMP_INT_ENA (BIT(4)) -#define I2C_SLAVE_TRAN_COMP_INT_ENA_M (BIT(4)) -#define I2C_SLAVE_TRAN_COMP_INT_ENA_V 0x1 -#define I2C_SLAVE_TRAN_COMP_INT_ENA_S 4 +#define I2C_BYTE_TRANS_DONE_INT_ENA (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_ENA_M (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_ENA_V 0x1 +#define I2C_BYTE_TRANS_DONE_INT_ENA_S 4 /* I2C_END_DETECT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ /*description: */ #define I2C_END_DETECT_INT_ENA (BIT(3)) @@ -588,20 +610,26 @@ extern "C" { #define I2C_RXFIFO_OVF_INT_ENA_M (BIT(2)) #define I2C_RXFIFO_OVF_INT_ENA_V 0x1 #define I2C_RXFIFO_OVF_INT_ENA_S 2 -/* I2C_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/* I2C_TXFIFO_WM_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ /*description: */ -#define I2C_TXFIFO_EMPTY_INT_ENA (BIT(1)) -#define I2C_TXFIFO_EMPTY_INT_ENA_M (BIT(1)) -#define I2C_TXFIFO_EMPTY_INT_ENA_V 0x1 -#define I2C_TXFIFO_EMPTY_INT_ENA_S 1 -/* I2C_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +#define I2C_TXFIFO_WM_INT_ENA (BIT(1)) +#define I2C_TXFIFO_WM_INT_ENA_M (BIT(1)) +#define I2C_TXFIFO_WM_INT_ENA_V 0x1 +#define I2C_TXFIFO_WM_INT_ENA_S 1 +/* I2C_RXFIFO_WM_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ /*description: */ -#define I2C_RXFIFO_FULL_INT_ENA (BIT(0)) -#define I2C_RXFIFO_FULL_INT_ENA_M (BIT(0)) -#define I2C_RXFIFO_FULL_INT_ENA_V 0x1 -#define I2C_RXFIFO_FULL_INT_ENA_S 0 +#define I2C_RXFIFO_WM_INT_ENA (BIT(0)) +#define I2C_RXFIFO_WM_INT_ENA_M (BIT(0)) +#define I2C_RXFIFO_WM_INT_ENA_V 0x1 +#define I2C_RXFIFO_WM_INT_ENA_S 0 #define I2C_INT_STATUS_REG(i) (REG_I2C_BASE(i) + 0x002c) +/* I2C_SLAVE_STRETCH_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define I2C_SLAVE_STRETCH_INT_ST (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_ST_M (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_ST_V 0x1 +#define I2C_SLAVE_STRETCH_INT_ST_S 16 /* I2C_DET_START_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ /*description: */ #define I2C_DET_START_INT_ST (BIT(15)) @@ -620,24 +648,24 @@ extern "C" { #define I2C_SCL_ST_TO_INT_ST_M (BIT(13)) #define I2C_SCL_ST_TO_INT_ST_V 0x1 #define I2C_SCL_ST_TO_INT_ST_S 13 -/* I2C_TX_SEND_EMPTY_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/* I2C_RXFIFO_UDF_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ /*description: */ -#define I2C_TX_SEND_EMPTY_INT_ST (BIT(12)) -#define I2C_TX_SEND_EMPTY_INT_ST_M (BIT(12)) -#define I2C_TX_SEND_EMPTY_INT_ST_V 0x1 -#define I2C_TX_SEND_EMPTY_INT_ST_S 12 -/* I2C_RX_REC_FULL_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +#define I2C_RXFIFO_UDF_INT_ST (BIT(12)) +#define I2C_RXFIFO_UDF_INT_ST_M (BIT(12)) +#define I2C_RXFIFO_UDF_INT_ST_V 0x1 +#define I2C_RXFIFO_UDF_INT_ST_S 12 +/* I2C_TXFIFO_OVF_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ /*description: */ -#define I2C_RX_REC_FULL_INT_ST (BIT(11)) -#define I2C_RX_REC_FULL_INT_ST_M (BIT(11)) -#define I2C_RX_REC_FULL_INT_ST_V 0x1 -#define I2C_RX_REC_FULL_INT_ST_S 11 -/* I2C_ACK_ERR_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +#define I2C_TXFIFO_OVF_INT_ST (BIT(11)) +#define I2C_TXFIFO_OVF_INT_ST_M (BIT(11)) +#define I2C_TXFIFO_OVF_INT_ST_V 0x1 +#define I2C_TXFIFO_OVF_INT_ST_S 11 +/* I2C_NACK_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ /*description: */ -#define I2C_ACK_ERR_INT_ST (BIT(10)) -#define I2C_ACK_ERR_INT_ST_M (BIT(10)) -#define I2C_ACK_ERR_INT_ST_V 0x1 -#define I2C_ACK_ERR_INT_ST_S 10 +#define I2C_NACK_INT_ST (BIT(10)) +#define I2C_NACK_INT_ST_M (BIT(10)) +#define I2C_NACK_INT_ST_V 0x1 +#define I2C_NACK_INT_ST_S 10 /* I2C_TRANS_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ /*description: */ #define I2C_TRANS_START_INT_ST (BIT(9)) @@ -656,24 +684,24 @@ extern "C" { #define I2C_TRANS_COMPLETE_INT_ST_M (BIT(7)) #define I2C_TRANS_COMPLETE_INT_ST_V 0x1 #define I2C_TRANS_COMPLETE_INT_ST_S 7 -/* I2C_MASTER_TRAN_COMP_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/* I2C_MST_TXFIFO_UDF_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ /*description: */ -#define I2C_MASTER_TRAN_COMP_INT_ST (BIT(6)) -#define I2C_MASTER_TRAN_COMP_INT_ST_M (BIT(6)) -#define I2C_MASTER_TRAN_COMP_INT_ST_V 0x1 -#define I2C_MASTER_TRAN_COMP_INT_ST_S 6 +#define I2C_MST_TXFIFO_UDF_INT_ST (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_ST_M (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_ST_V 0x1 +#define I2C_MST_TXFIFO_UDF_INT_ST_S 6 /* I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ /*description: */ #define I2C_ARBITRATION_LOST_INT_ST (BIT(5)) #define I2C_ARBITRATION_LOST_INT_ST_M (BIT(5)) #define I2C_ARBITRATION_LOST_INT_ST_V 0x1 #define I2C_ARBITRATION_LOST_INT_ST_S 5 -/* I2C_SLAVE_TRAN_COMP_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/* I2C_BYTE_TRANS_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ /*description: */ -#define I2C_SLAVE_TRAN_COMP_INT_ST (BIT(4)) -#define I2C_SLAVE_TRAN_COMP_INT_ST_M (BIT(4)) -#define I2C_SLAVE_TRAN_COMP_INT_ST_V 0x1 -#define I2C_SLAVE_TRAN_COMP_INT_ST_S 4 +#define I2C_BYTE_TRANS_DONE_INT_ST (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_ST_M (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_ST_V 0x1 +#define I2C_BYTE_TRANS_DONE_INT_ST_S 4 /* I2C_END_DETECT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ /*description: */ #define I2C_END_DETECT_INT_ST (BIT(3)) @@ -686,18 +714,18 @@ extern "C" { #define I2C_RXFIFO_OVF_INT_ST_M (BIT(2)) #define I2C_RXFIFO_OVF_INT_ST_V 0x1 #define I2C_RXFIFO_OVF_INT_ST_S 2 -/* I2C_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/* I2C_TXFIFO_WM_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ /*description: */ -#define I2C_TXFIFO_EMPTY_INT_ST (BIT(1)) -#define I2C_TXFIFO_EMPTY_INT_ST_M (BIT(1)) -#define I2C_TXFIFO_EMPTY_INT_ST_V 0x1 -#define I2C_TXFIFO_EMPTY_INT_ST_S 1 -/* I2C_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +#define I2C_TXFIFO_WM_INT_ST (BIT(1)) +#define I2C_TXFIFO_WM_INT_ST_M (BIT(1)) +#define I2C_TXFIFO_WM_INT_ST_V 0x1 +#define I2C_TXFIFO_WM_INT_ST_S 1 +/* I2C_RXFIFO_WM_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ /*description: */ -#define I2C_RXFIFO_FULL_INT_ST (BIT(0)) -#define I2C_RXFIFO_FULL_INT_ST_M (BIT(0)) -#define I2C_RXFIFO_FULL_INT_ST_V 0x1 -#define I2C_RXFIFO_FULL_INT_ST_S 0 +#define I2C_RXFIFO_WM_INT_ST (BIT(0)) +#define I2C_RXFIFO_WM_INT_ST_M (BIT(0)) +#define I2C_RXFIFO_WM_INT_ST_V 0x1 +#define I2C_RXFIFO_WM_INT_ST_S 0 #define I2C_SDA_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0030) /* I2C_SDA_HOLD_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */ @@ -762,31 +790,31 @@ extern "C" { #define I2C_SCL_STOP_SETUP_TIME_S 0 #define I2C_SCL_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x0050) -/* I2C_SCL_FILTER_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/* I2C_SCL_FILTER_EN : R/W ;bitpos:[4] ;default: 1'b1 ; */ /*description: */ -#define I2C_SCL_FILTER_EN (BIT(3)) -#define I2C_SCL_FILTER_EN_M (BIT(3)) +#define I2C_SCL_FILTER_EN (BIT(4)) +#define I2C_SCL_FILTER_EN_M (BIT(4)) #define I2C_SCL_FILTER_EN_V 0x1 -#define I2C_SCL_FILTER_EN_S 3 -/* I2C_SCL_FILTER_THRES : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ +#define I2C_SCL_FILTER_EN_S 4 +/* I2C_SCL_FILTER_THRES : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ /*description: */ -#define I2C_SCL_FILTER_THRES 0x00000007 +#define I2C_SCL_FILTER_THRES 0x0000000F #define I2C_SCL_FILTER_THRES_M ((I2C_SCL_FILTER_THRES_V)<<(I2C_SCL_FILTER_THRES_S)) -#define I2C_SCL_FILTER_THRES_V 0x7 +#define I2C_SCL_FILTER_THRES_V 0xF #define I2C_SCL_FILTER_THRES_S 0 #define I2C_SDA_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x0054) -/* I2C_SDA_FILTER_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/* I2C_SDA_FILTER_EN : R/W ;bitpos:[4] ;default: 1'b1 ; */ /*description: */ -#define I2C_SDA_FILTER_EN (BIT(3)) -#define I2C_SDA_FILTER_EN_M (BIT(3)) +#define I2C_SDA_FILTER_EN (BIT(4)) +#define I2C_SDA_FILTER_EN_M (BIT(4)) #define I2C_SDA_FILTER_EN_V 0x1 -#define I2C_SDA_FILTER_EN_S 3 -/* I2C_SDA_FILTER_THRES : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ +#define I2C_SDA_FILTER_EN_S 4 +/* I2C_SDA_FILTER_THRES : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ /*description: */ -#define I2C_SDA_FILTER_THRES 0x00000007 +#define I2C_SDA_FILTER_THRES 0x0000000F #define I2C_SDA_FILTER_THRES_M ((I2C_SDA_FILTER_THRES_V)<<(I2C_SDA_FILTER_THRES_S)) -#define I2C_SDA_FILTER_THRES_V 0x7 +#define I2C_SDA_FILTER_THRES_V 0xF #define I2C_SDA_FILTER_THRES_S 0 #define I2C_COMD0_REG(i) (REG_I2C_BASE(i) + 0x0058) @@ -1055,15 +1083,37 @@ extern "C" { #define I2C_SCL_RST_SLV_EN_V 0x1 #define I2C_SCL_RST_SLV_EN_S 0 +#define I2C_SCL_STRETCH_CONF_REG(i) (REG_I2C_BASE(i) + 0x00a4) +/* I2C_SLAVE_SCL_STRETCH_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define I2C_SLAVE_SCL_STRETCH_CLR (BIT(11)) +#define I2C_SLAVE_SCL_STRETCH_CLR_M (BIT(11)) +#define I2C_SLAVE_SCL_STRETCH_CLR_V 0x1 +#define I2C_SLAVE_SCL_STRETCH_CLR_S 11 +/* I2C_SLAVE_SCL_STRETCH_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define I2C_SLAVE_SCL_STRETCH_EN (BIT(10)) +#define I2C_SLAVE_SCL_STRETCH_EN_M (BIT(10)) +#define I2C_SLAVE_SCL_STRETCH_EN_V 0x1 +#define I2C_SLAVE_SCL_STRETCH_EN_S 10 +/* I2C_STRETCH_PROTECT_NUM : R/W ;bitpos:[9:0] ;default: 10'b0 ; */ +/*description: */ +#define I2C_STRETCH_PROTECT_NUM 0x000003FF +#define I2C_STRETCH_PROTECT_NUM_M ((I2C_STRETCH_PROTECT_NUM_V)<<(I2C_STRETCH_PROTECT_NUM_S)) +#define I2C_STRETCH_PROTECT_NUM_V 0x3FF +#define I2C_STRETCH_PROTECT_NUM_S 0 + #define I2C_DATE_REG(i) (REG_I2C_BASE(i) + 0x00F8) -/* I2C_DATE : R/W ;bitpos:[31:0] ;default: 32'h18073100 ; */ +/* I2C_DATE : R/W ;bitpos:[31:0] ;default: 32'h19052000 ; */ /*description: */ #define I2C_DATE 0xFFFFFFFF #define I2C_DATE_M ((I2C_DATE_V)<<(I2C_DATE_S)) #define I2C_DATE_V 0xFFFFFFFF #define I2C_DATE_S 0 -#define I2C_FIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x0100) +#define I2C_TXFIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x0100) + +#define I2C_RXFIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x0180) #ifdef __cplusplus } @@ -1073,4 +1123,3 @@ extern "C" { #endif /*_SOC_I2C_REG_H_ */ - diff --git a/components/soc/soc/esp32s2/include/soc/i2c_struct.h b/components/soc/soc/esp32s2/include/soc/i2c_struct.h index f14269eb1..3330d9303 100644 --- a/components/soc/soc/esp32s2/include/soc/i2c_struct.h +++ b/components/soc/soc/esp32s2/include/soc/i2c_struct.h @@ -1,9 +1,9 @@ -// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at -// + // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software @@ -27,25 +27,25 @@ typedef volatile struct { } scl_low_period; union { struct { - uint32_t sda_force_out: 1; - uint32_t scl_force_out: 1; - uint32_t sample_scl_level: 1; - uint32_t ack_level: 1; - uint32_t ms_mode: 1; - uint32_t trans_start: 1; - uint32_t tx_lsb_first: 1; - uint32_t rx_lsb_first: 1; - uint32_t clk_en: 1; - uint32_t arbitration_en: 1; - uint32_t fsm_rst: 1; - uint32_t ref_always_on: 1; - uint32_t reserved12: 20; + uint32_t sda_force_out: 1; + uint32_t scl_force_out: 1; + uint32_t sample_scl_level: 1; + uint32_t rx_full_ack_level: 1; + uint32_t ms_mode: 1; + uint32_t trans_start: 1; + uint32_t tx_lsb_first: 1; + uint32_t rx_lsb_first: 1; + uint32_t clk_en: 1; + uint32_t arbitration_en: 1; + uint32_t fsm_rst: 1; + uint32_t ref_always_on: 1; + uint32_t reserved12: 20; }; uint32_t val; } ctr; union { struct { - uint32_t ack_rec: 1; + uint32_t resp_rec: 1; uint32_t slave_rw: 1; uint32_t time_out: 1; uint32_t arb_lost: 1; @@ -54,7 +54,8 @@ typedef volatile struct { uint32_t byte_trans: 1; uint32_t reserved7: 1; uint32_t rx_fifo_cnt: 6; - uint32_t reserved14: 4; + uint32_t stretch_cause: 2; + uint32_t reserved16: 2; uint32_t tx_fifo_cnt: 6; uint32_t scl_main_state_last: 3; uint32_t reserved27: 1; @@ -87,117 +88,121 @@ typedef volatile struct { uint32_t tx_fifo_end_addr: 5; uint32_t rx_update: 1; uint32_t tx_update: 1; - uint32_t tx_fifo_init_raddr: 5; - uint32_t rx_fifo_init_waddr: 5; + uint32_t slave_rw_point: 8; + uint32_t reserved30: 2; }; uint32_t val; } fifo_st; union { struct { - uint32_t rx_fifo_full_thrhd: 5; - uint32_t tx_fifo_empty_thrhd: 5; - uint32_t nonfifo_en: 1; - uint32_t fifo_addr_cfg_en: 1; - uint32_t rx_fifo_rst: 1; - uint32_t tx_fifo_rst: 1; - uint32_t nonfifo_rx_thres: 6; - uint32_t nonfifo_tx_thres: 6; - uint32_t reserved26: 6; + uint32_t rx_fifo_wm_thrhd: 5; + uint32_t tx_fifo_wm_thrhd: 5; + uint32_t nonfifo_en: 1; + uint32_t fifo_addr_cfg_en: 1; + uint32_t rx_fifo_rst: 1; + uint32_t tx_fifo_rst: 1; + uint32_t nonfifo_rx_thres: 6; + uint32_t nonfifo_tx_thres: 6; + uint32_t fifo_prt_en: 1; + uint32_t reserved27: 5; }; uint32_t val; } fifo_conf; union { struct { - uint8_t data; - uint8_t reserved[3]; + uint32_t data; }; uint32_t val; } fifo_data; union { struct { - uint32_t rx_fifo_full: 1; - uint32_t tx_fifo_empty: 1; + uint32_t rx_fifo_wm: 1; + uint32_t tx_fifo_wm: 1; uint32_t rx_fifo_ovf: 1; uint32_t end_detect: 1; - uint32_t slave_tran_comp: 1; + uint32_t byte_trans_done: 1; uint32_t arbitration_lost: 1; - uint32_t master_tran_comp: 1; + uint32_t mst_tx_fifo_udf: 1; uint32_t trans_complete: 1; uint32_t time_out: 1; uint32_t trans_start: 1; - uint32_t ack_err: 1; - uint32_t rx_rec_full: 1; - uint32_t tx_send_empty: 1; + uint32_t nack: 1; + uint32_t tx_fifo_ovf: 1; + uint32_t rx_fifo_udf: 1; uint32_t scl_st_to: 1; uint32_t scl_main_st_to: 1; uint32_t det_start: 1; - uint32_t reserved16: 16; + uint32_t slave_stretch: 1; + uint32_t reserved17: 15; }; uint32_t val; } int_raw; union { struct { - uint32_t rx_fifo_full: 1; - uint32_t tx_fifo_empty: 1; + uint32_t rx_fifo_wm: 1; + uint32_t tx_fifo_wm: 1; uint32_t rx_fifo_ovf: 1; uint32_t end_detect: 1; - uint32_t slave_tran_comp: 1; + uint32_t byte_trans_done: 1; uint32_t arbitration_lost: 1; - uint32_t master_tran_comp: 1; + uint32_t mst_tx_fifo_udf: 1; uint32_t trans_complete: 1; uint32_t time_out: 1; uint32_t trans_start: 1; - uint32_t ack_err: 1; - uint32_t rx_rec_full: 1; - uint32_t tx_send_empty: 1; + uint32_t nack: 1; + uint32_t tx_fifo_ovf: 1; + uint32_t rx_fifo_udf: 1; uint32_t scl_st_to: 1; uint32_t scl_main_st_to: 1; uint32_t det_start: 1; - uint32_t reserved16: 16; + uint32_t slave_stretch: 1; + uint32_t reserved17: 15; }; uint32_t val; } int_clr; union { struct { - uint32_t rx_fifo_full: 1; - uint32_t tx_fifo_empty: 1; + uint32_t rx_fifo_wm: 1; + uint32_t tx_fifo_wm: 1; uint32_t rx_fifo_ovf: 1; uint32_t end_detect: 1; - uint32_t slave_tran_comp: 1; + uint32_t byte_trans_done: 1; uint32_t arbitration_lost: 1; - uint32_t master_tran_comp: 1; + uint32_t mst_tx_fifo_udf: 1; uint32_t trans_complete: 1; uint32_t time_out: 1; uint32_t trans_start: 1; - uint32_t ack_err: 1; - uint32_t rx_rec_full: 1; - uint32_t tx_send_empty: 1; + uint32_t nack: 1; + uint32_t tx_fifo_ovf: 1; + uint32_t rx_fifo_udf: 1; uint32_t scl_st_to: 1; uint32_t scl_main_st_to: 1; uint32_t det_start: 1; - uint32_t reserved16: 16; + uint32_t slave_stretch: 1; + uint32_t reserved17: 15; }; uint32_t val; } int_ena; union { struct { - uint32_t rx_fifo_full: 1; - uint32_t tx_fifo_empty: 1; + uint32_t rx_fifo_wm: 1; + uint32_t tx_fifo_wm: 1; uint32_t rx_fifo_ovf: 1; uint32_t end_detect: 1; - uint32_t slave_tran_comp: 1; + uint32_t byte_trans_done: 1; uint32_t arbitration_lost: 1; - uint32_t master_tran_comp: 1; + uint32_t mst_tx_fifo_udf: 1; uint32_t trans_complete: 1; uint32_t time_out: 1; uint32_t trans_start: 1; - uint32_t ack_err: 1; - uint32_t rx_rec_full: 1; - uint32_t tx_send_empty: 1; + uint32_t nack: 1; + uint32_t tx_fifo_ovf: 1; + uint32_t rx_fifo_udf: 1; uint32_t scl_st_to: 1; uint32_t scl_main_st_to: 1; uint32_t det_start: 1; - uint32_t reserved16: 16; + uint32_t slave_stretch: 1; + uint32_t reserved17: 15; }; uint32_t val; } int_status; @@ -254,29 +259,29 @@ typedef volatile struct { } scl_stop_setup; union { struct { - uint32_t thres: 3; + uint32_t thres: 4; uint32_t en: 1; - uint32_t reserved4: 28; + uint32_t reserved5: 27; }; uint32_t val; } scl_filter_cfg; union { struct { - uint32_t thres: 3; + uint32_t thres: 4; uint32_t en: 1; - uint32_t reserved4: 28; + uint32_t reserved5: 27; }; uint32_t val; } sda_filter_cfg; union { struct { - uint32_t byte_num: 8; /*Byte_num represent the number of data need to be send or data need to be received.*/ - uint32_t ack_en: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ - uint32_t ack_exp: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ - uint32_t ack_val: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ - uint32_t op_code: 3; /*op_code is the command 0：RSTART 1：WRITE 2：READ 3：STOP . 4:END.*/ + uint32_t byte_num: 8; + uint32_t ack_en: 1; + uint32_t ack_exp: 1; + uint32_t ack_val: 1; + uint32_t op_code: 3; uint32_t reserved14: 17; - uint32_t done: 1; /*When command0 is done in I2C Master mode this bit changes to high level.*/ + uint32_t done: 1; }; uint32_t val; } command[16]; @@ -304,7 +309,15 @@ typedef volatile struct { }; uint32_t val; } scl_sp_conf; - uint32_t reserved_a4; + union { + struct { + uint32_t stretch_protect_num: 10; + uint32_t slave_scl_stretch_en: 1; + uint32_t slave_scl_stretch_clr: 1; + uint32_t reserved12: 20; + }; + uint32_t val; + } scl_stretch_conf; uint32_t reserved_a8; uint32_t reserved_ac; uint32_t reserved_b0; @@ -327,7 +340,39 @@ typedef volatile struct { uint32_t reserved_f4; uint32_t date; /**/ uint32_t reserved_fc; - uint32_t ram_data[32]; /**/ + uint32_t txfifo_start_addr; /**/ + uint32_t reserved_104; + uint32_t reserved_108; + uint32_t reserved_10c; + uint32_t reserved_110; + uint32_t reserved_114; + uint32_t reserved_118; + uint32_t reserved_11c; + uint32_t reserved_120; + uint32_t reserved_124; + uint32_t reserved_128; + uint32_t reserved_12c; + uint32_t reserved_130; + uint32_t reserved_134; + uint32_t reserved_138; + uint32_t reserved_13c; + uint32_t reserved_140; + uint32_t reserved_144; + uint32_t reserved_148; + uint32_t reserved_14c; + uint32_t reserved_150; + uint32_t reserved_154; + uint32_t reserved_158; + uint32_t reserved_15c; + uint32_t reserved_160; + uint32_t reserved_164; + uint32_t reserved_168; + uint32_t reserved_16c; + uint32_t reserved_170; + uint32_t reserved_174; + uint32_t reserved_178; + uint32_t reserved_17c; + uint32_t fifo_start_addr; /**/ } i2c_dev_t; extern i2c_dev_t I2C0; extern i2c_dev_t I2C1; @@ -335,4 +380,4 @@ extern i2c_dev_t I2C1; } #endif -#endif /* _SOC_I2C_STRUCT_H_ */ +#endif /* _SOC_I2C_STRUCT_H_ */ \ No newline at end of file diff --git a/components/soc/src/esp32s2/include/hal/i2c_ll.h b/components/soc/src/esp32s2/include/hal/i2c_ll.h index f06bd8d11..66a375ae1 100644 --- a/components/soc/src/esp32s2/include/hal/i2c_ll.h +++ b/components/soc/src/esp32s2/include/hal/i2c_ll.h @@ -71,13 +71,13 @@ typedef struct { // Get the I2C hardware FIFO address #define I2C_LL_GET_FIFO_ADDR(i2c_num) (I2C_DATA_APB_REG(i2c_num)) // I2C master TX interrupt bitmap -#define I2C_LL_MASTER_TX_INT (I2C_ACK_ERR_INT_ENA_M|I2C_TIME_OUT_INT_ENA_M|I2C_TRANS_COMPLETE_INT_ENA_M|I2C_ARBITRATION_LOST_INT_ENA_M|I2C_END_DETECT_INT_ENA_M) +#define I2C_LL_MASTER_TX_INT (I2C_NACK_INT_ENA_M|I2C_TIME_OUT_INT_ENA_M|I2C_TRANS_COMPLETE_INT_ENA_M|I2C_ARBITRATION_LOST_INT_ENA_M|I2C_END_DETECT_INT_ENA_M) // I2C master RX interrupt bitmap #define I2C_LL_MASTER_RX_INT (I2C_TIME_OUT_INT_ENA_M|I2C_TRANS_COMPLETE_INT_ENA_M|I2C_ARBITRATION_LOST_INT_ENA_M|I2C_END_DETECT_INT_ENA_M) // I2C slave TX interrupt bitmap -#define I2C_LL_SLAVE_TX_INT (I2C_TXFIFO_EMPTY_INT_ENA_M) +#define I2C_LL_SLAVE_TX_INT (I2C_TXFIFO_WM_INT_ENA_M) // I2C slave RX interrupt bitmap -#define I2C_LL_SLAVE_RX_INT (I2C_RXFIFO_FULL_INT_ENA_M | I2C_TRANS_COMPLETE_INT_ENA_M) +#define I2C_LL_SLAVE_RX_INT (I2C_RXFIFO_WM_INT_ENA_M | I2C_TRANS_COMPLETE_INT_ENA_M) /** @@ -248,7 +248,8 @@ static inline void i2c_ll_set_fifo_mode(i2c_dev_t *hw, bool fifo_mode_en) */ static inline void i2c_ll_set_tout(i2c_dev_t *hw, int tout) { - hw->timeout.tout = tout; + hw->timeout.tout = tout; + hw->timeout.time_out_en = tout > 0; } /** @@ -335,7 +336,7 @@ static inline void i2c_ll_set_sda_timing(i2c_dev_t *hw, int sda_sample, int sda_ */ static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr) { - hw->fifo_conf.tx_fifo_empty_thrhd = empty_thr; + hw->fifo_conf.tx_fifo_wm_thrhd = empty_thr; } /** @@ -348,7 +349,7 @@ static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr) */ static inline void i2c_ll_set_rxfifo_full_thr(i2c_dev_t *hw, uint8_t full_thr) { - hw->fifo_conf.rx_fifo_full_thrhd = full_thr; + hw->fifo_conf.rx_fifo_wm_thrhd = full_thr; } /** @@ -763,11 +764,9 @@ static inline void i2c_ll_master_fsm_rst(i2c_dev_t *hw) */ static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw) { - uint32_t reg_val = hw->scl_sp_conf.val; - hw->scl_sp_conf.scl_pd_en = 1; - hw->scl_sp_conf.sda_pd_en = 1; + hw->scl_sp_conf.scl_rst_slv_num = 9; + hw->scl_sp_conf.scl_rst_slv_en = 0; hw->scl_sp_conf.scl_rst_slv_en = 1; - hw->scl_sp_conf.val = reg_val & 0xfe; } /** @@ -796,7 +795,7 @@ static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *even typeof(hw->int_status) int_sts = hw->int_status; if (int_sts.arbitration_lost) { *event = I2C_INTR_EVENT_ARBIT_LOST; - } else if (int_sts.ack_err) { + } else if (int_sts.nack) { *event = I2C_INTR_EVENT_NACK; } else if (int_sts.time_out) { *event = I2C_INTR_EVENT_TOUT; @@ -820,11 +819,11 @@ static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *even static inline void i2c_ll_slave_get_event(i2c_dev_t *hw, i2c_intr_event_t *event) { typeof(hw->int_status) int_sts = hw->int_status; - if (int_sts.tx_fifo_empty) { + if (int_sts.tx_fifo_wm) { *event = I2C_INTR_EVENT_TXFIFO_EMPTY; } else if (int_sts.trans_complete) { *event = I2C_INTR_EVENT_TRANS_DONE; - } else if (int_sts.rx_fifo_full) { + } else if (int_sts.rx_fifo_wm) { *event = I2C_INTR_EVENT_RXFIFO_FULL; } else { *event = I2C_INTR_EVENT_ERR; @@ -850,6 +849,22 @@ static inline void i2c_ll_master_init(i2c_dev_t *hw) hw->ctr.val = ctrl_reg.val; } +/** + * @brief Enable I2C internal open-drain mode + * If internal open-drain of the I2C module is disabled, scl and sda gpio should be configured in open-drain mode. + * Otherwise it is not needed. + * + * @param hw Beginning address of the peripheral registers + * @param internal_od_ena Set true to enble internal open-drain, otherwise, set it false. + * + * @return None + */ +static inline void i2c_ll_internal_od_enable(i2c_dev_t *hw, bool internal_od_ena) +{ + hw->ctr.sda_force_out = (internal_od_ena == false); + hw->ctr.scl_force_out = (internal_od_ena == false); +} + /** * @brief Init I2C slave * @@ -861,12 +876,14 @@ static inline void i2c_ll_slave_init(i2c_dev_t *hw) { typeof(hw->ctr) ctrl_reg; ctrl_reg.val = 0; + //Open-drain output via GPIO ctrl_reg.sda_force_out = 1; ctrl_reg.scl_force_out = 1; //Disable REF tick; ctrl_reg.ref_always_on = 1; hw->ctr.val = ctrl_reg.val; hw->fifo_conf.fifo_addr_cfg_en = 0; + hw->scl_stretch_conf.slave_scl_stretch_en = 0; } #ifdef __cplusplus