From 5ce7a33c87aa2e8b20a85f7cd30f389a2fd2032a Mon Sep 17 00:00:00 2001 From: Felipe Neves Date: Mon, 14 Oct 2019 14:02:35 -0300 Subject: [PATCH] freertos/xtensa_context.S: fix some dread tabs --- components/freertos/xtensa_context.S | 28 +++++++++++++--------------- 1 file changed, 13 insertions(+), 15 deletions(-) diff --git a/components/freertos/xtensa_context.S b/components/freertos/xtensa_context.S index b0490c5e6..4f33e7cc8 100644 --- a/components/freertos/xtensa_context.S +++ b/components/freertos/xtensa_context.S @@ -161,7 +161,6 @@ _xt_context_save: call0 xthal_save_extra_nw /* destroys a0,2,3,4,5 */ #endif - #ifndef __XTENSA_CALL0_ABI__ #ifdef XT_USE_OVLY l32i a9, sp, XT_STK_PC /* recover saved PC */ @@ -169,22 +168,21 @@ _xt_context_save: s32i a9, sp, XT_STK_OVLY /* save overlay state */ #endif - rsr a2, PS /* We need to enable window execptions to */ - movi a3, PS_INTLEVEL_MASK /* perform spill registers*/ - and a2, a2, a3 - bnez a2, _not_l1 - rsr a2, PS - movi a3, PS_INTLEVEL(1) /* For some curious reason the level 1 interrupts */ - or a2, a2, a3 /* dont set the intlevel correctly on PS, we need to */ - wsr a2, PS /* do this manually */ - + rsr a2, PS /* We need to enable window execptions to */ + movi a3, PS_INTLEVEL_MASK /* perform spill registers*/ + and a2, a2, a3 + bnez a2, _not_l1 + rsr a2, PS + movi a3, PS_INTLEVEL(1) /* For some curious reason the level 1 interrupts */ + or a2, a2, a3 /* dont set the intlevel correctly on PS, we need to */ + wsr a2, PS /* do this manually */ _not_l1: - rsr a2, PS /* finally umask the window exceptions */ - movi a3, ~(PS_EXCM_MASK) - and a2, a2, a3 - wsr a2, PS + rsr a2, PS /* finally umask the window exceptions */ + movi a3, ~(PS_EXCM_MASK) + and a2, a2, a3 + wsr a2, PS rsync - + addi sp, sp, XT_STK_FRMSZ /* go back to spill register region */ SPILL_ALL_WINDOWS /* place the live register windows there */ addi sp, sp, -XT_STK_FRMSZ /* return the current stack pointer and proceed with conext save*/