Remove superfluous task_is_internal check, port dport interrupt to separate int handler
This commit is contained in:
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5c50419aef
commit
5c13d7385c
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@ -254,17 +254,6 @@ config MEMMAP_SPIRAM_ALLOC_LIMIT_INTERNAL
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endif
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endif
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choice NUMBER_OF_MAC_ADDRESS_GENERATED_FROM_EFUSE
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bool "Number of MAC address generated from the hardware MAC address in efuse"
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default FOUR_MAC_ADDRESS_FROM_EFUSE
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help
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Config the number of MAC address which is generated from the hardware MAC address in efuse.
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If the number is two, the MAC addresses of WiFi station and bluetooth are generated from
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the hardware MAC address in efuse. The MAC addresses of WiFi softap and ethernet are derived
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from that of WiFi station and bluetooth respectively.
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If the number is four, the MAC addresses of WiFi station, WiFi softap, bluetooth and ethernet
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are all generated from the hardware MAC address in efuse.
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choice NUMBER_OF_UNIVERSAL_MAC_ADDRESS
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choice NUMBER_OF_UNIVERSAL_MAC_ADDRESS
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bool "Number of universally administered (by IEEE) MAC address"
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bool "Number of universally administered (by IEEE) MAC address"
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default FOUR_UNIVERSAL_MAC_ADDRESS
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default FOUR_UNIVERSAL_MAC_ADDRESS
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@ -37,6 +37,7 @@ COMPONENT_ADD_LDFLAGS := -lesp32 \
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-T esp32_out.ld \
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-T esp32_out.ld \
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-u ld_include_panic_highint_hdl \
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-u ld_include_panic_highint_hdl \
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-u ld_include_psram_tst \
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-u ld_include_psram_tst \
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-u ld_include_dport_int \
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$(addprefix -T ,$(LINKER_SCRIPTS))
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$(addprefix -T ,$(LINKER_SCRIPTS))
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ALL_LIB_FILES := $(patsubst %,$(COMPONENT_PATH)/lib/lib%.a,$(LIBS))
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ALL_LIB_FILES := $(patsubst %,$(COMPONENT_PATH)/lib/lib%.a,$(LIBS))
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101
components/esp32/dport_int.S
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101
components/esp32/dport_int.S
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@ -0,0 +1,101 @@
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#include <xtensa/coreasm.h>
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#include <xtensa/corebits.h>
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#include <xtensa/config/system.h>
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#include <xtensa/simcall.h>
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#include "esp_panic.h"
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#include "sdkconfig.h"
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#include "soc/soc.h"
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#include "soc/dport_reg.h"
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#include "freertos/xtensa_context.h"
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#define L5_INTR_STACK_SIZE 8
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#define L5_INTR_A2_OFFSET 0
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#define L5_INTR_A3_OFFSET 4
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.data
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_l5_intr_stack:
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.space L5_INTR_STACK_SIZE
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.section .iram1,"ax"
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.global xt_highint5
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.type _xt_highint5,@function
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.align 4
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_xt_highint5:
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#ifdef XT_INTEXC_HOOKS
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/* Call interrupt hook if present to (pre)handle interrupts. */
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movi a0, _xt_intexc_hooks
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l32i a0, a0, 5<<2
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beqz a0, 1f
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.Ln_xt_highint5_call_hook:
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callx0 a0 /* must NOT disturb stack! */
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1:
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#endif
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/* This section is for access dport register protection */
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/* Allocate exception frame and save minimal context. */
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/* Because the interrupt cause code have protection that only
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allow one cpu enter in L5 interrupt at one time, so
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there needn't have two _l5_intr_stack for each cpu */
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movi a0, _l5_intr_stack
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s32i a2, a0, L5_INTR_A2_OFFSET
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s32i a3, a0, L5_INTR_A3_OFFSET
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/* Check interrupt */
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rsr a0, INTERRUPT
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extui a0, a0, ETS_DPORT_INUM, 1 /* get dport int bit */
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beqz a0, 1f
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/* handle dport interrupt */
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/* get CORE_ID */
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getcoreid a0
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beqz a0, 2f
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/* current cpu is 1 */
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movi a0, DPORT_CPU_INTR_FROM_CPU_3_REG
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movi a2, 0
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s32i a2, a0, 0 /* clear intr */
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movi a0, 0 /* other cpu id */
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j 3f
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2:
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/* current cpu is 0 */
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movi a0, DPORT_CPU_INTR_FROM_CPU_2_REG
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movi a2, 0
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s32i a2, a0, 0 /* clear intr */
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movi a0, 1 /* other cpu id */
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3:
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/* set and wait flag */
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movi a2, dport_access_start
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addx4 a2, a0, a2
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movi a3, 1
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s32i a3, a2, 0
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memw
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movi a2, dport_access_end
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addx4 a2, a0, a2
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.check_dport_access_end:
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l32i a3, a2, 0
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beqz a3, .check_dport_access_end
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1:
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movi a0, _l5_intr_stack
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l32i a2, a0, L5_INTR_A2_OFFSET
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l32i a3, a0, L5_INTR_A3_OFFSET
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rsync /* ensure register restored */
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rsr a0, EXCSAVE_5 /* restore a0 */
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rfi 5
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.align 4
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.L_xt_highint5_exit:
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rsr a0, EXCSAVE_5 /* restore a0 */
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rfi 5
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/* The linker has no reason to link in this file; all symbols it exports are already defined
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(weakly!) in the default int handler. Define a symbol here so we can use it to have the
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linker inspect this anyway. */
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.global ld_include_dport_int
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ld_include_dport_int:
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33
components/esp32/include/esp_cache_err_int.h
Normal file
33
components/esp32/include/esp_cache_err_int.h
Normal file
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@ -0,0 +1,33 @@
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// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/**
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* @brief initialize cache invalid access interrupt
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*
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* This function enables cache invalid access interrupt source and connects it
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* to interrupt input number ETS_CACHEERR_INUM (see soc/soc.h). It is called
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* from the startup code.
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*/
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void esp_cache_err_int_init();
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/**
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* @brief get the CPU which caused cache invalid access interrupt
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* @return
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* - PRO_CPU_NUM, if PRO_CPU has caused cache IA interrupt
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* - APP_CPU_NUM, if APP_CPU has caused cache IA interrupt
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* - (-1) otherwise
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*/
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int esp_cache_err_get_cpuid();
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@ -116,7 +116,6 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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#define XIE_ARG 4
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#define XIE_ARG 4
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#define XIE_SIZE 8
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#define XIE_SIZE 8
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/*
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/*
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Macro get_percpu_entry_for - convert a per-core ID into a multicore entry.
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Macro get_percpu_entry_for - convert a per-core ID into a multicore entry.
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Basically does reg=reg*portNUM_PROCESSORS+current_core_id
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Basically does reg=reg*portNUM_PROCESSORS+current_core_id
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@ -137,6 +136,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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add \reg,\scratch,\reg
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add \reg,\scratch,\reg
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#endif
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#endif
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.endm
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.endm
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/*
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/*
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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Macro extract_msb - return the input with only the highest bit set.
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Macro extract_msb - return the input with only the highest bit set.
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@ -103,7 +103,6 @@ size_t IRAM_ATTR spi_flash_get_chip_size()
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static inline void IRAM_ATTR spi_flash_guard_start()
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static inline void IRAM_ATTR spi_flash_guard_start()
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{
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{
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assert(esp32_task_stack_is_internal() && "SPI operation called from task which has its stack in external memory");
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if (s_flash_guard_ops && s_flash_guard_ops->start) {
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if (s_flash_guard_ops && s_flash_guard_ops->start) {
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s_flash_guard_ops->start();
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s_flash_guard_ops->start();
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}
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}
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