diff --git a/components/esp32/Makefile.projbuild b/components/esp32/Makefile.projbuild index e832f2984..63318dd66 100644 --- a/components/esp32/Makefile.projbuild +++ b/components/esp32/Makefile.projbuild @@ -36,8 +36,5 @@ endif # CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION ifdef CONFIG_SPIRAM_CACHE_WORKAROUND CFLAGS+=-mfix-esp32-psram-cache-issue CXXFLAGS+=-mfix-esp32-psram-cache-issue -#Filter out the standard libstdc++ linkage. The component.mk will add a specific -#cache-workaround-enabled version. -LDFLAGS:=$(filter-out -lstdc++,$(LDFLAGS)) endif diff --git a/components/esp32/component.mk b/components/esp32/component.mk index ee7b39f83..cdd174779 100644 --- a/components/esp32/component.mk +++ b/components/esp32/component.mk @@ -38,11 +38,6 @@ COMPONENT_ADD_LDFLAGS += $(COMPONENT_PATH)/libhal.a \ -u ld_include_panic_highint_hdl \ $(addprefix -T ,$(LINKER_SCRIPTS)) -#The cache workaround also needs a c++ standard library recompiled with the workaround. -ifdef CONFIG_SPIRAM_CACHE_WORKAROUND -COMPONENT_ADD_LDFLAGS += $(COMPONENT_PATH)/libstdc++-psram-workaround.a -endif - ALL_LIB_FILES := $(patsubst %,$(COMPONENT_PATH)/lib/lib%.a,$(LIBS)) COMPONENT_SUBMODULES += lib diff --git a/components/esp32/libstdc++-psram-workaround.a b/components/esp32/libstdc++-psram-workaround.a deleted file mode 100644 index 808cb03c4..000000000 Binary files a/components/esp32/libstdc++-psram-workaround.a and /dev/null differ diff --git a/components/soc/esp32/include/soc/rtc_i2c_reg.h b/components/soc/esp32/include/soc/rtc_i2c_reg.h new file mode 100644 index 000000000..be7b64c6b --- /dev/null +++ b/components/soc/esp32/include/soc/rtc_i2c_reg.h @@ -0,0 +1,288 @@ +// Copyright 2016-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "soc.h" + +/** + * This file lists peripheral registers of an I2C controller which is part of the RTC. + * ULP coprocessor uses this controller to implement I2C_RD and I2C_WR instructions. + * + * Part of the functionality of this controller (such as slave mode, and multi-byte + * transfers) is not wired to the ULP, and is such, is not available to the + * ULP programs. + */ + +#define RTC_I2C_SCL_LOW_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x000) +/* RTC_I2C_SCL_LOW_PERIOD : R/W ;bitpos:[18:0] ;default: 19'b0 ; */ +/*description: number of cycles that scl == 0 */ +#define RTC_I2C_SCL_LOW_PERIOD 0x1FFFFFF +#define RTC_I2C_SCL_LOW_PERIOD_M ((RTC_I2C_SCL_LOW_PERIOD_V)<<(RTC_I2C_SCL_LOW_PERIOD_S)) +#define RTC_I2C_SCL_LOW_PERIOD_V 0x1FFFFFF +#define RTC_I2C_SCL_LOW_PERIOD_S 0 + +#define RTC_I2C_CTRL_REG (DR_REG_RTC_I2C_BASE + 0x004) +/* RTC_I2C_RX_LSB_FIRST : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Send LSB first */ +#define RTC_I2C_RX_LSB_FIRST BIT(7) +#define RTC_I2C_RX_LSB_FIRST_M BIT(7) +#define RTC_I2C_RX_LSB_FIRST_V (1) +#define RTC_I2C_RX_LSB_FIRST_S (7) +/* RTC_I2C_TX_LSB_FIRST : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Receive LSB first */ +#define RTC_I2C_TX_LSB_FIRST BIT(6) +#define RTC_I2C_TX_LSB_FIRST_M BIT(6) +#define RTC_I2C_TX_LSB_FIRST_V (1) +#define RTC_I2C_TX_LSB_FIRST_S (6) +/* RTC_I2C_TRANS_START : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Force to generate start condition */ +#define RTC_I2C_TRANS_START BIT(5) +#define RTC_I2C_TRANS_START_M BIT(5) +#define RTC_I2C_TRANS_START_V (1) +#define RTC_I2C_TRANS_START_S (5) +/* RTC_I2C_MS_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Master (1) or slave (0) */ +#define RTC_I2C_MS_MODE BIT(4) +#define RTC_I2C_MS_MODE_M BIT(4) +#define RTC_I2C_MS_MODE_V (1) +#define RTC_I2C_MS_MODE_S (4) +/* RTC_I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: SCL is push-pull (1) or open-drain (0) */ +#define RTC_I2C_SCL_FORCE_OUT BIT(1) +#define RTC_I2C_SCL_FORCE_OUT_M BIT(1) +#define RTC_I2C_SCL_FORCE_OUT_V (1) +#define RTC_I2C_SCL_FORCE_OUT_S (1) +/* RTC_I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: SDA is push-pull (1) or open-drain (0) */ +#define RTC_I2C_SDA_FORCE_OUT BIT(0) +#define RTC_I2C_SDA_FORCE_OUT_M BIT(0) +#define RTC_I2C_SDA_FORCE_OUT_V (1) +#define RTC_I2C_SDA_FORCE_OUT_S (0) + +#define RTC_I2C_DEBUG_STATUS_REG (DR_REG_RTC_I2C_BASE + 0x008) +/* RTC_I2C_SCL_STATE : R/W ;bitpos:[30:28] ;default: 3'b0 ; */ +/*description: state of SCL state machine */ +#define RTC_I2C_SCL_STATE 0x7 +#define RTC_I2C_SCL_STATE_M ((RTC_I2C_SCL_STATE_V)<<(RTC_I2C_SCL_STATE_S)) +#define RTC_I2C_SCL_STATE_V 0x7 +#define RTC_I2C_SCL_STATE_S 28 +/* RTC_I2C_MAIN_STATE : R/W ;bitpos:[27:25] ;default: 3'b0 ; */ +/*description: state of the main state machine */ +#define RTC_I2C_MAIN_STATE 0x7 +#define RTC_I2C_MAIN_STATE_M ((RTC_I2C_MAIN_STATE_V)<<(RTC_I2C_MAIN_STATE_S)) +#define RTC_I2C_MAIN_STATE_V 0x7 +#define RTC_I2C_MAIN_STATE_S 25 +/* RTC_I2C_BYTE_TRANS : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: 8 bit transmit done */ +#define RTC_I2C_BYTE_TRANS BIT(6) +#define RTC_I2C_BYTE_TRANS_M BIT(6) +#define RTC_I2C_BYTE_TRANS_V (1) +#define RTC_I2C_BYTE_TRANS_S (6) +/* RTC_I2C_SLAVE_ADDR_MATCH : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: When working as a slave, whether address was matched */ +#define RTC_I2C_SLAVE_ADDR_MATCH BIT(5) +#define RTC_I2C_SLAVE_ADDR_MATCH_M BIT(5) +#define RTC_I2C_SLAVE_ADDR_MATCH_V (1) +#define RTC_I2C_SLAVE_ADDR_MATCH_S (5) +/* RTC_I2C_BUS_BUSY : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: operation is in progress */ +#define RTC_I2C_BUS_BUSY BIT(4) +#define RTC_I2C_BUS_BUSY_M BIT(4) +#define RTC_I2C_BUS_BUSY_V (1) +#define RTC_I2C_BUS_BUSY_S (4) +/* RTC_I2C_ARB_LOST : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: When working as a master, lost control of I2C bus */ +#define RTC_I2C_ARB_LOST BIT(3) +#define RTC_I2C_ARB_LOST_M BIT(3) +#define RTC_I2C_ARB_LOST_V (1) +#define RTC_I2C_ARB_LOST_S (3) +/* RTC_I2C_TIMED_OUT : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Transfer has timed out */ +#define RTC_I2C_TIMED_OUT BIT(2) +#define RTC_I2C_TIMED_OUT_M BIT(2) +#define RTC_I2C_TIMED_OUT_V (1) +#define RTC_I2C_TIMED_OUT_S (2) +/* RTC_I2C_SLAVE_RW : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: When working as a slave, the value of R/W bit received */ +#define RTC_I2C_SLAVE_RW BIT(1) +#define RTC_I2C_SLAVE_RW_M BIT(1) +#define RTC_I2C_SLAVE_RW_V (1) +#define RTC_I2C_SLAVE_RW_S (1) +/* RTC_I2C_ACK_VAL : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The value of an acknowledge signal on the bus */ +#define RTC_I2C_ACK_VAL BIT(0) +#define RTC_I2C_ACK_VAL_M BIT(0) +#define RTC_I2C_ACK_VAL_V (1) +#define RTC_I2C_ACK_VAL_S (0) + +#define RTC_I2C_TIMEOUT_REG (DR_REG_RTC_I2C_BASE + 0x00c) +/* RTC_I2C_TIMEOUT : R/W ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: Maximum number of FAST_CLK cycles that the transmission can take */ +#define RTC_I2C_TIMEOUT 0xFFFFF +#define RTC_I2C_TIMEOUT_M ((RTC_I2C_TIMEOUT_V)<<(RTC_I2C_TIMEOUT_S)) +#define RTC_I2C_TIMEOUT_V 0xFFFFF +#define RTC_I2C_TIMEOUT_S 0 + +#define RTC_I2C_SLAVE_ADDR_REG (DR_REG_RTC_I2C_BASE + 0x010) +/* RTC_I2C_SLAVE_ADDR_10BIT : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Set if local slave address is 10-bit */ +#define RTC_I2C_SLAVE_ADDR_10BIT BIT(31) +#define RTC_I2C_SLAVE_ADDR_10BIT_M BIT(31) +#define RTC_I2C_SLAVE_ADDR_10BIT_V (1) +#define RTC_I2C_SLAVE_ADDR_10BIT_S (31) +/* RTC_I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */ +/*description: local slave address */ +#define RTC_I2C_SLAVE_ADDR 0x7FFF +#define RTC_I2C_SLAVE_ADDR_M ((RTC_I2C_SLAVE_ADDR_V)<<(RTC_I2C_SLAVE_ADDR_S)) +#define RTC_I2C_SLAVE_ADDR_V 0x7FFF +#define RTC_I2C_SLAVE_ADDR_S 0 + +/* Result of last read operation. Not used directly as the data will be + * returned to the ULP. Listed for debugging purposes. + */ +#define RTC_I2C_DATA_REG (DR_REG_RTC_I2C_BASE + 0x01c) + +/* Interrupt registers; since the interrupt from RTC_I2C is not connected, + * these registers are only listed for debugging purposes. + */ + +/* Interrupt raw status register */ +#define RTC_I2C_INT_RAW_REG (DR_REG_RTC_I2C_BASE + 0x020) +/* RTC_I2C_TIME_OUT_INT_RAW : R/O ;bitpos:[7] ;default: 1'b0 ; */ +/*description: time out interrupt raw status */ +#define RTC_I2C_TIME_OUT_INT_RAW BIT(7) +#define RTC_I2C_TIME_OUT_INT_RAW_M BIT(7) +#define RTC_I2C_TIME_OUT_INT_RAW_V (1) +#define RTC_I2C_TIME_OUT_INT_RAW_S (7) +/* RTC_I2C_TRANS_COMPLETE_INT_RAW : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Stop condition has been detected interrupt raw status */ +#define RTC_I2C_TRANS_COMPLETE_INT_RAW BIT(6) +#define RTC_I2C_TRANS_COMPLETE_INT_RAW_M BIT(6) +#define RTC_I2C_TRANS_COMPLETE_INT_RAW_V (1) +#define RTC_I2C_TRANS_COMPLETE_INT_RAW_S (6) +/* RTC_I2C_MASTER_TRANS_COMPLETE_INT_RAW : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define RTC_I2C_MASTER_TRANS_COMPLETE_INT_RAW BIT(5) +#define RTC_I2C_MASTER_TRANS_COMPLETE_INT_RAW_M BIT(5) +#define RTC_I2C_MASTER_TRANS_COMPLETE_INT_RAW_V (1) +#define RTC_I2C_MASTER_TRANS_COMPLETE_INT_RAW_S (5) +/* RTC_I2C_ARBITRATION_LOST_INT_RAW : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Master lost arbitration */ +#define RTC_I2C_ARBITRATION_LOST_INT_RAW BIT(4) +#define RTC_I2C_ARBITRATION_LOST_INT_RAW_M BIT(4) +#define RTC_I2C_ARBITRATION_LOST_INT_RAW_V (1) +#define RTC_I2C_ARBITRATION_LOST_INT_RAW_S (4) +/* RTC_I2C_SLAVE_TRANS_COMPLETE_INT_RAW : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Slave accepted 1 byte and address matched */ +#define RTC_I2C_SLAVE_TRANS_COMPLETE_INT_RAW BIT(3) +#define RTC_I2C_SLAVE_TRANS_COMPLETE_INT_RAW_M BIT(3) +#define RTC_I2C_SLAVE_TRANS_COMPLETE_INT_RAW_V (1) +#define RTC_I2C_SLAVE_TRANS_COMPLETE_INT_RAW_S (3) + +/* Interrupt clear register */ +#define RTC_I2C_INT_CLR_REG (DR_REG_RTC_I2C_BASE + 0x024) +/* RTC_I2C_TIME_OUT_INT_CLR : W/O ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define RTC_I2C_TIME_OUT_INT_CLR BIT(8) +#define RTC_I2C_TIME_OUT_INT_CLR_M BIT(8) +#define RTC_I2C_TIME_OUT_INT_CLR_V (1) +#define RTC_I2C_TIME_OUT_INT_CLR_S (8) +/* RTC_I2C_TRANS_COMPLETE_INT_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define RTC_I2C_TRANS_COMPLETE_INT_CLR BIT(7) +#define RTC_I2C_TRANS_COMPLETE_INT_CLR_M BIT(7) +#define RTC_I2C_TRANS_COMPLETE_INT_CLR_V (1) +#define RTC_I2C_TRANS_COMPLETE_INT_CLR_S (7) +/* RTC_I2C_MASTER_TRANS_COMPLETE_INT_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define RTC_I2C_MASTER_TRANS_COMPLETE_INT_CLR BIT(6) +#define RTC_I2C_MASTER_TRANS_COMPLETE_INT_CLR_M BIT(6) +#define RTC_I2C_MASTER_TRANS_COMPLETE_INT_CLR_V (1) +#define RTC_I2C_MASTER_TRANS_COMPLETE_INT_CLR_S (6) +/* RTC_I2C_ARBITRATION_LOST_INT_CLR : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define RTC_I2C_ARBITRATION_LOST_INT_CLR BIT(5) +#define RTC_I2C_ARBITRATION_LOST_INT_CLR_M BIT(5) +#define RTC_I2C_ARBITRATION_LOST_INT_CLR_V (1) +#define RTC_I2C_ARBITRATION_LOST_INT_CLR_S (5) +/* RTC_I2C_SLAVE_TRANS_COMPLETE_INT_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RTC_I2C_SLAVE_TRANS_COMPLETE_INT_CLR BIT(4) +#define RTC_I2C_SLAVE_TRANS_COMPLETE_INT_CLR_M BIT(4) +#define RTC_I2C_SLAVE_TRANS_COMPLETE_INT_CLR_V (1) +#define RTC_I2C_SLAVE_TRANS_COMPLETE_INT_CLR_S (4) + +/* Interrupt enable register. + * Bit definitions are not given here, because interrupt functionality + * of RTC_I2C is not used. + */ +#define RTC_I2C_INT_EN_REG (DR_REG_RTC_I2C_BASE + 0x028) + +/* Masked interrupt status register. + * Bit definitions are not given here, because interrupt functionality + * of RTC_I2C is not used. + */ +#define RTC_I2C_INT_ST_REG (DR_REG_RTC_I2C_BASE + 0x02c) + +#define RTC_I2C_SDA_DUTY_REG (DR_REG_RTC_I2C_BASE + 0x030) +/* RTC_I2C_SDA_DUTY : R/W ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: Number of FAST_CLK cycles SDA will switch after falling edge of SCL */ +#define RTC_I2C_SDA_DUTY 0xFFFFF +#define RTC_I2C_SDA_DUTY_M ((RTC_I2C_SDA_DUTY_V)<<(RTC_I2C_SDA_DUTY_S)) +#define RTC_I2C_SDA_DUTY_V 0xFFFFF +#define RTC_I2C_SDA_DUTY_S 0 + +#define RTC_I2C_SCL_HIGH_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x038) +/* RTC_I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: Number of FAST_CLK cycles for SCL to be high */ +#define RTC_I2C_SCL_HIGH_PERIOD 0xFFFFF +#define RTC_I2C_SCL_HIGH_PERIOD_M ((RTC_I2C_SCL_HIGH_PERIOD_V)<<(RTC_I2C_SCL_HIGH_PERIOD_S)) +#define RTC_I2C_SCL_HIGH_PERIOD_V 0xFFFFF +#define RTC_I2C_SCL_HIGH_PERIOD_S 0 + +#define RTC_I2C_SCL_START_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x040) +/* RTC_I2C_SCL_START_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: Number of FAST_CLK cycles to wait before generating start condition */ +#define RTC_I2C_SCL_START_PERIOD 0xFFFFF +#define RTC_I2C_SCL_START_PERIOD_M ((RTC_I2C_SCL_START_PERIOD_V)<<(RTC_I2C_SCL_START_PERIOD_S)) +#define RTC_I2C_SCL_START_PERIOD_V 0xFFFFF +#define RTC_I2C_SCL_START_PERIOD_S 0 + +#define RTC_I2C_SCL_STOP_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x044) +/* RTC_I2C_SCL_STOP_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: Number of FAST_CLK cycles to wait before generating stop condition */ +#define RTC_I2C_SCL_STOP_PERIOD 0xFFFFF +#define RTC_I2C_SCL_STOP_PERIOD_M ((RTC_I2C_SCL_STOP_PERIOD_V)<<(RTC_I2C_SCL_STOP_PERIOD_S)) +#define RTC_I2C_SCL_STOP_PERIOD_V 0xFFFFF +#define RTC_I2C_SCL_STOP_PERIOD_S 0 + +/* A block of 16 RTC_I2C_CMD registers which describe I2C operation to be + * performed. Unused when ULP is controlling RTC_I2C. + */ +#define RTC_I2C_CMD_REG_COUNT 16 +#define RTC_I2C_CMD_REG(i) (DR_REG_RTC_I2C_BASE + 0x048 + (i) * 4) +/* RTC_I2C_CMD_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Bit is set by HW when command is done */ +#define RTC_I2C_CMD_DONE BIT(31) +#define RTC_I2C_CMD_DONE_M BIT(31) +#define RTC_I2C_CMD_DONE_V (1) +#define RTC_I2C_CMD_DONE_S (31) +/* RTC_I2C_VAL : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: Command content */ +#define RTC_I2C_VAL 0 +#define RTC_I2C_VAL_M ((RTC_I2C_VAL_V)<<(RTC_I2C_VAL_S)) +#define RTC_I2C_VAL_V 0x3FFF +#define RTC_I2C_VAL_S 0 + diff --git a/components/soc/esp32/include/soc/soc.h b/components/soc/esp32/include/soc/soc.h index 007a69c90..7c7517d46 100644 --- a/components/soc/esp32/include/soc/soc.h +++ b/components/soc/esp32/include/soc/soc.h @@ -1,4 +1,4 @@ -// Copyright 2010-2017 Espressif Systems (Shanghai) PTE LTD +// Copyright 2010-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -89,11 +89,8 @@ #define DR_REG_RTCCNTL_BASE 0x3ff48000 #define DR_REG_RTCIO_BASE 0x3ff48400 #define DR_REG_SENS_BASE 0x3ff48800 +#define DR_REG_RTC_I2C_BASE 0x3ff48C00 #define DR_REG_IO_MUX_BASE 0x3ff49000 -#define DR_REG_RTCMEM0_BASE 0x3ff61000 -#define DR_REG_RTCMEM1_BASE 0x3ff62000 -#define DR_REG_RTCMEM2_BASE 0x3ff63000 -#define DR_REG_SYSCON_BASE 0x3ff66000 #define DR_REG_HINF_BASE 0x3ff4B000 #define DR_REG_UHCI1_BASE 0x3ff4C000 #define DR_REG_I2S_BASE 0x3ff4F000 @@ -113,9 +110,13 @@ #define DR_REG_PWM_BASE 0x3ff5E000 #define DR_REG_TIMERGROUP0_BASE 0x3ff5F000 #define DR_REG_TIMERGROUP1_BASE 0x3ff60000 +#define DR_REG_RTCMEM0_BASE 0x3ff61000 +#define DR_REG_RTCMEM1_BASE 0x3ff62000 +#define DR_REG_RTCMEM2_BASE 0x3ff63000 #define DR_REG_SPI2_BASE 0x3ff64000 #define DR_REG_SPI3_BASE 0x3ff65000 -#define DR_REG_APB_CTRL_BASE 0x3ff66000 +#define DR_REG_SYSCON_BASE 0x3ff66000 +#define DR_REG_APB_CTRL_BASE 0x3ff66000 /* Old name for SYSCON, to be removed */ #define DR_REG_I2C1_EXT_BASE 0x3ff67000 #define DR_REG_SDMMC_BASE 0x3ff68000 #define DR_REG_EMAC_BASE 0x3ff69000 diff --git a/components/soc/esp32/include/soc/soc_ulp.h b/components/soc/esp32/include/soc/soc_ulp.h index ad1f4f50c..e8c20d2b5 100644 --- a/components/soc/esp32/include/soc/soc_ulp.h +++ b/components/soc/esp32/include/soc/soc_ulp.h @@ -26,7 +26,7 @@ #define MASK_TO_WIDTH_HELPER32(m, i) (MASK_TO_WIDTH_HELPER16(m, i) + MASK_TO_WIDTH_HELPER16(m, i + 16)) // Peripheral register access macros, build around REG_RD and REG_WR instructions. -// Registers defined in rtc_cntl_reg.h, rtc_io_reg.h, and sens_reg.h are usable with these macros. +// Registers defined in rtc_cntl_reg.h, rtc_io_reg.h, sens_reg.h, and rtc_i2c_reg.h are usable with these macros. // Read from rtc_reg[low_bit + bit_width - 1 : low_bit] into R0, bit_width <= 16 #define READ_RTC_REG(rtc_reg, low_bit, bit_width) \ diff --git a/components/ulp/include/esp32/ulp.h b/components/ulp/include/esp32/ulp.h index ae539d84d..64bfff8c4 100644 --- a/components/ulp/include/esp32/ulp.h +++ b/components/ulp/include/esp32/ulp.h @@ -1,4 +1,4 @@ -// Copyright 2016 Espressif Systems (Shanghai) PTE LTD +// Copyright 2016-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -50,6 +50,7 @@ extern "C" { #define RD_REG_PERIPH_RTC_CNTL 0 /*!< Identifier of RTC_CNTL peripheral for RD_REG and WR_REG instructions */ #define RD_REG_PERIPH_RTC_IO 1 /*!< Identifier of RTC_IO peripheral for RD_REG and WR_REG instructions */ #define RD_REG_PERIPH_SENS 2 /*!< Identifier of SARADC peripheral for RD_REG and WR_REG instructions */ +#define RD_REG_PERIPH_RTC_I2C 3 /*!< Identifier of RTC_I2C peripheral for RD_REG and WR_REG instructions */ #define OPCODE_I2C 3 /*!< Instruction: read/write I2C (not implemented yet) */ @@ -286,7 +287,7 @@ _Static_assert(sizeof(ulp_insn_t) == 4, "ULP coprocessor instruction size should * Map SoC peripheral register to periph_sel field of RD_REG and WR_REG * instructions. * - * @param reg peripheral register in RTC_CNTL_, RTC_IO_, SENS_ peripherals. + * @param reg peripheral register in RTC_CNTL_, RTC_IO_, SENS_, RTC_I2C peripherals. * @return periph_sel value for the peripheral to which this register belongs. */ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) { @@ -297,8 +298,10 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) { ret = RD_REG_PERIPH_RTC_CNTL; } else if (reg < DR_REG_SENS_BASE) { ret = RD_REG_PERIPH_RTC_IO; - } else if (reg < DR_REG_RTCMEM0_BASE){ + } else if (reg < DR_REG_RTC_I2C_BASE){ ret = RD_REG_PERIPH_SENS; + } else if (reg < DR_REG_IO_MUX_BASE){ + ret = RD_REG_PERIPH_RTC_I2C; } else { assert(0 && "invalid register base"); } @@ -309,7 +312,7 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) { * Write literal value to a peripheral register * * reg[high_bit : low_bit] = val - * This instruction can access RTC_CNTL_, RTC_IO_, and SENS_ peripheral registers. + * This instruction can access RTC_CNTL_, RTC_IO_, SENS_, and RTC_I2C peripheral registers. */ #define I_WR_REG(reg, low_bit, high_bit, val) {.wr_reg = {\ .addr = (reg & 0xff) / sizeof(uint32_t), \ @@ -323,7 +326,7 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) { * Read from peripheral register into R0 * * R0 = reg[high_bit : low_bit] - * This instruction can access RTC_CNTL_, RTC_IO_, and SENS_ peripheral registers. + * This instruction can access RTC_CNTL_, RTC_IO_, SENS_, and RTC_I2C peripheral registers. */ #define I_RD_REG(reg, low_bit, high_bit) {.rd_reg = {\ .addr = (reg & 0xff) / sizeof(uint32_t), \ @@ -337,7 +340,7 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) { * Set or clear a bit in the peripheral register. * * Sets bit (1 << shift) of register reg to value val. - * This instruction can access RTC_CNTL_, RTC_IO_, and SENS_ peripheral registers. + * This instruction can access RTC_CNTL_, RTC_IO_, SENS_, and RTC_I2C peripheral registers. */ #define I_WR_REG_BIT(reg, shift, val) I_WR_REG(reg, shift, shift, val) diff --git a/docs/api-guides/ulp_instruction_set.rst b/docs/api-guides/ulp_instruction_set.rst index 893fcc56e..6f123d672 100755 --- a/docs/api-guides/ulp_instruction_set.rst +++ b/docs/api-guides/ulp_instruction_set.rst @@ -814,7 +814,7 @@ Note that when accessing RTC memories and RTC registers, ULP coprocessor has low **Description** The instruction reads up to 16 bits from a peripheral register into a general purpose register: ``R0 = REG[Addr][High:Low]``. - This instruction can access registers in RTC_CNTL, RTC_IO, and SENS peripherals. Address of the the register, as seen from the ULP, + This instruction can access registers in RTC_CNTL, RTC_IO, SENS, and RTC_I2C peripherals. Address of the the register, as seen from the ULP, can be calculated from the address of the same register on the DPORT bus as follows:: addr_ulp = (addr_dport - DR_REG_RTCCNTL_BASE) / 4 @@ -842,7 +842,7 @@ Note that when accessing RTC memories and RTC registers, ULP coprocessor has low **Description** The instruction writes up to 8 bits from a general purpose register into a peripheral register. ``REG[Addr][High:Low] = data`` - This instruction can access registers in RTC_CNTL, RTC_IO, and SENS peripherals. Address of the the register, as seen from the ULP, + This instruction can access registers in RTC_CNTL, RTC_IO, SENS, and RTC_I2C peripherals. Address of the the register, as seen from the ULP, can be calculated from the address of the same register on the DPORT bus as follows:: addr_ulp = (addr_dport - DR_REG_RTCCNTL_BASE) / 4 @@ -857,7 +857,7 @@ Convenience macros for peripheral registers access ULP source files are passed through C preprocessor before the assembler. This allows certain macros to be used to facilitate access to peripheral registers. Some existing macros are defined in ``soc/soc_ulp.h`` header file. These macros allow access to the fields of peripheral registers by their names. -Peripheral registers names which can be used with these macros are the ones defined in ``soc/rtc_cntl_reg.h``, ``soc/rtc_io_reg.h``, and ``soc/sens_reg.h``. +Peripheral registers names which can be used with these macros are the ones defined in ``soc/rtc_cntl_reg.h``, ``soc/rtc_io_reg.h``, ``soc/sens_reg.h``, and ``soc_rtc_i2c_reg.h``. READ_RTC_REG(rtc_reg, low_bit, bit_width) Read up to 16 bits from rtc_reg[low_bit + bit_width - 1 : low_bit] into R0. For example:: diff --git a/docs/get-started/linux-setup.rst b/docs/get-started/linux-setup.rst index ec3dbf62a..17d49c93b 100644 --- a/docs/get-started/linux-setup.rst +++ b/docs/get-started/linux-setup.rst @@ -28,17 +28,17 @@ ESP32 toolchain for Linux is available for download from Espressif website: - for 64-bit Linux: - https://dl.espressif.com/dl/xtensa-esp32-elf-linux64-1.22.0-75-gbaf03c2-5.2.0.tar.gz + https://dl.espressif.com/dl/xtensa-esp32-elf-linux64-1.22.0-80-g6c4433a-5.2.0.tar.gz - for 32-bit Linux: - https://dl.espressif.com/dl/xtensa-esp32-elf-linux32-1.22.0-75-gbaf03c2-5.2.0.tar.gz + https://dl.espressif.com/dl/xtensa-esp32-elf-linux32-1.22.0-80-g6c4433a-5.2.0.tar.gz 1. Download this file, then extract it in ``~/esp`` directory:: mkdir -p ~/esp cd ~/esp - tar -xzf ~/Downloads/xtensa-esp32-elf-linux64-1.22.0-75-gbaf03c2-5.2.0.tar.gz + tar -xzf ~/Downloads/xtensa-esp32-elf-linux64-1.22.0-80-g6c4433a-5.2.0.tar.gz .. _setup-linux-toolchain-add-it-to-path: diff --git a/docs/get-started/macos-setup.rst b/docs/get-started/macos-setup.rst index 3333ac17a..14764601b 100644 --- a/docs/get-started/macos-setup.rst +++ b/docs/get-started/macos-setup.rst @@ -19,13 +19,13 @@ Toolchain Setup ESP32 toolchain for macOS is available for download from Espressif website: -https://dl.espressif.com/dl/xtensa-esp32-elf-osx-1.22.0-75-gbaf03c2-5.2.0.tar.gz +https://dl.espressif.com/dl/xtensa-esp32-elf-osx-1.22.0-80-g6c4433a-5.2.0.tar.gz Download this file, then extract it in ``~/esp`` directory:: mkdir -p ~/esp cd ~/esp - tar -xzf ~/Downloads/xtensa-esp32-elf-osx-1.22.0-75-gbaf03c2-5.2.0.tar.gz + tar -xzf ~/Downloads/xtensa-esp32-elf-osx-1.22.0-80-g6c4433a-5.2.0.tar.gz .. _setup-macos-toolchain-add-it-to-path: diff --git a/docs/get-started/windows-setup-scratch.rst b/docs/get-started/windows-setup-scratch.rst index ac343ef1e..4c772eeb3 100644 --- a/docs/get-started/windows-setup-scratch.rst +++ b/docs/get-started/windows-setup-scratch.rst @@ -78,7 +78,7 @@ Alternative Setup: Just download a toolchain If you already have an MSYS2 install or want to do things differently, you can download just the toolchain here: -https://dl.espressif.com/dl/xtensa-esp32-elf-win32-1.22.0-75-gbaf03c2-5.2.0.zip +https://dl.espressif.com/dl/xtensa-esp32-elf-win32-1.22.0-80-g6c4433a-5.2.0.zip .. note:: diff --git a/docs/get-started/windows-setup.rst b/docs/get-started/windows-setup.rst index 858a7966a..b2404996e 100644 --- a/docs/get-started/windows-setup.rst +++ b/docs/get-started/windows-setup.rst @@ -13,7 +13,7 @@ Toolchain Setup The quick setup is to download the Windows all-in-one toolchain & MSYS2 zip file from dl.espressif.com: -https://dl.espressif.com/dl/esp32_win32_msys2_environment_and_toolchain-20171123.zip +https://dl.espressif.com/dl/esp32_win32_msys2_environment_and_toolchain-20180110.zip Unzip the zip file to ``C:\`` (or some other location, but this guide assumes ``C:\``) and it will create an ``msys32`` directory with a pre-prepared environment. diff --git a/make/project.mk b/make/project.mk index b9a04a3b3..31f72bc5f 100644 --- a/make/project.mk +++ b/make/project.mk @@ -527,7 +527,7 @@ TOOLCHAIN_COMMIT_DESC := $(shell $(CC) --version | sed -E -n 's|.*crosstool-ng-( TOOLCHAIN_GCC_VER := $(shell $(CC) --version | sed -E -n 's|xtensa-esp32-elf-gcc.*\ \(.*\)\ (.*)|\1|gp') # Officially supported version(s) -SUPPORTED_TOOLCHAIN_COMMIT_DESC := 1.22.0-75-gbaf03c2 +SUPPORTED_TOOLCHAIN_COMMIT_DESC := 1.22.0-80-g6c4433a SUPPORTED_TOOLCHAIN_GCC_VERSIONS := 5.2.0 ifdef TOOLCHAIN_COMMIT_DESC diff --git a/tools/windows/windows_install_prerequisites.sh b/tools/windows/windows_install_prerequisites.sh index b43a7c514..66ee2236d 100644 --- a/tools/windows/windows_install_prerequisites.sh +++ b/tools/windows/windows_install_prerequisites.sh @@ -44,7 +44,7 @@ python -m pip install --upgrade pip pip install pyserial # Automatically download precompiled toolchain, unpack at /opt/xtensa-esp32-elf/ -TOOLCHAIN_ZIP=xtensa-esp32-elf-win32-1.22.0-75-gbaf03c2-5.2.0.zip +TOOLCHAIN_ZIP=xtensa-esp32-elf-win32-1.22.0-80-g6c4433a-5.2.0.zip echo "Downloading precompiled toolchain ${TOOLCHAIN_ZIP}..." cd ~ curl -LO --retry 10 http://dl.espressif.com/dl/${TOOLCHAIN_ZIP}