diff --git a/components/esp32/include/esp_sleep.h b/components/esp32/include/esp_sleep.h
index 8e50c7e20..ff5b5c0fc 100644
--- a/components/esp32/include/esp_sleep.h
+++ b/components/esp32/include/esp_sleep.h
@@ -319,6 +319,12 @@ esp_deep_sleep_wake_stub_fn_t esp_get_deep_sleep_wake_stub(void);
  */
 void esp_default_wake_deep_sleep(void);
 
+/**
+ *  @brief Disable logging from the ROM code after deep sleep.
+ *
+ *  Using LSB of RTC_STORE4.
+ */
+void esp_deep_sleep_disable_rom_logging(void);
 
 #ifdef __cplusplus
 }
diff --git a/components/esp32/include/rom/rtc.h b/components/esp32/include/rom/rtc.h
index 9ebd1020b..6d9d29774 100644
--- a/components/esp32/include/rom/rtc.h
+++ b/components/esp32/include/rom/rtc.h
@@ -55,7 +55,7 @@ extern "C" {
   *     RTC_CNTL_STORE1_REG     RTC_SLOW_CLK calibration value
   *     RTC_CNTL_STORE2_REG     Boot time, low word
   *     RTC_CNTL_STORE3_REG     Boot time, high word
-  *     RTC_CNTL_STORE4_REG     External XTAL frequency
+  *     RTC_CNTL_STORE4_REG     External XTAL frequency. The frequency must necessarily be even, otherwise there will be a conflict with the low bit, which is used to disable logs in the ROM code.
   *     RTC_CNTL_STORE5_REG     APB bus frequency
   *     RTC_CNTL_STORE6_REG     FAST_RTC_MEMORY_ENTRY
   *     RTC_CNTL_STORE7_REG     FAST_RTC_MEMORY_CRC
@@ -71,6 +71,7 @@ extern "C" {
 #define RTC_RESET_CAUSE_REG     RTC_CNTL_STORE6_REG
 #define RTC_MEMORY_CRC_REG      RTC_CNTL_STORE7_REG
 
+#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.
 
 typedef enum {
     AWAKE = 0,             //<CPU ON
diff --git a/components/esp32/sleep_modes.c b/components/esp32/sleep_modes.c
index ac9ea70dc..f25a28443 100644
--- a/components/esp32/sleep_modes.c
+++ b/components/esp32/sleep_modes.c
@@ -658,3 +658,13 @@ static uint32_t get_power_down_flags()
     }
     return pd_flags;
 }
+
+void esp_deep_sleep_disable_rom_logging(void)
+{
+    /* To disable logging in the ROM, only the least significant bit of the register is used,
+     * but since this register is also used to store the frequency of the main crystal (RTC_XTAL_FREQ_REG),
+     * you need to write to this register in the same format.
+     * Namely, the upper 16 bits and lower should be the same.
+     */
+    REG_SET_BIT(RTC_CNTL_STORE4_REG, RTC_DISABLE_ROM_LOG);
+}
diff --git a/components/soc/esp32/rtc_clk.c b/components/soc/esp32/rtc_clk.c
index 30f20e0eb..7911c6098 100644
--- a/components/soc/esp32/rtc_clk.c
+++ b/components/soc/esp32/rtc_clk.c
@@ -727,11 +727,15 @@ rtc_xtal_freq_t rtc_clk_xtal_freq_get()
     if (!clk_val_is_valid(xtal_freq_reg)) {
         return RTC_XTAL_FREQ_AUTO;
     }
-    return reg_val_to_clk_val(xtal_freq_reg);
+    return reg_val_to_clk_val(xtal_freq_reg & ~RTC_DISABLE_ROM_LOG);
 }
 
 void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq)
 {
+    uint32_t reg = READ_PERI_REG(RTC_XTAL_FREQ_REG) & RTC_DISABLE_ROM_LOG;
+    if (reg == RTC_DISABLE_ROM_LOG) {
+        xtal_freq |= 1;
+    }
     WRITE_PERI_REG(RTC_XTAL_FREQ_REG, clk_val_to_reg_val(xtal_freq));
 }
 
diff --git a/examples/system/ulp/README.md b/examples/system/ulp/README.md
index 17ba58f21..4b2c5341a 100644
--- a/examples/system/ulp/README.md
+++ b/examples/system/ulp/README.md
@@ -14,8 +14,6 @@ In this example the input signal is connected to GPIO0. Note that this pin was c
 
 ## Example output
 
-Note: GPIO15 is connected to GND to disable ROM bootloader output.
-
 ```
 Not ULP wakeup, initializing ULP
 Entering deep sleep
diff --git a/examples/system/ulp/main/ulp_example_main.c b/examples/system/ulp/main/ulp_example_main.c
index 74c4febe4..a6e76bacb 100644
--- a/examples/system/ulp/main/ulp_example_main.c
+++ b/examples/system/ulp/main/ulp_example_main.c
@@ -75,11 +75,11 @@ static void init_ulp_program()
 
     /* Disconnect GPIO12 and GPIO15 to remove current drain through
      * pullup/pulldown resistors.
-     * GPIO15 may be connected to ground to suppress boot messages.
      * GPIO12 may be pulled high to select flash voltage.
      */
     rtc_gpio_isolate(GPIO_NUM_12);
     rtc_gpio_isolate(GPIO_NUM_15);
+    esp_deep_sleep_disable_rom_logging(); // suppress boot messages
 
     /* Set ULP wake up period to T = 20ms.
      * Minimum pulse width has to be T * (ulp_debounce_counter + 1) = 80ms.
diff --git a/examples/system/ulp_adc/main/ulp_adc_example_main.c b/examples/system/ulp_adc/main/ulp_adc_example_main.c
index fd7d4ef43..80f9fc1eb 100644
--- a/examples/system/ulp_adc/main/ulp_adc_example_main.c
+++ b/examples/system/ulp_adc/main/ulp_adc_example_main.c
@@ -76,11 +76,11 @@ static void init_ulp_program()
 
     /* Disconnect GPIO12 and GPIO15 to remove current drain through
      * pullup/pulldown resistors.
-     * GPIO15 may be connected to ground to suppress boot messages.
      * GPIO12 may be pulled high to select flash voltage.
      */
     rtc_gpio_isolate(GPIO_NUM_12);
     rtc_gpio_isolate(GPIO_NUM_15);
+    esp_deep_sleep_disable_rom_logging(); // suppress boot messages
 }
 
 static void start_ulp_program()