diff --git a/components/bootloader/src/main/bootloader_start.c b/components/bootloader/src/main/bootloader_start.c
index 5b1e15207..e1bcc18fd 100644
--- a/components/bootloader/src/main/bootloader_start.c
+++ b/components/bootloader/src/main/bootloader_start.c
@@ -51,7 +51,7 @@ extern void Cache_Flush(int);
 void bootloader_main();
 void unpack_load_app(const esp_partition_pos_t *app_node);
 void print_flash_info(const esp_image_header_t* pfhdr);
-void IRAM_ATTR set_cache_and_start_app(uint32_t drom_addr,
+void set_cache_and_start_app(uint32_t drom_addr,
     uint32_t drom_load_addr,
     uint32_t drom_size,
     uint32_t irom_addr,
@@ -445,7 +445,7 @@ void unpack_load_app(const esp_partition_pos_t* partition)
         image_header.entry_addr);
 }
 
-void IRAM_ATTR set_cache_and_start_app(
+void set_cache_and_start_app(
     uint32_t drom_addr,
     uint32_t drom_load_addr,
     uint32_t drom_size,
@@ -456,9 +456,7 @@ void IRAM_ATTR set_cache_and_start_app(
 {
     ESP_LOGD(TAG, "configure drom and irom and start");
     Cache_Read_Disable( 0 );
-    Cache_Read_Disable( 1 );
     Cache_Flush( 0 );
-    Cache_Flush( 1 );
     uint32_t drom_page_count = (drom_size + 64*1024 - 1) / (64*1024); // round up to 64k
     ESP_LOGV(TAG, "d mmu set paddr=%08x vaddr=%08x size=%d n=%d", drom_addr & 0xffff0000, drom_load_addr & 0xffff0000, drom_size, drom_page_count );
     int rc = cache_flash_mmu_set( 0, 0, drom_load_addr & 0xffff0000, drom_addr & 0xffff0000, 64, drom_page_count );
@@ -474,7 +472,8 @@ void IRAM_ATTR set_cache_and_start_app(
     REG_CLR_BIT( DPORT_PRO_CACHE_CTRL1_REG, (DPORT_PRO_CACHE_MASK_IRAM0) | (DPORT_PRO_CACHE_MASK_IRAM1 & 0) | (DPORT_PRO_CACHE_MASK_IROM0 & 0) | DPORT_PRO_CACHE_MASK_DROM0 | DPORT_PRO_CACHE_MASK_DRAM1 );
     REG_CLR_BIT( DPORT_APP_CACHE_CTRL1_REG, (DPORT_APP_CACHE_MASK_IRAM0) | (DPORT_APP_CACHE_MASK_IRAM1 & 0) | (DPORT_APP_CACHE_MASK_IROM0 & 0) | DPORT_APP_CACHE_MASK_DROM0 | DPORT_APP_CACHE_MASK_DRAM1 );
     Cache_Read_Enable( 0 );
-    Cache_Read_Enable( 1 );
+
+    // Application will need to do Cache_Flush(1) and Cache_Read_Enable(1)
 
     ESP_LOGD(TAG, "start: 0x%08x", entry_addr);
     typedef void (*entry_t)(void);
diff --git a/components/bootloader/src/main/esp32.bootloader.ld b/components/bootloader/src/main/esp32.bootloader.ld
index af97bda3a..6a77eb6ad 100644
--- a/components/bootloader/src/main/esp32.bootloader.ld
+++ b/components/bootloader/src/main/esp32.bootloader.ld
@@ -15,7 +15,7 @@ MEMORY
   of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
   are connected to the data port of the CPU and eg allow bytewise access. */
   dport0_seg (RW) :                 	org = 0x3FF00000, len = 0x10		/* IO */
-  iram_seg (RWX) :                 	org = 0x40098000, len = 0x1000		
+  iram_seg (RWX) :                 	org = 0x40080000, len = 0x400		/* 1k of IRAM used by bootloader functions which need to flush/enable APP CPU cache */ 
   iram_pool_1_seg (RWX) :           org = 0x40078000, len = 0x8000    /* IRAM POOL1, used for APP CPU cache. We can abuse it in bootloader because APP CPU is still held in reset, until we enable APP CPU cache */
   dram_seg (RW) :                  	org = 0x3FFC0000, len = 0x20000		/* Shared RAM, minus rom bss/data/stack.*/
 }
diff --git a/components/esp32/cpu_start.c b/components/esp32/cpu_start.c
index c82c52859..2688cd7f8 100644
--- a/components/esp32/cpu_start.c
+++ b/components/esp32/cpu_start.c
@@ -20,6 +20,7 @@
 #include "rom/ets_sys.h"
 #include "rom/uart.h"
 #include "rom/rtc.h"
+#include "rom/cache.h"
 
 #include "soc/cpu.h"
 #include "soc/dport_reg.h"
@@ -110,7 +111,9 @@ void IRAM_ATTR call_start_cpu0()
 
 #if !CONFIG_FREERTOS_UNICORE
     ESP_EARLY_LOGI(TAG, "Starting app cpu, entry point is %p", call_start_cpu1);
-
+    //Flush and enable icache for APP CPU
+    Cache_Flush(1);
+    Cache_Read_Enable(1);
     //Un-stall the app cpu; the panic handler may have stalled it.
     CLEAR_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, RTC_CNTL_SW_STALL_APPCPU_C1_M);
     CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_STALL_APPCPU_C0_M);