From 55a1bd0fb679e48485587270bf1129e861887799 Mon Sep 17 00:00:00 2001 From: chenjianqiang Date: Fri, 3 Jul 2020 22:26:50 +0800 Subject: [PATCH] feat(esp32): support for esp32-pico-v3-02 --- .../src/bootloader_flash_config_esp32.c | 17 +++++------------ .../src/esp32/bootloader_esp32.c | 17 +++++------------ .../bootloader_support/src/flash_qio_mode.c | 9 +++++---- components/esp32/spiram_psram.c | 13 +++++++++++++ components/esp32/system_api_esp32.c | 3 ++- .../soc/soc/esp32/include/soc/efuse_reg.h | 1 + 6 files changed, 31 insertions(+), 29 deletions(-) diff --git a/components/bootloader_support/src/bootloader_flash_config_esp32.c b/components/bootloader_support/src/bootloader_flash_config_esp32.c index 5d2c8ecc2..dcc8faadb 100644 --- a/components/bootloader_support/src/bootloader_flash_config_esp32.c +++ b/components/bootloader_support/src/bootloader_flash_config_esp32.c @@ -75,18 +75,11 @@ void IRAM_ATTR bootloader_flash_gpio_config(const esp_image_header_t* pfhdr) uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG); uint32_t pkg_ver = chip_ver & 0x7; - if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5) { - // For ESP32D2WD the SPI pins are already configured - // flash clock signal should come from IO MUX. - PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK); - SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S); - } else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2) { - // For ESP32PICOD2 the SPI pins are already configured - // flash clock signal should come from IO MUX. - PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK); - SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S); - } else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4) { - // For ESP32PICOD4 the SPI pins are already configured + if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 || + pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 || + pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 || + pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302) { + // For ESP32D2WD or ESP32-PICO series,the SPI pins are already configured // flash clock signal should come from IO MUX. PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK); SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S); diff --git a/components/bootloader_support/src/esp32/bootloader_esp32.c b/components/bootloader_support/src/esp32/bootloader_esp32.c index c1e8a618e..bfcca07b2 100644 --- a/components/bootloader_support/src/esp32/bootloader_esp32.c +++ b/components/bootloader_support/src/esp32/bootloader_esp32.c @@ -55,18 +55,11 @@ void bootloader_configure_spi_pins(int drv) uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG); uint32_t pkg_ver = chip_ver & 0x7; - if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5) { - // For ESP32D2WD the SPI pins are already configured - // flash clock signal should come from IO MUX. - PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK); - SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S); - } else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2) { - // For ESP32PICOD2 the SPI pins are already configured - // flash clock signal should come from IO MUX. - PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK); - SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S); - } else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4) { - // For ESP32PICOD4 the SPI pins are already configured + if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 || + pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 || + pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 || + pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302) { + // For ESP32D2WD or ESP32-PICO series,the SPI pins are already configured // flash clock signal should come from IO MUX. PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK); SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S); diff --git a/components/bootloader_support/src/flash_qio_mode.c b/components/bootloader_support/src/flash_qio_mode.c index 94da524f9..4c5bda6e6 100644 --- a/components/bootloader_support/src/flash_qio_mode.c +++ b/components/bootloader_support/src/flash_qio_mode.c @@ -229,15 +229,16 @@ static esp_err_t enable_qio_mode(read_status_fn_t read_status_fn, // spiconfig specifies a custom efuse pin configuration. This config defines all pins -except- WP, // which is compiled into the bootloader instead. // - // Most commonly an overriden pin mapping means ESP32-D2WD or ESP32-PICOD4. - //Warn if chip is ESP32-D2WD/ESP32-PICOD4 but someone has changed the WP pin + // Most commonly an overriden pin mapping means ESP32-D2WD or ESP32-PICO series. + //Warn if chip is ESP32-D2WD/ESP32-PICO series but someone has changed the WP pin //assignment from that chip's WP pin. uint32_t pkg_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG); if (CONFIG_BOOTLOADER_SPI_WP_PIN != ESP32_D2WD_WP_GPIO && (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 || pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 || - pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4)) { - ESP_LOGW(TAG, "Chip is ESP32-D2WD/ESP32-PICOD4 but flash WP pin is different value to internal flash"); + pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 || + pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302)) { + ESP_LOGW(TAG, "Chip is ESP32-D2WD/ESP32-PICO series, but flash WP pin is different value to internal flash"); } } #endif diff --git a/components/esp32/spiram_psram.c b/components/esp32/spiram_psram.c index 442de5f1d..ae19d75ea 100644 --- a/components/esp32/spiram_psram.c +++ b/components/esp32/spiram_psram.c @@ -120,6 +120,9 @@ typedef enum { #define PICO_PSRAM_CLK_IO 6 #define PICO_PSRAM_CS_IO CONFIG_PICO_PSRAM_CS_IO // Default value is 10 +#define PICO_V3_02_PSRAM_CLK_IO 10 +#define PICO_V3_02_PSRAM_CS_IO 9 + typedef struct { uint8_t flash_clk_io; uint8_t flash_cs_io; @@ -821,6 +824,16 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad s_clk_mode = PSRAM_CLK_MODE_NORM; psram_io.psram_clk_io = PICO_PSRAM_CLK_IO; psram_io.psram_cs_io = PICO_PSRAM_CS_IO; + } else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302) { + ESP_EARLY_LOGI(TAG, "This chip is ESP32-PICO-V3-02"); + rtc_vddsdio_config_t cfg = rtc_vddsdio_get_config(); + if (cfg.tieh != RTC_VDDSDIO_TIEH_3_3V) { + ESP_EARLY_LOGE(TAG, "VDDSDIO is not 3.3V"); + return ESP_FAIL; + } + s_clk_mode = PSRAM_CLK_MODE_NORM; + psram_io.psram_clk_io = PICO_V3_02_PSRAM_CLK_IO; + psram_io.psram_cs_io = PICO_V3_02_PSRAM_CS_IO; } else if ((pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ6) || (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ5)){ ESP_EARLY_LOGI(TAG, "This chip is ESP32-D0WD"); psram_io.psram_clk_io = D0WD_PSRAM_CLK_IO; diff --git a/components/esp32/system_api_esp32.c b/components/esp32/system_api_esp32.c index b93c222ce..5afbe6e7b 100644 --- a/components/esp32/system_api_esp32.c +++ b/components/esp32/system_api_esp32.c @@ -157,7 +157,8 @@ void esp_chip_info(esp_chip_info_t* out_info) int package = (efuse_rd3 & EFUSE_RD_CHIP_VER_PKG_M) >> EFUSE_RD_CHIP_VER_PKG_S; if (package == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 || package == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 || - package == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4) { + package == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 || + package == EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302) { out_info->features |= CHIP_FEATURE_EMB_FLASH; } } diff --git a/components/soc/soc/esp32/include/soc/efuse_reg.h b/components/soc/soc/esp32/include/soc/efuse_reg.h index bbe967713..8aa78999b 100644 --- a/components/soc/soc/esp32/include/soc/efuse_reg.h +++ b/components/soc/soc/esp32/include/soc/efuse_reg.h @@ -114,6 +114,7 @@ #define EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 2 #define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 4 #define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 5 +#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302 6 /* EFUSE_RD_SPI_PAD_CONFIG_HD : RO ;bitpos:[8:4] ;default: 5'b0 ; */ /*description: read for SPI_pad_config_hd*/ #define EFUSE_RD_SPI_PAD_CONFIG_HD 0x0000001F