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uart: fix uart_tx_wait_idle to wait for fifo empty

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In some cases, when data was just written into UART FIFO, transmitter
state could be still zero while the FIFO did contain some data.
This resulted in uart_tx_wait_idle occasionally returning before all
the data was sent out.
Fix by checking both UART transmitter state and TX FIFO count.
This commit is contained in:
Ivan Grokhotkov 2018-10-15 20:08:16 +08:00
parent 88625a2501
commit 508fb79a26
2 changed files with 8 additions and 4 deletions
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8
components/esp32/include/rom/uart.h
View file

@ -267,9 +267,11 @@ void uart_tx_flush(uint8_t uart_no);
* here for compatibility.
*/
static inline void IRAM_ATTR uart_tx_wait_idle(uint8_t uart_no) {
while(REG_GET_FIELD(UART_STATUS_REG(uart_no), UART_ST_UTX_OUT)) {
;
}
uint32_t status;
do {
status = READ_PERI_REG(UART_STATUS_REG(uart_no));
/* either tx count or state is non-zero */
} while ((status & (UART_ST_UTX_OUT_M | UART_TXFIFO_CNT_M)) != 0);
}
/**

4
components/esp32/sleep_modes.c
View file

@ -159,7 +159,9 @@ static void IRAM_ATTR suspend_uarts()
{
for (int i = 0; i < 3; ++i) {
REG_SET_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XOFF);
uart_tx_wait_idle(i);
while (REG_GET_FIELD(UART_STATUS_REG(i), UART_ST_UTX_OUT) != 0) {
;
}
}
}