diff --git a/components/esp32/include/rom/rtc.h b/components/esp32/include/rom/rtc.h
index 9577119f5..1ff7f033b 100644
--- a/components/esp32/include/rom/rtc.h
+++ b/components/esp32/include/rom/rtc.h
@@ -44,8 +44,8 @@ extern "C" {
   *************************************************************************************
   *     rtc memory addr         type    size            usage
   *     0x3ff61000(0x50000000)  Slow    SIZE_CP         Co-Processor code/Reset Entry
-  *     0x3ff61000+SIZE_CP      Slow    6144-SIZE_CP
-  *     0x3ff62800              Slow    2048            Reserved
+  *     0x3ff61000+SIZE_CP      Slow    4096-SIZE_CP
+  *     0x3ff62800              Slow    4096            Reserved
   *
   *     0x3ff80000(0x400c0000)  Fast    8192            deep sleep entry code
   *
diff --git a/components/esp32/ld/esp32.ld b/components/esp32/ld/esp32.ld
index 7ecfd19e5..d6b0ac42d 100644
--- a/components/esp32/ld/esp32.ld
+++ b/components/esp32/ld/esp32.ld
@@ -48,7 +48,7 @@ MEMORY
      Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.
   */
   rtc_slow_seg(RW)  :                org = 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM,
-                                     len = 0x2000 - CONFIG_ULP_COPROC_RESERVE_MEM
+                                     len = 0x1000 - CONFIG_ULP_COPROC_RESERVE_MEM
 }
 
 /* Heap ends at top of dram0_0_seg */