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components/bootloader: fix enabling cache for APP CPU

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This is a workaround for a hardware bug with cache initialization.
Only two lines of code related to DPORT_APP_CACHE_MMU_IA_CLR were added around mmu_init(1); call,
and two lines at the end of comment block.
I reformatted surrounding lines to use spaces for indentation, like the rest of the code in this file does.
This commit is contained in:
Ivan Grokhotkov 2016-08-24 16:25:04 +08:00
parent be112daa71
commit 4d1084120c
1 changed files with 22 additions and 17 deletions
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5
components/bootloader/src/main/bootloader_start.c
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@ -99,13 +99,18 @@ void IRAM_ATTR call_start_cpu0()
Cache_Flush(0); Cache_Flush(0);
Cache_Flush(1); Cache_Flush(1);
mmu_init(0); mmu_init(0);
REG_SET_BIT(APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
mmu_init(1); mmu_init(1);
REG_CLR_BIT(APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
/* (above steps probably unnecessary for most serial bootloader /* (above steps probably unnecessary for most serial bootloader
usage, all that's absolutely needed is that we unmask DROM0 usage, all that's absolutely needed is that we unmask DROM0
cache on the following two lines - normal ROM boot exits with cache on the following two lines - normal ROM boot exits with
DROM0 cache unmasked, but serial bootloader exits with it DROM0 cache unmasked, but serial bootloader exits with it
masked. However can't hurt to be thorough and reset masked. However can't hurt to be thorough and reset
everything.) everything.)
The lines which manipulate DPORT_APP_CACHE_MMU_IA_CLR bit are
necessary to work around a hardware bug.
*/ */
REG_CLR_BIT(PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MASK_DROM0); REG_CLR_BIT(PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MASK_DROM0);
REG_CLR_BIT(APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DROM0); REG_CLR_BIT(APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DROM0);