From 4cc962353cf68e75ea7c66170f20cd5eb16bc3a7 Mon Sep 17 00:00:00 2001 From: chenjianqiang Date: Fri, 14 Jun 2019 11:01:30 +0800 Subject: [PATCH] feat(uart): update uart driver for esp32s2beta --- components/driver/include/driver/uart.h | 26 ++ components/driver/uart.c | 66 ++- .../common/include/esp_modbus_common.h | 8 +- components/freemodbus/port/portserial.c | 2 +- components/freemodbus/port/portserial_m.c | 2 +- .../modbus_controller/mbc_serial_master.c | 2 +- .../modbus_controller/mbc_serial_slave.c | 2 +- components/soc/esp32/include/soc/uart_caps.h | 26 ++ .../soc/esp32s2beta/include/soc/uart_caps.h | 26 ++ .../soc/esp32s2beta/include/soc/uart_struct.h | 389 +++++++++--------- components/vfs/vfs_uart.c | 36 +- .../main/uart_events_example_main.c | 4 + 12 files changed, 367 insertions(+), 222 deletions(-) create mode 100644 components/soc/esp32/include/soc/uart_caps.h create mode 100644 components/soc/esp32s2beta/include/soc/uart_caps.h diff --git a/components/driver/include/driver/uart.h b/components/driver/include/driver/uart.h index 4f0c8c1ca..130f0bda6 100644 --- a/components/driver/include/driver/uart.h +++ b/components/driver/include/driver/uart.h @@ -21,6 +21,7 @@ extern "C" { #endif #include "soc/uart_periph.h" +#include "soc/uart_caps.h" #include "esp_err.h" #include "esp_intr_alloc.h" #include "driver/periph_ctrl.h" @@ -82,7 +83,9 @@ typedef enum { typedef enum { UART_NUM_0 = 0x0, /*!< UART base address 0x3ff40000*/ UART_NUM_1 = 0x1, /*!< UART base address 0x3ff50000*/ +#if SOC_UART_NUM > 2 UART_NUM_2 = 0x2, /*!< UART base address 0x3ff6e000*/ +#endif UART_NUM_MAX, } uart_port_t; @@ -674,6 +677,7 @@ esp_err_t uart_get_buffered_data_len(uart_port_t uart_num, size_t* size); */ esp_err_t uart_disable_pattern_det_intr(uart_port_t uart_num); +#if CONFIG_IDF_TARGET_ESP32 /** * @brief UART enable pattern detect function. * Designed for applications like 'AT commands'. @@ -694,6 +698,28 @@ esp_err_t uart_disable_pattern_det_intr(uart_port_t uart_num); * - ESP_FAIL Parameter error */ esp_err_t uart_enable_pattern_det_intr(uart_port_t uart_num, char pattern_chr, uint8_t chr_num, int chr_tout, int post_idle, int pre_idle); +#elif CONFIG_IDF_TARGET_ESP32S2BETA +/** + * @brief UART enable pattern detect function. + * Designed for applications like 'AT commands'. + * When the hardware detect a series of one same character, the interrupt will be triggered. + * + * @param uart_num UART port number. + * @param pattern_chr character of the pattern + * @param chr_num number of the character, 8bit value. + * @param chr_tout timeout of the interval between each pattern characters, 16bit value, unit is baud rate. + * When the duration is more than this value, it will not take this data as at_cmd char + * @param post_idle idle time after the last pattern character, 16bit value, unit is baud rate. + * When the duration is less than this value, it will not take the previous data as the last at_cmd char + * @param pre_idle idle time before the first pattern character, 16bit value, unit is baud rate. + * When the duration is less than this value, it will not take this data as the first at_cmd char + * + * @return + * - ESP_OK Success + * - ESP_FAIL Parameter error + */ +esp_err_t uart_enable_pattern_det_intr(uart_port_t uart_num, char pattern_chr, uint8_t chr_num, int chr_tout, int post_idle, int pre_idle); +#endif /** * @brief Return the nearest detected pattern position in buffer. diff --git a/components/driver/uart.c b/components/driver/uart.c index 37925e54d..239881eb9 100644 --- a/components/driver/uart.c +++ b/components/driver/uart.c @@ -34,6 +34,8 @@ #include "esp32s2beta/clk.h" #endif +#define UART_NUM SOC_UART_NUM + #define XOFF (char)0x13 #define XON (char)0x11 @@ -118,8 +120,20 @@ typedef struct { static uart_obj_t *p_uart_obj[UART_NUM_MAX] = {0}; /* DRAM_ATTR is required to avoid UART array placed in flash, due to accessed from ISR */ -static DRAM_ATTR uart_dev_t* const UART[UART_NUM_MAX] = {&UART0, &UART1, &UART2}; -static portMUX_TYPE uart_spinlock[UART_NUM_MAX] = {portMUX_INITIALIZER_UNLOCKED, portMUX_INITIALIZER_UNLOCKED, portMUX_INITIALIZER_UNLOCKED}; +static DRAM_ATTR uart_dev_t* const UART[UART_NUM_MAX] = { + &UART0, + &UART1, +#if UART_NUM > 2 + &UART2 +#endif +}; +static portMUX_TYPE uart_spinlock[UART_NUM_MAX] = { + portMUX_INITIALIZER_UNLOCKED, + portMUX_INITIALIZER_UNLOCKED, +#if UART_NUM > 2 + portMUX_INITIALIZER_UNLOCKED +#endif +}; static portMUX_TYPE uart_selectlock = portMUX_INITIALIZER_UNLOCKED; esp_err_t uart_set_word_length(uart_port_t uart_num, uart_word_length_t data_bit) @@ -145,6 +159,7 @@ esp_err_t uart_set_stop_bits(uart_port_t uart_num, uart_stop_bits_t stop_bit) UART_CHECK((stop_bit < UART_STOP_BITS_MAX), "stop bit error", ESP_FAIL); UART_ENTER_CRITICAL(&uart_spinlock[uart_num]); +#if UART_NUM > 2 //workaround for hardware bug, when uart stop bit set as 2-bit mode. if (stop_bit == UART_STOP_BITS_2) { stop_bit = UART_STOP_BITS_1; @@ -152,6 +167,7 @@ esp_err_t uart_set_stop_bits(uart_port_t uart_num, uart_stop_bits_t stop_bit) } else { UART[uart_num]->rs485_conf.dl1_en = 0; } +#endif UART[uart_num]->conf0.stop_bit_num = stop_bit; UART_EXIT_CRITICAL(&uart_spinlock[uart_num]); return ESP_OK; @@ -160,12 +176,16 @@ esp_err_t uart_set_stop_bits(uart_port_t uart_num, uart_stop_bits_t stop_bit) esp_err_t uart_get_stop_bits(uart_port_t uart_num, uart_stop_bits_t* stop_bit) { UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL); +#if CONFIG_IDF_TARGET_ESP32 //workaround for hardware bug, when uart stop bit set as 2-bit mode. if (UART[uart_num]->rs485_conf.dl1_en == 1 && UART[uart_num]->conf0.stop_bit_num == UART_STOP_BITS_1) { (*stop_bit) = UART_STOP_BITS_2; } else { (*stop_bit) = UART[uart_num]->conf0.stop_bit_num; } +#elif CONFIG_IDF_TARGET_ESP32S2BETA + (*stop_bit) = UART[uart_num]->conf0.stop_bit_num; +#endif return ESP_OK; } @@ -252,10 +272,17 @@ esp_err_t uart_set_sw_flow_ctrl(uart_port_t uart_num, bool enable, uint8_t rx_t UART_ENTER_CRITICAL(&uart_spinlock[uart_num]); UART[uart_num]->flow_conf.sw_flow_con_en = enable? 1:0; UART[uart_num]->flow_conf.xonoff_del = enable?1:0; +#if CONFIG_IDF_TARGET_ESP32 UART[uart_num]->swfc_conf.xon_threshold = rx_thresh_xon; UART[uart_num]->swfc_conf.xoff_threshold = rx_thresh_xoff; UART[uart_num]->swfc_conf.xon_char = XON; UART[uart_num]->swfc_conf.xoff_char = XOFF; +#elif CONFIG_IDF_TARGET_ESP32S2BETA + UART[uart_num]->swfc_conf1.xon_threshold = rx_thresh_xon; + UART[uart_num]->swfc_conf0.xoff_threshold = rx_thresh_xoff; + UART[uart_num]->swfc_conf1.xon_char = XON; + UART[uart_num]->swfc_conf0.xoff_char = XOFF; +#endif UART_EXIT_CRITICAL(&uart_spinlock[uart_num]); return ESP_OK; } @@ -268,7 +295,11 @@ esp_err_t uart_set_hw_flow_ctrl(uart_port_t uart_num, uart_hw_flowcontrol_t flow UART_CHECK((flow_ctrl < UART_HW_FLOWCTRL_MAX), "hw_flowctrl mode error", ESP_FAIL); UART_ENTER_CRITICAL(&uart_spinlock[uart_num]); if(flow_ctrl & UART_HW_FLOWCTRL_RTS) { +#if CONFIG_IDF_TARGET_ESP32 UART[uart_num]->conf1.rx_flow_thrhd = rx_thresh; +#elif CONFIG_IDF_TARGET_ESP32S2BETA + UART[uart_num]->mem_conf.rx_flow_thrhd = rx_thresh; +#endif UART[uart_num]->conf1.rx_flow_en = 1; } else { UART[uart_num]->conf1.rx_flow_en = 0; @@ -299,11 +330,11 @@ esp_err_t uart_get_hw_flow_ctrl(uart_port_t uart_num, uart_hw_flowcontrol_t* flo static esp_err_t uart_reset_rx_fifo(uart_port_t uart_num) { UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL); +#if CONFIG_IDF_TARGET_ESP32 //Due to hardware issue, we can not use fifo_rst to reset uart fifo. //See description about UART_TXFIFO_RST and UART_RXFIFO_RST in <> v2.6 or later. // we read the data out and make `fifo_len == 0 && rd_addr == wr_addr`. -#if CONFIG_IDF_TARGET_ESP32 while(UART[uart_num]->status.rxfifo_cnt != 0 || (UART[uart_num]->mem_rx_status.wr_addr != UART[uart_num]->mem_rx_status.rd_addr)) { READ_PERI_REG(UART_FIFO_REG(uart_num)); } @@ -538,9 +569,11 @@ esp_err_t uart_isr_register(uart_port_t uart_num, void (*fn)(void*), void * arg, case UART_NUM_1: ret=esp_intr_alloc(ETS_UART1_INTR_SOURCE, intr_alloc_flags, fn, arg, handle); break; +#if UART_NUM > 2 case UART_NUM_2: ret=esp_intr_alloc(ETS_UART2_INTR_SOURCE, intr_alloc_flags, fn, arg, handle); break; +#endif case UART_NUM_0: default: ret=esp_intr_alloc(ETS_UART0_INTR_SOURCE, intr_alloc_flags, fn, arg, handle); @@ -587,7 +620,7 @@ esp_err_t uart_set_pin(uart_port_t uart_num, int tx_io_num, int rx_io_num, int r rts_sig = U1RTS_OUT_IDX; cts_sig = U1CTS_IN_IDX; break; -#if CONFIG_IDF_TARGET_ESP32 +#if UART_NUM > 2 case UART_NUM_2: tx_sig = U2TXD_OUT_IDX; rx_sig = U2RXD_IN_IDX; @@ -668,11 +701,9 @@ esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_conf periph_module_enable(PERIPH_UART0_MODULE); } else if(uart_num == UART_NUM_1) { periph_module_enable(PERIPH_UART1_MODULE); +#if UART_NUM > 2 } else if(uart_num == UART_NUM_2) { -#if CONFIG_IDF_TARGET_ESP32 periph_module_enable(PERIPH_UART2_MODULE); -#else - return ESP_FAIL; #endif } r = uart_set_hw_flow_ctrl(uart_num, uart_config->flow_ctrl, uart_config->rx_flow_ctrl_thresh); @@ -702,6 +733,7 @@ esp_err_t uart_intr_config(uart_port_t uart_num, const uart_intr_config_t *intr_ UART_ENTER_CRITICAL(&uart_spinlock[uart_num]); UART[uart_num]->int_clr.val = UART_INTR_MASK; if(intr_conf->intr_enable_mask & UART_RXFIFO_TOUT_INT_ENA_M) { +#if CONFIG_IDF_TARGET_ESP32 //Hardware issue workaround: when using ref_tick, the rx timeout threshold needs increase to 10 times. //T_ref = T_apb * APB_CLK/(REF_TICK << CLKDIV_FRAG_BIT_WIDTH) if(UART[uart_num]->conf0.tick_ref_always_on == 0) { @@ -709,6 +741,9 @@ esp_err_t uart_intr_config(uart_port_t uart_num, const uart_intr_config_t *intr_ } else { UART[uart_num]->conf1.rx_tout_thrhd = ((intr_conf->rx_timeout_thresh) & UART_RX_TOUT_THRHD_V); } +#elif CONFIG_IDF_TARGET_ESP32S2BETA + UART[uart_num]->mem_conf.rx_tout_thrhd = ((intr_conf->rx_timeout_thresh) & UART_RX_TOUT_THRHD_V); +#endif UART[uart_num]->conf1.rx_tout_en = 1; } else { UART[uart_num]->conf1.rx_tout_en = 0; @@ -1480,11 +1515,9 @@ esp_err_t uart_driver_delete(uart_port_t uart_num) periph_module_disable(PERIPH_UART0_MODULE); } else if(uart_num == UART_NUM_1) { periph_module_disable(PERIPH_UART1_MODULE); +#if UART_NUM > 2 } else if(uart_num == UART_NUM_2) { -#if CONFIG_IDF_TARGET_ESP32 - periph_module_disable(PERIPH_UART2_MODULE); -#else - return ESP_FAIL; + periph_module_disable(PERIPH_UART2_MODULE); #endif } } @@ -1502,6 +1535,7 @@ portMUX_TYPE *uart_get_selectlock() { return &uart_selectlock; } + // Set UART mode esp_err_t uart_set_mode(uart_port_t uart_num, uart_mode_t mode) { @@ -1570,7 +1604,15 @@ esp_err_t uart_set_rx_timeout(uart_port_t uart_num, const uint8_t tout_thresh) // The tout_thresh = 1, defines TOUT interrupt timeout equal to // transmission time of one symbol (~11 bit) on current baudrate if (tout_thresh > 0) { - UART[uart_num]->conf1.rx_tout_thrhd = (tout_thresh & UART_RX_TOUT_THRHD_V); +#if CONFIG_IDF_TARGET_ESP32 + if(UART[uart_num]->conf0.tick_ref_always_on == 0) { + UART[uart_num]->conf1.rx_tout_thrhd = ((tout_thresh * UART_TOUT_REF_FACTOR_DEFAULT) & UART_RX_TOUT_THRHD_V); + } else { + UART[uart_num]->conf1.rx_tout_thrhd = ((tout_thresh) & UART_RX_TOUT_THRHD_V); + } +#elif CONFIG_IDF_TARGET_ESP32S2BETA + UART[uart_num]->mem_conf.rx_tout_thrhd = ((tout_thresh) & UART_RX_TOUT_THRHD_V); +#endif UART[uart_num]->conf1.rx_tout_en = 1; } else { UART[uart_num]->conf1.rx_tout_en = 0; diff --git a/components/freemodbus/common/include/esp_modbus_common.h b/components/freemodbus/common/include/esp_modbus_common.h index 7bec02476..34810cf36 100644 --- a/components/freemodbus/common/include/esp_modbus_common.h +++ b/components/freemodbus/common/include/esp_modbus_common.h @@ -22,10 +22,10 @@ #define MB_CONTROLLER_PRIORITY (CONFIG_FMB_SERIAL_TASK_PRIO - 1) // priority of MB controller task // Default port defines -#define MB_DEVICE_ADDRESS (1) // Default slave device address in Modbus -#define MB_DEVICE_SPEED (115200) // Default Modbus speed for now hard defined -#define MB_UART_PORT (UART_NUM_2) // Default UART port number -#define MB_PAR_INFO_TOUT (10) // Timeout for get parameter info +#define MB_DEVICE_ADDRESS (1) // Default slave device address in Modbus +#define MB_DEVICE_SPEED (115200) // Default Modbus speed for now hard defined +#define MB_UART_PORT (UART_NUM_MAX - 1) // Default UART port number +#define MB_PAR_INFO_TOUT (10) // Timeout for get parameter info #define MB_PARITY_NONE (UART_PARITY_DISABLE) // The Macros below handle the endianness while transfer N byte data into buffer diff --git a/components/freemodbus/port/portserial.c b/components/freemodbus/port/portserial.c index 54bbe8318..10967af7a 100644 --- a/components/freemodbus/port/portserial.c +++ b/components/freemodbus/port/portserial.c @@ -78,7 +78,7 @@ static TaskHandle_t xMbTaskHandle; static const CHAR *TAG = "MB_SERIAL"; // The UART hardware port number -static UCHAR ucUartNumber = UART_NUM_2; +static UCHAR ucUartNumber = UART_NUM_MAX - 1; static BOOL bRxStateEnabled = FALSE; // Receiver enabled flag static BOOL bTxStateEnabled = FALSE; // Transmitter enabled flag diff --git a/components/freemodbus/port/portserial_m.c b/components/freemodbus/port/portserial_m.c index 74a4a1be0..330269101 100644 --- a/components/freemodbus/port/portserial_m.c +++ b/components/freemodbus/port/portserial_m.c @@ -73,7 +73,7 @@ static QueueHandle_t xMbUartQueue; static TaskHandle_t xMbTaskHandle; // The UART hardware port number -static UCHAR ucUartNumber = UART_NUM_2; +static UCHAR ucUartNumber = UART_NUM_MAX - 1; static BOOL bRxStateEnabled = FALSE; // Receiver enabled flag static BOOL bTxStateEnabled = FALSE; // Transmitter enabled flag diff --git a/components/freemodbus/serial_master/modbus_controller/mbc_serial_master.c b/components/freemodbus/serial_master/modbus_controller/mbc_serial_master.c index 8db15aea4..30aae200f 100644 --- a/components/freemodbus/serial_master/modbus_controller/mbc_serial_master.c +++ b/components/freemodbus/serial_master/modbus_controller/mbc_serial_master.c @@ -83,7 +83,7 @@ static esp_err_t mbc_serial_master_setup(void* comm_info) MB_MASTER_CHECK(((comm_info_ptr->mode == MB_MODE_RTU) || (comm_info_ptr->mode == MB_MODE_ASCII)), ESP_ERR_INVALID_ARG, "mb incorrect mode = (0x%x).", (uint32_t)comm_info_ptr->mode); - MB_MASTER_CHECK((comm_info_ptr->port <= UART_NUM_2), ESP_ERR_INVALID_ARG, + MB_MASTER_CHECK((comm_info_ptr->port < UART_NUM_MAX), ESP_ERR_INVALID_ARG, "mb wrong port to set = (0x%x).", (uint32_t)comm_info_ptr->port); MB_MASTER_CHECK((comm_info_ptr->parity <= UART_PARITY_EVEN), ESP_ERR_INVALID_ARG, "mb wrong parity option = (0x%x).", (uint32_t)comm_info_ptr->parity); diff --git a/components/freemodbus/serial_slave/modbus_controller/mbc_serial_slave.c b/components/freemodbus/serial_slave/modbus_controller/mbc_serial_slave.c index 86e9616d0..72d753e52 100644 --- a/components/freemodbus/serial_slave/modbus_controller/mbc_serial_slave.c +++ b/components/freemodbus/serial_slave/modbus_controller/mbc_serial_slave.c @@ -69,7 +69,7 @@ static esp_err_t mbc_serial_slave_setup(void* comm_info) MB_SLAVE_CHECK((comm_settings->slave_addr <= MB_ADDRESS_MAX), ESP_ERR_INVALID_ARG, "mb wrong slave address = (0x%x).", (uint32_t)comm_settings->slave_addr); - MB_SLAVE_CHECK((comm_settings->port <= UART_NUM_2), ESP_ERR_INVALID_ARG, + MB_SLAVE_CHECK((comm_settings->port < UART_NUM_MAX), ESP_ERR_INVALID_ARG, "mb wrong port to set = (0x%x).", (uint32_t)comm_settings->port); MB_SLAVE_CHECK((comm_settings->parity <= UART_PARITY_EVEN), ESP_ERR_INVALID_ARG, "mb wrong parity option = (0x%x).", (uint32_t)comm_settings->parity); diff --git a/components/soc/esp32/include/soc/uart_caps.h b/components/soc/esp32/include/soc/uart_caps.h new file mode 100644 index 000000000..97b0894fe --- /dev/null +++ b/components/soc/esp32/include/soc/uart_caps.h @@ -0,0 +1,26 @@ +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_UART_CAPS_H_ +#define _SOC_UART_CAPS_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define SOC_UART_NUM 3 + +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_UART_CAPS_H_ */ diff --git a/components/soc/esp32s2beta/include/soc/uart_caps.h b/components/soc/esp32s2beta/include/soc/uart_caps.h new file mode 100644 index 000000000..a1c263e7c --- /dev/null +++ b/components/soc/esp32s2beta/include/soc/uart_caps.h @@ -0,0 +1,26 @@ +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_UART_CAPS_H_ +#define _SOC_UART_CAPS_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define SOC_UART_NUM 2 + +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_UART_CAPS_H_ */ diff --git a/components/soc/esp32s2beta/include/soc/uart_struct.h b/components/soc/esp32s2beta/include/soc/uart_struct.h index c4096d5f9..07f27e905 100644 --- a/components/soc/esp32s2beta/include/soc/uart_struct.h +++ b/components/soc/esp32s2beta/include/soc/uart_struct.h @@ -20,354 +20,353 @@ extern "C" { typedef volatile struct { union { struct { - uint8_t rw_byte; /*This register stores one byte data read by rx fifo.*/ + uint8_t rw_byte; uint8_t reserved[3]; }; uint32_t val; } ahb_fifo; union { struct { - uint32_t rxfifo_full: 1; /*This interrupt raw bit turns to high level when receiver receives more data than (rx_flow_thrhd_h3 rx_flow_thrhd).*/ - uint32_t txfifo_empty: 1; /*This interrupt raw bit turns to high level when the amount of data in transmitter's fifo is less than ((tx_mem_cnttxfifo_cnt) .*/ - uint32_t parity_err: 1; /*This interrupt raw bit turns to high level when receiver detects the parity error of data.*/ - uint32_t frm_err: 1; /*This interrupt raw bit turns to high level when receiver detects data's frame error .*/ - uint32_t rxfifo_ovf: 1; /*This interrupt raw bit turns to high level when receiver receives more data than the fifo can store.*/ - uint32_t dsr_chg: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of dsrn signal.*/ - uint32_t cts_chg: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of ctsn signal.*/ - uint32_t brk_det: 1; /*This interrupt raw bit turns to high level when receiver detects the 0 after the stop bit.*/ - uint32_t rxfifo_tout: 1; /*This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.*/ - uint32_t sw_xon: 1; /*This interrupt raw bit turns to high level when receiver receives xoff char with uart_sw_flow_con_en is set to 1.*/ - uint32_t sw_xoff: 1; /*This interrupt raw bit turns to high level when receiver receives xon char with uart_sw_flow_con_en is set to 1.*/ - uint32_t glitch_det: 1; /*This interrupt raw bit turns to high level when receiver detects the start bit.*/ - uint32_t tx_brk_done: 1; /*This interrupt raw bit turns to high level when transmitter completes sending 0 after all the data in transmitter's fifo are send.*/ - uint32_t tx_brk_idle_done: 1; /*This interrupt raw bit turns to high level when transmitter has kept the shortest duration after the last data has been send.*/ - uint32_t tx_done: 1; /*This interrupt raw bit turns to high level when transmitter has send all the data in fifo.*/ - uint32_t rs485_parity_err: 1; /*This interrupt raw bit turns to high level when rs485 detects the parity error.*/ - uint32_t rs485_frm_err: 1; /*This interrupt raw bit turns to high level when rs485 detects the data frame error.*/ - uint32_t rs485_clash: 1; /*This interrupt raw bit turns to high level when rs485 detects the clash between transmitter and receiver.*/ - uint32_t at_cmd_char_det: 1; /*This interrupt raw bit turns to high level when receiver detects the configured at_cmd chars.*/ - uint32_t reserved19: 13; + uint32_t rxfifo_full: 1; + uint32_t txfifo_empty: 1; + uint32_t parity_err: 1; + uint32_t frm_err: 1; + uint32_t rxfifo_ovf: 1; + uint32_t dsr_chg: 1; + uint32_t cts_chg: 1; + uint32_t brk_det: 1; + uint32_t rxfifo_tout: 1; + uint32_t sw_xon: 1; + uint32_t sw_xoff: 1; + uint32_t glitch_det: 1; + uint32_t tx_brk_done: 1; + uint32_t tx_brk_idle_done: 1; + uint32_t tx_done: 1; + uint32_t rs485_parity_err: 1; + uint32_t rs485_frm_err: 1; + uint32_t rs485_clash: 1; + uint32_t at_cmd_char_det: 1; + uint32_t wakeup: 1; + uint32_t reserved20: 12; }; uint32_t val; } int_raw; union { struct { - uint32_t rxfifo_full: 1; /*This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.*/ - uint32_t txfifo_empty: 1; /*This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1.*/ - uint32_t parity_err: 1; /*This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.*/ - uint32_t frm_err: 1; /*This is the status bit for frm_err_int_raw when fm_err_int_ena is set to 1.*/ - uint32_t rxfifo_ovf: 1; /*This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.*/ - uint32_t dsr_chg: 1; /*This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/ - uint32_t cts_chg: 1; /*This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/ - uint32_t brk_det: 1; /*This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/ - uint32_t rxfifo_tout: 1; /*This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.*/ - uint32_t sw_xon: 1; /*This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/ - uint32_t sw_xoff: 1; /*This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/ - uint32_t glitch_det: 1; /*This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.*/ - uint32_t tx_brk_done: 1; /*This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.*/ - uint32_t tx_brk_idle_done: 1; /*This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/ - uint32_t tx_done: 1; /*This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/ - uint32_t rs485_parity_err: 1; /*This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.*/ - uint32_t rs485_frm_err: 1; /*This is the status bit for rs485_fm_err_int_raw when rs485_fm_err_int_ena is set to 1.*/ - uint32_t rs485_clash: 1; /*This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.*/ - uint32_t at_cmd_char_det: 1; /*This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.*/ - uint32_t reserved19: 13; + uint32_t rxfifo_full: 1; + uint32_t txfifo_empty: 1; + uint32_t parity_err: 1; + uint32_t frm_err: 1; + uint32_t rxfifo_ovf: 1; + uint32_t dsr_chg: 1; + uint32_t cts_chg: 1; + uint32_t brk_det: 1; + uint32_t rxfifo_tout: 1; + uint32_t sw_xon: 1; + uint32_t sw_xoff: 1; + uint32_t glitch_det: 1; + uint32_t tx_brk_done: 1; + uint32_t tx_brk_idle_done: 1; + uint32_t tx_done: 1; + uint32_t rs485_parity_err: 1; + uint32_t rs485_frm_err: 1; + uint32_t rs485_clash: 1; + uint32_t at_cmd_char_det: 1; + uint32_t wakeup: 1; + uint32_t reserved20: 12; }; uint32_t val; } int_st; union { struct { - uint32_t rxfifo_full: 1; /*This is the enable bit for rxfifo_full_int_st register.*/ - uint32_t txfifo_empty: 1; /*This is the enable bit for rxfifo_full_int_st register.*/ - uint32_t parity_err: 1; /*This is the enable bit for parity_err_int_st register.*/ - uint32_t frm_err: 1; /*This is the enable bit for frm_err_int_st register.*/ - uint32_t rxfifo_ovf: 1; /*This is the enable bit for rxfifo_ovf_int_st register.*/ - uint32_t dsr_chg: 1; /*This is the enable bit for dsr_chg_int_st register.*/ - uint32_t cts_chg: 1; /*This is the enable bit for cts_chg_int_st register.*/ - uint32_t brk_det: 1; /*This is the enable bit for brk_det_int_st register.*/ - uint32_t rxfifo_tout: 1; /*This is the enable bit for rxfifo_tout_int_st register.*/ - uint32_t sw_xon: 1; /*This is the enable bit for sw_xon_int_st register.*/ - uint32_t sw_xoff: 1; /*This is the enable bit for sw_xoff_int_st register.*/ - uint32_t glitch_det: 1; /*This is the enable bit for glitch_det_int_st register.*/ - uint32_t tx_brk_done: 1; /*This is the enable bit for tx_brk_done_int_st register.*/ - uint32_t tx_brk_idle_done: 1; /*This is the enable bit for tx_brk_idle_done_int_st register.*/ - uint32_t tx_done: 1; /*This is the enable bit for tx_done_int_st register.*/ - uint32_t rs485_parity_err: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/ - uint32_t rs485_frm_err: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/ - uint32_t rs485_clash: 1; /*This is the enable bit for rs485_clash_int_st register.*/ - uint32_t at_cmd_char_det: 1; /*This is the enable bit for at_cmd_char_det_int_st register.*/ - uint32_t reserved19: 13; + uint32_t rxfifo_full: 1; + uint32_t txfifo_empty: 1; + uint32_t parity_err: 1; + uint32_t frm_err: 1; + uint32_t rxfifo_ovf: 1; + uint32_t dsr_chg: 1; + uint32_t cts_chg: 1; + uint32_t brk_det: 1; + uint32_t rxfifo_tout: 1; + uint32_t sw_xon: 1; + uint32_t sw_xoff: 1; + uint32_t glitch_det: 1; + uint32_t tx_brk_done: 1; + uint32_t tx_brk_idle_done: 1; + uint32_t tx_done: 1; + uint32_t rs485_parity_err: 1; + uint32_t rs485_frm_err: 1; + uint32_t rs485_clash: 1; + uint32_t at_cmd_char_det: 1; + uint32_t wakeup: 1; + uint32_t reserved20: 12; }; uint32_t val; } int_ena; union { struct { - uint32_t rxfifo_full: 1; /*Set this bit to clear the rxfifo_full_int_raw interrupt.*/ - uint32_t txfifo_empty: 1; /*Set this bit to clear txfifo_empty_int_raw interrupt.*/ - uint32_t parity_err: 1; /*Set this bit to clear parity_err_int_raw interrupt.*/ - uint32_t frm_err: 1; /*Set this bit to clear frm_err_int_raw interrupt.*/ - uint32_t rxfifo_ovf: 1; /*Set this bit to clear rxfifo_ovf_int_raw interrupt.*/ - uint32_t dsr_chg: 1; /*Set this bit to clear the dsr_chg_int_raw interrupt.*/ - uint32_t cts_chg: 1; /*Set this bit to clear the cts_chg_int_raw interrupt.*/ - uint32_t brk_det: 1; /*Set this bit to clear the brk_det_int_raw interrupt.*/ - uint32_t rxfifo_tout: 1; /*Set this bit to clear the rxfifo_tout_int_raw interrupt.*/ - uint32_t sw_xon: 1; /*Set this bit to clear the sw_xon_int_raw interrupt.*/ - uint32_t sw_xoff: 1; /*Set this bit to clear the sw_xon_int_raw interrupt.*/ - uint32_t glitch_det: 1; /*Set this bit to clear the glitch_det_int_raw interrupt.*/ - uint32_t tx_brk_done: 1; /*Set this bit to clear the tx_brk_done_int_raw interrupt..*/ - uint32_t tx_brk_idle_done: 1; /*Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/ - uint32_t tx_done: 1; /*Set this bit to clear the tx_done_int_raw interrupt.*/ - uint32_t rs485_parity_err: 1; /*Set this bit to clear the rs485_parity_err_int_raw interrupt.*/ - uint32_t rs485_frm_err: 1; /*Set this bit to clear the rs485_frm_err_int_raw interrupt.*/ - uint32_t rs485_clash: 1; /*Set this bit to clear the rs485_clash_int_raw interrupt.*/ - uint32_t at_cmd_char_det: 1; /*Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/ - uint32_t reserved19: 13; + uint32_t rxfifo_full: 1; + uint32_t txfifo_empty: 1; + uint32_t parity_err: 1; + uint32_t frm_err: 1; + uint32_t rxfifo_ovf: 1; + uint32_t dsr_chg: 1; + uint32_t cts_chg: 1; + uint32_t brk_det: 1; + uint32_t rxfifo_tout: 1; + uint32_t sw_xon: 1; + uint32_t sw_xoff: 1; + uint32_t glitch_det: 1; + uint32_t tx_brk_done: 1; + uint32_t tx_brk_idle_done: 1; + uint32_t tx_done: 1; + uint32_t rs485_parity_err: 1; + uint32_t rs485_frm_err: 1; + uint32_t rs485_clash: 1; + uint32_t at_cmd_char_det: 1; + uint32_t wakeup: 1; + uint32_t reserved20: 12; }; uint32_t val; } int_clr; union { struct { - uint32_t div_int: 20; /*The register value is the integer part of the frequency divider's factor.*/ - uint32_t div_frag: 4; /*The register value is the decimal part of the frequency divider's factor.*/ + uint32_t div_int: 20; + uint32_t div_frag: 4; uint32_t reserved24: 8; }; uint32_t val; } clk_div; union { struct { - uint32_t en: 1; /*This is the enable bit for detecting baudrate.*/ + uint32_t en: 1; uint32_t reserved1: 7; - uint32_t glitch_filt: 8; /*when input pulse width is lower then this value ignore this pulse.this register is used in auto-baud detect process.*/ + uint32_t glitch_filt: 8; uint32_t reserved16: 16; }; uint32_t val; } auto_baud; union { struct { - uint32_t rxfifo_cnt: 8; /*(rx_mem_cnt rxfifo_cnt) stores the byte number of valid data in receiver's fifo. rx_mem_cnt register stores the 3 most significant bits rxfifo_cnt stores the 8 least significant bits.*/ - uint32_t st_urx_out: 4; /*This register stores the value of receiver's finite state machine. 0:RX_IDLE 1:RX_STRT 2:RX_DAT0 3:RX_DAT1 4:RX_DAT2 5:RX_DAT3 6:RX_DAT4 7:RX_DAT5 8:RX_DAT6 9:RX_DAT7 10:RX_PRTY 11:RX_STP1 12:RX_STP2 13:RX_DL1*/ - uint32_t reserved12: 1; - uint32_t dsrn: 1; /*This register stores the level value of the internal uart dsr signal.*/ - uint32_t ctsn: 1; /*This register stores the level value of the internal uart cts signal.*/ - uint32_t rxd: 1; /*This register stores the level value of the internal uart rxd signal.*/ - uint32_t txfifo_cnt: 8; /*(tx_mem_cnt txfifo_cnt) stores the byte number of valid data in transmitter's fifo.tx_mem_cnt stores the 3 most significant bits txfifo_cnt stores the 8 least significant bits.*/ - uint32_t st_utx_out: 4; /*This register stores the value of transmitter's finite state machine. 0:TX_IDLE 1:TX_STRT 2:TX_DAT0 3:TX_DAT1 4:TX_DAT2 5:TX_DAT3 6:TX_DAT4 7:TX_DAT5 8:TX_DAT6 9:TX_DAT7 10:TX_PRTY 11:TX_STP1 12:TX_STP2 13:TX_DL0 14:TX_DL1*/ - uint32_t reserved28: 1; - uint32_t dtrn: 1; /*The register represent the level value of the internal uart dsr signal.*/ - uint32_t rtsn: 1; /*This register represent the level value of the internal uart cts signal.*/ - uint32_t txd: 1; /*This register represent the level value of the internal uart rxd signal.*/ + uint32_t rxfifo_cnt:10; + uint32_t reserved10: 3; + uint32_t dsrn: 1; + uint32_t ctsn: 1; + uint32_t rxd: 1; + uint32_t txfifo_cnt:10; + uint32_t reserved26: 3; + uint32_t dtrn: 1; + uint32_t rtsn: 1; + uint32_t txd: 1; }; uint32_t val; } status; union { struct { - uint32_t parity: 1; /*This register is used to configure the parity check mode. 0:even 1:odd*/ - uint32_t parity_en: 1; /*Set this bit to enable uart parity check.*/ - uint32_t bit_num: 2; /*This register is used to set the length of data: 0:5bits 1:6bits 2:7bits 3:8bits*/ - uint32_t stop_bit_num: 2; /*This register is used to set the length of stop bit. 1:1bit 2:1.5bits 3:2bits*/ - uint32_t sw_rts: 1; /*This register is used to configure the software rts signal which is used in software flow control.*/ - uint32_t sw_dtr: 1; /*This register is used to configure the software dtr signal which is used in software flow control..*/ - uint32_t txd_brk: 1; /*Set this bit to enable transmitter to send 0 when the process of sending data is done.*/ - uint32_t irda_dplx: 1; /*Set this bit to enable irda loop-back mode.*/ - uint32_t irda_tx_en: 1; /*This is the start enable bit for irda transmitter.*/ - uint32_t irda_wctl: 1; /*1：the irda transmitter's 11th bit is the same to the 10th bit. 0：set irda transmitter's 11th bit to 0.*/ - uint32_t irda_tx_inv: 1; /*Set this bit to inverse the level value of irda transmitter's level.*/ - uint32_t irda_rx_inv: 1; /*Set this bit to inverse the level value of irda receiver's level.*/ - uint32_t loopback: 1; /*Set this bit to enable uart loop-back test mode.*/ - uint32_t tx_flow_en: 1; /*Set this bit to enable transmitter's flow control function.*/ - uint32_t irda_en: 1; /*Set this bit to enable irda protocol.*/ - uint32_t rxfifo_rst: 1; /*Set this bit to reset uart receiver's fifo.*/ - uint32_t txfifo_rst: 1; /*Set this bit to reset uart transmitter's fifo.*/ - uint32_t rxd_inv: 1; /*Set this bit to inverse the level value of uart rxd signal.*/ - uint32_t cts_inv: 1; /*Set this bit to inverse the level value of uart cts signal.*/ - uint32_t dsr_inv: 1; /*Set this bit to inverse the level value of uart dsr signal.*/ - uint32_t txd_inv: 1; /*Set this bit to inverse the level value of uart txd signal.*/ - uint32_t rts_inv: 1; /*Set this bit to inverse the level value of uart rts signal.*/ - uint32_t dtr_inv: 1; /*Set this bit to inverse the level value of uart dtr signal.*/ - uint32_t clk_en: 1; /*1：force clock on for registers：support clock only when write registers*/ - uint32_t err_wr_mask: 1; /*1：receiver stops storing data int fifo when data is wrong. 0：receiver stores the data even if the received data is wrong.*/ - uint32_t tick_ref_always_on: 1; /*This register is used to select the clock.1：apb clock：ref_tick*/ + uint32_t parity: 1; + uint32_t parity_en: 1; + uint32_t bit_num: 2; + uint32_t stop_bit_num: 2; + uint32_t sw_rts: 1; + uint32_t sw_dtr: 1; + uint32_t txd_brk: 1; + uint32_t irda_dplx: 1; + uint32_t irda_tx_en: 1; + uint32_t irda_wctl: 1; + uint32_t irda_tx_inv: 1; + uint32_t irda_rx_inv: 1; + uint32_t loopback: 1; + uint32_t tx_flow_en: 1; + uint32_t irda_en: 1; + uint32_t rxfifo_rst: 1; + uint32_t txfifo_rst: 1; + uint32_t rxd_inv: 1; + uint32_t cts_inv: 1; + uint32_t dsr_inv: 1; + uint32_t txd_inv: 1; + uint32_t rts_inv: 1; + uint32_t dtr_inv: 1; + uint32_t clk_en: 1; + uint32_t err_wr_mask: 1; + uint32_t tick_ref_always_on: 1; uint32_t reserved28: 4; }; uint32_t val; } conf0; union { struct { - uint32_t rxfifo_full_thrhd: 7; - uint32_t reserved7: 1; - uint32_t txfifo_empty_thrhd: 7; + uint32_t rxfifo_full_thrhd: 9; + uint32_t txfifo_empty_thrhd: 9; + uint32_t reserved18: 11; uint32_t rx_tout_flow_dis: 1; - uint32_t rx_flow_thrhd: 7; uint32_t rx_flow_en: 1; - uint32_t rx_tout_thrhd: 7; uint32_t rx_tout_en: 1; }; uint32_t val; } conf1; union { struct { - uint32_t min_cnt: 20; /*This register stores the value of the minimum duration time for the low level pulse， it is used in baudrate-detect process.*/ - uint32_t reserved20: 12; + uint32_t min_cnt: 20; + uint32_t reserved20: 12; }; uint32_t val; } lowpulse; union { struct { - uint32_t min_cnt: 20; /*This register stores the value of the maximum duration time for the high level pulse， it is used in baudrate-detect process.*/ - uint32_t reserved20: 12; + uint32_t min_cnt: 20; + uint32_t reserved20: 12; }; uint32_t val; } highpulse; union { struct { - uint32_t edge_cnt: 10; /*This register stores the count of rxd edge change， it is used in baudrate-detect process.*/ + uint32_t edge_cnt: 10; uint32_t reserved10: 22; }; uint32_t val; } rxd_cnt; union { struct { - uint32_t sw_flow_con_en: 1; /*Set this bit to enable software flow control. it is used with register sw_xon or sw_xoff .*/ - uint32_t xonoff_del: 1; /*Set this bit to remove flow control char from the received data.*/ - uint32_t force_xon: 1; /*Set this bit to clear ctsn to stop the transmitter from sending data.*/ - uint32_t force_xoff: 1; /*Set this bit to set ctsn to enable the transmitter to go on sending data.*/ - uint32_t send_xon: 1; /*Set this bit to send xon char， it is cleared by hardware automatically.*/ - uint32_t send_xoff: 1; /*Set this bit to send xoff char， it is cleared by hardware automatically.*/ + uint32_t sw_flow_con_en: 1; + uint32_t xonoff_del: 1; + uint32_t force_xon: 1; + uint32_t force_xoff: 1; + uint32_t send_xon: 1; + uint32_t send_xoff: 1; uint32_t reserved6: 26; }; uint32_t val; } flow_conf; union { struct { - uint32_t active_threshold:10; /*When the input rxd edge changes more than this register value， the uart is active from light sleeping mode.*/ + uint32_t active_threshold:10; uint32_t reserved10: 22; }; uint32_t val; } sleep_conf; union { struct { - uint32_t xon_threshold: 8; /*when the data amount in receiver's fifo is more than this register value， it will send a xoff char with uart_sw_flow_con_en set to 1.*/ - uint32_t xoff_threshold: 8; /*When the data amount in receiver's fifo is less than this register value， it will send a xon char with uart_sw_flow_con_en set to 1.*/ - uint32_t xon_char: 8; /*This register stores the xon flow control char.*/ - uint32_t xoff_char: 8; /*This register stores the xoff flow control char.*/ + uint32_t xoff_threshold: 9; + uint32_t xoff_char: 8; + uint32_t reserved17: 15; }; uint32_t val; - } swfc_conf; + } swfc_conf0; union { struct { - uint32_t rx_idle_thrhd:10; /*when receiver takes more time than this register value to receive a byte data， it will produce frame end signal for uhci to stop receiving data.*/ - uint32_t tx_idle_num: 10; /*This register is used to configure the duration time between transfers.*/ - uint32_t tx_brk_num: 8; /*This register is used to configure the number of 0 send after the process of sending data is done. it is active when txd_brk is set to 1.*/ + uint32_t xon_threshold: 9; + uint32_t xon_char: 8; + uint32_t reserved17: 15; + }; + uint32_t val; + } swfc_conf1; + union { + struct { + uint32_t rx_idle_thrhd:10; + uint32_t tx_idle_num: 10; + uint32_t tx_brk_num: 8; uint32_t reserved28: 4; }; uint32_t val; } idle_conf; union { struct { - uint32_t en: 1; /*Set this bit to choose rs485 mode.*/ - uint32_t dl0_en: 1; /*Set this bit to delay the stop bit by 1 bit.*/ - uint32_t dl1_en: 1; /*Set this bit to delay the stop bit by 1 bit.*/ - uint32_t tx_rx_en: 1; /*Set this bit to enable loop-back transmitter's output data signal to receiver's input data signal.*/ - uint32_t rx_busy_tx_en: 1; /*1: enable rs485's transmitter to send data when rs485's receiver is busy. 0:rs485's transmitter should not send data when its receiver is busy.*/ - uint32_t rx_dly_num: 1; /*This register is used to delay the receiver's internal data signal.*/ - uint32_t tx_dly_num: 4; /*This register is used to delay the transmitter's internal data signal.*/ + uint32_t en: 1; + uint32_t dl0_en: 1; + uint32_t dl1_en: 1; + uint32_t tx_rx_en: 1; + uint32_t rx_busy_tx_en: 1; + uint32_t rx_dly_num: 1; + uint32_t tx_dly_num: 4; uint32_t reserved10: 22; }; uint32_t val; } rs485_conf; union { struct { - uint32_t pre_idle_num:24; /*This register is used to configure the idle duration time before the first at_cmd is received by receiver， when the the duration is less than this register value it will not take the next data received as at_cmd char.*/ - uint32_t reserved24: 8; + uint32_t pre_idle_num:16; + uint32_t reserved16: 16; }; uint32_t val; } at_cmd_precnt; union { struct { - uint32_t post_idle_num:24; /*This register is used to configure the duration time between the last at_cmd and the next data， when the duration is less than this register value it will not take the previous data as at_cmd char.*/ - uint32_t reserved24: 8; + uint32_t post_idle_num:16; + uint32_t reserved16: 16; }; uint32_t val; } at_cmd_postcnt; union { struct { - uint32_t rx_gap_tout:24; /*This register is used to configure the duration time between the at_cmd chars， when the duration time is less than this register value it will not take the data as continous at_cmd chars.*/ - uint32_t reserved24: 8; + uint32_t rx_gap_tout:16; + uint32_t reserved16: 16; }; uint32_t val; } at_cmd_gaptout; union { struct { - uint32_t data: 8; /*This register is used to configure the content of at_cmd char.*/ - uint32_t char_num: 8; /*This register is used to configure the number of continuous at_cmd chars received by receiver.*/ + uint32_t data: 8; + uint32_t char_num: 8; uint32_t reserved16: 16; }; uint32_t val; } at_cmd_char; union { struct { - uint32_t mem_pd: 1; /*Set this bit to power down memory，when reg_mem_pd registers in the 3 uarts are all set to 1 memory will enter low power mode.*/ - uint32_t reserved1: 1; - uint32_t reserved2: 1; - uint32_t rx_size: 4; /*This register is used to configure the amount of mem allocated to receiver's fifo. the default byte num is 128.*/ - uint32_t tx_size: 4; /*This register is used to configure the amount of mem allocated to transmitter's fifo.the default byte num is 128.*/ - uint32_t reserved11: 4; - uint32_t rx_flow_thrhd_h3: 3; /*refer to the rx_flow_thrhd's description.*/ - uint32_t rx_tout_thrhd_h3: 3; /*refer to the rx_tout_thrhd's description.*/ - uint32_t xon_threshold_h2: 2; /*refer to the uart_xon_threshold's description.*/ - uint32_t xoff_threshold_h2: 2; /*refer to the uart_xoff_threshold's description.*/ - uint32_t rx_mem_full_thrhd: 3; /*refer to the rxfifo_full_thrhd's description.*/ - uint32_t tx_mem_empty_thrhd: 3; /*refer to txfifo_empty_thrhd 's description.*/ - uint32_t reserved31: 1; + uint32_t mem_pd: 1; + uint32_t rx_size: 3; + uint32_t tx_size: 3; + uint32_t rx_flow_thrhd: 9; + uint32_t rx_tout_thrhd:10; + uint32_t reserved26: 6; }; uint32_t val; } mem_conf; union { struct { - uint32_t apb_tx_waddr:11; - uint32_t tx_raddr: 11; - uint32_t reserved22: 10; + uint32_t apb_tx_waddr:10; + uint32_t reserved10: 1; + uint32_t tx_raddr: 10; + uint32_t reserved21: 11; }; uint32_t val; } mem_tx_status; union { struct { - uint32_t apb_rx_raddr:11; - uint32_t rx_waddr: 11; - uint32_t reserved22: 10; + uint32_t apb_rx_raddr:10; + uint32_t reserved10: 1; + uint32_t rx_waddr: 10; + uint32_t reserved21: 11; }; uint32_t val; } mem_rx_status; union { struct { - uint32_t rx_cnt: 3; /*refer to the rxfifo_cnt's description.*/ - uint32_t tx_cnt: 3; /*refer to the txfifo_cnt's description.*/ - uint32_t reserved6: 26; + uint32_t st_urx_out: 4; + uint32_t st_utx_out: 4; + uint32_t reserved8: 24; }; uint32_t val; - } mem_cnt_status; + } fsm_status; union { struct { - uint32_t min_cnt: 20; /*This register stores the count of rxd pos-edge edge， it is used in baudrate-detect process.*/ - uint32_t reserved20: 12; + uint32_t min_cnt: 20; + uint32_t reserved20: 12; }; uint32_t val; } pospulse; union { struct { - uint32_t min_cnt: 20; /*This register stores the count of rxd neg-edge edge， it is used in baudrate-detect process.*/ - uint32_t reserved20: 12; + uint32_t min_cnt: 20; + uint32_t reserved20: 12; }; uint32_t val; } negpulse; - uint32_t reserved_70; - uint32_t reserved_74; - uint32_t date; /**/ - uint32_t id; /**/ + uint32_t date; /**/ + uint32_t id; /**/ } uart_dev_t; extern uart_dev_t UART0; extern uart_dev_t UART1; -extern uart_dev_t UART2; #ifdef __cplusplus } #endif diff --git a/components/vfs/vfs_uart.c b/components/vfs/vfs_uart.c index 2bb365a60..5e33e4c20 100644 --- a/components/vfs/vfs_uart.c +++ b/components/vfs/vfs_uart.c @@ -32,7 +32,7 @@ #endif // TODO: make the number of UARTs chip dependent -#define UART_NUM 3 +#define UART_NUM SOC_UART_NUM // Token signifying that no character is available #define NONE -1 @@ -51,12 +51,27 @@ static void uart_tx_char_via_driver(int fd, int c); static int uart_rx_char_via_driver(int fd); // Pointers to UART peripherals -static uart_dev_t* s_uarts[UART_NUM] = {&UART0, &UART1, &UART2}; +static uart_dev_t* s_uarts[UART_NUM] = { + &UART0, + &UART1, +#if UART_NUM > 2 + &UART2 +#endif +}; + +// One-character buffer used for newline conversion code, per UART +static int s_peek_char[UART_NUM] = { + NONE, + NONE, +#if UART_NUM > 2 + NONE +#endif +}; + // per-UART locks, lazily initialized static _lock_t s_uart_read_locks[UART_NUM]; static _lock_t s_uart_write_locks[UART_NUM]; -// One-character buffer used for newline conversion code, per UART -static int s_peek_char[UART_NUM] = { NONE, NONE, NONE }; + // Per-UART non-blocking flag. Note: default implementation does not honor this // flag, all reads are non-blocking. This option becomes effective if UART // driver is used. @@ -98,15 +113,22 @@ static void uart_end_select(); // Functions used to write bytes to UART. Default to "basic" functions. static tx_func_t s_uart_tx_func[UART_NUM] = { - &uart_tx_char, &uart_tx_char, &uart_tx_char + &uart_tx_char, + &uart_tx_char, +#if UART_NUM > 2 + &uart_tx_char +#endif }; // Functions used to read bytes from UART. Default to "basic" functions. static rx_func_t s_uart_rx_func[UART_NUM] = { - &uart_rx_char, &uart_rx_char, &uart_rx_char + &uart_rx_char, + &uart_rx_char, +#if UART_NUM > 2 + &uart_rx_char +#endif }; - static int uart_open(const char * path, int flags, int mode) { // this is fairly primitive, we should check if file is opened read only, diff --git a/examples/peripherals/uart/uart_events/main/uart_events_example_main.c b/examples/peripherals/uart/uart_events/main/uart_events_example_main.c index 8c9f545cb..48b7bc49b 100644 --- a/examples/peripherals/uart/uart_events/main/uart_events_example_main.c +++ b/examples/peripherals/uart/uart_events/main/uart_events_example_main.c @@ -140,7 +140,11 @@ void app_main() uart_driver_install(EX_UART_NUM, BUF_SIZE * 2, BUF_SIZE * 2, 20, &uart0_queue, 0); //Set uart pattern detect function. +#if CONFIG_IDF_TARGET_ESP32 uart_enable_pattern_det_intr(EX_UART_NUM, '+', PATTERN_CHR_NUM, 10000, 10, 10); +#elif CONFIG_IDF_TARGET_ESP32S2BETA + uart_enable_pattern_det_intr(EX_UART_NUM, '+', PATTERN_CHR_NUM, 9, 0, 0); +#endif //Reset the pattern queue length to record at most 20 pattern positions. uart_pattern_queue_reset(EX_UART_NUM, 20);