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Merge branch 'feature/add_psram_workaround_option_4.0' into 'release/v4.0'

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make psram workaround depend on chip revison(v4.0)

See merge request espressif/esp-idf!6115
This commit is contained in:
Angus Gratton 2019-10-10 11:00:29 +08:00
parent 28a2e6a775 546026d018
commit 4cafa3e76e
2 changed files with 4 additions and 2 deletions
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2
components/efuse/src/esp_efuse_fields.c
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@ -35,7 +35,7 @@ uint8_t esp_efuse_get_chip_ver(void)
uint8_t eco_bit0, eco_bit1, eco_bit2;
esp_efuse_read_field_blob(ESP_EFUSE_CHIP_VER_REV1, &eco_bit0, 1);
esp_efuse_read_field_blob(ESP_EFUSE_CHIP_VER_REV2, &eco_bit1, 1);
eco_bit2 = (REG_READ(APB_CTRL_DATE_REG) & 80000000) >> 31;
eco_bit2 = (REG_READ(APB_CTRL_DATE_REG) & 0x80000000) >> 31;
uint32_t combine_value = (eco_bit2 << 2) | (eco_bit1 << 1) | eco_bit0;
uint8_t chip_ver = 0;
switch (combine_value) {

4
components/esp32/Kconfig
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@ -149,7 +149,7 @@ menu "ESP32-specific"
config SPIRAM_CACHE_WORKAROUND
bool "Enable workaround for bug in SPI RAM cache for Rev1 ESP32s"
depends on SPIRAM_USE_MEMMAP || SPIRAM_USE_CAPS_ALLOC || SPIRAM_USE_MALLOC
depends on (SPIRAM_USE_MEMMAP || SPIRAM_USE_CAPS_ALLOC || SPIRAM_USE_MALLOC) && (ESP32_REV_MIN < 3)
default "y"
help
Revision 1 of the ESP32 has a bug that can cause a write to PSRAM not to take place in some situations
@ -160,6 +160,8 @@ menu "ESP32-specific"
This will also not use any bits of newlib that are located in ROM, opting for a version that is
compiled with the workaround and located in flash instead.
The workaround is not required for ESP32 revision 3 and above.
config SPIRAM_BANKSWITCH_ENABLE
bool "Enable bank switching for >4MiB external RAM"
default y