Fix uart fifo overflow bug
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2ddee72996
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492db0591d
3 changed files with 32 additions and 13 deletions
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@ -271,8 +271,11 @@ esp_err_t uart_get_hw_flow_ctrl(uart_port_t uart_num, uart_hw_flowcontrol_t* flo
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static esp_err_t uart_reset_rx_fifo(uart_port_t uart_num)
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{
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UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
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// Read all data from the FIFO
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while (UART[uart_num]->status.rxfifo_cnt) {
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//Due to hardware issue, we can not use fifo_rst to reset uart fifo.
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//See description about UART_TXFIFO_RST and UART_RXFIFO_RST in <<esp32_technical_reference_manual>> v2.6 or later.
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// we read the data out and make `fifo_len == 0 && rd_addr == wr_addr`.
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while(UART[uart_num]->status.rxfifo_cnt != 0 || (UART[uart_num]->mem_rx_status.wr_addr != UART[uart_num]->mem_rx_status.rd_addr)) {
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READ_PERI_REG(UART_FIFO_REG(uart_num));
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}
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return ESP_OK;
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@ -542,7 +545,6 @@ static void uart_rx_intr_handler_default(void *param)
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int rx_fifo_len = 0;
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uart_event_t uart_event;
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portBASE_TYPE HPTaskAwoken = 0;
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while(uart_intr_status != 0x0) {
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buf_idx = 0;
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uart_event.type = UART_EVENT_MAX;
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@ -691,13 +693,11 @@ static void uart_rx_intr_handler_default(void *param)
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UART_EXIT_CRITICAL_ISR(&uart_spinlock[uart_num]);
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uart_event.type = UART_BUFFER_FULL;
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}
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} else if(uart_intr_status & UART_RXFIFO_OVF_INT_ST_M) {
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UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]);
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// Read all data from the FIFO
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rx_fifo_len = uart_reg->status.rxfifo_cnt;
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for (int i = 0; i < rx_fifo_len; i++) {
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READ_PERI_REG(UART_FIFO_REG(uart_num));
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}
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// When fifo overflows, we reset the fifo.
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else if(uart_intr_status & UART_RXFIFO_OVF_INT_ST_M) {
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UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]);
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uart_reset_rx_fifo(uart_num);
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uart_reg->int_clr.rxfifo_ovf = 1;
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UART_EXIT_CRITICAL_ISR(&uart_spinlock[uart_num]);
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uart_event.type = UART_FIFO_OVF;
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@ -1105,11 +1105,24 @@
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#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x60)
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/* UART_MEM_RX_STATUS : RO ;bitpos:[23:0] ;default: 24'h0 ; */
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/*description: */
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/*description: This register stores the current uart rx mem read address
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and rx mem write address */
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#define UART_MEM_RX_STATUS 0x00FFFFFF
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#define UART_MEM_RX_STATUS_M ((UART_MEM_RX_STATUS_V)<<(UART_MEM_RX_STATUS_S))
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#define UART_MEM_RX_STATUS_V 0xFFFFFF
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#define UART_MEM_RX_STATUS_S 0
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/* UART_MEM_RX_RD_ADDR : RO ;bitpos:[12:2] ;default: 11'h0 ; */
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/*description: This register stores the rx mem read address */
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#define UART_MEM_RX_RD_ADDR 0x000007FF
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#define UART_MEM_RX_RD_ADDR_M ((UART_MEM_RX_RD_ADDR_V)<<(UART_MEM_RX_RD_ADDR_S))
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#define UART_MEM_RX_RD_ADDR_V (0x7FF)
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#define UART_MEM_RX_RD_ADDR_S (2)
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/* UART_MEM_RX_WR_ADDR : RO ;bitpos:[23:13] ;default: 11'h0 ; */
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/*description: This register stores the rx mem write address */
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#define UART_MEM_RX_WR_ADDR 0x000007FF
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#define UART_MEM_RX_WR_ADDR_M ((UART_MEM_RX_WR_ADDR_V)<<(UART_MEM_RX_WR_ADDR_S))
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#define UART_MEM_RX_WR_ADDR_V (0x7FF)
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#define UART_MEM_RX_WR_ADDR_S (13)
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#define UART_MEM_CNT_STATUS_REG(i) (REG_UART_BASE(i) + 0x64)
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/* UART_TX_MEM_CNT : RO ;bitpos:[5:3] ;default: 3'b0 ; */
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@ -335,6 +335,12 @@ typedef volatile struct {
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uint32_t status: 24;
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uint32_t reserved24: 8;
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};
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struct {
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uint32_t reserved0: 2;
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uint32_t rd_addr: 11; /*This register stores the rx mem read address.*/
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uint32_t wr_addr: 11; /*This register stores the rx mem write address.*/
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uint32_t reserved: 8;
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};
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uint32_t val;
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} mem_rx_status;
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union {
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