diff --git a/components/esp32/include/soc/gpio_sd_struct.h b/components/esp32/include/soc/gpio_sd_struct.h new file mode 100644 index 000000000..a1b17bfc5 --- /dev/null +++ b/components/esp32/include/soc/gpio_sd_struct.h @@ -0,0 +1,48 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_GPIO_SD_STRUCT_H_ +#define _SOC_GPIO_SD_STRUCT_H_ +typedef struct { + union { + struct { + volatile uint32_t sd_in: 8; + volatile uint32_t prescale: 8; + volatile uint32_t reserved16: 16; + }; + volatile uint32_t val; + }sigmadelta[8]; + union { + struct { + volatile uint32_t reserved0: 31; + volatile uint32_t clk_en: 1; + }; + volatile uint32_t val; + }sigmadelta_cg; + union { + struct { + volatile uint32_t reserved0: 31; + volatile uint32_t spi_swap: 1; + }; + volatile uint32_t val; + }sigmadelta_misc; + union { + struct { + volatile uint32_t date: 28; + volatile uint32_t reserved28: 4; + }; + volatile uint32_t val; + }sigmadelta_version; +} gpio_sd_dev_t; +extern volatile gpio_sd_dev_t SIGMADELTA; +#endif /* _SOC_GPIO_SD_STRUCT_H_ */ diff --git a/components/esp32/include/soc/gpio_struct.h b/components/esp32/include/soc/gpio_struct.h new file mode 100644 index 000000000..f42de7a29 --- /dev/null +++ b/components/esp32/include/soc/gpio_struct.h @@ -0,0 +1,204 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_GPIO_STRUCT_H_ +#define _SOC_GPIO_STRUCT_H_ +typedef struct { + volatile uint32_t bt_select; /*NA*/ + volatile uint32_t out; /*GPIO0~31 output value*/ + volatile uint32_t out_w1ts; /*GPIO0~31 output value write 1 to set*/ + volatile uint32_t out_w1tc; /*GPIO0~31 output value write 1 to clear*/ + union { + struct { + volatile uint32_t out_data: 8; /*GPIO32~39 output value*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }out1; + union { + struct { + volatile uint32_t out_data: 8; /*GPIO32~39 output value write 1 to set*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }out1_w1ts; + union { + struct { + volatile uint32_t out_data: 8; /*GPIO32~39 output value write 1 to clear*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }out1_w1tc; + union { + struct { + volatile uint32_t sdio_sel: 8; /*SDIO PADS on/off control from outside*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }sdio_select; + volatile uint32_t enable; /*GPIO0~31 output enable*/ + volatile uint32_t enable_w1ts; /*GPIO0~31 output enable write 1 to set*/ + volatile uint32_t enable_w1tc; /*GPIO0~31 output enable write 1 to clear*/ + union { + struct { + volatile uint32_t enable_data: 8; /*GPIO32~39 output enable*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }enable1; + union { + struct { + volatile uint32_t enable_data: 8; /*GPIO32~39 output enable write 1 to set*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }enable1_w1ts; + union { + struct { + volatile uint32_t enable_data: 8; /*GPIO32~39 output enable write 1 to clear*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }enable1_w1tc; + union { + struct { + volatile uint32_t strapping: 16; /*GPIO strapping results: {2'd0 boot_sel_dig[7:1] vsdio_boot_sel boot_sel_chip[5:0]}. Boot_sel_dig[7:1]: {U0RXD SD_CLK SD_CMD SD_DATA0 SD_DATA1 SD_DATA2 SD_DATA3}. vsdio_boot_sel: MTDI. boot_sel_chip[5:0]: {GPIO0 U0TXD GPIO2 GPIO4 MTDO GPIO5}*/ + volatile uint32_t reserved16:16; + }; + volatile uint32_t val; + }strap; + volatile uint32_t in; /*GPIO0~31 input value*/ + union { + struct { + volatile uint32_t in_data: 8; /*GPIO32~39 input value*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }in1; + volatile uint32_t status; /*GPIO0~31 interrupt status*/ + volatile uint32_t status_w1ts; /*GPIO0~31 interrupt status write 1 to set*/ + volatile uint32_t status_w1tc; /*GPIO0~31 interrupt status write 1 to clear*/ + union { + struct { + volatile uint32_t status_interrupt: 8; /*GPIO32~39 interrupt status*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }status1; + union { + struct { + volatile uint32_t status_interrupt: 8; /*GPIO32~39 interrupt status write 1 to set*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }status1_w1ts; + union { + struct { + volatile uint32_t status_interrupt: 8; /*GPIO32~39 interrupt status write 1 to clear*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }status1_w1tc; + volatile uint32_t reserved_5c; + volatile uint32_t acpu_int; /*GPIO0~31 APP CPU interrupt status*/ + volatile uint32_t acpu_nmi_int; /*GPIO0~31 APP CPU non-maskable interrupt status*/ + volatile uint32_t pcpu_int; /*GPIO0~31 PRO CPU interrupt status*/ + volatile uint32_t pcpu_nmi_int; /*GPIO0~31 PRO CPU non-maskable interrupt status*/ + volatile uint32_t cpusdio_int; /*SDIO's extent GPIO0~31 interrupt*/ + union { + struct { + volatile uint32_t appcpu_int: 8; /*GPIO32~39 APP CPU interrupt status*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }acpu_int1; + union { + struct { + volatile uint32_t appcpu_nmi_int: 8; /*GPIO32~39 APP CPU non-maskable interrupt status*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }acpu_nmi_int1; + union { + struct { + volatile uint32_t procpu_int: 8; /*GPIO32~39 PRO CPU interrupt status*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }pcpu_int1; + union { + struct { + volatile uint32_t procpu_nmi_int: 8; /*GPIO32~39 PRO CPU non-maskable interrupt status*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }pcpu_nmi_int1; + union { + struct { + volatile uint32_t sdio_int: 8; /*SDIO's extent GPIO32~39 interrupt*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }cpusdio_int1; + union { + struct { + volatile uint32_t reserved0: 2; + volatile uint32_t pin_pad_driver: 1; /*if set to 0: normal output if set to 1: open drain*/ + volatile uint32_t reserved3: 4; + volatile uint32_t pin_int_type: 3; /*if set to 0: GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ + volatile uint32_t pin_wakeup_enable: 1; /*GPIO wake up enable only available in light sleep*/ + volatile uint32_t pin_config: 2; /*NA*/ + volatile uint32_t pin_int_ena: 5; /*bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ + volatile uint32_t reserved18: 14; + }; + volatile uint32_t val; + }pin[40]; + union { + struct { + volatile uint32_t cali_rtc_max:10; + volatile uint32_t reserved10: 21; + volatile uint32_t cali_start: 1; + }; + volatile uint32_t val; + }cali_conf; + union { + struct { + volatile uint32_t cali_value_sync2:20; + volatile uint32_t reserved20: 10; + volatile uint32_t cali_rdy_real: 1; + volatile uint32_t cali_rdy_sync2: 1; + }; + volatile uint32_t val; + }cali_data; + union { + struct { + volatile uint32_t func_in_sel: 6; /*select one of the 256 inputs*/ + volatile uint32_t func_in_inv_sel: 1; /*revert the value of the input if you want to revert please set the value to 1*/ + volatile uint32_t sig_in_sel: 1; /*if the slow signal bypass the io matrix or not if you want setting the value to 1*/ + volatile uint32_t reserved8: 24; /*The 256 registers below are selection control for 256 input signals connected to GPIO matrix's 40 GPIO input if GPIO_FUNCx_IN_SEL is set to n(0<=n<40): it means GPIOn input is used for input signal x if GPIO_FUNCx_IN_SEL is set to 0x38: the input signal x is set to 1 if GPIO_FUNCx_IN_SEL is set to 0x30: the input signal x is set to 0*/ + }; + volatile uint32_t val; + }func_in_sel_cfg[256]; + union { + struct { + volatile uint32_t func_out_sel: 9; /*select one of the 256 output to 40 GPIO*/ + volatile uint32_t func_out_inv_sel: 1; /*invert the output value if you want to revert the output value setting the value to 1*/ + volatile uint32_t func_oen_sel: 1; /*weather using the logical oen signal or not using the value setting by the register*/ + volatile uint32_t func_oen_inv_sel: 1; /*invert the output enable value if you want to revert the output enable value setting the value to 1*/ + volatile uint32_t reserved12: 20; /*The 40 registers below are selection control for 40 GPIO output if GPIO_FUNCx_OUT_SEL is set to n(0<=n<256): it means GPIOn input is used for output signal x if GPIO_FUNCx_OUT_INV_SEL is set to 1 the output signal x is set to ~value. if GPIO_FUNC0_OUT_SEL is 256 or GPIO_FUNC0_OEN_SEL is 1 using GPIO_ENABLE_DATA[x] for the enable value else using the signal enable*/ + }; + volatile uint32_t val; + }func_out_sel_cfg[40]; +} gpio_dev_t; +extern volatile gpio_dev_t GPIO; +#endif /* _SOC_GPIO_STRUCT_H_ */ diff --git a/components/esp32/include/soc/i2c_struct.h b/components/esp32/include/soc/i2c_struct.h new file mode 100644 index 000000000..78f895c02 --- /dev/null +++ b/components/esp32/include/soc/i2c_struct.h @@ -0,0 +1,289 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_I2C_STRUCT_H_ +#define _SOC_I2C_STRUCT_H_ +typedef struct { + union { + struct { + volatile uint32_t scl_low_period:14; /*This register is used to configure the low level width of SCL clock.*/ + volatile uint32_t reserved14: 18; + }; + volatile uint32_t val; + }scl_low_period; + union { + struct { + volatile uint32_t sda_force_out: 1; /*1：normally output sda data 0: exchange the function of sda_o and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal)*/ + volatile uint32_t scl_force_out: 1; /*1：normally output scl clock 0: exchange the function of scl_o and scl_oe (scl_o is the original internal output scl signal scl_oe is the enable bit for the internal output scl signal)*/ + volatile uint32_t sample_scl_level: 1; /*Set this bit to sample data in SCL low level. clear this bit to sample data in SCL high level.*/ + volatile uint32_t reserved3: 1; + volatile uint32_t ms_mode: 1; /*Set this bit to configure the module as i2c master clear this bit to configure the module as i2c slave.*/ + volatile uint32_t trans_start: 1; /*Set this bit to start sending data in tx_fifo.*/ + volatile uint32_t tx_lsb_first: 1; /*This bit is used to control the sending mode for data need to be send. 1：receive data from most significant bit 0：receive data from least significant bit*/ + volatile uint32_t rx_lsb_first: 1; /*This bit is used to control the storage mode for received data. 1：receive data from most significant bit 0：receive data from least significant bit*/ + volatile uint32_t clk_en: 1; /*This is the clock gating control bit for reading or writing registers.*/ + volatile uint32_t reserved9: 23; + }; + volatile uint32_t val; + }ctr; + union { + struct { + volatile uint32_t ack_rec: 1; /*This register stores the value of ACK bit.*/ + volatile uint32_t slave_rw: 1; /*when in slave mode 1：master read slave 0: master write slave.*/ + volatile uint32_t time_out: 1; /*when I2C takes more than time_out_reg clocks to receive a data then this register changes to high level.*/ + volatile uint32_t arb_lost: 1; /*when I2C lost control of SDA line this register changes to high level.*/ + volatile uint32_t bus_busy: 1; /*1:I2C bus is busy transferring data. 0:I2C bus is in idle state.*/ + volatile uint32_t slave_addressed: 1; /*when configured as i2c slave and the address send by master is equal to slave's address then this bit will be high level.*/ + volatile uint32_t byte_trans: 1; /*This register changes to high level when one byte is transferred.*/ + volatile uint32_t reserved7: 1; + volatile uint32_t rx_fifo_cnt: 6; /*This register represent the amount of data need to send.*/ + volatile uint32_t reserved14: 4; + volatile uint32_t tx_fifo_cnt: 6; /*This register stores the amount of received data in ram.*/ + volatile uint32_t scl_main_state_last: 3; /*This register stores the value of state machine for i2c module. 3'h0: SCL_MAIN_IDLE 3'h1: SCL_ADDRESS_SHIFT 3'h2: SCL_ACK_ADDRESS 3'h3: SCL_RX_DATA 3'h4 SCL_TX_DATA 3'h5:SCL_SEND_ACK 3'h6:SCL_WAIT_ACK*/ + volatile uint32_t reserved27: 1; + volatile uint32_t scl_state_last: 3; /*This register stores the value of state machine to produce SCL. 3'h0: SCL_IDLE 3'h1:SCL_START 3'h2:SCL_LOW_EDGE 3'h3: SCL_LOW 3'h4:SCL_HIGH_EDGE 3'h5:SCL_HIGH 3'h6:SCL_STOP*/ + volatile uint32_t reserved31: 1; + }; + volatile uint32_t val; + }status_reg; + union { + struct { + volatile uint32_t time_out: 20; /*This register is used to configure the max clock number of receiving a data.*/ + volatile uint32_t reserved20:12; + }; + volatile uint32_t val; + }timeout; + union { + struct { + volatile uint32_t slave_addr: 15; /*when configured as i2c slave this register is used to configure slave's address.*/ + volatile uint32_t reserved15: 16; + volatile uint32_t addr_10bit_en: 1; /*This register is used to enable slave 10bit address mode.*/ + }; + volatile uint32_t val; + }slave_addr; + union { + struct { + volatile uint32_t rx_fifo_start_addr: 5; /*This is the offset address of the last receiving data as described in nonfifo_rx_thres_register.*/ + volatile uint32_t rx_fifo_end_addr: 5; /*This is the offset address of the first receiving data as described in nonfifo_rx_thres_register.*/ + volatile uint32_t tx_fifo_start_addr: 5; /*This is the offset address of the first sending data as described in nonfifo_tx_thres register.*/ + volatile uint32_t tx_fifo_end_addr: 5; /*This is the offset address of the last sending data as described in nonfifo_tx_thres register.*/ + volatile uint32_t reserved20: 12; + }; + volatile uint32_t val; + }rx_fifo_st; + union { + struct { + volatile uint32_t rx_fifo_full_thrhd: 5; + volatile uint32_t tx_fifo_empty_thrhd:5; /*Config tx_fifo empty threhd value when using apb fifo access*/ + volatile uint32_t nonfifo_en: 1; /*Set this bit to enble apb nonfifo access.*/ + volatile uint32_t fifo_addr_cfg_en: 1; /*When this bit is set to 1 then the byte after address represent the offset address of I2C Slave's ram.*/ + volatile uint32_t rx_fifo_rst: 1; /*Set this bit to reset rx fifo when using apb fifo access.*/ + volatile uint32_t tx_fifo_rst: 1; /*Set this bit to reset tx fifo when using apb fifo access.*/ + volatile uint32_t nonfifo_rx_thres: 6; /*when I2C receives more than nonfifo_rx_thres data it will produce rx_send_full_int_raw interrupt and update the current offset address of the receiving data.*/ + volatile uint32_t nonfifo_tx_thres: 6; /*when I2C sends more than nonfifo_tx_thres data it will produce tx_send_empty_int_raw interrupt and update the current offset address of the sending data.*/ + volatile uint32_t reserved26: 6; + }; + volatile uint32_t val; + }fifo_conf; + union { + struct { + volatile uint32_t fifo_rdata: 8; /*The register represent the byte data read from rx_fifo when use apb fifo access*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }fifo_data; + union { + struct { + volatile uint32_t rx_fifo_full_int_raw: 1; /*The raw interrupt status bit for rx_fifo full when use apb fifo access.*/ + volatile uint32_t tx_fifo_empty_int_raw: 1; /*The raw interrupt status bit for tx_fifo empty when use apb fifo access.*/ + volatile uint32_t rx_fifo_ovf_int_raw: 1; /*The raw interrupt status bit for receiving data overflow when use apb fifo access.*/ + volatile uint32_t end_detect_int_raw: 1; /*The raw interrupt status bit for end_detect_int interrupt. when I2C deals with the END command it will produce end_detect_int interrupt.*/ + volatile uint32_t slave_tran_comp_int_raw: 1; /*The raw interrupt status bit for slave_tran_comp_int interrupt. when I2C Slave detects the STOP bit it will produce slave_tran_comp_int interrupt.*/ + volatile uint32_t arbitration_lost_int_raw: 1; /*The raw interrupt status bit for arbitration_lost_int interrupt.when I2C lost the usage right of I2C BUS it will produce arbitration_lost_int interrupt.*/ + volatile uint32_t master_tran_comp_int_raw: 1; /*The raw interrupt status bit for master_tra_comp_int interrupt. when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt.*/ + volatile uint32_t trans_complete_int_raw: 1; /*The raw interrupt status bit for trans_complete_int interrupt. when I2C Master finished STOP command it will produce trans_complete_int interrupt.*/ + volatile uint32_t time_out_int_raw: 1; /*The raw interrupt status bit for time_out_int interrupt. when I2C takes a lot of time to receive a data it will produce time_out_int interrupt.*/ + volatile uint32_t trans_start_int_raw: 1; /*The raw interrupt status bit for trans_start_int interrupt. when I2C sends the START bit it will produce trans_start_int interrupt.*/ + volatile uint32_t ack_err_int_raw: 1; /*The raw interrupt status bit for ack_err_int interrupt. when I2C receives a wrong ACK bit it will produce ack_err_int interrupt..*/ + volatile uint32_t rx_rec_full_int_raw: 1; /*The raw interrupt status bit for rx_rec_full_int interrupt. when I2C receives more data than nonfifo_rx_thres it will produce rx_rec_full_int interrupt.*/ + volatile uint32_t tx_send_empty_int_raw: 1; /*The raw interrupt status bit for tx_send_empty_int interrupt.when I2C sends more data than nonfifo_tx_thres it will produce tx_send_empty_int interrupt..*/ + volatile uint32_t reserved13: 19; + }; + volatile uint32_t val; + }int_raw; + union { + struct { + volatile uint32_t rx_fifo_full_int_clr: 1; /*Set this bit to clear the rx_fifo_full_int interrupt.*/ + volatile uint32_t tx_fifo_empty_int_clr: 1; /*Set this bit to clear the tx_fifo_empty_int interrupt.*/ + volatile uint32_t rx_fifo_ovf_int_clr: 1; /*Set this bit to clear the rx_fifo_ovf_int interrupt.*/ + volatile uint32_t end_detect_int_clr: 1; /*Set this bit to clear the end_detect_int interrupt.*/ + volatile uint32_t slave_tran_comp_int_clr: 1; /*Set this bit to clear the slave_tran_comp_int interrupt.*/ + volatile uint32_t arbitration_lost_int_clr: 1; /*Set this bit to clear the arbitration_lost_int interrupt.*/ + volatile uint32_t master_tran_comp_int_clr: 1; /*Set this bit to clear the master_tran_comp interrupt.*/ + volatile uint32_t trans_complete_int_clr: 1; /*Set this bit to clear the trans_complete_int interrupt.*/ + volatile uint32_t time_out_int_clr: 1; /*Set this bit to clear the time_out_int interrupt.*/ + volatile uint32_t trans_start_int_clr: 1; /*Set this bit to clear the trans_start_int interrupt.*/ + volatile uint32_t ack_err_int_clr: 1; /*Set this bit to clear the ack_err_int interrupt.*/ + volatile uint32_t rx_rec_full_int_clr: 1; /*Set this bit to clear the rx_rec_full_int interrupt.*/ + volatile uint32_t tx_send_empty_int_clr: 1; /*Set this bit to clear the tx_send_empty_int interrupt.*/ + volatile uint32_t reserved13: 19; + }; + volatile uint32_t val; + }int_clr; + union { + struct { + volatile uint32_t rx_fifo_full_int_ena: 1; /*The enable bit for rx_fifo_full_int interrupt.*/ + volatile uint32_t tx_fifo_empty_int_ena: 1; /*The enable bit for tx_fifo_empty_int interrupt.*/ + volatile uint32_t rx_fifo_ovf_int_ena: 1; /*The enable bit for rx_fifo_ovf_int interrupt.*/ + volatile uint32_t end_detect_int_ena: 1; /*The enable bit for end_detect_int interrupt.*/ + volatile uint32_t slave_tran_comp_int_ena: 1; /*The enable bit for slave_tran_comp_int interrupt.*/ + volatile uint32_t arbitration_lost_int_ena: 1; /*The enable bit for arbitration_lost_int interrupt.*/ + volatile uint32_t master_tran_comp_int_ena: 1; /*The enable bit for master_tran_comp_int interrupt.*/ + volatile uint32_t trans_complete_int_ena: 1; /*The enable bit for trans_complete_int interrupt.*/ + volatile uint32_t time_out_int_ena: 1; /*The enable bit for time_out_int interrupt.*/ + volatile uint32_t trans_start_int_ena: 1; /*The enable bit for trans_start_int interrupt.*/ + volatile uint32_t ack_err_int_ena: 1; /*The enable bit for ack_err_int interrupt.*/ + volatile uint32_t rx_rec_full_int_ena: 1; /*The enable bit for rx_rec_full_int interrupt.*/ + volatile uint32_t tx_send_empty_int_ena: 1; /*The enable bit for tx_send_empty_int interrupt.*/ + volatile uint32_t reserved13: 19; + }; + volatile uint32_t val; + }int_ena; + union { + struct { + volatile uint32_t rx_fifo_full_int_st: 1; /*The masked interrupt status for rx_fifo_full_int interrupt.*/ + volatile uint32_t tx_fifo_empty_int_st: 1; /*The masked interrupt status for tx_fifo_empty_int interrupt.*/ + volatile uint32_t rx_fifo_ovf_int_st: 1; /*The masked interrupt status for rx_fifo_ovf_int interrupt.*/ + volatile uint32_t end_detect_int_st: 1; /*The masked interrupt status for end_detect_int interrupt.*/ + volatile uint32_t slave_tran_comp_int_st: 1; /*The masked interrupt status for slave_tran_comp_int interrupt.*/ + volatile uint32_t arbitration_lost_int_st: 1; /*The masked interrupt status for arbitration_lost_int interrupt.*/ + volatile uint32_t master_tran_comp_int_st: 1; /*The masked interrupt status for master_tran_comp_int interrupt.*/ + volatile uint32_t trans_complete_int_st: 1; /*The masked interrupt status for trans_complete_int interrupt.*/ + volatile uint32_t time_out_int_st: 1; /*The masked interrupt status for time_out_int interrupt.*/ + volatile uint32_t trans_start_int_st: 1; /*The masked interrupt status for trans_start_int interrupt.*/ + volatile uint32_t ack_err_int_st: 1; /*The masked interrupt status for ack_err_int interrupt.*/ + volatile uint32_t rx_rec_full_int_st: 1; /*The masked interrupt status for rx_rec_full_int interrupt.*/ + volatile uint32_t tx_send_empty_int_st: 1; /*The masked interrupt status for tx_send_empty_int interrupt.*/ + volatile uint32_t reserved13: 19; + }; + volatile uint32_t val; + }int_status; + union { + struct { + volatile uint32_t sda_hold_time:10; /*This register is used to configure the clock num I2C used to hold the data after the negedge of SCL.*/ + volatile uint32_t reserved10: 22; + }; + volatile uint32_t val; + }sda_hold; + union { + struct { + volatile uint32_t sda_sample_time:10; /*This register is used to configure the clock num I2C used to sample data on SDA after the posedge of SCL*/ + volatile uint32_t reserved10: 22; + }; + volatile uint32_t val; + }sda_sample; + union { + struct { + volatile uint32_t scl_high_period:14; /*This register is used to configure the clock num during SCL is low level.*/ + volatile uint32_t reserved14: 18; + }; + volatile uint32_t val; + }scl_high_period; + volatile uint32_t reserved_3c; + union { + struct { + volatile uint32_t scl_start_hold_time:10; /*This register is used to configure the clock num between the negedge of SDA and negedge of SCL for start mark.*/ + volatile uint32_t reserved10: 22; + }; + volatile uint32_t val; + }scl_start_hold; + union { + struct { + volatile uint32_t scl_rstart_setup_time:10; /*This register is used to configure the clock num between the posedge of SCL and the negedge of SDA for restart mark.*/ + volatile uint32_t reserved10: 22; + }; + volatile uint32_t val; + }scl_rstart_setup; + union { + struct { + volatile uint32_t scl_stop_hold_time:14; /*This register is used to configure the clock num after the STOP bit's posedge.*/ + volatile uint32_t reserved14: 18; + }; + volatile uint32_t val; + }scl_stop_hold; + union { + struct { + volatile uint32_t scl_stop_setup_time:10; /*This register is used to configure the clock num between the posedge of SCL and the posedge of SDA.*/ + volatile uint32_t reserved10: 22; + }; + volatile uint32_t val; + }scl_stop_setup; + union { + struct { + volatile uint32_t scl_filter_thres: 3; /*When input SCL's pulse width is smaller than this register value I2C ignores this pulse.*/ + volatile uint32_t scl_filter_en: 1; /*This is the filter enable bit for SCL.*/ + volatile uint32_t reserved4: 28; + }; + volatile uint32_t val; + }scl_filter_cfg; + union { + struct { + volatile uint32_t sda_filter_thres: 3; /*When input SCL's pulse width is smaller than this register value I2C ignores this pulse.*/ + volatile uint32_t sda_filter_en: 1; /*This is the filter enable bit for SDA.*/ + volatile uint32_t reserved4: 28; + }; + volatile uint32_t val; + }sda_filter_cfg; + union { + struct { + volatile uint32_t byte_num: 8; /*Byte_num represent the number of data need to be send or data need to be received.*/ + volatile uint32_t ack_en: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ + volatile uint32_t ack_exp: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ + volatile uint32_t ack_val: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ + volatile uint32_t op_code: 3; /*op_code is the command 0：RSTART 1：WRITE 2：READ 3：STOP . 4:END.*/ + volatile uint32_t reserved14: 17; + volatile uint32_t command_done: 1; /*When command0 is done in I2C Master mode this bit changes to high level.*/ + }; + volatile uint32_t val; + }command[16]; + volatile uint32_t reserved_98; + volatile uint32_t reserved_9c; + volatile uint32_t reserved_a0; + volatile uint32_t reserved_a4; + volatile uint32_t reserved_a8; + volatile uint32_t reserved_ac; + volatile uint32_t reserved_b0; + volatile uint32_t reserved_b4; + volatile uint32_t reserved_b8; + volatile uint32_t reserved_bc; + volatile uint32_t reserved_c0; + volatile uint32_t reserved_c4; + volatile uint32_t reserved_c8; + volatile uint32_t reserved_cc; + volatile uint32_t reserved_d0; + volatile uint32_t reserved_d4; + volatile uint32_t reserved_d8; + volatile uint32_t reserved_dc; + volatile uint32_t reserved_e0; + volatile uint32_t reserved_e4; + volatile uint32_t reserved_e8; + volatile uint32_t reserved_ec; + volatile uint32_t reserved_f0; + volatile uint32_t reserved_f4; + volatile uint32_t date; /**/ + volatile uint32_t reserved_fc; + volatile uint32_t fifo_start_addr; /*This the start address for ram when use apb nonfifo access.*/ +} i2c_dev_t; +extern volatile i2c_dev_t I2C0; +extern volatile i2c_dev_t I2C1; +#endif /* _SOC_I2C_STRUCT_H_ */ diff --git a/components/esp32/include/soc/i2s_struct.h b/components/esp32/include/soc/i2s_struct.h new file mode 100644 index 000000000..beea328a3 --- /dev/null +++ b/components/esp32/include/soc/i2s_struct.h @@ -0,0 +1,461 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_I2S_STRUCT_H_ +#define _SOC_I2S_STRUCT_H_ +typedef struct { + volatile uint32_t reserved_0; + volatile uint32_t reserved_4; + union { + struct { + volatile uint32_t tx_reset: 1; + volatile uint32_t rx_reset: 1; + volatile uint32_t tx_fifo_reset: 1; + volatile uint32_t rx_fifo_reset: 1; + volatile uint32_t tx_start: 1; + volatile uint32_t rx_start: 1; + volatile uint32_t tx_slave_mod: 1; + volatile uint32_t rx_slave_mod: 1; + volatile uint32_t tx_right_first: 1; + volatile uint32_t rx_right_first: 1; + volatile uint32_t tx_msb_shift: 1; + volatile uint32_t rx_msb_shift: 1; + volatile uint32_t tx_short_sync: 1; + volatile uint32_t rx_short_sync: 1; + volatile uint32_t tx_mono: 1; + volatile uint32_t rx_mono: 1; + volatile uint32_t tx_msb_right: 1; + volatile uint32_t rx_msb_right: 1; + volatile uint32_t sig_loopback: 1; + volatile uint32_t reserved19: 13; + }; + volatile uint32_t val; + }conf; + union { + struct { + volatile uint32_t rx_take_data_int_raw: 1; + volatile uint32_t tx_put_data_int_raw: 1; + volatile uint32_t rx_wfull_int_raw: 1; + volatile uint32_t rx_rempty_int_raw: 1; + volatile uint32_t tx_wfull_int_raw: 1; + volatile uint32_t tx_rempty_int_raw: 1; + volatile uint32_t rx_hung_int_raw: 1; + volatile uint32_t tx_hung_int_raw: 1; + volatile uint32_t in_done_int_raw: 1; + volatile uint32_t in_suc_eof_int_raw: 1; + volatile uint32_t in_err_eof_int_raw: 1; + volatile uint32_t out_done_int_raw: 1; + volatile uint32_t out_eof_int_raw: 1; + volatile uint32_t in_dscr_err_int_raw: 1; + volatile uint32_t out_dscr_err_int_raw: 1; + volatile uint32_t in_dscr_empty_int_raw: 1; + volatile uint32_t out_total_eof_int_raw: 1; + volatile uint32_t reserved17: 15; + }; + volatile uint32_t val; + }int_raw; + union { + struct { + volatile uint32_t rx_take_data_int_st: 1; + volatile uint32_t tx_put_data_int_st: 1; + volatile uint32_t rx_wfull_int_st: 1; + volatile uint32_t rx_rempty_int_st: 1; + volatile uint32_t tx_wfull_int_st: 1; + volatile uint32_t tx_rempty_int_st: 1; + volatile uint32_t rx_hung_int_st: 1; + volatile uint32_t tx_hung_int_st: 1; + volatile uint32_t in_done_int_st: 1; + volatile uint32_t in_suc_eof_int_st: 1; + volatile uint32_t in_err_eof_int_st: 1; + volatile uint32_t out_done_int_st: 1; + volatile uint32_t out_eof_int_st: 1; + volatile uint32_t in_dscr_err_int_st: 1; + volatile uint32_t out_dscr_err_int_st: 1; + volatile uint32_t in_dscr_empty_int_st: 1; + volatile uint32_t out_total_eof_int_st: 1; + volatile uint32_t reserved17: 15; + }; + volatile uint32_t val; + }int_st; + union { + struct { + volatile uint32_t rx_take_data_int_ena: 1; + volatile uint32_t tx_put_data_int_ena: 1; + volatile uint32_t rx_wfull_int_ena: 1; + volatile uint32_t rx_rempty_int_ena: 1; + volatile uint32_t tx_wfull_int_ena: 1; + volatile uint32_t tx_rempty_int_ena: 1; + volatile uint32_t rx_hung_int_ena: 1; + volatile uint32_t tx_hung_int_ena: 1; + volatile uint32_t in_done_int_ena: 1; + volatile uint32_t in_suc_eof_int_ena: 1; + volatile uint32_t in_err_eof_int_ena: 1; + volatile uint32_t out_done_int_ena: 1; + volatile uint32_t out_eof_int_ena: 1; + volatile uint32_t in_dscr_err_int_ena: 1; + volatile uint32_t out_dscr_err_int_ena: 1; + volatile uint32_t in_dscr_empty_int_ena: 1; + volatile uint32_t out_total_eof_int_ena: 1; + volatile uint32_t reserved17: 15; + }; + volatile uint32_t val; + }int_ena; + union { + struct { + volatile uint32_t take_data_int_clr: 1; + volatile uint32_t put_data_int_clr: 1; + volatile uint32_t rx_wfull_int_clr: 1; + volatile uint32_t rx_rempty_int_clr: 1; + volatile uint32_t tx_wfull_int_clr: 1; + volatile uint32_t tx_rempty_int_clr: 1; + volatile uint32_t rx_hung_int_clr: 1; + volatile uint32_t tx_hung_int_clr: 1; + volatile uint32_t in_done_int_clr: 1; + volatile uint32_t in_suc_eof_int_clr: 1; + volatile uint32_t in_err_eof_int_clr: 1; + volatile uint32_t out_done_int_clr: 1; + volatile uint32_t out_eof_int_clr: 1; + volatile uint32_t in_dscr_err_int_clr: 1; + volatile uint32_t out_dscr_err_int_clr: 1; + volatile uint32_t in_dscr_empty_int_clr: 1; + volatile uint32_t out_total_eof_int_clr: 1; + volatile uint32_t reserved17: 15; + }; + volatile uint32_t val; + }int_clr; + union { + struct { + volatile uint32_t tx_bck_in_delay: 2; + volatile uint32_t tx_ws_in_delay: 2; + volatile uint32_t rx_bck_in_delay: 2; + volatile uint32_t rx_ws_in_delay: 2; + volatile uint32_t rx_sd_in_delay: 2; + volatile uint32_t tx_bck_out_delay: 2; + volatile uint32_t tx_ws_out_delay: 2; + volatile uint32_t tx_sd_out_delay: 2; + volatile uint32_t rx_ws_out_delay: 2; + volatile uint32_t rx_bck_out_delay: 2; + volatile uint32_t tx_dsync_sw: 1; + volatile uint32_t rx_dsync_sw: 1; + volatile uint32_t data_enable_delay: 2; + volatile uint32_t tx_bck_in_inv: 1; + volatile uint32_t reserved25: 7; + }; + volatile uint32_t val; + }timing; + union { + struct { + volatile uint32_t rx_data_num: 6; + volatile uint32_t tx_data_num: 6; + volatile uint32_t dscr_en: 1; + volatile uint32_t tx_fifo_mod: 3; + volatile uint32_t rx_fifo_mod: 3; + volatile uint32_t tx_fifo_mod_force_en: 1; + volatile uint32_t rx_fifo_mod_force_en: 1; + volatile uint32_t reserved21: 11; + }; + volatile uint32_t val; + }fifo_conf; + volatile uint32_t rx_eof_num; + volatile uint32_t conf_single_data; + union { + struct { + volatile uint32_t tx_chan_mod: 3; + volatile uint32_t rx_chan_mod: 2; + volatile uint32_t reserved5: 27; + }; + volatile uint32_t val; + }conf_chan; + union { + struct { + volatile uint32_t outlink_addr: 20; + volatile uint32_t reserved20: 8; + volatile uint32_t outlink_stop: 1; + volatile uint32_t outlink_start: 1; + volatile uint32_t outlink_restart: 1; + volatile uint32_t outlink_park: 1; + }; + volatile uint32_t val; + }out_link; + union { + struct { + volatile uint32_t inlink_addr: 20; + volatile uint32_t reserved20: 8; + volatile uint32_t inlink_stop: 1; + volatile uint32_t inlink_start: 1; + volatile uint32_t inlink_restart: 1; + volatile uint32_t inlink_park: 1; + }; + volatile uint32_t val; + }in_link; + volatile uint32_t out_eof_des_addr; + volatile uint32_t in_eof_des_addr; + volatile uint32_t out_eof_bfr_des_addr; + union { + struct { + volatile uint32_t ahb_testmode: 3; + volatile uint32_t reserved3: 1; + volatile uint32_t ahb_testaddr: 2; + volatile uint32_t reserved6: 26; + }; + volatile uint32_t val; + }ahb_test; + volatile uint32_t in_link_dscr; + volatile uint32_t in_link_dscr_bf0; + volatile uint32_t in_link_dscr_bf1; + volatile uint32_t out_link_dscr; + volatile uint32_t out_link_dscr_bf0; + volatile uint32_t out_link_dscr_bf1; + union { + struct { + volatile uint32_t in_rst: 1; + volatile uint32_t out_rst: 1; + volatile uint32_t ahbm_fifo_rst: 1; + volatile uint32_t ahbm_rst: 1; + volatile uint32_t out_loop_test: 1; + volatile uint32_t in_loop_test: 1; + volatile uint32_t out_auto_wrback: 1; + volatile uint32_t out_no_restart_clr: 1; + volatile uint32_t out_eof_mode: 1; + volatile uint32_t outdscr_burst_en: 1; + volatile uint32_t indscr_burst_en: 1; + volatile uint32_t out_data_burst_en: 1; + volatile uint32_t check_owner: 1; + volatile uint32_t mem_trans_en: 1; + volatile uint32_t reserved14: 18; + }; + volatile uint32_t val; + }lc_conf; + union { + struct { + volatile uint32_t out_fifo_wdata: 9; + volatile uint32_t reserved9: 7; + volatile uint32_t out_fifo_push: 1; + volatile uint32_t reserved17: 15; + }; + volatile uint32_t val; + }out_fifo_push; + union { + struct { + volatile uint32_t in_fifo_rdata:12; + volatile uint32_t reserved12: 4; + volatile uint32_t in_fifo_pop: 1; + volatile uint32_t reserved17: 15; + }; + volatile uint32_t val; + }in_fifo_pop; + volatile uint32_t lc_state0; + volatile uint32_t lc_state1; + union { + struct { + volatile uint32_t lc_fifo_timeout: 8; + volatile uint32_t lc_fifo_timeout_shift: 3; + volatile uint32_t lc_fifo_timeout_ena: 1; + volatile uint32_t reserved12: 20; + }; + volatile uint32_t val; + }lc_hung_conf; + volatile uint32_t reserved_78; + volatile uint32_t reserved_7c; + union { + struct { + volatile uint32_t cvsd_y_max:16; + volatile uint32_t cvsd_y_min:16; + }; + volatile uint32_t val; + }cvsd_conf0; + union { + struct { + volatile uint32_t cvsd_sigma_max:16; + volatile uint32_t cvsd_sigma_min:16; + }; + volatile uint32_t val; + }cvsd_conf1; + union { + struct { + volatile uint32_t cvsd_k: 3; + volatile uint32_t cvsd_j: 3; + volatile uint32_t cvsd_beta: 10; + volatile uint32_t cvsd_h: 3; + volatile uint32_t reserved19:13; + }; + volatile uint32_t val; + }cvsd_conf2; + union { + struct { + volatile uint32_t good_pack_max: 6; + volatile uint32_t n_err_seg: 3; + volatile uint32_t shift_rate: 3; + volatile uint32_t max_slide_sample: 8; + volatile uint32_t pack_len_8k: 5; + volatile uint32_t n_min_err: 3; + volatile uint32_t reserved28: 4; + }; + volatile uint32_t val; + }plc_conf0; + union { + struct { + volatile uint32_t bad_cef_atten_para: 8; + volatile uint32_t bad_cef_atten_para_shift: 4; + volatile uint32_t bad_ola_win2_para_shift: 4; + volatile uint32_t bad_ola_win2_para: 8; + volatile uint32_t slide_win_len: 8; + }; + volatile uint32_t val; + }plc_conf1; + union { + struct { + volatile uint32_t cvsd_seg_mod: 2; + volatile uint32_t min_period: 5; + volatile uint32_t reserved7: 25; + }; + volatile uint32_t val; + }plc_conf2; + union { + struct { + volatile uint32_t esco_en: 1; + volatile uint32_t esco_chan_mod: 1; + volatile uint32_t esco_cvsd_dec_pack_err: 1; + volatile uint32_t esco_cvsd_pack_len_8k: 5; + volatile uint32_t esco_cvsd_inf_en: 1; + volatile uint32_t cvsd_dec_start: 1; + volatile uint32_t cvsd_dec_reset: 1; + volatile uint32_t plc_en: 1; + volatile uint32_t plc2dma_en: 1; + volatile uint32_t reserved13: 19; + }; + volatile uint32_t val; + }esco_conf0; + union { + struct { + volatile uint32_t sco_with_en: 1; + volatile uint32_t sco_no_en: 1; + volatile uint32_t cvsd_enc_start: 1; + volatile uint32_t cvsd_enc_reset: 1; + volatile uint32_t reserved4: 28; + }; + volatile uint32_t val; + }sco_conf0; + union { + struct { + volatile uint32_t tx_pcm_conf: 3; + volatile uint32_t tx_pcm_bypass: 1; + volatile uint32_t rx_pcm_conf: 3; + volatile uint32_t rx_pcm_bypass: 1; + volatile uint32_t tx_stop_en: 1; + volatile uint32_t tx_zeros_rm_en: 1; + volatile uint32_t reserved10: 22; + }; + volatile uint32_t val; + }conf1; + union { + struct { + volatile uint32_t fifo_force_pd: 1; + volatile uint32_t fifo_force_pu: 1; + volatile uint32_t plc_mem_force_pd: 1; + volatile uint32_t plc_mem_force_pu: 1; + volatile uint32_t reserved4: 28; + }; + volatile uint32_t val; + }pd_conf; + union { + struct { + volatile uint32_t camera_en: 1; + volatile uint32_t lcd_tx_wrx2_en: 1; + volatile uint32_t lcd_tx_sdx2_en: 1; + volatile uint32_t data_enable_test_en: 1; + volatile uint32_t data_enable: 1; + volatile uint32_t lcd_en: 1; + volatile uint32_t ext_adc_start_en: 1; + volatile uint32_t inter_valid_en: 1; + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }conf2; + union { + struct { + volatile uint32_t clkm_div_num: 8; + volatile uint32_t clkm_div_b: 6; + volatile uint32_t clkm_div_a: 6; + volatile uint32_t clk_en: 1; + volatile uint32_t clka_ena: 1; + volatile uint32_t reserved22: 10; + }; + volatile uint32_t val; + }clkm_conf; + union { + struct { + volatile uint32_t tx_bck_div_num: 6; + volatile uint32_t rx_bck_div_num: 6; + volatile uint32_t tx_bits_mod: 6; + volatile uint32_t rx_bits_mod: 6; + volatile uint32_t reserved24: 8; + }; + volatile uint32_t val; + }sample_rate_conf; + union { + struct { + volatile uint32_t tx_pdm_en: 1; + volatile uint32_t rx_pdm_en: 1; + volatile uint32_t pcm2pdm_conv_en: 1; + volatile uint32_t pdm2pcm_conv_en: 1; + volatile uint32_t tx_pdm_sinc_osr2: 4; + volatile uint32_t tx_pdm_prescale: 8; + volatile uint32_t tx_pdm_hp_in_shift: 2; + volatile uint32_t tx_pdm_lp_in_shift: 2; + volatile uint32_t tx_pdm_sinc_in_shift: 2; + volatile uint32_t tx_pdm_sigmadelta_in_shift: 2; + volatile uint32_t rx_pdm_sinc_dsr_16_en: 1; + volatile uint32_t tx_pdm_hp_bypass: 1; + volatile uint32_t reserved26: 6; + }; + volatile uint32_t val; + }pdm_conf; + union { + struct { + volatile uint32_t tx_pdm_fs: 10; + volatile uint32_t tx_pdm_fp: 10; + volatile uint32_t reserved20:12; + }; + volatile uint32_t val; + }pdm_freq_conf; + union { + struct { + volatile uint32_t tx_idle: 1; + volatile uint32_t tx_fifo_reset_back: 1; + volatile uint32_t rx_fifo_reset_back: 1; + volatile uint32_t reserved3: 29; + }; + volatile uint32_t val; + }state; + volatile uint32_t reserved_c0; + volatile uint32_t reserved_c4; + volatile uint32_t reserved_c8; + volatile uint32_t reserved_cc; + volatile uint32_t reserved_d0; + volatile uint32_t reserved_d4; + volatile uint32_t reserved_d8; + volatile uint32_t reserved_dc; + volatile uint32_t reserved_e0; + volatile uint32_t reserved_e4; + volatile uint32_t reserved_e8; + volatile uint32_t reserved_ec; + volatile uint32_t reserved_f0; + volatile uint32_t reserved_f4; + volatile uint32_t reserved_f8; + volatile uint32_t date; /**/ +} i2s_dev_t; +extern volatile i2s_dev_t I2S0; +extern volatile i2s_dev_t I2S1; + +#endif /* _SOC_I2S_STRUCT_H_ */ diff --git a/components/esp32/include/soc/ledc_struct.h b/components/esp32/include/soc/ledc_struct.h new file mode 100644 index 000000000..302a9e4bc --- /dev/null +++ b/components/esp32/include/soc/ledc_struct.h @@ -0,0 +1,300 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_LEDC_STRUCT_H_ +#define _SOC_LEDC_STRUCT_H_ +typedef struct { + struct{ + union { + struct { + volatile uint32_t timer_sel: 2; /*There are four high speed timers the two bits are used to select one of them for high speed channel. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ + volatile uint32_t sig_out_en: 1; /*This is the output enable control bit for high speed channel*/ + volatile uint32_t idle_lv: 1; /*This bit is used to control the output value when high speed channel is off.*/ + volatile uint32_t reserved4: 27; + volatile uint32_t clk_en: 1; /*This bit is clock gating control signal. when software configure LED_PWM internal registers it controls the register clock.*/ + }; + volatile uint32_t val; + }conf0; + union { + struct { + volatile uint32_t hpoint: 20; /*The output value changes to high when htimerx(x=[0 3]) selected by high speed channel has reached reg_hpoint_hsch0[19:0]*/ + volatile uint32_t reserved20: 12; + }; + volatile uint32_t val; + }hpoint; + union { + struct { + volatile uint32_t duty: 25; /*The register is used to control output duty. When hstimerx(x=[0 3]) chosen by high speed channel has reached reg_lpoint_hsch0 the output signal changes to low. reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4]) (1) reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ + volatile uint32_t reserved25: 7; + }; + volatile uint32_t val; + }duty; + union { + struct { + volatile uint32_t duty_scale:10; /*This register controls the increase or decrease step scale for high speed channel.*/ + volatile uint32_t duty_cycle:10; /*This register is used to increase or decrease the duty every reg_duty_cycle_hsch0 cycles for high speed channel.*/ + volatile uint32_t duty_num: 10; /*This register is used to control the number of increased or decreased times for high speed channel.*/ + volatile uint32_t duty_inc: 1; /*This register is used to increase the duty of output signal or decrease the duty of output signal for high speed channel.*/ + volatile uint32_t duty_start: 1; /*When reg_duty_num_hsch0 reg_duty_cycle_hsch0 and reg_duty_scale_hsch0 has been configured. these register won't take effect until set reg_duty_start_hsch0. this bit is automatically cleared by hardware.*/ + }; + volatile uint32_t val; + }conf1; + union { + struct { + volatile uint32_t duty_read: 25; /*This register represents the current duty of the output signal for high speed channel.*/ + volatile uint32_t reserved25: 7; + }; + volatile uint32_t val; + }duty_rd; + }high_speed_channel[8]; + struct{ + union { + struct { + volatile uint32_t timer_sel: 2; /*There are four low speed timers the two bits are used to select one of them for low speed channel. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ + volatile uint32_t sig_out_en: 1; /*This is the output enable control bit for low speed channel.*/ + volatile uint32_t idle_lv: 1; /*This bit is used to control the output value when low speed channel is off.*/ + volatile uint32_t para_up: 1; /*This bit is used to update register LEDC_LSCH0_HPOINT and LEDC_LSCH0_DUTY for low speed channel.*/ + volatile uint32_t reserved5: 27; + }; + volatile uint32_t val; + }conf0; + union { + struct { + volatile uint32_t hpoint: 20; /*The output value changes to high when lstimerx(x=[0 3]) selected by low speed channel has reached reg_hpoint_lsch0[19:0]*/ + volatile uint32_t reserved20: 12; + }; + volatile uint32_t val; + }hpoint; + union { + struct { + volatile uint32_t duty: 25; /*The register is used to control output duty. When lstimerx(x=[0 3]) choosed by low speed channel has reached reg_lpoint_lsch0 the output signal changes to low. reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4]) (1) reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ + volatile uint32_t reserved25: 7; + }; + volatile uint32_t val; + }duty; + union { + struct { + volatile uint32_t duty_scale:10; /*This register controls the increase or decrease step scale for low speed channel.*/ + volatile uint32_t duty_cycle:10; /*This register is used to increase or decrease the duty every reg_duty_cycle_lsch0 cycles for low speed channel.*/ + volatile uint32_t duty_num: 10; /*This register is used to control the num of increased or decreased times for low speed channel6.*/ + volatile uint32_t duty_inc: 1; /*This register is used to increase the duty of output signal or decrease the duty of output signal for low speed channel6.*/ + volatile uint32_t duty_start: 1; /*When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ + }; + volatile uint32_t val; + }conf1; + union { + struct { + volatile uint32_t duty_read: 25; /*This register represents the current duty of the output signal for low speed channel.*/ + volatile uint32_t reserved25: 7; + }; + volatile uint32_t val; + }duty_r; + }low_speed_channel[8]; + struct{ + union { + struct { + volatile uint32_t timer_lim: 5; /*This register controls the range of the counter in high speed timer. the counter range is [0 2**reg_hstimer0_lim] the max bit width for counter is 20.*/ + volatile uint32_t div_num: 18; /*This register is used to configure parameter for divider in high speed timer the least significant eight bits represent the decimal part.*/ + volatile uint32_t pause: 1; /*This bit is used to pause the counter in high speed timer*/ + volatile uint32_t rst: 1; /*This bit is used to reset high speed timer the counter will be 0 after reset.*/ + volatile uint32_t tick_sel: 1; /*This bit is used to choose apb_clk or ref_tick for high speed timer. 1'b1:apb_clk 0:ref_tick*/ + volatile uint32_t reserved26: 6; + }; + volatile uint32_t val; + }conf; + union { + struct { + volatile uint32_t timer_cnt: 20; /*software can read this register to get the current counter value in high speed timer*/ + volatile uint32_t reserved20: 12; + }; + volatile uint32_t val; + }value; + }high_speed_timer[4]; + struct{ + union { + struct { + volatile uint32_t timer_lim: 5; /*This register controls the range of the counter in low speed timer. the counter range is [0 2**reg_lstimer0_lim] the max bit width for counter is 20.*/ + volatile uint32_t div_num: 18; /*This register is used to configure parameter for divider in low speed timer the least significant eight bits represent the decimal part.*/ + volatile uint32_t pause: 1; /*This bit is used to pause the counter in low speed timer.*/ + volatile uint32_t rst: 1; /*This bit is used to reset low speed timer the counter will be 0 after reset.*/ + volatile uint32_t tick_sel: 1; /*This bit is used to choose slow_clk or ref_tick for low speed timer. 1'b1:slow_clk 0:ref_tick*/ + volatile uint32_t param_update: 1; /*Set this bit to update reg_div_num_lstime0 and reg_lstimer0_lim.*/ + volatile uint32_t reserved27: 5; + }; + volatile uint32_t val; + }conf; + union { + struct { + volatile uint32_t timer_cnt: 20; /*software can read this register to get the current counter value in low speed timer.*/ + volatile uint32_t reserved20: 12; + }; + volatile uint32_t val; + }value; + }low_speed_timer[4]; + union { + struct { + volatile uint32_t hstimer0_ovf_int_raw: 1; /*The interrupt raw bit for high speed channel0 counter overflow.*/ + volatile uint32_t hstimer1_ovf_int_raw: 1; /*The interrupt raw bit for high speed channel1 counter overflow.*/ + volatile uint32_t hstimer2_ovf_int_raw: 1; /*The interrupt raw bit for high speed channel2 counter overflow.*/ + volatile uint32_t hstimer3_ovf_int_raw: 1; /*The interrupt raw bit for high speed channel3 counter overflow.*/ + volatile uint32_t lstimer0_ovf_int_raw: 1; /*The interrupt raw bit for low speed channel0 counter overflow.*/ + volatile uint32_t lstimer1_ovf_int_raw: 1; /*The interrupt raw bit for low speed channel1 counter overflow.*/ + volatile uint32_t lstimer2_ovf_int_raw: 1; /*The interrupt raw bit for low speed channel2 counter overflow.*/ + volatile uint32_t lstimer3_ovf_int_raw: 1; /*The interrupt raw bit for low speed channel3 counter overflow.*/ + volatile uint32_t duty_chng_end_hsch0_int_raw: 1; /*The interrupt raw bit for high speed channel 0 duty change done.*/ + volatile uint32_t duty_chng_end_hsch1_int_raw: 1; /*The interrupt raw bit for high speed channel 1 duty change done.*/ + volatile uint32_t duty_chng_end_hsch2_int_raw: 1; /*The interrupt raw bit for high speed channel 2 duty change done.*/ + volatile uint32_t duty_chng_end_hsch3_int_raw: 1; /*The interrupt raw bit for high speed channel 3 duty change done.*/ + volatile uint32_t duty_chng_end_hsch4_int_raw: 1; /*The interrupt raw bit for high speed channel 4 duty change done.*/ + volatile uint32_t duty_chng_end_hsch5_int_raw: 1; /*The interrupt raw bit for high speed channel 5 duty change done.*/ + volatile uint32_t duty_chng_end_hsch6_int_raw: 1; /*The interrupt raw bit for high speed channel 6 duty change done.*/ + volatile uint32_t duty_chng_end_hsch7_int_raw: 1; /*The interrupt raw bit for high speed channel 7 duty change done.*/ + volatile uint32_t duty_chng_end_lsch0_int_raw: 1; /*The interrupt raw bit for low speed channel 0 duty change done.*/ + volatile uint32_t duty_chng_end_lsch1_int_raw: 1; /*The interrupt raw bit for low speed channel 1 duty change done.*/ + volatile uint32_t duty_chng_end_lsch2_int_raw: 1; /*The interrupt raw bit for low speed channel 2 duty change done.*/ + volatile uint32_t duty_chng_end_lsch3_int_raw: 1; /*The interrupt raw bit for low speed channel 3 duty change done.*/ + volatile uint32_t duty_chng_end_lsch4_int_raw: 1; /*The interrupt raw bit for low speed channel 4 duty change done.*/ + volatile uint32_t duty_chng_end_lsch5_int_raw: 1; /*The interrupt raw bit for low speed channel 5 duty change done.*/ + volatile uint32_t duty_chng_end_lsch6_int_raw: 1; /*The interrupt raw bit for low speed channel 6 duty change done.*/ + volatile uint32_t duty_chng_end_lsch7_int_raw: 1; /*The interrupt raw bit for low speed channel 7 duty change done.*/ + volatile uint32_t reserved24: 8; + }; + volatile uint32_t val; + }int_raw; + union { + struct { + volatile uint32_t hstimer0_ovf_int_st: 1; /*The interrupt status bit for high speed channel0 counter overflow event.*/ + volatile uint32_t hstimer1_ovf_int_st: 1; /*The interrupt status bit for high speed channel1 counter overflow event.*/ + volatile uint32_t hstimer2_ovf_int_st: 1; /*The interrupt status bit for high speed channel2 counter overflow event.*/ + volatile uint32_t hstimer3_ovf_int_st: 1; /*The interrupt status bit for high speed channel3 counter overflow event.*/ + volatile uint32_t lstimer0_ovf_int_st: 1; /*The interrupt status bit for low speed channel0 counter overflow event.*/ + volatile uint32_t lstimer1_ovf_int_st: 1; /*The interrupt status bit for low speed channel1 counter overflow event.*/ + volatile uint32_t lstimer2_ovf_int_st: 1; /*The interrupt status bit for low speed channel2 counter overflow event.*/ + volatile uint32_t lstimer3_ovf_int_st: 1; /*The interrupt status bit for low speed channel3 counter overflow event.*/ + volatile uint32_t duty_chng_end_hsch0_int_st: 1; /*The interrupt status bit for high speed channel 0 duty change done event.*/ + volatile uint32_t duty_chng_end_hsch1_int_st: 1; /*The interrupt status bit for high speed channel 1 duty change done event.*/ + volatile uint32_t duty_chng_end_hsch2_int_st: 1; /*The interrupt status bit for high speed channel 2 duty change done event.*/ + volatile uint32_t duty_chng_end_hsch3_int_st: 1; /*The interrupt status bit for high speed channel 3 duty change done event.*/ + volatile uint32_t duty_chng_end_hsch4_int_st: 1; /*The interrupt status bit for high speed channel 4 duty change done event.*/ + volatile uint32_t duty_chng_end_hsch5_int_st: 1; /*The interrupt status bit for high speed channel 5 duty change done event.*/ + volatile uint32_t duty_chng_end_hsch6_int_st: 1; /*The interrupt status bit for high speed channel 6 duty change done event.*/ + volatile uint32_t duty_chng_end_hsch7_int_st: 1; /*The interrupt status bit for high speed channel 7 duty change done event.*/ + volatile uint32_t duty_chng_end_lsch0_int_st: 1; /*The interrupt status bit for low speed channel 0 duty change done event.*/ + volatile uint32_t duty_chng_end_lsch1_int_st: 1; /*The interrupt status bit for low speed channel 1 duty change done event.*/ + volatile uint32_t duty_chng_end_lsch2_int_st: 1; /*The interrupt status bit for low speed channel 2 duty change done event.*/ + volatile uint32_t duty_chng_end_lsch3_int_st: 1; /*The interrupt status bit for low speed channel 3 duty change done event.*/ + volatile uint32_t duty_chng_end_lsch4_int_st: 1; /*The interrupt status bit for low speed channel 4 duty change done event.*/ + volatile uint32_t duty_chng_end_lsch5_int_st: 1; /*The interrupt status bit for low speed channel 5 duty change done event.*/ + volatile uint32_t duty_chng_end_lsch6_int_st: 1; /*The interrupt status bit for low speed channel 6 duty change done event.*/ + volatile uint32_t duty_chng_end_lsch7_int_st: 1; /*The interrupt status bit for low speed channel 7 duty change done event*/ + volatile uint32_t reserved24: 8; + }; + volatile uint32_t val; + }int_st; + union { + struct { + volatile uint32_t hstimer0_ovf_int_ena: 1; /*The interrupt enable bit for high speed channel0 counter overflow interrupt.*/ + volatile uint32_t hstimer1_ovf_int_ena: 1; /*The interrupt enable bit for high speed channel1 counter overflow interrupt.*/ + volatile uint32_t hstimer2_ovf_int_ena: 1; /*The interrupt enable bit for high speed channel2 counter overflow interrupt.*/ + volatile uint32_t hstimer3_ovf_int_ena: 1; /*The interrupt enable bit for high speed channel3 counter overflow interrupt.*/ + volatile uint32_t lstimer0_ovf_int_ena: 1; /*The interrupt enable bit for low speed channel0 counter overflow interrupt.*/ + volatile uint32_t lstimer1_ovf_int_ena: 1; /*The interrupt enable bit for low speed channel1 counter overflow interrupt.*/ + volatile uint32_t lstimer2_ovf_int_ena: 1; /*The interrupt enable bit for low speed channel2 counter overflow interrupt.*/ + volatile uint32_t lstimer3_ovf_int_ena: 1; /*The interrupt enable bit for low speed channel3 counter overflow interrupt.*/ + volatile uint32_t duty_chng_end_hsch0_int_ena: 1; /*The interrupt enable bit for high speed channel 0 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_hsch1_int_ena: 1; /*The interrupt enable bit for high speed channel 1 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_hsch2_int_ena: 1; /*The interrupt enable bit for high speed channel 2 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_hsch3_int_ena: 1; /*The interrupt enable bit for high speed channel 3 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_hsch4_int_ena: 1; /*The interrupt enable bit for high speed channel 4 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_hsch5_int_ena: 1; /*The interrupt enable bit for high speed channel 5 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_hsch6_int_ena: 1; /*The interrupt enable bit for high speed channel 6 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_hsch7_int_ena: 1; /*The interrupt enable bit for high speed channel 7 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_lsch0_int_ena: 1; /*The interrupt enable bit for low speed channel 0 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_lsch1_int_ena: 1; /*The interrupt enable bit for low speed channel 1 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_lsch2_int_ena: 1; /*The interrupt enable bit for low speed channel 2 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_lsch3_int_ena: 1; /*The interrupt enable bit for low speed channel 3 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_lsch4_int_ena: 1; /*The interrupt enable bit for low speed channel 4 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_lsch5_int_ena: 1; /*The interrupt enable bit for low speed channel 5 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_lsch6_int_ena: 1; /*The interrupt enable bit for low speed channel 6 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_lsch7_int_ena: 1; /*The interrupt enable bit for low speed channel 7 duty change done interrupt.*/ + volatile uint32_t reserved24: 8; + }; + volatile uint32_t val; + }int_ena; + union { + struct { + volatile uint32_t hstimer0_ovf_int_clr: 1; /*Set this bit to clear high speed channel0 counter overflow interrupt.*/ + volatile uint32_t hstimer1_ovf_int_clr: 1; /*Set this bit to clear high speed channel1 counter overflow interrupt.*/ + volatile uint32_t hstimer2_ovf_int_clr: 1; /*Set this bit to clear high speed channel2 counter overflow interrupt.*/ + volatile uint32_t hstimer3_ovf_int_clr: 1; /*Set this bit to clear high speed channel3 counter overflow interrupt.*/ + volatile uint32_t lstimer0_ovf_int_clr: 1; /*Set this bit to clear low speed channel0 counter overflow interrupt.*/ + volatile uint32_t lstimer1_ovf_int_clr: 1; /*Set this bit to clear low speed channel1 counter overflow interrupt.*/ + volatile uint32_t lstimer2_ovf_int_clr: 1; /*Set this bit to clear low speed channel2 counter overflow interrupt.*/ + volatile uint32_t lstimer3_ovf_int_clr: 1; /*Set this bit to clear low speed channel3 counter overflow interrupt.*/ + volatile uint32_t duty_chng_end_hsch0_int_clr: 1; /*Set this bit to clear high speed channel 0 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_hsch1_int_clr: 1; /*Set this bit to clear high speed channel 1 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_hsch2_int_clr: 1; /*Set this bit to clear high speed channel 2 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_hsch3_int_clr: 1; /*Set this bit to clear high speed channel 3 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_hsch4_int_clr: 1; /*Set this bit to clear high speed channel 4 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_hsch5_int_clr: 1; /*Set this bit to clear high speed channel 5 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_hsch6_int_clr: 1; /*Set this bit to clear high speed channel 6 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_hsch7_int_clr: 1; /*Set this bit to clear high speed channel 7 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_lsch0_int_clr: 1; /*Set this bit to clear low speed channel 0 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_lsch1_int_clr: 1; /*Set this bit to clear low speed channel 1 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_lsch2_int_clr: 1; /*Set this bit to clear low speed channel 2 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_lsch3_int_clr: 1; /*Set this bit to clear low speed channel 3 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_lsch4_int_clr: 1; /*Set this bit to clear low speed channel 4 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_lsch5_int_clr: 1; /*Set this bit to clear low speed channel 5 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_lsch6_int_clr: 1; /*Set this bit to clear low speed channel 6 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_lsch7_int_clr: 1; /*Set this bit to clear low speed channel 7 duty change done interrupt.*/ + volatile uint32_t reserved24: 8; + }; + volatile uint32_t val; + }int_clr; + union { + struct { + volatile uint32_t apb_clk_sel: 1; /*This bit is used to set the frequency of slow_clk. 1'b1:80mhz 1'b0:8mhz*/ + volatile uint32_t reserved1: 31; + }; + volatile uint32_t val; + }conf; + volatile uint32_t reserved_194; + volatile uint32_t reserved_198; + volatile uint32_t reserved_19c; + volatile uint32_t reserved_1a0; + volatile uint32_t reserved_1a4; + volatile uint32_t reserved_1a8; + volatile uint32_t reserved_1ac; + volatile uint32_t reserved_1b0; + volatile uint32_t reserved_1b4; + volatile uint32_t reserved_1b8; + volatile uint32_t reserved_1bc; + volatile uint32_t reserved_1c0; + volatile uint32_t reserved_1c4; + volatile uint32_t reserved_1c8; + volatile uint32_t reserved_1cc; + volatile uint32_t reserved_1d0; + volatile uint32_t reserved_1d4; + volatile uint32_t reserved_1d8; + volatile uint32_t reserved_1dc; + volatile uint32_t reserved_1e0; + volatile uint32_t reserved_1e4; + volatile uint32_t reserved_1e8; + volatile uint32_t reserved_1ec; + volatile uint32_t reserved_1f0; + volatile uint32_t reserved_1f4; + volatile uint32_t reserved_1f8; + volatile uint32_t date; /*This register represents the version .*/ +} ledc_dev_t; +extern volatile ledc_dev_t LEDC; +#endif /* _SOC_LEDC_STRUCT_H_ */ diff --git a/components/esp32/include/soc/pcnt_struct.h b/components/esp32/include/soc/pcnt_struct.h new file mode 100644 index 000000000..bf9679399 --- /dev/null +++ b/components/esp32/include/soc/pcnt_struct.h @@ -0,0 +1,161 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_PCNT_STRUCT_H_ +#define _SOC_PCNT_STRUCT_H_ +typedef struct { + struct{ + union { + struct { + volatile uint32_t filter_thres: 10; /*This register is used to filter pulse whose width is smaller than this value for unit0.*/ + volatile uint32_t filter_en: 1; /*This is the enable bit for filtering input signals for unit0.*/ + volatile uint32_t thr_zero_en: 1; /*This is the enable bit for comparing unit0's count with 0 value.*/ + volatile uint32_t thr_h_lim_en: 1; /*This is the enable bit for comparing unit0's count with thr_h_lim value.*/ + volatile uint32_t thr_l_lim_en: 1; /*This is the enable bit for comparing unit0's count with thr_l_lim value.*/ + volatile uint32_t thr_thres0_en: 1; /*This is the enable bit for comparing unit0's count with thres0 value.*/ + volatile uint32_t thr_thres1_en: 1; /*This is the enable bit for comparing unit0's count with thres1 value .*/ + volatile uint32_t ch0_neg_mode: 2; /*This register is used to control the mode of channel0's input neg-edge signal for unit0. 2'd1：increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ + volatile uint32_t ch0_pos_mode: 2; /*This register is used to control the mode of channel0's input pos-edge signal for unit0. 2'd1：increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ + volatile uint32_t ch0_hctrl_mode: 2; /*This register is used to control the mode of channel0's high control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/ + volatile uint32_t ch0_lctrl_mode: 2; /*This register is used to control the mode of channel0's low control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/ + volatile uint32_t ch1_neg_mode: 2; /*This register is used to control the mode of channel1's input neg-edge signal for unit0. 2'd1：increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ + volatile uint32_t ch1_pos_mode: 2; /*This register is used to control the mode of channel1's input pos-edge signal for unit0. 2'd1：increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ + volatile uint32_t ch1_hctrl_mode: 2; /*This register is used to control the mode of channel1's high control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/ + volatile uint32_t ch1_lctrl_mode: 2; /*This register is used to control the mode of channel1's low control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/ + }; + volatile uint32_t val; + }conf0; + union { + struct { + volatile uint32_t cnt_thres0:16; /*This register is used to configure thres0 value for unit0.*/ + volatile uint32_t cnt_thres1:16; /*This register is used to configure thres1 value for unit0.*/ + }; + volatile uint32_t val; + }conf1; + union { + struct { + volatile uint32_t cnt_h_lim:16; /*This register is used to configure thr_h_lim value for unit0.*/ + volatile uint32_t cnt_l_lim:16; /*This register is used to configure thr_l_lim value for unit0.*/ + }; + volatile uint32_t val; + }conf2; + }conf_unit[8]; + union { + struct { + volatile uint32_t cnt_val : 16; /*This register stores the current pulse count value for unit0.*/ + volatile uint32_t reserved16: 16; + }; + volatile uint32_t val; + }cnt_unit[8]; + union { + struct { + volatile uint32_t cnt_thr_event_u0_int_raw: 1; /*This is the interrupt raw bit for channel0 event.*/ + volatile uint32_t cnt_thr_event_u1_int_raw: 1; /*This is the interrupt raw bit for channel1 event.*/ + volatile uint32_t cnt_thr_event_u2_int_raw: 1; /*This is the interrupt raw bit for channel2 event.*/ + volatile uint32_t cnt_thr_event_u3_int_raw: 1; /*This is the interrupt raw bit for channel3 event.*/ + volatile uint32_t cnt_thr_event_u4_int_raw: 1; /*This is the interrupt raw bit for channel4 event.*/ + volatile uint32_t cnt_thr_event_u5_int_raw: 1; /*This is the interrupt raw bit for channel5 event.*/ + volatile uint32_t cnt_thr_event_u6_int_raw: 1; /*This is the interrupt raw bit for channel6 event.*/ + volatile uint32_t cnt_thr_event_u7_int_raw: 1; /*This is the interrupt raw bit for channel7 event.*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }int_raw; + union { + struct { + volatile uint32_t cnt_thr_event_u0_int_st: 1; /*This is the interrupt status bit for channel0 event.*/ + volatile uint32_t cnt_thr_event_u1_int_st: 1; /*This is the interrupt status bit for channel1 event.*/ + volatile uint32_t cnt_thr_event_u2_int_st: 1; /*This is the interrupt status bit for channel2 event.*/ + volatile uint32_t cnt_thr_event_u3_int_st: 1; /*This is the interrupt status bit for channel3 event.*/ + volatile uint32_t cnt_thr_event_u4_int_st: 1; /*This is the interrupt status bit for channel4 event.*/ + volatile uint32_t cnt_thr_event_u5_int_st: 1; /*This is the interrupt status bit for channel5 event.*/ + volatile uint32_t cnt_thr_event_u6_int_st: 1; /*This is the interrupt status bit for channel6 event.*/ + volatile uint32_t cnt_thr_event_u7_int_st: 1; /*This is the interrupt status bit for channel7 event.*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }int_st; + union { + struct { + volatile uint32_t cnt_thr_event_u0_int_ena: 1; /*This is the interrupt enable bit for channel0 event.*/ + volatile uint32_t cnt_thr_event_u1_int_ena: 1; /*This is the interrupt enable bit for channel1 event.*/ + volatile uint32_t cnt_thr_event_u2_int_ena: 1; /*This is the interrupt enable bit for channel2 event.*/ + volatile uint32_t cnt_thr_event_u3_int_ena: 1; /*This is the interrupt enable bit for channel3 event.*/ + volatile uint32_t cnt_thr_event_u4_int_ena: 1; /*This is the interrupt enable bit for channel4 event.*/ + volatile uint32_t cnt_thr_event_u5_int_ena: 1; /*This is the interrupt enable bit for channel5 event.*/ + volatile uint32_t cnt_thr_event_u6_int_ena: 1; /*This is the interrupt enable bit for channel6 event.*/ + volatile uint32_t cnt_thr_event_u7_int_ena: 1; /*This is the interrupt enable bit for channel7 event.*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }int_ena; + union { + struct { + volatile uint32_t cnt_thr_event_u0_int_clr: 1; /*Set this bit to clear channel0 event interrupt.*/ + volatile uint32_t cnt_thr_event_u1_int_clr: 1; /*Set this bit to clear channel1 event interrupt.*/ + volatile uint32_t cnt_thr_event_u2_int_clr: 1; /*Set this bit to clear channel2 event interrupt.*/ + volatile uint32_t cnt_thr_event_u3_int_clr: 1; /*Set this bit to clear channel3 event interrupt.*/ + volatile uint32_t cnt_thr_event_u4_int_clr: 1; /*Set this bit to clear channel4 event interrupt.*/ + volatile uint32_t cnt_thr_event_u5_int_clr: 1; /*Set this bit to clear channel5 event interrupt.*/ + volatile uint32_t cnt_thr_event_u6_int_clr: 1; /*Set this bit to clear channel6 event interrupt.*/ + volatile uint32_t cnt_thr_event_u7_int_clr: 1; /*Set this bit to clear channel7 event interrupt.*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }int_clr; + volatile uint32_t status_unit[8]; + union { + struct { + volatile uint32_t cnt_rst_u0: 1; /*Set this bit to clear unit0's counter.*/ + volatile uint32_t cnt_pause_u0: 1; /*Set this bit to pause unit0's counter.*/ + volatile uint32_t cnt_rst_u1: 1; /*Set this bit to clear unit1's counter.*/ + volatile uint32_t cnt_pause_u1: 1; /*Set this bit to pause unit1's counter.*/ + volatile uint32_t cnt_rst_u2: 1; /*Set this bit to clear unit2's counter.*/ + volatile uint32_t cnt_pause_u2: 1; /*Set this bit to pause unit2's counter.*/ + volatile uint32_t cnt_rst_u3: 1; /*Set this bit to clear unit3's counter.*/ + volatile uint32_t cnt_pause_u3: 1; /*Set this bit to pause unit3's counter.*/ + volatile uint32_t cnt_rst_u4: 1; /*Set this bit to clear unit4's counter.*/ + volatile uint32_t cnt_pause_u4: 1; /*Set this bit to pause unit4's counter.*/ + volatile uint32_t cnt_rst_u5: 1; /*Set this bit to clear unit5's counter.*/ + volatile uint32_t cnt_pause_u5: 1; /*Set this bit to pause unit5's counter.*/ + volatile uint32_t cnt_rst_u6: 1; /*Set this bit to clear unit6's counter.*/ + volatile uint32_t cnt_pause_u6: 1; /*Set this bit to pause unit6's counter.*/ + volatile uint32_t cnt_rst_u7: 1; /*Set this bit to clear unit7's counter.*/ + volatile uint32_t cnt_pause_u7: 1; /*Set this bit to pause unit7's counter.*/ + volatile uint32_t clk_en: 1; + volatile uint32_t reserved17: 15; + }; + volatile uint32_t val; + }ctrl; + volatile uint32_t reserved_b4; + volatile uint32_t reserved_b8; + volatile uint32_t reserved_bc; + volatile uint32_t reserved_c0; + volatile uint32_t reserved_c4; + volatile uint32_t reserved_c8; + volatile uint32_t reserved_cc; + volatile uint32_t reserved_d0; + volatile uint32_t reserved_d4; + volatile uint32_t reserved_d8; + volatile uint32_t reserved_dc; + volatile uint32_t reserved_e0; + volatile uint32_t reserved_e4; + volatile uint32_t reserved_e8; + volatile uint32_t reserved_ec; + volatile uint32_t reserved_f0; + volatile uint32_t reserved_f4; + volatile uint32_t reserved_f8; + volatile uint32_t date; /**/ +} pcnt_dev_t; +extern volatile pcnt_dev_t PCNT; +#endif /* _SOC_PCNT_STRUCT_H_ */ diff --git a/components/esp32/include/soc/rmt_struct.h b/components/esp32/include/soc/rmt_struct.h new file mode 100644 index 000000000..7310e18d5 --- /dev/null +++ b/components/esp32/include/soc/rmt_struct.h @@ -0,0 +1,228 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_RMT_STRUCT_H_ +#define _SOC_RMT_STRUCT_H_ +typedef struct { + volatile uint32_t data_ch[8]; /*The R/W ram address for channel0-7 by apb fifo access.*/ + struct{ + union { + struct { + volatile uint32_t div_cnt: 8; /*This register is used to configure the frequency divider's factor in channel0-7.*/ + volatile uint32_t idle_thres: 16; /*In receive mode when no edge is detected on the input signal for longer than reg_idle_thres_ch0 then the receive process is done.*/ + volatile uint32_t mem_size: 4; /*This register is used to configure the the amount of memory blocks allocated to channel0-7.*/ + volatile uint32_t carrier_en: 1; /*This is the carrier modulation enable control bit for channel0-7.*/ + volatile uint32_t carrier_out_lv: 1; /*This bit is used to configure the way carrier wave is modulated for channel0-7.1'b1:transmit on low output level 1'b0:transmit on high output level.*/ + volatile uint32_t mem_pd: 1; /*This bit is used to reduce power consumed by memory. 1:memory is in low power state.*/ + volatile uint32_t clk_en: 1; /*This bit is used to control clock.when software configure RMT internal registers it controls the register clock.*/ + }; + volatile uint32_t val; + }conf0; + union { + struct { + volatile uint32_t tx_start: 1; /*Set this bit to start sending data for channel0-7.*/ + volatile uint32_t rx_en: 1; /*Set this bit to enable receiving data for channel0-7.*/ + volatile uint32_t mem_wr_rst: 1; /*Set this bit to reset write ram address for channel0-7 by receiver access.*/ + volatile uint32_t mem_rd_rst: 1; /*Set this bit to reset read ram address for channel0-7 by transmitter access.*/ + volatile uint32_t apb_mem_rst: 1; /*Set this bit to reset W/R ram address for channel0-7 by apb fifo access*/ + volatile uint32_t mem_owner: 1; /*This is the mark of channel0-7's ram usage right.1'b1：receiver uses the ram 0：transmitter uses the ram*/ + volatile uint32_t tx_conti_mode: 1; /*Set this bit to continue sending from the first data to the last data in channel0-7 again and again.*/ + volatile uint32_t rx_filter_en: 1; /*This is the receive filter enable bit for channel0-7.*/ + volatile uint32_t rx_filter_thres: 8; /*in receive mode channel0-7 ignore input pulse when the pulse width is smaller then this value.*/ + volatile uint32_t ref_cnt_rst: 1; /*This bit is used to reset divider in channel0-7.*/ + volatile uint32_t ref_always_on: 1; /*This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ + volatile uint32_t idle_out_lv: 1; /*This bit configures the output signal's level for channel0-7 in IDLE state.*/ + volatile uint32_t idle_out_en: 1; /*This is the output enable control bit for channel0-7 in IDLE state.*/ + volatile uint32_t reserved20: 12; + }; + volatile uint32_t val; + }conf1; + }conf_ch[8]; + volatile uint32_t status_ch[8]; /*The status for channel0-7*/ + volatile uint32_t apb_mem_addr_ch[8]; /*The ram relative address in channel0-7 by apb fifo access*/ + union { + struct { + volatile uint32_t ch0_tx_end_int_raw: 1; /*The interrupt raw bit for channel 0 turns to high level when the transmit process is done.*/ + volatile uint32_t ch0_rx_end_int_raw: 1; /*The interrupt raw bit for channel 0 turns to high level when the receive process is done.*/ + volatile uint32_t ch0_err_int_raw: 1; /*The interrupt raw bit for channel 0 turns to high level when channel 0 detects some errors.*/ + volatile uint32_t ch1_tx_end_int_raw: 1; /*The interrupt raw bit for channel 1 turns to high level when the transmit process is done.*/ + volatile uint32_t ch1_rx_end_int_raw: 1; /*The interrupt raw bit for channel 1 turns to high level when the receive process is done.*/ + volatile uint32_t ch1_err_int_raw: 1; /*The interrupt raw bit for channel 1 turns to high level when channel 1 detects some errors.*/ + volatile uint32_t ch2_tx_end_int_raw: 1; /*The interrupt raw bit for channel 2 turns to high level when the transmit process is done.*/ + volatile uint32_t ch2_rx_end_int_raw: 1; /*The interrupt raw bit for channel 2 turns to high level when the receive process is done.*/ + volatile uint32_t ch2_err_int_raw: 1; /*The interrupt raw bit for channel 2 turns to high level when channel 2 detects some errors.*/ + volatile uint32_t ch3_tx_end_int_raw: 1; /*The interrupt raw bit for channel 3 turns to high level when the transmit process is done.*/ + volatile uint32_t ch3_rx_end_int_raw: 1; /*The interrupt raw bit for channel 3 turns to high level when the receive process is done.*/ + volatile uint32_t ch3_err_int_raw: 1; /*The interrupt raw bit for channel 3 turns to high level when channel 3 detects some errors.*/ + volatile uint32_t ch4_tx_end_int_raw: 1; /*The interrupt raw bit for channel 4 turns to high level when the transmit process is done.*/ + volatile uint32_t ch4_rx_end_int_raw: 1; /*The interrupt raw bit for channel 4 turns to high level when the receive process is done.*/ + volatile uint32_t ch4_err_int_raw: 1; /*The interrupt raw bit for channel 4 turns to high level when channel 4 detects some errors.*/ + volatile uint32_t ch5_tx_end_int_raw: 1; /*The interrupt raw bit for channel 5 turns to high level when the transmit process is done.*/ + volatile uint32_t ch5_rx_end_int_raw: 1; /*The interrupt raw bit for channel 5 turns to high level when the receive process is done.*/ + volatile uint32_t ch5_err_int_raw: 1; /*The interrupt raw bit for channel 5 turns to high level when channel 5 detects some errors.*/ + volatile uint32_t ch6_tx_end_int_raw: 1; /*The interrupt raw bit for channel 6 turns to high level when the transmit process is done.*/ + volatile uint32_t ch6_rx_end_int_raw: 1; /*The interrupt raw bit for channel 6 turns to high level when the receive process is done.*/ + volatile uint32_t ch6_err_int_raw: 1; /*The interrupt raw bit for channel 6 turns to high level when channel 6 detects some errors.*/ + volatile uint32_t ch7_tx_end_int_raw: 1; /*The interrupt raw bit for channel 7 turns to high level when the transmit process is done.*/ + volatile uint32_t ch7_rx_end_int_raw: 1; /*The interrupt raw bit for channel 7 turns to high level when the receive process is done.*/ + volatile uint32_t ch7_err_int_raw: 1; /*The interrupt raw bit for channel 7 turns to high level when channel 7 detects some errors.*/ + volatile uint32_t ch0_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 0 turns to high level when transmitter in channel0 have send data more than reg_rmt_tx_lim_ch0 after detecting this interrupt software can updata the old data with new data.*/ + volatile uint32_t ch1_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 1 turns to high level when transmitter in channel1 have send data more than reg_rmt_tx_lim_ch1 after detecting this interrupt software can updata the old data with new data.*/ + volatile uint32_t ch2_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 2 turns to high level when transmitter in channel2 have send data more than reg_rmt_tx_lim_ch2 after detecting this interrupt software can updata the old data with new data.*/ + volatile uint32_t ch3_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 3 turns to high level when transmitter in channel3 have send data more than reg_rmt_tx_lim_ch3 after detecting this interrupt software can updata the old data with new data.*/ + volatile uint32_t ch4_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 4 turns to high level when transmitter in channel4 have send data more than reg_rmt_tx_lim_ch4 after detecting this interrupt software can updata the old data with new data.*/ + volatile uint32_t ch5_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 5 turns to high level when transmitter in channel5 have send data more than reg_rmt_tx_lim_ch5 after detecting this interrupt software can updata the old data with new data.*/ + volatile uint32_t ch6_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 6 turns to high level when transmitter in channel6 have send data more than reg_rmt_tx_lim_ch6 after detecting this interrupt software can updata the old data with new data.*/ + volatile uint32_t ch7_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 7 turns to high level when transmitter in channel7 have send data more than reg_rmt_tx_lim_ch7 after detecting this interrupt software can updata the old data with new data.*/ + }; + volatile uint32_t val; + }int_raw; + union { + struct { + volatile uint32_t ch0_tx_end_int_st: 1; /*The interrupt state bit for channel 0's mt_ch0_tx_end_int_raw when mt_ch0_tx_end_int_ena is set to 0.*/ + volatile uint32_t ch0_rx_end_int_st: 1; /*The interrupt state bit for channel 0's rmt_ch0_rx_end_int_raw when rmt_ch0_rx_end_int_ena is set to 0.*/ + volatile uint32_t ch0_err_int_st: 1; /*The interrupt state bit for channel 0's rmt_ch0_err_int_raw when rmt_ch0_err_int_ena is set to 0.*/ + volatile uint32_t ch1_tx_end_int_st: 1; /*The interrupt state bit for channel 1's mt_ch1_tx_end_int_raw when mt_ch1_tx_end_int_ena is set to 1.*/ + volatile uint32_t ch1_rx_end_int_st: 1; /*The interrupt state bit for channel 1's rmt_ch1_rx_end_int_raw when rmt_ch1_rx_end_int_ena is set to 1.*/ + volatile uint32_t ch1_err_int_st: 1; /*The interrupt state bit for channel 1's rmt_ch1_err_int_raw when rmt_ch1_err_int_ena is set to 1.*/ + volatile uint32_t ch2_tx_end_int_st: 1; /*The interrupt state bit for channel 2's mt_ch2_tx_end_int_raw when mt_ch2_tx_end_int_ena is set to 1.*/ + volatile uint32_t ch2_rx_end_int_st: 1; /*The interrupt state bit for channel 2's rmt_ch2_rx_end_int_raw when rmt_ch2_rx_end_int_ena is set to 1.*/ + volatile uint32_t ch2_err_int_st: 1; /*The interrupt state bit for channel 2's rmt_ch2_err_int_raw when rmt_ch2_err_int_ena is set to 1.*/ + volatile uint32_t ch3_tx_end_int_st: 1; /*The interrupt state bit for channel 3's mt_ch3_tx_end_int_raw when mt_ch3_tx_end_int_ena is set to 1.*/ + volatile uint32_t ch3_rx_end_int_st: 1; /*The interrupt state bit for channel 3's rmt_ch3_rx_end_int_raw when rmt_ch3_rx_end_int_ena is set to 1.*/ + volatile uint32_t ch3_err_int_st: 1; /*The interrupt state bit for channel 3's rmt_ch3_err_int_raw when rmt_ch3_err_int_ena is set to 1.*/ + volatile uint32_t ch4_tx_end_int_st: 1; /*The interrupt state bit for channel 4's mt_ch4_tx_end_int_raw when mt_ch4_tx_end_int_ena is set to 1.*/ + volatile uint32_t ch4_rx_end_int_st: 1; /*The interrupt state bit for channel 4's rmt_ch4_rx_end_int_raw when rmt_ch4_rx_end_int_ena is set to 1.*/ + volatile uint32_t ch4_err_int_st: 1; /*The interrupt state bit for channel 4's rmt_ch4_err_int_raw when rmt_ch4_err_int_ena is set to 1.*/ + volatile uint32_t ch5_tx_end_int_st: 1; /*The interrupt state bit for channel 5's mt_ch5_tx_end_int_raw when mt_ch5_tx_end_int_ena is set to 1.*/ + volatile uint32_t ch5_rx_end_int_st: 1; /*The interrupt state bit for channel 5's rmt_ch5_rx_end_int_raw when rmt_ch5_rx_end_int_ena is set to 1.*/ + volatile uint32_t ch5_err_int_st: 1; /*The interrupt state bit for channel 5's rmt_ch5_err_int_raw when rmt_ch5_err_int_ena is set to 1.*/ + volatile uint32_t ch6_tx_end_int_st: 1; /*The interrupt state bit for channel 6's mt_ch6_tx_end_int_raw when mt_ch6_tx_end_int_ena is set to 1.*/ + volatile uint32_t ch6_rx_end_int_st: 1; /*The interrupt state bit for channel 6's rmt_ch6_rx_end_int_raw when rmt_ch6_rx_end_int_ena is set to 1.*/ + volatile uint32_t ch6_err_int_st: 1; /*The interrupt state bit for channel 6's rmt_ch6_err_int_raw when rmt_ch6_err_int_ena is set to 1.*/ + volatile uint32_t ch7_tx_end_int_st: 1; /*The interrupt state bit for channel 7's mt_ch7_tx_end_int_raw when mt_ch7_tx_end_int_ena is set to 1.*/ + volatile uint32_t ch7_rx_end_int_st: 1; /*The interrupt state bit for channel 7's rmt_ch7_rx_end_int_raw when rmt_ch7_rx_end_int_ena is set to 1.*/ + volatile uint32_t ch7_err_int_st: 1; /*The interrupt state bit for channel 7's rmt_ch7_err_int_raw when rmt_ch7_err_int_ena is set to 1.*/ + volatile uint32_t ch0_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 0's rmt_ch0_tx_thr_event_int_raw when mt_ch0_tx_thr_event_int_ena is set to 1.*/ + volatile uint32_t ch1_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 1's rmt_ch1_tx_thr_event_int_raw when mt_ch1_tx_thr_event_int_ena is set to 1.*/ + volatile uint32_t ch2_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 2's rmt_ch2_tx_thr_event_int_raw when mt_ch2_tx_thr_event_int_ena is set to 1.*/ + volatile uint32_t ch3_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 3's rmt_ch3_tx_thr_event_int_raw when mt_ch3_tx_thr_event_int_ena is set to 1.*/ + volatile uint32_t ch4_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 4's rmt_ch4_tx_thr_event_int_raw when mt_ch4_tx_thr_event_int_ena is set to 1.*/ + volatile uint32_t ch5_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 5's rmt_ch5_tx_thr_event_int_raw when mt_ch5_tx_thr_event_int_ena is set to 1.*/ + volatile uint32_t ch6_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 6's rmt_ch6_tx_thr_event_int_raw when mt_ch6_tx_thr_event_int_ena is set to 1.*/ + volatile uint32_t ch7_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 7's rmt_ch7_tx_thr_event_int_raw when mt_ch7_tx_thr_event_int_ena is set to 1.*/ + }; + volatile uint32_t val; + }int_st; + union { + struct { + volatile uint32_t ch0_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch0_tx_end_int_st.*/ + volatile uint32_t ch0_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch0_rx_end_int_st.*/ + volatile uint32_t ch0_err_int_ena: 1; /*Set this bit to enable rmt_ch0_err_int_st.*/ + volatile uint32_t ch1_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch1_tx_end_int_st.*/ + volatile uint32_t ch1_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch1_rx_end_int_st.*/ + volatile uint32_t ch1_err_int_ena: 1; /*Set this bit to enable rmt_ch1_err_int_st.*/ + volatile uint32_t ch2_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch2_tx_end_int_st.*/ + volatile uint32_t ch2_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch2_rx_end_int_st.*/ + volatile uint32_t ch2_err_int_ena: 1; /*Set this bit to enable rmt_ch2_err_int_st.*/ + volatile uint32_t ch3_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch3_tx_end_int_st.*/ + volatile uint32_t ch3_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch3_rx_end_int_st.*/ + volatile uint32_t ch3_err_int_ena: 1; /*Set this bit to enable rmt_ch3_err_int_st.*/ + volatile uint32_t ch4_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch4_tx_end_int_st.*/ + volatile uint32_t ch4_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch4_rx_end_int_st.*/ + volatile uint32_t ch4_err_int_ena: 1; /*Set this bit to enable rmt_ch4_err_int_st.*/ + volatile uint32_t ch5_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch5_tx_end_int_st.*/ + volatile uint32_t ch5_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch5_rx_end_int_st.*/ + volatile uint32_t ch5_err_int_ena: 1; /*Set this bit to enable rmt_ch5_err_int_st.*/ + volatile uint32_t ch6_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch6_tx_end_int_st.*/ + volatile uint32_t ch6_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch6_rx_end_int_st.*/ + volatile uint32_t ch6_err_int_ena: 1; /*Set this bit to enable rmt_ch6_err_int_st.*/ + volatile uint32_t ch7_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch7_tx_end_int_st.*/ + volatile uint32_t ch7_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch7_rx_end_int_st.*/ + volatile uint32_t ch7_err_int_ena: 1; /*Set this bit to enable rmt_ch7_err_int_st.*/ + volatile uint32_t ch0_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch0_tx_thr_event_int_st.*/ + volatile uint32_t ch1_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch1_tx_thr_event_int_st.*/ + volatile uint32_t ch2_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch2_tx_thr_event_int_st.*/ + volatile uint32_t ch3_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch3_tx_thr_event_int_st.*/ + volatile uint32_t ch4_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch4_tx_thr_event_int_st.*/ + volatile uint32_t ch5_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch5_tx_thr_event_int_st.*/ + volatile uint32_t ch6_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch6_tx_thr_event_int_st.*/ + volatile uint32_t ch7_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch7_tx_thr_event_int_st.*/ + }; + volatile uint32_t val; + }int_ena; + union { + struct { + volatile uint32_t ch0_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch0_rx_end_int_raw..*/ + volatile uint32_t ch0_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch0_tx_end_int_raw.*/ + volatile uint32_t ch0_err_int_clr: 1; /*Set this bit to clear the rmt_ch0_err_int_raw.*/ + volatile uint32_t ch1_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch1_rx_end_int_raw..*/ + volatile uint32_t ch1_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch1_tx_end_int_raw.*/ + volatile uint32_t ch1_err_int_clr: 1; /*Set this bit to clear the rmt_ch1_err_int_raw.*/ + volatile uint32_t ch2_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch2_rx_end_int_raw..*/ + volatile uint32_t ch2_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch2_tx_end_int_raw.*/ + volatile uint32_t ch2_err_int_clr: 1; /*Set this bit to clear the rmt_ch2_err_int_raw.*/ + volatile uint32_t ch3_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch3_rx_end_int_raw..*/ + volatile uint32_t ch3_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch3_tx_end_int_raw.*/ + volatile uint32_t ch3_err_int_clr: 1; /*Set this bit to clear the rmt_ch3_err_int_raw.*/ + volatile uint32_t ch4_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch4_rx_end_int_raw..*/ + volatile uint32_t ch4_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch4_tx_end_int_raw.*/ + volatile uint32_t ch4_err_int_clr: 1; /*Set this bit to clear the rmt_ch4_err_int_raw.*/ + volatile uint32_t ch5_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch5_rx_end_int_raw..*/ + volatile uint32_t ch5_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch5_tx_end_int_raw.*/ + volatile uint32_t ch5_err_int_clr: 1; /*Set this bit to clear the rmt_ch5_err_int_raw.*/ + volatile uint32_t ch6_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch6_rx_end_int_raw..*/ + volatile uint32_t ch6_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch6_tx_end_int_raw.*/ + volatile uint32_t ch6_err_int_clr: 1; /*Set this bit to clear the rmt_ch6_err_int_raw.*/ + volatile uint32_t ch7_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch7_rx_end_int_raw..*/ + volatile uint32_t ch7_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch7_tx_end_int_raw.*/ + volatile uint32_t ch7_err_int_clr: 1; /*Set this bit to clear the rmt_ch7_err_int_raw.*/ + volatile uint32_t ch0_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch0_tx_thr_event_int_raw interrupt.*/ + volatile uint32_t ch1_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch1_tx_thr_event_int_raw interrupt.*/ + volatile uint32_t ch2_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch2_tx_thr_event_int_raw interrupt.*/ + volatile uint32_t ch3_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch3_tx_thr_event_int_raw interrupt.*/ + volatile uint32_t ch4_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch4_tx_thr_event_int_raw interrupt.*/ + volatile uint32_t ch5_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch5_tx_thr_event_int_raw interrupt.*/ + volatile uint32_t ch6_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch6_tx_thr_event_int_raw interrupt.*/ + volatile uint32_t ch7_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch7_tx_thr_event_int_raw interrupt.*/ + }; + volatile uint32_t val; + }int_clr; + union { + struct { + volatile uint32_t carrier_low: 16; /*This register is used to configure carrier wave's low level value for channel0-7.*/ + volatile uint32_t carrier_high:16; /*This register is used to configure carrier wave's high level value for channel0-7.*/ + }; + volatile uint32_t val; + }carrier_duty_ch[8]; + union { + struct { + volatile uint32_t tx_lim: 9; /*When channel0-7 sends more than reg_rmt_tx_lim_ch0 data then channel0-7 produce the relative interrupt.*/ + volatile uint32_t reserved9: 23; + }; + volatile uint32_t val; + }tx_lim_ch[8]; + union { + struct { + volatile uint32_t apb_fifo_mask: 1; /*Set this bit to disable apb fifo access*/ + volatile uint32_t mem_tx_wrap_en: 1; /*when data need to be send is more than channel's mem can store then set this bit to enable reuse of mem this bit is used together with reg_rmt_tx_lim_chn.*/ + volatile uint32_t reserved2: 30; + }; + volatile uint32_t val; + }apb_conf; + volatile uint32_t reserved_f4; + volatile uint32_t reserved_f8; + volatile uint32_t date; /*This is the version register.*/ +} rmt_dev_t; +extern volatile rmt_dev_t RMT; +#endif /* _SOC_RMT_STRUCT_H_ */ diff --git a/components/esp32/include/soc/spi_struct.h b/components/esp32/include/soc/spi_struct.h new file mode 100644 index 000000000..e76590537 --- /dev/null +++ b/components/esp32/include/soc/spi_struct.h @@ -0,0 +1,677 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_SPI_STRUCT_H_ +#define _SOC_SPI_STRUCT_H_ +typedef struct { + union { + struct { + volatile uint32_t reserved0: 16; /*reserved*/ + volatile uint32_t flash_per: 1; /*program erase resume bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + volatile uint32_t flash_pes: 1; /*program erase suspend bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + volatile uint32_t usr: 1; /*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + volatile uint32_t flash_hpm: 1; /*Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable.*/ + volatile uint32_t flash_res: 1; /*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/ + volatile uint32_t flash_dp: 1; /*Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + volatile uint32_t flash_ce: 1; /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + volatile uint32_t flash_be: 1; /*Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + volatile uint32_t flash_se: 1; /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + volatile uint32_t flash_pp: 1; /*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/ + volatile uint32_t flash_wrsr: 1; /*Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + volatile uint32_t flash_rdsr: 1; /*Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + volatile uint32_t flash_rdid: 1; /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ + volatile uint32_t flash_wrdi: 1; /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ + volatile uint32_t flash_wren: 1; /*Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ + volatile uint32_t flash_read: 1; /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ + }; + volatile uint32_t val; + }cmd; + union { + struct { + volatile uint32_t reserved : 8; + volatile uint32_t usr_addr_value:24; /*[31:8]:address to slave [7:0]:Reserved.*/ + }; + volatile uint32_t val; + }addr; + union { + struct { + volatile uint32_t reserved0: 10; /*reserved*/ + volatile uint32_t fcs_crc_en: 1; /*For SPI1 initialize crc32 module before writing encrypted data to flash. Active low.*/ + volatile uint32_t tx_crc_en: 1; /*For SPI1 enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/ + volatile uint32_t wait_flash_idle_en: 1; /*wait flash idle when program flash or erase flash. 1: enable 0: disable.*/ + volatile uint32_t fastrd_mode: 1; /*This bit enable the bits: spi_fread_qio spi_fread_dio spi_fread_qout and spi_fread_dout. 1: enable 0: disable.*/ + volatile uint32_t fread_dual: 1; /*In the read operations read-data phase apply 2 signals. 1: enable 0: disable.*/ + volatile uint32_t resandres: 1; /*The Device ID is read out to SPI_RD_STATUS register, this bit combine with spi_flash_res bit. 1: enable 0: disable.*/ + volatile uint32_t reserved16: 4; /*reserved*/ + volatile uint32_t fread_quad: 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/ + volatile uint32_t wp: 1; /*Write protect signal output when SPI is idle. 1: output high 0: output low.*/ + volatile uint32_t wrsr_2b: 1; /*two bytes data will be written to status register when it is set. 1: enable 0: disable.*/ + volatile uint32_t fread_dio: 1; /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.*/ + volatile uint32_t fread_qio: 1; /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.*/ + volatile uint32_t rd_bit_order: 1; /*In read-data (MISO) phase 1: LSB first 0: MSB first*/ + volatile uint32_t wr_bit_order: 1; /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first*/ + volatile uint32_t reserved27: 5; /*reserved*/ + }; + volatile uint32_t val; + }ctrl; + union { + struct { + volatile uint32_t reserved0: 16; /*reserved*/ + volatile uint32_t cs_hold_delay_res:12; /*Delay cycles of resume Flash when resume Flash is enable by spi clock.*/ + volatile uint32_t cs_hold_delay: 4; /*SPI cs signal is delayed by spi clock cycles*/ + }; + volatile uint32_t val; + }ctrl1; + union { + struct { + volatile uint32_t status: 16; /*In the slave mode, it is the status for master to read out.*/ + volatile uint32_t wb_mode: 8; /*Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit.*/ + volatile uint32_t status_ext: 8; /*In the slave mode,it is the status for master to read out.*/ + }; + volatile uint32_t val; + }rd_status; + union { + struct { + volatile uint32_t setup_time: 4; /*(cycles-1) of ,prepare, phase by spi clock, this bits combined with spi_cs_setup bit.*/ + volatile uint32_t hold_time: 4; /*delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit.*/ + volatile uint32_t ck_out_low_mode: 4; /*modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits.*/ + volatile uint32_t ck_out_high_mode: 4; /*modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits.*/ + volatile uint32_t miso_delay_mode: 2; /*MISO signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ + volatile uint32_t miso_delay_num: 3; /*MISO signals are delayed by system clock cycles*/ + volatile uint32_t mosi_delay_mode: 2; /*MOSI signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ + volatile uint32_t mosi_delay_num: 3; /*MOSI signals are delayed by system clock cycles*/ + volatile uint32_t cs_delay_mode: 2; /*spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ + volatile uint32_t cs_delay_num: 4; /*spi_cs signal is delayed by system clock cycles*/ + }; + volatile uint32_t val; + }ctrl2; + union { + struct { + volatile uint32_t clkcnt_l: 6; /*In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0.*/ + volatile uint32_t clkcnt_h: 6; /*In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0.*/ + volatile uint32_t clkcnt_n: 6; /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)*/ + volatile uint32_t clkdiv_pre: 13; /*In the master mode it is pre-divider of spi_clk.*/ + volatile uint32_t clk_equ_sysclk: 1; /*In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock.*/ + }; + volatile uint32_t val; + }clock; + union { + struct { + volatile uint32_t doutdin: 1; /*Set the bit to enable full duplex communication. 1: enable 0: disable.*/ + volatile uint32_t reserved1: 3; /*reserved*/ + volatile uint32_t cs_hold: 1; /*spi cs keep low when spi is in ,done, phase. 1: enable 0: disable.*/ + volatile uint32_t cs_setup: 1; /*spi cs is enable when spi is in ,prepare, phase. 1: enable 0: disable.*/ + volatile uint32_t ck_i_edge: 1; /*In the slave mode the bit is same as spi_ck_out_edge in master mode. It is combined with spi_miso_delay_mode bits.*/ + volatile uint32_t ck_out_edge: 1; /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode.*/ + volatile uint32_t reserved8: 2; /*reserved*/ + volatile uint32_t rd_byte_order: 1; /*In read-data (MISO) phase 1: big-endian 0: little_endian*/ + volatile uint32_t wr_byte_order: 1; /*In command address write-data (MOSI) phases 1: big-endian 0: litte_endian*/ + volatile uint32_t fwrite_dual: 1; /*In the write operations read-data phase apply 2 signals*/ + volatile uint32_t fwrite_quad: 1; /*In the write operations read-data phase apply 4 signals*/ + volatile uint32_t fwrite_dio: 1; /*In the write operations address phase and read-data phase apply 2 signals.*/ + volatile uint32_t fwrite_qio: 1; /*In the write operations address phase and read-data phase apply 4 signals.*/ + volatile uint32_t sio: 1; /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable.*/ + volatile uint32_t usr_hold_pol: 1; /*It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low*/ + volatile uint32_t usr_dout_hold: 1; /*spi is hold at data out state the bit combined with spi_usr_hold_pol bit.*/ + volatile uint32_t usr_din_hold: 1; /*spi is hold at data in state the bit combined with spi_usr_hold_pol bit.*/ + volatile uint32_t usr_dummy_hold: 1; /*spi is hold at dummy state the bit combined with spi_usr_hold_pol bit.*/ + volatile uint32_t usr_addr_hold: 1; /*spi is hold at address state the bit combined with spi_usr_hold_pol bit.*/ + volatile uint32_t usr_cmd_hold: 1; /*spi is hold at command state the bit combined with spi_usr_hold_pol bit.*/ + volatile uint32_t usr_prep_hold: 1; /*spi is hold at prepare state the bit combined with spi_usr_hold_pol bit.*/ + volatile uint32_t usr_miso_highpart: 1; /*read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.*/ + volatile uint32_t usr_mosi_highpart: 1; /*write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.*/ + volatile uint32_t usr_dummy_idle: 1; /*spi clock is disable in dummy phase when the bit is enable.*/ + volatile uint32_t usr_mosi: 1; /*This bit enable the write-data phase of an operation.*/ + volatile uint32_t usr_miso: 1; /*This bit enable the read-data phase of an operation.*/ + volatile uint32_t usr_dummy: 1; /*This bit enable the dummy phase of an operation.*/ + volatile uint32_t usr_addr: 1; /*This bit enable the address phase of an operation.*/ + volatile uint32_t usr_command: 1; /*This bit enable the command phase of an operation.*/ + }; + volatile uint32_t val; + }user; + union { + struct { + volatile uint32_t usr_dummy_cyclelen: 8; /*The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/ + volatile uint32_t reserved8: 18; /*reserved*/ + volatile uint32_t usr_addr_bitlen: 6; /*The length in bits of address phase. The register value shall be (bit_num-1).*/ + }; + volatile uint32_t val; + }user1; + union { + struct { + volatile uint32_t usr_command_value: 16; /*The value of command.*/ + volatile uint32_t reserved16: 12; /*reserved*/ + volatile uint32_t usr_command_bitlen: 4; /*The length in bits of command phase. The register value shall be (bit_num-1)*/ + }; + volatile uint32_t val; + }user2; + union { + struct { + volatile uint32_t usr_mosi_dbitlen:24; /*The length in bits of write-data. The register value shall be (bit_num-1).*/ + volatile uint32_t reserved24: 8; /*reserved*/ + }; + volatile uint32_t val; + }mosi_dlen; + union { + struct { + volatile uint32_t usr_miso_dbitlen:24; /*The length in bits of read-data. The register value shall be (bit_num-1).*/ + volatile uint32_t reserved24: 8; /*reserved*/ + }; + volatile uint32_t val; + }miso_dlen; + volatile uint32_t slv_wr_status; /*In the slave mode this register are the status register for the master to write into. In the master mode this register are the higher 32bits in the 64 bits address condition.*/ + union { + struct { + volatile uint32_t cs0_dis: 1; /*SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin*/ + volatile uint32_t cs1_dis: 1; /*SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin*/ + volatile uint32_t cs2_dis: 1; /*SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin*/ + volatile uint32_t reserved3: 2; /*reserved*/ + volatile uint32_t ck_dis: 1; /*1: spi clk out disable 0: spi clk out enable*/ + volatile uint32_t master_cs_pol: 5; /*In the master mode the bits are the polarity of spi cs line the value is equivalent to spi_cs ^ spi_master_cs_pol.*/ + volatile uint32_t master_ck_sel: 5; /*In the master mode spi cs line is enable as spi clk it is combined with spi_cs0_dis spi_cs1_dis spi_cs2_dis.*/ + volatile uint32_t reserved16: 13; /*reserved*/ + volatile uint32_t ck_idle_edge: 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle*/ + volatile uint32_t cs_keep_active: 1; /*spi cs line keep low when the bit is set.*/ + volatile uint32_t reserved31: 1; /*reserved*/ + }; + volatile uint32_t val; + }pin; + union { + struct { + volatile uint32_t slv_rd_buf_done: 1; /*The interrupt raw bit for the completion of read-buffer operation in the slave mode.*/ + volatile uint32_t slv_wr_buf_done: 1; /*The interrupt raw bit for the completion of write-buffer operation in the slave mode.*/ + volatile uint32_t slv_rd_sta_done: 1; /*The interrupt raw bit for the completion of read-status operation in the slave mode.*/ + volatile uint32_t slv_wr_sta_done: 1; /*The interrupt raw bit for the completion of write-status operation in the slave mode.*/ + volatile uint32_t trans_done: 1; /*The interrupt raw bit for the completion of any operation in both the master mode and the slave mode.*/ + volatile uint32_t int_en: 5; /*Interrupt enable bits for the below 5 sources*/ + volatile uint32_t cs_i_mode: 2; /*In the slave mode this bits used to synchronize the input spi cs signal and eliminate spi cs jitter.*/ + volatile uint32_t reserved12: 5; /*reserved*/ + volatile uint32_t slv_last_command: 3; /*In the slave mode it is the value of command.*/ + volatile uint32_t slv_last_state: 3; /*In the slave mode it is the state of spi state machine.*/ + volatile uint32_t trans_cnt: 4; /*The operations counter in both the master mode and the slave mode. 4: read-status*/ + volatile uint32_t slv_cmd_define: 1; /*1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as: 1: write-status 2: write-buffer and 3: read-buffer.*/ + volatile uint32_t slv_wr_rd_sta_en: 1; /*write and read status enable in the slave mode*/ + volatile uint32_t slv_wr_rd_buf_en: 1; /*write and read buffer enable in the slave mode*/ + volatile uint32_t slave_mode: 1; /*1: slave mode 0: master mode.*/ + volatile uint32_t sync_reset: 1; /*Software reset enable, reset the spi clock line cs line and data lines.*/ + }; + volatile uint32_t val; + }slave; + union { + struct { + volatile uint32_t slv_rdbuf_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for read-buffer operations.*/ + volatile uint32_t slv_wrbuf_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for write-buffer operations.*/ + volatile uint32_t slv_rdsta_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for read-status operations.*/ + volatile uint32_t slv_wrsta_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for write-status operations.*/ + volatile uint32_t slv_wr_addr_bitlen: 6; /*In the slave mode it is the address length in bits for write-buffer operation. The register value shall be (bit_num-1).*/ + volatile uint32_t slv_rd_addr_bitlen: 6; /*In the slave mode it is the address length in bits for read-buffer operation. The register value shall be (bit_num-1).*/ + volatile uint32_t reserved16: 9; /*reserved*/ + volatile uint32_t slv_status_readback: 1; /*In the slave mode 1:read register of SPI_SLV_WR_STATUS 0: read register of SPI_RD_STATUS.*/ + volatile uint32_t slv_status_fast_en: 1; /*In the slave mode enable fast read status.*/ + volatile uint32_t slv_status_bitlen: 5; /*In the slave mode it is the length of status bit.*/ + }; + volatile uint32_t val; + }slave1; + union { + struct { + volatile uint32_t slv_rdsta_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for read-status operations. The register value shall be (cycle_num-1).*/ + volatile uint32_t slv_wrsta_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for write-status operations. The register value shall be (cycle_num-1).*/ + volatile uint32_t slv_rdbuf_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for read-buffer operations. The register value shall be (cycle_num-1).*/ + volatile uint32_t slv_wrbuf_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for write-buffer operations. The register value shall be (cycle_num-1).*/ + }; + volatile uint32_t val; + }slave2; + union { + struct { + volatile uint32_t slv_rdbuf_cmd_value: 8; /*In the slave mode it is the value of read-buffer command.*/ + volatile uint32_t slv_wrbuf_cmd_value: 8; /*In the slave mode it is the value of write-buffer command.*/ + volatile uint32_t slv_rdsta_cmd_value: 8; /*In the slave mode it is the value of read-status command.*/ + volatile uint32_t slv_wrsta_cmd_value: 8; /*In the slave mode it is the value of write-status command.*/ + }; + volatile uint32_t val; + }slave3; + union { + struct { + volatile uint32_t slv_wrbuf_dbitlen:24; /*In the slave mode it is the length in bits for write-buffer operations. The register value shall be (bit_num-1).*/ + volatile uint32_t reserved24: 8; /*reserved*/ + }; + volatile uint32_t val; + }slv_wrbuf_dlen; + union { + struct { + volatile uint32_t slv_rdbuf_dbitlen:24; /*In the slave mode it is the length in bits for read-buffer operations. The register value shall be (bit_num-1).*/ + volatile uint32_t reserved24: 8; /*reserved*/ + }; + volatile uint32_t val; + }slv_rdbuf_dlen; + union { + struct { + volatile uint32_t cache_req_en: 1; /*For SPI0 Cache access enable 1: enable 0:disable.*/ + volatile uint32_t cache_usr_cmd_4byte: 1; /*For SPI0 cache read flash with 4 bytes command 1: enable 0:disable.*/ + volatile uint32_t cache_flash_usr_cmd: 1; /*For SPI0 cache read flash for user define command 1: enable 0:disable.*/ + volatile uint32_t cache_flash_pes_en: 1; /*For SPI0 spi1 send suspend command before cache read flash 1: enable 0:disable.*/ + volatile uint32_t reserved4: 28; /*reserved*/ + }; + volatile uint32_t val; + }cache_fctrl; + union { + struct { + volatile uint32_t reserved0: 1; /*reserved*/ + volatile uint32_t usr_sram_dio: 1; /*For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable*/ + volatile uint32_t usr_sram_qio: 1; /*For SPI0 In the spi sram mode spi quad I/O mode enable 1: enable 0:disable*/ + volatile uint32_t usr_wr_sram_dummy: 1; /*For SPI0 In the spi sram mode it is the enable bit of dummy phase for write operations.*/ + volatile uint32_t usr_rd_sram_dummy: 1; /*For SPI0 In the spi sram mode it is the enable bit of dummy phase for read operations.*/ + volatile uint32_t cache_sram_usr_rcmd: 1; /*For SPI0 In the spi sram mode cache read sram for user define command.*/ + volatile uint32_t sram_bytes_len: 8; /*For SPI0 In the sram mode it is the byte length of spi read sram data.*/ + volatile uint32_t sram_dummy_cyclelen: 8; /*For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).*/ + volatile uint32_t sram_addr_bitlen: 6; /*For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).*/ + volatile uint32_t cache_sram_usr_wcmd: 1; /*For SPI0 In the spi sram mode cache write sram for user define command*/ + volatile uint32_t reserved29: 3; /*reserved*/ + }; + volatile uint32_t val; + }cache_sctrl; + union { + struct { + volatile uint32_t sram_dio: 1; /*For SPI0 SRAM DIO mode enable . SRAM DIO enable command will be send when the bit is set. The bit will be cleared once the operation done.*/ + volatile uint32_t sram_qio: 1; /*For SPI0 SRAM QIO mode enable . SRAM QIO enable command will be send when the bit is set. The bit will be cleared once the operation done.*/ + volatile uint32_t reserved2: 2; /*For SPI0 SRAM write enable . SRAM write operation will be triggered when the bit is set. The bit will be cleared once the operation done.*/ + volatile uint32_t sram_rstio: 1; /*For SPI0 SRAM IO mode reset enable. SRAM IO mode reset operation will be triggered when the bit is set. The bit will be cleared once the operation done*/ + volatile uint32_t reserved5: 27; /*reserved*/ + }; + volatile uint32_t val; + }sram_cmd; + union { + struct { + volatile uint32_t cache_sram_usr_rd_cmd_value: 16; /*For SPI0 When cache mode is enable it is the read command value of command phase for SRAM.*/ + volatile uint32_t reserved16: 12; /*reserved*/ + volatile uint32_t cache_sram_usr_rd_cmd_bitlen: 4; /*For SPI0 When cache mode is enable it is the length in bits of command phase for SRAM. The register value shall be (bit_num-1).*/ + }; + volatile uint32_t val; + }sram_drd_cmd; + union { + struct { + volatile uint32_t cache_sram_usr_wr_cmd_value: 16; /*For SPI0 When cache mode is enable it is the write command value of command phase for SRAM.*/ + volatile uint32_t reserved16: 12; /*reserved*/ + volatile uint32_t cache_sram_usr_wr_cmd_bitlen: 4; /*For SPI0 When cache mode is enable it is the in bits of command phase for SRAM. The register value shall be (bit_num-1).*/ + }; + volatile uint32_t val; + }sram_dwr_cmd; + union { + struct { + volatile uint32_t slv_rdata_bit:24; /*In the slave mode it is the bit length of read data. The value is the length - 1.*/ + volatile uint32_t reserved24: 8; /*reserved*/ + }; + volatile uint32_t val; + }slv_rd_bit; + volatile uint32_t reserved_68; + volatile uint32_t reserved_6c; + volatile uint32_t reserved_70; + volatile uint32_t reserved_74; + volatile uint32_t reserved_78; + volatile uint32_t reserved_7c; + volatile uint32_t data_buf[16]; /*data buffer*/ + volatile uint32_t tx_crc; /*For SPI1 the value of crc32 for 256 bits data.*/ + volatile uint32_t reserved_c4; + volatile uint32_t reserved_c8; + volatile uint32_t reserved_cc; + volatile uint32_t reserved_d0; + volatile uint32_t reserved_d4; + volatile uint32_t reserved_d8; + volatile uint32_t reserved_dc; + volatile uint32_t reserved_e0; + volatile uint32_t reserved_e4; + volatile uint32_t reserved_e8; + volatile uint32_t reserved_ec; + union { + struct { + volatile uint32_t t_pp_time: 12; /*page program delay time by system clock.*/ + volatile uint32_t reserved12: 4; /*reserved*/ + volatile uint32_t t_pp_shift: 4; /*page program delay time shift .*/ + volatile uint32_t reserved20:11; /*reserved*/ + volatile uint32_t t_pp_ena: 1; /*page program delay enable.*/ + }; + volatile uint32_t val; + }ext0; + union { + struct { + volatile uint32_t t_erase_time: 12; /*erase flash delay time by system clock.*/ + volatile uint32_t reserved12: 4; /*reserved*/ + volatile uint32_t t_erase_shift: 4; /*erase flash delay time shift.*/ + volatile uint32_t reserved20: 11; /*reserved*/ + volatile uint32_t t_erase_ena: 1; /*erase flash delay enable.*/ + }; + volatile uint32_t val; + }ext1; + union { + struct { + volatile uint32_t st: 3; /*The status of spi state machine .*/ + volatile uint32_t reserved3: 29; /*reserved*/ + }; + volatile uint32_t val; + }ext2; + union { + struct { + volatile uint32_t int_hold_ena: 2; /*This register is for two SPI masters to share the same cs clock and data signals. The bits of one SPI are set if the other SPI is busy the SPI will be hold. 1(3): hold at ,idle, phase 2: hold at ,prepare, phase.*/ + volatile uint32_t reserved2: 30; /*reserved*/ + }; + volatile uint32_t val; + }ext3; + union { + struct { + volatile uint32_t reserved0: 2; /*reserved*/ + volatile uint32_t in_rst: 1; /*The bit is used to reset in dma fsm and in data fifo pointer.*/ + volatile uint32_t out_rst: 1; /*The bit is used to reset out dma fsm and out data fifo pointer.*/ + volatile uint32_t ahbm_fifo_rst: 1; /*reset spi dma ahb master fifo pointer.*/ + volatile uint32_t ahbm_rst: 1; /*reset spi dma ahb master.*/ + volatile uint32_t in_loop_test: 1; /*Set bit to test in link.*/ + volatile uint32_t out_loop_test: 1; /*Set bit to test out link.*/ + volatile uint32_t out_auto_wrback: 1; /*when the link is empty jump to next automatically.*/ + volatile uint32_t out_eof_mode: 1; /*out eof flag generation mode . 1: when dma pop all data from fifo 0:when ahb push all data to fifo.*/ + volatile uint32_t outdscr_burst_en: 1; /*read descriptor use burst mode when read data for memory.*/ + volatile uint32_t indscr_burst_en: 1; /*read descriptor use burst mode when write data to memory.*/ + volatile uint32_t out_data_burst_en: 1; /*spi dma read data from memory in burst mode.*/ + volatile uint32_t reserved13: 1; /*reserved*/ + volatile uint32_t dma_rx_stop: 1; /*spi dma read data stop when in continue tx/rx mode.*/ + volatile uint32_t dma_tx_stop: 1; /*spi dma write data stop when in continue tx/rx mode.*/ + volatile uint32_t dma_continue: 1; /*spi dma continue tx/rx data.*/ + volatile uint32_t reserved17: 15; /*reserved*/ + }; + volatile uint32_t val; + }dma_conf; + union { + struct { + volatile uint32_t outlink_addr: 20; /*The address of the first outlink descriptor.*/ + volatile uint32_t reserved20: 8; /*reserved*/ + volatile uint32_t outlink_stop: 1; /*Set the bit to stop to use outlink descriptor.*/ + volatile uint32_t outlink_start: 1; /*Set the bit to start to use outlink descriptor.*/ + volatile uint32_t outlink_restart: 1; /*Set the bit to mount on new outlink descriptors.*/ + volatile uint32_t reserved31: 1; /*reserved*/ + }; + volatile uint32_t val; + }dma_out_link; + union { + struct { + volatile uint32_t inlink_addr: 20; /*The address of the first inlink descriptor.*/ + volatile uint32_t inlink_auto_ret: 1; /*when the bit is set inlink descriptor returns to the next descriptor while a packet is wrong*/ + volatile uint32_t reserved21: 7; /*reserved*/ + volatile uint32_t inlink_stop: 1; /*Set the bit to stop to use inlink descriptor.*/ + volatile uint32_t inlink_start: 1; /*Set the bit to start to use inlink descriptor.*/ + volatile uint32_t inlink_restart: 1; /*Set the bit to mount on new inlink descriptors.*/ + volatile uint32_t reserved31: 1; /*reserved*/ + }; + volatile uint32_t val; + }dma_in_link; + union { + struct { + volatile uint32_t dma_rx_en: 1; /*spi dma read data status bit.*/ + volatile uint32_t dma_tx_en: 1; /*spi dma write data status bit.*/ + volatile uint32_t reserved2: 30; /*spi dma read data from memory count.*/ + }; + volatile uint32_t val; + }dma_status; + union { + struct { + volatile uint32_t inlink_dscr_empty_int_ena: 1; /*The enable bit for lack of enough inlink descriptors.*/ + volatile uint32_t outlink_dscr_error_int_ena: 1; /*The enable bit for outlink descriptor error.*/ + volatile uint32_t inlink_dscr_error_int_ena: 1; /*The enable bit for inlink descriptor error.*/ + volatile uint32_t in_done_int_ena: 1; /*The enable bit for completing usage of a inlink descriptor.*/ + volatile uint32_t in_err_eof_int_ena: 1; /*The enable bit for receiving error.*/ + volatile uint32_t in_suc_eof_int_ena: 1; /*The enable bit for completing receiving all the packets from host.*/ + volatile uint32_t out_done_int_ena: 1; /*The enable bit for completing usage of a outlink descriptor .*/ + volatile uint32_t out_eof_int_ena: 1; /*The enable bit for sending a packet to host done.*/ + volatile uint32_t out_total_eof_int_ena: 1; /*The enable bit for sending all the packets to host done.*/ + volatile uint32_t reserved9: 23; /*reserved*/ + }; + volatile uint32_t val; + }dma_int_ena; + union { + struct { + volatile uint32_t inlink_dscr_empty_int_raw: 1; /*The raw bit for lack of enough inlink descriptors.*/ + volatile uint32_t outlink_dscr_error_int_raw: 1; /*The raw bit for outlink descriptor error.*/ + volatile uint32_t inlink_dscr_error_int_raw: 1; /*The raw bit for inlink descriptor error.*/ + volatile uint32_t in_done_int_raw: 1; /*The raw bit for completing usage of a inlink descriptor.*/ + volatile uint32_t in_err_eof_int_raw: 1; /*The raw bit for receiving error.*/ + volatile uint32_t in_suc_eof_int_raw: 1; /*The raw bit for completing receiving all the packets from host.*/ + volatile uint32_t out_done_int_raw: 1; /*The raw bit for completing usage of a outlink descriptor.*/ + volatile uint32_t out_eof_int_raw: 1; /*The raw bit for sending a packet to host done.*/ + volatile uint32_t out_total_eof_int_raw: 1; /*The raw bit for sending all the packets to host done.*/ + volatile uint32_t reserved9: 23; /*reserved*/ + }; + volatile uint32_t val; + }dma_int_raw; + union { + struct { + volatile uint32_t inlink_dscr_empty_int_st: 1; /*The status bit for lack of enough inlink descriptors.*/ + volatile uint32_t outlink_dscr_error_int_st: 1; /*The status bit for outlink descriptor error.*/ + volatile uint32_t inlink_dscr_error_int_st: 1; /*The status bit for inlink descriptor error.*/ + volatile uint32_t in_done_int_st: 1; /*The status bit for completing usage of a inlink descriptor.*/ + volatile uint32_t in_err_eof_int_st: 1; /*The status bit for receiving error.*/ + volatile uint32_t in_suc_eof_int_st: 1; /*The status bit for completing receiving all the packets from host.*/ + volatile uint32_t out_done_int_st: 1; /*The status bit for completing usage of a outlink descriptor.*/ + volatile uint32_t out_eof_int_st: 1; /*The status bit for sending a packet to host done.*/ + volatile uint32_t out_total_eof_int_st: 1; /*The status bit for sending all the packets to host done.*/ + volatile uint32_t reserved9: 23; /*reserved*/ + }; + volatile uint32_t val; + }dma_int_st; + union { + struct { + volatile uint32_t inlink_dscr_empty_int_clr: 1; /*The clear bit for lack of enough inlink descriptors.*/ + volatile uint32_t outlink_dscr_error_int_clr: 1; /*The clear bit for outlink descriptor error.*/ + volatile uint32_t inlink_dscr_error_int_clr: 1; /*The clear bit for inlink descriptor error.*/ + volatile uint32_t in_done_int_clr: 1; /*The clear bit for completing usage of a inlink descriptor.*/ + volatile uint32_t in_err_eof_int_clr: 1; /*The clear bit for receiving error.*/ + volatile uint32_t in_suc_eof_int_clr: 1; /*The clear bit for completing receiving all the packets from host.*/ + volatile uint32_t out_done_int_clr: 1; /*The clear bit for completing usage of a outlink descriptor.*/ + volatile uint32_t out_eof_int_clr: 1; /*The clear bit for sending a packet to host done.*/ + volatile uint32_t out_total_eof_int_clr: 1; /*The clear bit for sending all the packets to host done.*/ + volatile uint32_t reserved9: 23; /*reserved*/ + }; + volatile uint32_t val; + }dma_int_clr; + volatile uint32_t dma_in_err_eof_des_addr; /*The inlink descriptor address when spi dma produce receiving error.*/ + volatile uint32_t dma_in_suc_eof_des_addr; /*The last inlink descriptor address when spi dma produce from_suc_eof.*/ + volatile uint32_t dma_inlink_dscr; /*The content of current in descriptor pointer.*/ + volatile uint32_t dma_inlink_dscr_bf0; /*The content of next in descriptor pointer.*/ + volatile uint32_t dma_inlink_dscr_bf1; /*The content of current in descriptor data buffer pointer.*/ + volatile uint32_t dma_out_eof_bfr_des_addr; /*The address of buffer relative to the outlink descriptor that produce eof.*/ + volatile uint32_t dma_out_eof_des_addr; /*The last outlink descriptor address when spi dma produce to_eof.*/ + volatile uint32_t dma_outlink_dscr; /*The content of current out descriptor pointer.*/ + volatile uint32_t dma_outlink_dscr_bf0; /*The content of next out descriptor pointer.*/ + volatile uint32_t dma_outlink_dscr_bf1; /*The content of current out descriptor data buffer pointer.*/ + volatile uint32_t dma_rx_status; /*spi dma read data from memory status.*/ + volatile uint32_t dma_tx_status; /*spi dma write data to memory status.*/ + volatile uint32_t reserved_150; + volatile uint32_t reserved_154; + volatile uint32_t reserved_158; + volatile uint32_t reserved_15c; + volatile uint32_t reserved_160; + volatile uint32_t reserved_164; + volatile uint32_t reserved_168; + volatile uint32_t reserved_16c; + volatile uint32_t reserved_170; + volatile uint32_t reserved_174; + volatile uint32_t reserved_178; + volatile uint32_t reserved_17c; + volatile uint32_t reserved_180; + volatile uint32_t reserved_184; + volatile uint32_t reserved_188; + volatile uint32_t reserved_18c; + volatile uint32_t reserved_190; + volatile uint32_t reserved_194; + volatile uint32_t reserved_198; + volatile uint32_t reserved_19c; + volatile uint32_t reserved_1a0; + volatile uint32_t reserved_1a4; + volatile uint32_t reserved_1a8; + volatile uint32_t reserved_1ac; + volatile uint32_t reserved_1b0; + volatile uint32_t reserved_1b4; + volatile uint32_t reserved_1b8; + volatile uint32_t reserved_1bc; + volatile uint32_t reserved_1c0; + volatile uint32_t reserved_1c4; + volatile uint32_t reserved_1c8; + volatile uint32_t reserved_1cc; + volatile uint32_t reserved_1d0; + volatile uint32_t reserved_1d4; + volatile uint32_t reserved_1d8; + volatile uint32_t reserved_1dc; + volatile uint32_t reserved_1e0; + volatile uint32_t reserved_1e4; + volatile uint32_t reserved_1e8; + volatile uint32_t reserved_1ec; + volatile uint32_t reserved_1f0; + volatile uint32_t reserved_1f4; + volatile uint32_t reserved_1f8; + volatile uint32_t reserved_1fc; + volatile uint32_t reserved_200; + volatile uint32_t reserved_204; + volatile uint32_t reserved_208; + volatile uint32_t reserved_20c; + volatile uint32_t reserved_210; + volatile uint32_t reserved_214; + volatile uint32_t reserved_218; + volatile uint32_t reserved_21c; + volatile uint32_t reserved_220; + volatile uint32_t reserved_224; + volatile uint32_t reserved_228; + volatile uint32_t reserved_22c; + volatile uint32_t reserved_230; + volatile uint32_t reserved_234; + volatile uint32_t reserved_238; + volatile uint32_t reserved_23c; + volatile uint32_t reserved_240; + volatile uint32_t reserved_244; + volatile uint32_t reserved_248; + volatile uint32_t reserved_24c; + volatile uint32_t reserved_250; + volatile uint32_t reserved_254; + volatile uint32_t reserved_258; + volatile uint32_t reserved_25c; + volatile uint32_t reserved_260; + volatile uint32_t reserved_264; + volatile uint32_t reserved_268; + volatile uint32_t reserved_26c; + volatile uint32_t reserved_270; + volatile uint32_t reserved_274; + volatile uint32_t reserved_278; + volatile uint32_t reserved_27c; + volatile uint32_t reserved_280; + volatile uint32_t reserved_284; + volatile uint32_t reserved_288; + volatile uint32_t reserved_28c; + volatile uint32_t reserved_290; + volatile uint32_t reserved_294; + volatile uint32_t reserved_298; + volatile uint32_t reserved_29c; + volatile uint32_t reserved_2a0; + volatile uint32_t reserved_2a4; + volatile uint32_t reserved_2a8; + volatile uint32_t reserved_2ac; + volatile uint32_t reserved_2b0; + volatile uint32_t reserved_2b4; + volatile uint32_t reserved_2b8; + volatile uint32_t reserved_2bc; + volatile uint32_t reserved_2c0; + volatile uint32_t reserved_2c4; + volatile uint32_t reserved_2c8; + volatile uint32_t reserved_2cc; + volatile uint32_t reserved_2d0; + volatile uint32_t reserved_2d4; + volatile uint32_t reserved_2d8; + volatile uint32_t reserved_2dc; + volatile uint32_t reserved_2e0; + volatile uint32_t reserved_2e4; + volatile uint32_t reserved_2e8; + volatile uint32_t reserved_2ec; + volatile uint32_t reserved_2f0; + volatile uint32_t reserved_2f4; + volatile uint32_t reserved_2f8; + volatile uint32_t reserved_2fc; + volatile uint32_t reserved_300; + volatile uint32_t reserved_304; + volatile uint32_t reserved_308; + volatile uint32_t reserved_30c; + volatile uint32_t reserved_310; + volatile uint32_t reserved_314; + volatile uint32_t reserved_318; + volatile uint32_t reserved_31c; + volatile uint32_t reserved_320; + volatile uint32_t reserved_324; + volatile uint32_t reserved_328; + volatile uint32_t reserved_32c; + volatile uint32_t reserved_330; + volatile uint32_t reserved_334; + volatile uint32_t reserved_338; + volatile uint32_t reserved_33c; + volatile uint32_t reserved_340; + volatile uint32_t reserved_344; + volatile uint32_t reserved_348; + volatile uint32_t reserved_34c; + volatile uint32_t reserved_350; + volatile uint32_t reserved_354; + volatile uint32_t reserved_358; + volatile uint32_t reserved_35c; + volatile uint32_t reserved_360; + volatile uint32_t reserved_364; + volatile uint32_t reserved_368; + volatile uint32_t reserved_36c; + volatile uint32_t reserved_370; + volatile uint32_t reserved_374; + volatile uint32_t reserved_378; + volatile uint32_t reserved_37c; + volatile uint32_t reserved_380; + volatile uint32_t reserved_384; + volatile uint32_t reserved_388; + volatile uint32_t reserved_38c; + volatile uint32_t reserved_390; + volatile uint32_t reserved_394; + volatile uint32_t reserved_398; + volatile uint32_t reserved_39c; + volatile uint32_t reserved_3a0; + volatile uint32_t reserved_3a4; + volatile uint32_t reserved_3a8; + volatile uint32_t reserved_3ac; + volatile uint32_t reserved_3b0; + volatile uint32_t reserved_3b4; + volatile uint32_t reserved_3b8; + volatile uint32_t reserved_3bc; + volatile uint32_t reserved_3c0; + volatile uint32_t reserved_3c4; + volatile uint32_t reserved_3c8; + volatile uint32_t reserved_3cc; + volatile uint32_t reserved_3d0; + volatile uint32_t reserved_3d4; + volatile uint32_t reserved_3d8; + volatile uint32_t reserved_3dc; + volatile uint32_t reserved_3e0; + volatile uint32_t reserved_3e4; + volatile uint32_t reserved_3e8; + volatile uint32_t reserved_3ec; + volatile uint32_t reserved_3f0; + volatile uint32_t reserved_3f4; + volatile uint32_t reserved_3f8; + union { + struct { + volatile uint32_t date: 28; /*SPI register version.*/ + volatile uint32_t reserved28: 4; /*reserved*/ + }; + volatile uint32_t val; + }date; +} spi_dev_t; +extern volatile spi_dev_t SPI0; /* SPI0 IS FOR INTERNAL USE*/ +extern volatile spi_dev_t SPI1; +extern volatile spi_dev_t SPI2; +extern volatile spi_dev_t SPI3; +#endif /* _SOC_SPI_STRUCT_H_ */ diff --git a/components/esp32/include/soc/timer_group_struct.h b/components/esp32/include/soc/timer_group_struct.h new file mode 100644 index 000000000..b385f04f7 --- /dev/null +++ b/components/esp32/include/soc/timer_group_struct.h @@ -0,0 +1,195 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_TIMG_STRUCT_H_ +#define _SOC_TIMG_STRUCT_H_ +typedef struct { + struct{ + union { + struct { + volatile uint32_t reserved0: 10; + volatile uint32_t alarm_en: 1; /*When set alarm is enabled*/ + volatile uint32_t level_int_en: 1; /*When set level type interrupt will be generated during alarm*/ + volatile uint32_t edge_int_en: 1; /*When set edge type interrupt will be generated during alarm*/ + volatile uint32_t divider: 16; /*Timer clock (T0/1_clk) pre-scale value.*/ + volatile uint32_t autoreload: 1; /*When set timer 0/1 auto-reload at alarming is enabled*/ + volatile uint32_t increase: 1; /*When set timer 0/1 time-base counter increment. When cleared timer 0 time-base counter decrement.*/ + volatile uint32_t enable: 1; /*When set timer 0/1 time-base counter is enabled*/ + }; + volatile uint32_t val; + }config; + volatile uint32_t timer_cnt_low; /*Register to store timer 0/1 time-base counter current value lower 32 bits.*/ + volatile uint32_t timer_cnt_high; /*Register to store timer 0 time-base counter current value higher 32 bits.*/ + volatile uint32_t timer_update; /*Write any value will trigger a timer 0 time-base counter value update (timer 0 current value will be stored in registers above)*/ + volatile uint32_t timer_alarm_low; /*Timer 0 time-base counter value lower 32 bits that will trigger the alarm*/ + volatile uint32_t timer_alarm_high; /*Timer 0 time-base counter value higher 32 bits that will trigger the alarm*/ + volatile uint32_t timer_load_low; /*Lower 32 bits of the value that will load into timer 0 time-base counter*/ + volatile uint32_t timer_load_high; /*higher 32 bits of the value that will load into timer 0 time-base counter*/ + volatile uint32_t timer_reload; /*Write any value will trigger timer 0 time-base counter reload*/ + }hw_timer[2]; + union { + struct { + volatile uint32_t reserved0: 14; + volatile uint32_t wdt_flashboot_mod_en: 1; /*When set flash boot protection is enabled*/ + volatile uint32_t wdt_sys_reset_length: 3; /*length of system reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us*/ + volatile uint32_t wdt_cpu_reset_length: 3; /*length of CPU reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us*/ + volatile uint32_t wdt_level_int_en: 1; /*When set level type interrupt generation is enabled*/ + volatile uint32_t wdt_edge_int_en: 1; /*When set edge type interrupt generation is enabled*/ + volatile uint32_t wdt_stg3: 2; /*Stage 3 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ + volatile uint32_t wdt_stg2: 2; /*Stage 2 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ + volatile uint32_t wdt_stg1: 2; /*Stage 1 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ + volatile uint32_t wdt_stg0: 2; /*Stage 0 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ + volatile uint32_t wdt_en: 1; /*When set SWDT is enabled*/ + }; + volatile uint32_t val; + }wdt_config0; + union { + struct { + volatile uint32_t reserved0: 16; + volatile uint32_t wdt_clk_prescale:16; /*SWDT clock prescale value. Period = 12.5ns * value stored in this register*/ + }; + volatile uint32_t val; + }wdt_config1; + volatile uint32_t wdt_config2; /*Stage 0 timeout value in SWDT clock cycles*/ + volatile uint32_t wdt_config3; /*Stage 1 timeout value in SWDT clock cycles*/ + volatile uint32_t wdt_config4; /*Stage 2 timeout value in SWDT clock cycles*/ + volatile uint32_t wdt_config5; /*Stage 3 timeout value in SWDT clock cycles*/ + volatile uint32_t wdt_feed; /*Write any value will feed SWDT*/ + volatile uint32_t wdt_wprotect; /*If change its value from default then write protection is on.*/ + union { + struct { + volatile uint32_t reserved0: 12; + volatile uint32_t rtc_cali_start_cycling: 1; + volatile uint32_t rtc_cali_clk_sel: 2; + volatile uint32_t rtc_cali_rdy: 1; + volatile uint32_t rtc_cali_max: 15; + volatile uint32_t rtc_cali_start: 1; + }; + volatile uint32_t val; + }rtc_cali_cfg; + union { + struct { + volatile uint32_t reserved0: 7; + volatile uint32_t rtc_cali_value:25; + }; + volatile uint32_t val; + }rtc_cali_cfg1; + union { + struct { + volatile uint32_t reserved0: 7; + volatile uint32_t lact_rtc_only: 1; + volatile uint32_t lact_cpst_en: 1; + volatile uint32_t lact_lac_en: 1; + volatile uint32_t lact_alarm_en: 1; + volatile uint32_t lact_level_int_en: 1; + volatile uint32_t lact_edge_int_en: 1; + volatile uint32_t lact_divider: 16; + volatile uint32_t lact_autoreload: 1; + volatile uint32_t lact_increase: 1; + volatile uint32_t lact_en: 1; + }; + volatile uint32_t val; + }lactconfig; + union { + struct { + volatile uint32_t reserved0: 6; + volatile uint32_t lact_rtc_step_len:26; + }; + volatile uint32_t val; + }lactrtc; + volatile uint32_t lactlo; /**/ + volatile uint32_t lacthi; /**/ + volatile uint32_t lactupdate; /**/ + volatile uint32_t lactalarmlo; /**/ + volatile uint32_t lactalarmhi; /**/ + volatile uint32_t lactloadlo; /**/ + volatile uint32_t lactloadhi; /**/ + volatile uint32_t lactload; /**/ + union { + struct { + volatile uint32_t t0_int_ena: 1; /*interrupt when timer0 alarm*/ + volatile uint32_t t1_int_ena: 1; /*interrupt when timer1 alarm*/ + volatile uint32_t wdt_int_ena: 1; /*Interrupt when an interrupt stage timeout*/ + volatile uint32_t lact_int_ena: 1; + volatile uint32_t reserved4: 28; + }; + volatile uint32_t val; + }int_ena_timers; + union { + struct { + volatile uint32_t t0_int_raw: 1; /*interrupt when timer0 alarm*/ + volatile uint32_t t1_int_raw: 1; /*interrupt when timer1 alarm*/ + volatile uint32_t wdt_int_raw: 1; /*Interrupt when an interrupt stage timeout*/ + volatile uint32_t lact_int_raw: 1; + volatile uint32_t reserved4: 28; + }; + volatile uint32_t val; + }int_raw_timers; + union { + struct { + volatile uint32_t t0_int_st: 1; /*interrupt when timer0 alarm*/ + volatile uint32_t t1_int_st: 1; /*interrupt when timer1 alarm*/ + volatile uint32_t wdt_int_st: 1; /*Interrupt when an interrupt stage timeout*/ + volatile uint32_t lact_int_st: 1; + volatile uint32_t reserved4: 28; + }; + volatile uint32_t val; + }int_st_timers; + union { + struct { + volatile uint32_t t0_int_clr: 1; /*interrupt when timer0 alarm*/ + volatile uint32_t t1_int_clr: 1; /*interrupt when timer1 alarm*/ + volatile uint32_t wdt_int_clr: 1; /*Interrupt when an interrupt stage timeout*/ + volatile uint32_t lact_int_clr: 1; + volatile uint32_t reserved4: 28; + }; + volatile uint32_t val; + }int_clr_timers; + volatile uint32_t reserved_a8; + volatile uint32_t reserved_ac; + volatile uint32_t reserved_b0; + volatile uint32_t reserved_b4; + volatile uint32_t reserved_b8; + volatile uint32_t reserved_bc; + volatile uint32_t reserved_c0; + volatile uint32_t reserved_c4; + volatile uint32_t reserved_c8; + volatile uint32_t reserved_cc; + volatile uint32_t reserved_d0; + volatile uint32_t reserved_d4; + volatile uint32_t reserved_d8; + volatile uint32_t reserved_dc; + volatile uint32_t reserved_e0; + volatile uint32_t reserved_e4; + volatile uint32_t reserved_e8; + volatile uint32_t reserved_ec; + volatile uint32_t reserved_f0; + volatile uint32_t reserved_f4; + union { + struct { + volatile uint32_t date:28; /*Version of this regfile*/ + volatile uint32_t reserved28: 4; + }; + volatile uint32_t val; + }timg_date; + union { + struct { + volatile uint32_t reserved0: 31; + volatile uint32_t clk_en: 1; /*Force clock enable for this regfile*/ + }; + volatile uint32_t val; + }clk; +} timg_dev_t; +extern volatile timg_dev_t TIMERG0; +extern volatile timg_dev_t TIMERG1; +#endif /* _SOC_TIMG_STRUCT_H_ */ diff --git a/components/esp32/include/soc/uart_struct.h b/components/esp32/include/soc/uart_struct.h new file mode 100644 index 000000000..cd756bec3 --- /dev/null +++ b/components/esp32/include/soc/uart_struct.h @@ -0,0 +1,365 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_UART_STRUCT_H_ +#define _SOC_UART_STRUCT_H_ +typedef struct { + union { + struct { + volatile uint32_t fifo_rw_byte: 8; /*This register stores one byte data read by rx fifo.*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }fifo; + union { + struct { + volatile uint32_t rxfifo_full_int_raw: 1; /*This interrupt raw bit turns to high level when receiver receives more data than (rx_flow_thrhd_h3 rx_flow_thrhd).*/ + volatile uint32_t txfifo_empty_int_raw: 1; /*This interrupt raw bit turns to high level when the amount of data in transmitter's fifo is less than ((tx_mem_cnttxfifo_cnt) .*/ + volatile uint32_t parity_err_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects the parity error of data.*/ + volatile uint32_t frm_err_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects data's frame error .*/ + volatile uint32_t rxfifo_ovf_int_raw: 1; /*This interrupt raw bit turns to high level when receiver receives more data than the fifo can store.*/ + volatile uint32_t dsr_chg_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of dsrn signal.*/ + volatile uint32_t cts_chg_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of ctsn signal.*/ + volatile uint32_t brk_det_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects the 0 after the stop bit.*/ + volatile uint32_t rxfifo_tout_int_raw: 1; /*This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.*/ + volatile uint32_t sw_xon_int_raw: 1; /*This interrupt raw bit turns to high level when receiver receives xoff char with uart_sw_flow_con_en is set to 1.*/ + volatile uint32_t sw_xoff_int_raw: 1; /*This interrupt raw bit turns to high level when receiver receives xon char with uart_sw_flow_con_en is set to 1.*/ + volatile uint32_t glitch_det_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects the start bit.*/ + volatile uint32_t tx_brk_done_int_raw: 1; /*This interrupt raw bit turns to high level when transmitter completes sending 0 after all the data in transmitter's fifo are send.*/ + volatile uint32_t tx_brk_idle_done_int_raw: 1; /*This interrupt raw bit turns to high level when transmitter has kept the shortest duration after the last data has been send.*/ + volatile uint32_t tx_done_int_raw: 1; /*This interrupt raw bit turns to high level when transmitter has send all the data in fifo.*/ + volatile uint32_t rs485_parity_err_int_raw: 1; /*This interrupt raw bit turns to high level when rs485 detects the parity error.*/ + volatile uint32_t rs485_frm_err_int_raw: 1; /*This interrupt raw bit turns to high level when rs485 detects the data frame error.*/ + volatile uint32_t rs485_clash_int_raw: 1; /*This interrupt raw bit turns to high level when rs485 detects the clash between transmitter and receiver.*/ + volatile uint32_t at_cmd_char_det_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects the configured at_cmd chars.*/ + volatile uint32_t reserved19: 13; + }; + volatile uint32_t val; + }int_raw; + union { + struct { + volatile uint32_t rxfifo_full_int_st: 1; /*This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.*/ + volatile uint32_t txfifo_empty_int_st: 1; /*This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1.*/ + volatile uint32_t parity_err_int_st: 1; /*This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.*/ + volatile uint32_t frm_err_int_st: 1; /*This is the status bit for frm_err_int_raw when fm_err_int_ena is set to 1.*/ + volatile uint32_t rxfifo_ovf_int_st: 1; /*This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.*/ + volatile uint32_t dsr_chg_int_st: 1; /*This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/ + volatile uint32_t cts_chg_int_st: 1; /*This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/ + volatile uint32_t brk_det_int_st: 1; /*This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/ + volatile uint32_t rxfifo_tout_int_st: 1; /*This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.*/ + volatile uint32_t sw_xon_int_st: 1; /*This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/ + volatile uint32_t sw_xoff_int_st: 1; /*This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/ + volatile uint32_t glitch_det_int_st: 1; /*This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.*/ + volatile uint32_t tx_brk_done_int_st: 1; /*This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.*/ + volatile uint32_t tx_brk_idle_done_int_st: 1; /*This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/ + volatile uint32_t tx_done_int_st: 1; /*This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/ + volatile uint32_t rs485_parity_err_int_st: 1; /*This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.*/ + volatile uint32_t rs485_frm_err_int_st: 1; /*This is the status bit for rs485_fm_err_int_raw when rs485_fm_err_int_ena is set to 1.*/ + volatile uint32_t rs485_clash_int_st: 1; /*This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.*/ + volatile uint32_t at_cmd_char_det_int_st: 1; /*This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.*/ + volatile uint32_t reserved19: 13; + }; + volatile uint32_t val; + }int_st; + union { + struct { + volatile uint32_t rxfifo_full_int_ena: 1; /*This is the enable bit for rxfifo_full_int_st register.*/ + volatile uint32_t txfifo_empty_int_ena: 1; /*This is the enable bit for rxfifo_full_int_st register.*/ + volatile uint32_t parity_err_int_ena: 1; /*This is the enable bit for parity_err_int_st register.*/ + volatile uint32_t frm_err_int_ena: 1; /*This is the enable bit for frm_err_int_st register.*/ + volatile uint32_t rxfifo_ovf_int_ena: 1; /*This is the enable bit for rxfifo_ovf_int_st register.*/ + volatile uint32_t dsr_chg_int_ena: 1; /*This is the enable bit for dsr_chg_int_st register.*/ + volatile uint32_t cts_chg_int_ena: 1; /*This is the enable bit for cts_chg_int_st register.*/ + volatile uint32_t brk_det_int_ena: 1; /*This is the enable bit for brk_det_int_st register.*/ + volatile uint32_t rxfifo_tout_int_ena: 1; /*This is the enable bit for rxfifo_tout_int_st register.*/ + volatile uint32_t sw_xon_int_ena: 1; /*This is the enable bit for sw_xon_int_st register.*/ + volatile uint32_t sw_xoff_int_ena: 1; /*This is the enable bit for sw_xoff_int_st register.*/ + volatile uint32_t glitch_det_int_ena: 1; /*This is the enable bit for glitch_det_int_st register.*/ + volatile uint32_t tx_brk_done_int_ena: 1; /*This is the enable bit for tx_brk_done_int_st register.*/ + volatile uint32_t tx_brk_idle_done_int_ena: 1; /*This is the enable bit for tx_brk_idle_done_int_st register.*/ + volatile uint32_t tx_done_int_ena: 1; /*This is the enable bit for tx_done_int_st register.*/ + volatile uint32_t rs485_parity_err_int_ena: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/ + volatile uint32_t rs485_frm_err_int_ena: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/ + volatile uint32_t rs485_clash_int_ena: 1; /*This is the enable bit for rs485_clash_int_st register.*/ + volatile uint32_t at_cmd_char_det_int_ena: 1; /*This is the enable bit for at_cmd_char_det_int_st register.*/ + volatile uint32_t reserved19: 13; + }; + volatile uint32_t val; + }int_ena; + union { + struct { + volatile uint32_t rxfifo_full_int_clr: 1; /*Set this bit to clear the rxfifo_full_int_raw interrupt.*/ + volatile uint32_t txfifo_empty_int_clr: 1; /*Set this bit to clear txfifo_empty_int_raw interrupt.*/ + volatile uint32_t parity_err_int_clr: 1; /*Set this bit to clear parity_err_int_raw interrupt.*/ + volatile uint32_t frm_err_int_clr: 1; /*Set this bit to clear frm_err_int_raw interrupt.*/ + volatile uint32_t rxfifo_ovf_int_clr: 1; /*Set this bit to clear rxfifo_ovf_int_raw interrupt.*/ + volatile uint32_t dsr_chg_int_clr: 1; /*Set this bit to clear the dsr_chg_int_raw interrupt.*/ + volatile uint32_t cts_chg_int_clr: 1; /*Set this bit to clear the cts_chg_int_raw interrupt.*/ + volatile uint32_t brk_det_int_clr: 1; /*Set this bit to clear the brk_det_int_raw interrupt.*/ + volatile uint32_t rxfifo_tout_int_clr: 1; /*Set this bit to clear the rxfifo_tout_int_raw interrupt.*/ + volatile uint32_t sw_xon_int_clr: 1; /*Set this bit to clear the sw_xon_int_raw interrupt.*/ + volatile uint32_t sw_xoff_int_clr: 1; /*Set this bit to clear the sw_xon_int_raw interrupt.*/ + volatile uint32_t glitch_det_int_clr: 1; /*Set this bit to clear the glitch_det_int_raw interrupt.*/ + volatile uint32_t tx_brk_done_int_clr: 1; /*Set this bit to clear the tx_brk_done_int_raw interrupt..*/ + volatile uint32_t tx_brk_idle_done_int_clr: 1; /*Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/ + volatile uint32_t tx_done_int_clr: 1; /*Set this bit to clear the tx_done_int_raw interrupt.*/ + volatile uint32_t rs485_parity_err_int_clr: 1; /*Set this bit to clear the rs485_parity_err_int_raw interrupt.*/ + volatile uint32_t rs485_frm_err_int_clr: 1; /*Set this bit to clear the rs485_frm_err_int_raw interrupt.*/ + volatile uint32_t rs485_clash_int_clr: 1; /*Set this bit to clear the rs485_clash_int_raw interrupt.*/ + volatile uint32_t at_cmd_char_det_int_clr: 1; /*Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/ + volatile uint32_t reserved19: 13; + }; + volatile uint32_t val; + }int_clr; + union { + struct { + volatile uint32_t clkdiv: 20; /*The register value is the integer part of the frequency divider's factor.*/ + volatile uint32_t clkdiv_frag: 4; /*The register value is the decimal part of the frequency divider's factor.*/ + volatile uint32_t reserved24: 8; + }; + volatile uint32_t val; + }clk_div; + union { + struct { + volatile uint32_t auto_baud_en: 1; /*This is the enable bit for detecting baudrate.*/ + volatile uint32_t reserved1: 7; + volatile uint32_t glitch_filt: 8; /*when input pulse width is lower then this value ignore this pulse.this register is used in auto-baud detect process.*/ + volatile uint32_t reserved16: 16; + }; + volatile uint32_t val; + }auto_baud; + union { + struct { + volatile uint32_t rxfifo_cnt: 8; /*(rx_mem_cnt rxfifo_cnt) stores the byte number of valid data in receiver's fifo. rx_mem_cnt register stores the 3 most significant bits rxfifo_cnt stores the 8 least significant bits.*/ + volatile uint32_t st_urx_out: 4; /*This register stores the value of receiver's finite state machine. 0:RX_IDLE 1:RX_STRT 2:RX_DAT0 3:RX_DAT1 4:RX_DAT2 5:RX_DAT3 6:RX_DAT4 7:RX_DAT5 8:RX_DAT6 9:RX_DAT7 10:RX_PRTY 11:RX_STP1 12:RX_STP2 13:RX_DL1*/ + volatile uint32_t reserved12: 1; + volatile uint32_t dsrn: 1; /*This register stores the level value of the internal uart dsr signal.*/ + volatile uint32_t ctsn: 1; /*This register stores the level value of the internal uart cts signal.*/ + volatile uint32_t rxd: 1; /*This register stores the level value of the internal uart rxd signal.*/ + volatile uint32_t txfifo_cnt: 8; /*(tx_mem_cnt txfifo_cnt) stores the byte number of valid data in transmitter's fifo.tx_mem_cnt stores the 3 most significant bits txfifo_cnt stores the 8 least significant bits.*/ + volatile uint32_t st_utx_out: 4; /*This register stores the value of transmitter's finite state machine. 0:TX_IDLE 1:TX_STRT 2:TX_DAT0 3:TX_DAT1 4:TX_DAT2 5:TX_DAT3 6:TX_DAT4 7:TX_DAT5 8:TX_DAT6 9:TX_DAT7 10:TX_PRTY 11:TX_STP1 12:TX_STP2 13:TX_DL0 14:TX_DL1*/ + volatile uint32_t reserved28: 1; + volatile uint32_t dtrn: 1; /*The register represent the level value of the internal uart dsr signal.*/ + volatile uint32_t rtsn: 1; /*This register represent the level value of the internal uart cts signal.*/ + volatile uint32_t txd: 1; /*This register represent the level value of the internal uart rxd signal.*/ + }; + volatile uint32_t val; + }status; + union { + struct { + volatile uint32_t parity: 1; /*This register is used to configure the parity check mode. 0:even 1:odd*/ + volatile uint32_t parity_en: 1; /*Set this bit to enable uart parity check.*/ + volatile uint32_t bit_num: 2; /*This register is used to set the length of data: 0:5bits 1:6bits 2:7bits 3:8bits*/ + volatile uint32_t stop_bit_num: 2; /*This register is used to set the length of stop bit. 1:1bit 2:1.5bits 3:2bits*/ + volatile uint32_t sw_rts: 1; /*This register is used to configure the software rts signal which is used in software flow control.*/ + volatile uint32_t sw_dtr: 1; /*This register is used to configure the software dtr signal which is used in software flow control..*/ + volatile uint32_t txd_brk: 1; /*Set this bit to enable transmitter to send 0 when the process of sending data is done.*/ + volatile uint32_t irda_dplx: 1; /*Set this bit to enable irda loopback mode.*/ + volatile uint32_t irda_tx_en: 1; /*This is the start enable bit for irda transmitter.*/ + volatile uint32_t irda_wctl: 1; /*1：the irda transmitter's 11th bit is the same to the 10th bit. 0：set irda transmitter's 11th bit to 0.*/ + volatile uint32_t irda_tx_inv: 1; /*Set this bit to inverse the level value of irda transmitter's level.*/ + volatile uint32_t irda_rx_inv: 1; /*Set this bit to inverse the level value of irda receiver's level.*/ + volatile uint32_t loopback: 1; /*Set this bit to enable uart loop-back test mode.*/ + volatile uint32_t tx_flow_en: 1; /*Set this bit to enable transmitter's flow control function.*/ + volatile uint32_t irda_en: 1; /*Set this bit to enable irda protocol.*/ + volatile uint32_t rxfifo_rst: 1; /*Set this bit to reset uart receiver's fifo.*/ + volatile uint32_t txfifo_rst: 1; /*Set this bit to reset uart transmitter's fifo.*/ + volatile uint32_t rxd_inv: 1; /*Set this bit to inverse the level value of uart rxd signal.*/ + volatile uint32_t cts_inv: 1; /*Set this bit to inverse the level value of uart cts signal.*/ + volatile uint32_t dsr_inv: 1; /*Set this bit to inverse the level value of uart dsr signal.*/ + volatile uint32_t txd_inv: 1; /*Set this bit to inverse the level value of uart txd signal.*/ + volatile uint32_t rts_inv: 1; /*Set this bit to inverse the level value of uart rts signal.*/ + volatile uint32_t dtr_inv: 1; /*Set this bit to inverse the level value of uart dtr signal.*/ + volatile uint32_t clk_en: 1; /*1：force clock on for registers：support clock only when write registers*/ + volatile uint32_t err_wr_mask: 1; /*1：receiver stops storing data int fifo when data is wrong. 0：receiver stores the data even if the received data is wrong.*/ + volatile uint32_t tick_ref_always_on: 1; /*This register is used to select the clock.1：apb clock：ref_tick*/ + volatile uint32_t reserved28: 4; + }; + volatile uint32_t val; + }conf0; + union { + struct { + volatile uint32_t rxfifo_full_thrhd: 7; /*When receiver receives more data than its threshold value，receiver will produce rxfifo_full_int_raw interrupt.the threshold value is (rx_flow_thrhd_h3 rxfifo_full_thrhd).*/ + volatile uint32_t reserved7: 1; + volatile uint32_t txfifo_empty_thrhd: 7; /*when the data amount in transmitter fifo is less than its threshold value， it will produce txfifo_empty_int_raw interrupt. the threshold value is (tx_mem_empty_thrhd txfifo_empty_thrhd)*/ + volatile uint32_t reserved15: 1; + volatile uint32_t rx_flow_thrhd: 7; /*when receiver receives more data than its threshold value， receiver produce signal to tell the transmitter stop transferring data. the threshold value is (rx_flow_thrhd_h3 rx_flow_thrhd).*/ + volatile uint32_t rx_flow_en: 1; /*This is the flow enable bit for uart receiver. 1:choose software flow control with configuring sw_rts signal*/ + volatile uint32_t rx_tout_thrhd: 7; /*This register is used to configure the timeout value for uart receiver receiving a byte.*/ + volatile uint32_t rx_tout_en: 1; /*This is the enable bit for uart receiver's timeout function.*/ + }; + volatile uint32_t val; + }conf1; + union { + struct { + volatile uint32_t lowpulse_min_cnt:20; /*This register stores the value of the minimum duration time for the low level pulse， it is used in baudrate-detect process.*/ + volatile uint32_t reserved20: 12; + }; + volatile uint32_t val; + }lowpulse; + union { + struct { + volatile uint32_t highpulse_min_cnt:20; /*This register stores the value of the maximum duration time for the high level pulse， it is used in baudrate-detect process.*/ + volatile uint32_t reserved20: 12; + }; + volatile uint32_t val; + }highpulse; + union { + struct { + volatile uint32_t rxd_edge_cnt:10; /*This register stores the count of rxd edge change， it is used in baudrate-detect process.*/ + volatile uint32_t reserved10: 22; + }; + volatile uint32_t val; + }rxd_cnt; + union { + struct { + volatile uint32_t sw_flow_con_en: 1; /*Set this bit to enable software flow control. it is used with register sw_xon or sw_xoff .*/ + volatile uint32_t xonoff_del: 1; /*Set this bit to remove flow control char from the received data.*/ + volatile uint32_t force_xon: 1; /*Set this bit to clear ctsn to stop the transmitter from sending data.*/ + volatile uint32_t force_xoff: 1; /*Set this bit to set ctsn to enable the transmitter to go on sending data.*/ + volatile uint32_t send_xon: 1; /*Set this bit to send xon char， it is cleared by hardware automatically.*/ + volatile uint32_t send_xoff: 1; /*Set this bit to send xoff char， it is cleared by hardware automatically.*/ + volatile uint32_t reserved6: 26; + }; + volatile uint32_t val; + }flow_conf; + union { + struct { + volatile uint32_t active_threshold:10; /*When the input rxd edge changes more than this register value， the uart is active from light sleeping mode.*/ + volatile uint32_t reserved10: 22; + }; + volatile uint32_t val; + }sleep_conf; + union { + struct { + volatile uint32_t xon_threshold: 8; /*when the data amount in receiver's fifo is more than this register value， it will send a xoff char with uart_sw_flow_con_en set to 1.*/ + volatile uint32_t xoff_threshold: 8; /*When the data amount in receiver's fifo is less than this register value， it will send a xon char with uart_sw_flow_con_en set to 1.*/ + volatile uint32_t xon_char: 8; /*This register stores the xon flow control char.*/ + volatile uint32_t xoff_char: 8; /*This register stores the xoff flow control char.*/ + }; + volatile uint32_t val; + }swfc_conf; + union { + struct { + volatile uint32_t rx_idle_thrhd:10; /*when receiver takes more time than this register value to receive a byte data， it will produce frame end signal for uhci to stop receiving data.*/ + volatile uint32_t tx_idle_num: 10; /*This register is used to configure the duration time between transfers.*/ + volatile uint32_t tx_brk_num: 8; /*This register is used to configure the number of 0 send after the process of sending data is done. it is active when txd_brk is set to 1.*/ + volatile uint32_t reserved28: 4; + }; + volatile uint32_t val; + }idle_conf; + union { + struct { + volatile uint32_t rs485_en: 1; /*Set this bit to choose rs485 mode.*/ + volatile uint32_t dl0_en: 1; /*Set this bit to delay the stop bit by 1 bit.*/ + volatile uint32_t dl1_en: 1; /*Set this bit to delay the stop bit by 1 bit.*/ + volatile uint32_t rs485tx_rx_en: 1; /*Set this bit to enable loop-back transmitter's output data signal to receiver's input data signal.*/ + volatile uint32_t rs485rxby_tx_en: 1; /*1: enable rs485's transmitter to send data when rs485's receiver is busy. 0:rs485's transmitter should not send data when its receiver is busy.*/ + volatile uint32_t rs485_rx_dly_num: 1; /*This register is used to delay the receiver's internal data signal.*/ + volatile uint32_t rs485_tx_dly_num: 4; /*This register is used to delay the transmitter's internal data signal.*/ + volatile uint32_t reserved10: 22; + }; + volatile uint32_t val; + }rs485_conf; + union { + struct { + volatile uint32_t pre_idle_num:24; /*This register is used to configure the idle duration time before the first at_cmd is received by receiver， when the the duration is less than this register value it will not take the next data received as at_cmd char.*/ + volatile uint32_t reserved24: 8; + }; + volatile uint32_t val; + }at_cmd_precnt; + union { + struct { + volatile uint32_t post_idle_num:24; /*This register is used to configure the duration time between the last at_cmd and the next data， when the duration is less than this register value it will not take the previous data as at_cmd char.*/ + volatile uint32_t reserved24: 8; + }; + volatile uint32_t val; + }at_cmd_postcnt; + union { + struct { + volatile uint32_t rx_gap_tout:24; /*This register is used to configure the duration time between the at_cmd chars， when the duration time is less than this register value it will not take the data as continous at_cmd chars.*/ + volatile uint32_t reserved24: 8; + }; + volatile uint32_t val; + }at_cmd_gaptout; + union { + struct { + volatile uint32_t at_cmd_char: 8; /*This register is used to configure the content of at_cmd char.*/ + volatile uint32_t char_num: 8; /*This register is used to configure the number of continuous at_cmd chars received by receiver.*/ + volatile uint32_t reserved16: 16; + }; + volatile uint32_t val; + }at_cmd_char; + union { + struct { + volatile uint32_t mem_pd: 1; /*Set this bit to power down memory，when reg_mem_pd registers in the 3 uarts are all set to 1 memory will enter low power mode.*/ + volatile uint32_t reserved1: 1; + volatile uint32_t reserved2: 1; + volatile uint32_t rx_size: 4; /*This register is used to configure the amount of mem allocated to receiver's fifo. the default byte num is 128.*/ + volatile uint32_t tx_size: 4; /*This register is used to configure the amount of mem allocated to transmitter's fifo.the default byte num is 128.*/ + volatile uint32_t reserved11: 4; + volatile uint32_t rx_flow_thrhd_h3: 3; /*refer to the rx_flow_thrhd's description.*/ + volatile uint32_t rx_tout_thrhd_h3: 3; /*refer to the rx_tout_thrhd's description.*/ + volatile uint32_t xon_threshold_h2: 2; /*refer to the uart_xon_threshold's description.*/ + volatile uint32_t xoff_threshold_h2: 2; /*refer to the uart_xoff_threshold's description.*/ + volatile uint32_t rx_mem_full_thrhd: 3; /*refer to the rxfifo_full_thrhd's description.*/ + volatile uint32_t tx_mem_empty_thrhd: 3; /*refer to txfifo_empty_thrhd 's description.*/ + volatile uint32_t reserved31: 1; + }; + volatile uint32_t val; + }mem_conf; + union { + struct { + volatile uint32_t mem_tx_status:24; + volatile uint32_t reserved24: 8; + }; + volatile uint32_t val; + }mem_tx_status; + union { + struct { + volatile uint32_t mem_rx_status:24; + volatile uint32_t reserved24: 8; + }; + volatile uint32_t val; + }mem_rx_status; + union { + struct { + volatile uint32_t rx_mem_cnt: 3; /*refer to the rxfifo_cnt's description.*/ + volatile uint32_t tx_mem_cnt: 3; /*refer to the txfifo_cnt's description.*/ + volatile uint32_t reserved6: 26; + }; + volatile uint32_t val; + }mem_cnt_status; + union { + struct { + volatile uint32_t posedge_min_cnt:20; /*This register stores the count of rxd pos-edge edge， it is used in baudrate-detect process.*/ + volatile uint32_t reserved20: 12; + }; + volatile uint32_t val; + }pospulse; + union { + struct { + volatile uint32_t negedge_min_cnt:20; /*This register stores the count of rxd neg-edge edge， it is used in baudrate-detect process.*/ + volatile uint32_t reserved20: 12; + }; + volatile uint32_t val; + }negpulse; + volatile uint32_t reserved_70; + volatile uint32_t reserved_74; + volatile uint32_t date; /**/ + volatile uint32_t id; /**/ +} uart_dev_t; +extern volatile uart_dev_t UART0; +extern volatile uart_dev_t UART1; +extern volatile uart_dev_t UART2; +#endif /* _SOC_UART_STRUCT_H_ */ diff --git a/components/esp32/include/soc/uhci_struct.h b/components/esp32/include/soc/uhci_struct.h new file mode 100644 index 000000000..323d3beac --- /dev/null +++ b/components/esp32/include/soc/uhci_struct.h @@ -0,0 +1,337 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_UHCI_STRUCT_H_ +#define _SOC_UHCI_STRUCT_H_ +typedef struct { + union { + struct { + volatile uint32_t in_rst: 1; /*Set this bit to reset in link operations.*/ + volatile uint32_t out_rst: 1; /*Set this bit to reset out link operations.*/ + volatile uint32_t ahbm_fifo_rst: 1; /*Set this bit to reset dma ahb fifo.*/ + volatile uint32_t ahbm_rst: 1; /*Set this bit to reset dma ahb interface.*/ + volatile uint32_t in_loop_test: 1; /*Set this bit to enable loop test for in links.*/ + volatile uint32_t out_loop_test: 1; /*Set this bit to enable loop test for out links.*/ + volatile uint32_t out_auto_wrback: 1; /*when in link's length is 0 go on to use the next in link automatically.*/ + volatile uint32_t out_no_restart_clr: 1; /*don't use*/ + volatile uint32_t out_eof_mode: 1; /*Set this bit to produce eof after DMA pops all data clear this bit to produce eof after DMA pushes all data*/ + volatile uint32_t uart0_ce: 1; /*Set this bit to use UART to transmit or receive data.*/ + volatile uint32_t uart1_ce: 1; /*Set this bit to use UART1 to transmit or receive data.*/ + volatile uint32_t uart2_ce: 1; /*Set this bit to use UART2 to transmit or receive data.*/ + volatile uint32_t outdscr_burst_en: 1; /*Set this bit to enable DMA in links to use burst mode.*/ + volatile uint32_t indscr_burst_en: 1; /*Set this bit to enable DMA out links to use burst mode.*/ + volatile uint32_t out_data_burst_en: 1; /*Set this bit to enable DMA burst MODE*/ + volatile uint32_t mem_trans_en: 1; + volatile uint32_t seper_en: 1; /*Set this bit to use special char to separate the data frame.*/ + volatile uint32_t head_en: 1; /*Set this bit to enable to use head packet before the data frame.*/ + volatile uint32_t crc_rec_en: 1; /*Set this bit to enable receiver''s ability of crc calculation when crc_en bit in head packet is 1 then there will be crc bytes after data_frame*/ + volatile uint32_t uart_idle_eof_en: 1; /*Set this bit to enable to use idle time when the idle time after data frame is satisfied this means the end of a data frame.*/ + volatile uint32_t len_eof_en: 1; /*Set this bit to enable to use packet_len in packet head when the received data is equal to packet_len this means the end of a data frame.*/ + volatile uint32_t encode_crc_en: 1; /*Set this bit to enable crc calculation for data frame when bit6 in the head packet is 1.*/ + volatile uint32_t clk_en: 1; /*Set this bit to enable clock-gating for read or write registers.*/ + volatile uint32_t uart_rx_brk_eof_en: 1; /*Set this bit to enable to use brk char as the end of a data frame.*/ + volatile uint32_t reserved24: 8; + }; + volatile uint32_t val; + }conf0; + union { + struct { + volatile uint32_t rx_start_int_raw: 1; /*when a separator char has been send it will produce uhci_rx_start_int interrupt.*/ + volatile uint32_t tx_start_int_raw: 1; /*when DMA detects a separator char it will produce uhci_tx_start_int interrupt.*/ + volatile uint32_t rx_hung_int_raw: 1; /*when DMA takes a lot of time to receive a data it will produce uhci_rx_hung_int interrupt.*/ + volatile uint32_t tx_hung_int_raw: 1; /*when DMA takes a lot of time to read a data from RAM it will produce uhci_tx_hung_int interrupt.*/ + volatile uint32_t in_done_int_raw: 1; /*when a in link descriptor has been completed it will produce uhci_in_done_int interrupt.*/ + volatile uint32_t in_suc_eof_int_raw: 1; /*when a data packet has been received it will produce uhci_in_suc_eof_int interrupt.*/ + volatile uint32_t in_err_eof_int_raw: 1; /*when there are some errors about eof in in link descriptor it will produce uhci_in_err_eof_int interrupt.*/ + volatile uint32_t out_done_int_raw: 1; /*when a out link descriptor is completed it will produce uhci_out_done_int interrupt.*/ + volatile uint32_t out_eof_int_raw: 1; /*when the current descriptor's eof bit is 1 it will produce uhci_out_eof_int interrupt.*/ + volatile uint32_t in_dscr_err_int_raw: 1; /*when there are some errors about the out link descriptor it will produce uhci_in_dscr_err_int interrupt.*/ + volatile uint32_t out_dscr_err_int_raw: 1; /*when there are some errors about the in link descriptor it will produce uhci_out_dscr_err_int interrupt.*/ + volatile uint32_t in_dscr_empty_int_raw: 1; /*when there are not enough in links for DMA it will produce uhci_in_dscr_err_int interrupt.*/ + volatile uint32_t outlink_eof_err_int_raw: 1; /*when there are some errors about eof in outlink descriptor it will produce uhci_outlink_eof_err_int interrupt.*/ + volatile uint32_t out_total_eof_int_raw: 1; /*When all data have been send it will produce uhci_out_total_eof_int interrupt.*/ + volatile uint32_t send_s_q_int_raw: 1; /*When use single send registers to send a short packets it will produce this interrupt when dma has send the short packet.*/ + volatile uint32_t send_a_q_int_raw: 1; /*When use always_send registers to send a series of short packets it will produce this interrupt when dma has send the short packet.*/ + volatile uint32_t dma_infifo_full_wm_int_raw: 1; + volatile uint32_t reserved17: 15; + }; + volatile uint32_t val; + }int_raw; + union { + struct { + volatile uint32_t rx_start_int_st: 1; + volatile uint32_t tx_start_int_st: 1; + volatile uint32_t rx_hung_int_st: 1; + volatile uint32_t tx_hung_int_st: 1; + volatile uint32_t in_done_int_st: 1; + volatile uint32_t in_suc_eof_int_st: 1; + volatile uint32_t in_err_eof_int_st: 1; + volatile uint32_t out_done_int_st: 1; + volatile uint32_t out_eof_int_st: 1; + volatile uint32_t in_dscr_err_int_st: 1; + volatile uint32_t out_dscr_err_int_st: 1; + volatile uint32_t in_dscr_empty_int_st: 1; + volatile uint32_t outlink_eof_err_int_st: 1; + volatile uint32_t out_total_eof_int_st: 1; + volatile uint32_t send_s_q_int_st: 1; + volatile uint32_t send_a_q_int_st: 1; + volatile uint32_t dma_infifo_full_wm_int_st: 1; + volatile uint32_t reserved17: 15; + }; + volatile uint32_t val; + }int_st; + union { + struct { + volatile uint32_t rx_start_int_ena: 1; + volatile uint32_t tx_start_int_ena: 1; + volatile uint32_t rx_hung_int_ena: 1; + volatile uint32_t tx_hung_int_ena: 1; + volatile uint32_t in_done_int_ena: 1; + volatile uint32_t in_suc_eof_int_ena: 1; + volatile uint32_t in_err_eof_int_ena: 1; + volatile uint32_t out_done_int_ena: 1; + volatile uint32_t out_eof_int_ena: 1; + volatile uint32_t in_dscr_err_int_ena: 1; + volatile uint32_t out_dscr_err_int_ena: 1; + volatile uint32_t in_dscr_empty_int_ena: 1; + volatile uint32_t outlink_eof_err_int_ena: 1; + volatile uint32_t out_total_eof_int_ena: 1; + volatile uint32_t send_s_q_int_ena: 1; + volatile uint32_t send_a_q_int_ena: 1; + volatile uint32_t dma_infifo_full_wm_int_ena: 1; + volatile uint32_t reserved17: 15; + }; + volatile uint32_t val; + }int_ena; + union { + struct { + volatile uint32_t rx_start_int_clr: 1; + volatile uint32_t tx_start_int_clr: 1; + volatile uint32_t rx_hung_int_clr: 1; + volatile uint32_t tx_hung_int_clr: 1; + volatile uint32_t in_done_int_clr: 1; + volatile uint32_t in_suc_eof_int_clr: 1; + volatile uint32_t in_err_eof_int_clr: 1; + volatile uint32_t out_done_int_clr: 1; + volatile uint32_t out_eof_int_clr: 1; + volatile uint32_t in_dscr_err_int_clr: 1; + volatile uint32_t out_dscr_err_int_clr: 1; + volatile uint32_t in_dscr_empty_int_clr: 1; + volatile uint32_t outlink_eof_err_int_clr: 1; + volatile uint32_t out_total_eof_int_clr: 1; + volatile uint32_t send_s_q_int_clr: 1; + volatile uint32_t send_a_q_int_clr: 1; + volatile uint32_t dma_infifo_full_wm_int_clr: 1; + volatile uint32_t reserved17: 15; + }; + volatile uint32_t val; + }int_clr; + union { + struct { + volatile uint32_t out_full: 1; /*1:DMA out link descriptor's fifo is full.*/ + volatile uint32_t out_empty: 1; /*1:DMA in link descriptor's fifo is empty.*/ + volatile uint32_t reserved2: 30; + }; + volatile uint32_t val; + }dma_out_status; + union { + struct { + volatile uint32_t outfifo_wdata: 9; /*This is the data need to be pushed into out link descriptor's fifo.*/ + volatile uint32_t reserved9: 7; + volatile uint32_t outfifo_push: 1; /*Set this bit to push data in out link descriptor's fifo.*/ + volatile uint32_t reserved17: 15; + }; + volatile uint32_t val; + }dma_out_push; + union { + struct { + volatile uint32_t in_full: 1; + volatile uint32_t in_empty: 1; + volatile uint32_t reserved2: 2; + volatile uint32_t rx_err_cause: 3; /*This register stores the errors caused in out link descriptor's data packet.*/ + volatile uint32_t reserved7: 25; + }; + volatile uint32_t val; + }dma_in_status; + union { + struct { + volatile uint32_t infifo_rdata:12; /*This register stores the data pop from in link descriptor's fifo.*/ + volatile uint32_t reserved12: 4; + volatile uint32_t infifo_pop: 1; /*Set this bit to pop data in in link descriptor's fifo.*/ + volatile uint32_t reserved17: 15; + }; + volatile uint32_t val; + }dma_in_pop; + union { + struct { + volatile uint32_t outlink_addr: 20; /*This register stores the least 20 bits of the first out link descriptor's address.*/ + volatile uint32_t reserved20: 8; + volatile uint32_t outlink_stop: 1; /*Set this bit to stop dealing with the out link descriptors.*/ + volatile uint32_t outlink_start: 1; /*Set this bit to start dealing with the out link descriptors.*/ + volatile uint32_t outlink_restart: 1; /*Set this bit to mount on new out link descriptors*/ + volatile uint32_t outlink_park: 1; /*1： the out link descriptor's fsm is in idle state. 0:the out link descriptor's fsm is working.*/ + }; + volatile uint32_t val; + }dma_out_link; + union { + struct { + volatile uint32_t inlink_addr: 20; /*This register stores the least 20 bits of the first in link descriptor's address.*/ + volatile uint32_t inlink_auto_ret: 1; /*1:when a packet is wrong in link descriptor returns to the descriptor which is lately used.*/ + volatile uint32_t reserved21: 7; + volatile uint32_t inlink_stop: 1; /*Set this bit to stop dealing with the in link descriptors.*/ + volatile uint32_t inlink_start: 1; /*Set this bit to start dealing with the in link descriptors.*/ + volatile uint32_t inlink_restart: 1; /*Set this bit to mount on new in link descriptors*/ + volatile uint32_t inlink_park: 1; /*1:the in link descriptor's fsm is in idle state. 0:the in link descriptor's fsm is working*/ + }; + volatile uint32_t val; + }dma_in_link; + union { + struct { + volatile uint32_t check_sum_en: 1; /*Set this bit to enable decoder to check check_sum in packet header.*/ + volatile uint32_t check_seq_en: 1; /*Set this bit to enable decoder to check seq num in packet header.*/ + volatile uint32_t crc_disable: 1; /*Set this bit to disable crc calculation.*/ + volatile uint32_t save_head: 1; /*Set this bit to save packet header .*/ + volatile uint32_t tx_check_sum_re: 1; /*Set this bit to enable hardware replace check_sum in packet header automatically.*/ + volatile uint32_t tx_ack_num_re: 1; /*Set this bit to enable hardware replace ack num in packet header automatically.*/ + volatile uint32_t check_owner: 1; /*Set this bit to check the owner bit in link descriptor.*/ + volatile uint32_t wait_sw_start: 1; /*Set this bit to enable software way to add packet header.*/ + volatile uint32_t sw_start: 1; /*Set this bit to start inserting the packet header.*/ + volatile uint32_t dma_infifo_full_thrs:12; /*when data amount in link descriptor's fifo is more than this register value it will produce uhci_dma_infifo_full_wm_int interrupt.*/ + volatile uint32_t reserved21: 11; + }; + volatile uint32_t val; + }conf1; + volatile uint32_t state0; /**/ + volatile uint32_t state1; /**/ + volatile uint32_t dma_out_eof_des_addr; /*This register stores the address of out link description when eof bit in this descriptor is 1.*/ + volatile uint32_t dma_in_suc_eof_des_addr; /*This register stores the address of in link descriptor when eof bit in this descriptor is 1.*/ + volatile uint32_t dma_in_err_eof_des_addr; /*This register stores the address of in link descriptor when there are some errors in this descriptor.*/ + volatile uint32_t dma_out_eof_bfr_des_addr; /*This register stores the address of out link descriptor when there are some errors in this descriptor.*/ + union { + struct { + volatile uint32_t ahb_testmode: 3; /*bit2 is ahb bus test enable ，bit1 is used to choose write(1) or read(0) mode. bit0 is used to choose test only once(1) or continue(0)*/ + volatile uint32_t reserved3: 1; + volatile uint32_t ahb_testaddr: 2; /*The two bits represent ahb bus address bit[20:19]*/ + volatile uint32_t reserved6: 26; + }; + volatile uint32_t val; + }ahb_test; + volatile uint32_t dma_in_dscr; /*The content of current in link descriptor's third dword*/ + volatile uint32_t dma_in_dscr_bf0; /*The content of current in link descriptor's first dword*/ + volatile uint32_t dma_in_dscr_bf1; /*The content of current in link descriptor's second dword*/ + volatile uint32_t dma_out_dscr; /*The content of current out link descriptor's third dword*/ + volatile uint32_t dma_out_dscr_bf0; /*The content of current out link descriptor's first dword*/ + volatile uint32_t dma_out_dscr_bf1; /*The content of current out link descriptor's second dword*/ + union { + struct { + volatile uint32_t tx_c0_esc_en: 1; /*Set this bit to enable 0xc0 char decode when DMA receives data.*/ + volatile uint32_t tx_db_esc_en: 1; /*Set this bit to enable 0xdb char decode when DMA receives data.*/ + volatile uint32_t tx_11_esc_en: 1; /*Set this bit to enable flow control char 0x11 decode when DMA receives data.*/ + volatile uint32_t tx_13_esc_en: 1; /*Set this bit to enable flow control char 0x13 decode when DMA receives data.*/ + volatile uint32_t rx_c0_esc_en: 1; /*Set this bit to enable 0xc0 char replace when DMA sends data.*/ + volatile uint32_t rx_db_esc_en: 1; /*Set this bit to enable 0xdb char replace when DMA sends data.*/ + volatile uint32_t rx_11_esc_en: 1; /*Set this bit to enable flow control char 0x11 replace when DMA sends data.*/ + volatile uint32_t rx_13_esc_en: 1; /*Set this bit to enable flow control char 0x13 replace when DMA sends data.*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }escape_conf; + union { + struct { + volatile uint32_t txfifo_timeout: 8; /*This register stores the timeout value.when DMA takes more time than this register value to receive a data it will produce uhci_tx_hung_int interrupt.*/ + volatile uint32_t txfifo_timeout_shift: 3; /*The tick count is cleared when its value >=(17'd8000>>reg_txfifo_timeout_shift)*/ + volatile uint32_t txfifo_timeout_ena: 1; /*The enable bit for tx fifo receive data timeout*/ + volatile uint32_t rxfifo_timeout: 8; /*This register stores the timeout value.when DMA takes more time than this register value to read a data from RAM it will produce uhci_rx_hung_int interrupt.*/ + volatile uint32_t rxfifo_timeout_shift: 3; /*The tick count is cleared when its value >=(17'd8000>>reg_rxfifo_timeout_shift)*/ + volatile uint32_t rxfifo_timeout_ena: 1; /*This is the enable bit for DMA send data timeout*/ + volatile uint32_t reserved24: 8; + }; + volatile uint32_t val; + }hung_conf; + volatile uint32_t ack_num; /**/ + volatile uint32_t rx_head; /*This register stores the packet header received by DMA*/ + union { + struct { + volatile uint32_t single_send_num: 3; /*The bits are used to choose which short packet*/ + volatile uint32_t single_send_en: 1; /*Set this bit to enable send a short packet*/ + volatile uint32_t always_send_num: 3; /*The bits are used to choose which short packet*/ + volatile uint32_t always_send_en: 1; /*Set this bit to enable continuously send the same short packet*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }quick_sent; + struct{ + volatile uint32_t w_data[2]; /*This register stores the content of short packet's dword*/ + }q_data[7]; + union { + struct { + volatile uint32_t seper_char: 8; /*This register stores the separator char separator char is used to separate the data frame.*/ + volatile uint32_t seper_esc_char0: 8; /*This register stores the first char used to replace separator char in data.*/ + volatile uint32_t seper_esc_char1: 8; /*This register stores the second char used to replace separator char in data . 0xdc 0xdb replace 0xc0 by default.*/ + volatile uint32_t reserved24: 8; + }; + volatile uint32_t val; + }esc_conf0; + union { + struct { + volatile uint32_t esc_seq0: 8; /*This register stores the first substitute char used to replace the separate char.*/ + volatile uint32_t esc_seq0_char0: 8; /*This register stores the first char used to replace reg_esc_seq0 in data.*/ + volatile uint32_t esc_seq0_char1: 8; /*This register stores the second char used to replace the reg_esc_seq0 in data*/ + volatile uint32_t reserved24: 8; + }; + volatile uint32_t val; + }esc_conf1; + union { + struct { + volatile uint32_t esc_seq1: 8; /*This register stores the flow control char to turn on the flow_control*/ + volatile uint32_t esc_seq1_char0: 8; /*This register stores the first char used to replace the reg_esc_seq1 in data.*/ + volatile uint32_t esc_seq1_char1: 8; /*This register stores the second char used to replace the reg_esc_seq1 in data.*/ + volatile uint32_t reserved24: 8; + }; + volatile uint32_t val; + }esc_conf2; + union { + struct { + volatile uint32_t esc_seq2: 8; /*This register stores the flow_control char to turn off the flow_control*/ + volatile uint32_t esc_seq2_char0: 8; /*This register stores the first char used to replace the reg_esc_seq2 in data.*/ + volatile uint32_t esc_seq2_char1: 8; /*This register stores the second char used to replace the reg_esc_seq2 in data.*/ + volatile uint32_t reserved24: 8; + }; + volatile uint32_t val; + }esc_conf3; + union { + struct { + volatile uint32_t pkt_thrs: 13; /*when the amount of packet payload is larger than this value the process of receiving data is done.*/ + volatile uint32_t reserved13:19; + }; + volatile uint32_t val; + }pkt_thres; + volatile uint32_t reserved_c4; + volatile uint32_t reserved_c8; + volatile uint32_t reserved_cc; + volatile uint32_t reserved_d0; + volatile uint32_t reserved_d4; + volatile uint32_t reserved_d8; + volatile uint32_t reserved_dc; + volatile uint32_t reserved_e0; + volatile uint32_t reserved_e4; + volatile uint32_t reserved_e8; + volatile uint32_t reserved_ec; + volatile uint32_t reserved_f0; + volatile uint32_t reserved_f4; + volatile uint32_t reserved_f8; + volatile uint32_t date; /*version information*/ +} uhci_dev_t; +extern volatile uhci_dev_t UHCI0; +extern volatile uhci_dev_t UHCI1; +#endif /* _SOC_UHCI_STRUCT_H_ */ diff --git a/components/esp32/ld/esp32.rom.ld b/components/esp32/ld/esp32.rom.ld index 823ca4c6e..f8aa70631 100644 --- a/components/esp32/ld/esp32.rom.ld +++ b/components/esp32/ld/esp32.rom.ld @@ -1836,4 +1836,25 @@ PROVIDE ( _xtos_unhandled_exception = 0x4000c024 ); PROVIDE ( _xtos_unhandled_interrupt = 0x4000c01c ); PROVIDE ( _xtos_vpri_enabled = 0x3ffe0654 ); -PROVIDE ( I2S0 = 0x6000F000 ); +PROVIDE ( I2S0 = 0x3ff4F000 ); +PROVIDE ( I2S1 = 0x3ff6D000 ); +PROVIDE ( GPIO = 0x3ff44000 ); +PROVIDE ( SIGMADELTA = 0x3ff44f00 ); +PROVIDE ( I2C0 = 0x3ff53000 ); +PROVIDE ( I2C1 = 0x3ff67000 ); +PROVIDE ( LEDC = 0x3ff59000 ); +PROVIDE ( PCNT = 0x3ff57000 ); +PROVIDE ( RMT = 0x3ff56000 ); +PROVIDE ( SPI0 = 0x3ff43000 ); +PROVIDE ( SPI1 = 0x3ff42000 ); +PROVIDE ( SPI2 = 0x3ff64000 ); +PROVIDE ( SPI3 = 0x3ff65000 ); +PROVIDE ( TIMERG0 = 0x3ff5F000 ); +PROVIDE ( TIMERG1 = 0x3ff60000 ); +PROVIDE ( UART0 = 0x3ff40000 ); +PROVIDE ( UART1 = 0x3ff50000 ); +PROVIDE ( UART2 = 0x3ff6E000 ); +PROVIDE ( UHCI0 = 0x3ff54000 ); +PROVIDE ( UHCI1 = 0x3ff4C000 ); + +