diff --git a/components/driver/gpio.c b/components/driver/gpio.c index a7db2bde2..320533e8d 100644 --- a/components/driver/gpio.c +++ b/components/driver/gpio.c @@ -90,7 +90,6 @@ const uint32_t GPIO_PIN_MUX_REG[GPIO_PIN_COUNT] = { GPIO_PIN_REG_39 }; -#define IS_VALID_GPIO(gpio_num) ( (gpio_num < GPIO_PIN_COUNT && GPIO_PIN_MUX_REG[gpio_num] != 0)) static int is_valid_gpio(int gpio_num) { if(gpio_num >= GPIO_PIN_COUNT || GPIO_PIN_MUX_REG[gpio_num] == 0) { @@ -102,8 +101,9 @@ static int is_valid_gpio(int gpio_num) esp_err_t gpio_set_intr_type(gpio_num_t gpio_num, gpio_int_type_t intr_type) { - if(!is_valid_gpio(gpio_num)) + if(!is_valid_gpio(gpio_num)) { return ESP_ERR_INVALID_ARG; + } if(intr_type >= GPIO_INTR_MAX) { GPIO_ERROR("Unknown GPIO intr:%u\n",intr_type); return ESP_ERR_INVALID_ARG; @@ -114,8 +114,9 @@ esp_err_t gpio_set_intr_type(gpio_num_t gpio_num, gpio_int_type_t intr_type) esp_err_t gpio_intr_enable(gpio_num_t gpio_num) { - if(!is_valid_gpio(gpio_num)) + if(!is_valid_gpio(gpio_num)) { return ESP_ERR_INVALID_ARG; + } if(xPortGetCoreID() == 0) { GPIO.pin[gpio_num].int_ena = GPIO_PRO_CPU_INTR_ENA; //enable pro cpu intr } else { @@ -126,16 +127,18 @@ esp_err_t gpio_intr_enable(gpio_num_t gpio_num) esp_err_t gpio_intr_disable(gpio_num_t gpio_num) { - if(!is_valid_gpio(gpio_num)) + if(!is_valid_gpio(gpio_num)) { return ESP_ERR_INVALID_ARG; + } GPIO.pin[gpio_num].int_ena = 0; //disable GPIO intr return ESP_OK; } static esp_err_t gpio_output_disable(gpio_num_t gpio_num) { - if(!is_valid_gpio(gpio_num)) + if(!is_valid_gpio(gpio_num)) { return ESP_ERR_INVALID_ARG; + } if(gpio_num < 32) { GPIO.enable_w1tc = (0x1 << gpio_num); } else { @@ -150,8 +153,9 @@ static esp_err_t gpio_output_enable(gpio_num_t gpio_num) GPIO_ERROR("io_num=%d can only be input\n",gpio_num); return ESP_ERR_INVALID_ARG; } - if(!is_valid_gpio(gpio_num)) + if(!is_valid_gpio(gpio_num)) { return ESP_ERR_INVALID_ARG; + } if(gpio_num < 32) { GPIO.enable_w1ts = (0x1 << gpio_num); } else { @@ -162,18 +166,21 @@ static esp_err_t gpio_output_enable(gpio_num_t gpio_num) esp_err_t gpio_set_level(gpio_num_t gpio_num, uint32_t level) { - if(!IS_VALID_GPIO(gpio_num)) + if(!GPIO_IS_VALID_GPIO(gpio_num)) { return ESP_ERR_INVALID_ARG; + } if(level) { - if(gpio_num < 32) + if(gpio_num < 32) { GPIO.out_w1ts = (1 << gpio_num); - else + } else { GPIO.out1_w1ts.data = (1 << (gpio_num - 32)); + } } else { - if(gpio_num < 32) + if(gpio_num < 32) { GPIO.out_w1tc = (1 << gpio_num); - else + } else { GPIO.out1_w1tc.data = (1 << (gpio_num - 32)); + } } return ESP_OK; } @@ -189,8 +196,9 @@ int gpio_get_level(gpio_num_t gpio_num) esp_err_t gpio_set_pull_mode(gpio_num_t gpio_num, gpio_pull_mode_t pull) { - if(!is_valid_gpio(gpio_num)) + if(!is_valid_gpio(gpio_num)) { return ESP_ERR_INVALID_ARG; + } esp_err_t ret = ESP_OK; switch(pull) { case GPIO_PULLUP_ONLY: @@ -219,8 +227,9 @@ esp_err_t gpio_set_pull_mode(gpio_num_t gpio_num, gpio_pull_mode_t pull) esp_err_t gpio_set_direction(gpio_num_t gpio_num, gpio_mode_t mode) { - if(!is_valid_gpio(gpio_num)) + if(!is_valid_gpio(gpio_num)) { return ESP_ERR_INVALID_ARG; + } if(gpio_num >= 34 && (mode & (GPIO_MODE_DEF_OUTPUT))) { GPIO_ERROR("io_num=%d can only be input\n",gpio_num); return ESP_ERR_INVALID_ARG; @@ -290,7 +299,8 @@ esp_err_t gpio_config(gpio_config_t *pGPIOConfig) gpio_output_enable(io_num); } else { gpio_output_disable(io_num); - }GPIO_INFO("|"); + } + GPIO_INFO("|"); if(pGPIOConfig->pull_up_en) { GPIO_INFO("PU "); PIN_PULLUP_EN(io_reg); @@ -310,7 +320,7 @@ esp_err_t gpio_config(gpio_config_t *pGPIOConfig) } else { gpio_intr_disable(io_num); } - PIN_FUNC_SELECT(io_reg, GPIO_FUNC_SEL); /*function number 2 is GPIO_FUNC for each pin */ + PIN_FUNC_SELECT(io_reg, PIN_FUNC_GPIO); /*function number 2 is GPIO_FUNC for each pin */ } else if(bit_valid && (io_reg == 0)) { GPIO_WARNING("io_num=%d does not exist\n",io_num); } @@ -321,8 +331,9 @@ esp_err_t gpio_config(gpio_config_t *pGPIOConfig) esp_err_t gpio_isr_register(uint32_t gpio_intr_num, void (*fn)(void*), void * arg) { - if(fn == NULL) + if(fn == NULL) { return ESP_ERR_INVALID_ARG; + } ESP_INTR_DISABLE(gpio_intr_num); intr_matrix_set(xPortGetCoreID(), ETS_GPIO_INTR_SOURCE, gpio_intr_num); xt_set_interrupt_handler(gpio_intr_num, fn, arg); @@ -333,8 +344,9 @@ esp_err_t gpio_isr_register(uint32_t gpio_intr_num, void (*fn)(void*), void * ar /*only level interrupt can be used for wake-up function*/ esp_err_t gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type) { - if(!is_valid_gpio(gpio_num)) + if(!is_valid_gpio(gpio_num)) { return ESP_ERR_INVALID_ARG; + } esp_err_t ret = ESP_OK; if((intr_type == GPIO_INTR_LOW_LEVEL) || (intr_type == GPIO_INTR_HIGH_LEVEL)) { GPIO.pin[gpio_num].int_type = intr_type; @@ -348,8 +360,9 @@ esp_err_t gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type) esp_err_t gpio_wakeup_disable(gpio_num_t gpio_num) { - if(!is_valid_gpio(gpio_num)) + if(!is_valid_gpio(gpio_num)) { return ESP_ERR_INVALID_ARG; + } GPIO.pin[gpio_num].wakeup_enable = 0; return ESP_OK; } diff --git a/components/driver/include/driver/gpio.h b/components/driver/include/driver/gpio.h index d0ed5c9d7..9b47c88e6 100644 --- a/components/driver/include/driver/gpio.h +++ b/components/driver/include/driver/gpio.h @@ -14,7 +14,7 @@ #ifndef _DRIVER_GPIO_H_ #define _DRIVER_GPIO_H_ - +#include "esp_err.h" #include #include "soc/gpio_reg.h" #include "soc/gpio_struct.h" @@ -65,8 +65,6 @@ extern "C" { #define GPIO_SEL_38 ((uint64_t)(((uint64_t)1)<<38)) /* Pin 38 selected */ #define GPIO_SEL_39 ((uint64_t)(((uint64_t)1)<<39)) /* Pin 39 selected */ -#define GPIO_FUNC_SEL 2 - #define GPIO_PIN_REG_0 PERIPHS_IO_MUX_GPIO0_U #define GPIO_PIN_REG_1 PERIPHS_IO_MUX_U0TXD_U #define GPIO_PIN_REG_2 PERIPHS_IO_MUX_GPIO2_U @@ -115,6 +113,8 @@ extern "C" { #define GPIO_PIN_COUNT 40 extern const uint32_t GPIO_PIN_MUX_REG[GPIO_PIN_COUNT]; +#define GPIO_IS_VALID_GPIO(gpio_num) ((gpio_num < GPIO_PIN_COUNT && GPIO_PIN_MUX_REG[gpio_num] != 0)) //to decide whether it is a valid GPIO number +#define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) ((GPIO_IS_VALID_GPIO(gpio_num)) && (gpio_num < 34)) //to decide whether it can be a valid GPIO number of output mode typedef enum { GPIO_NUM_0 = 0, diff --git a/components/driver/include/driver/ledc.h b/components/driver/include/driver/ledc.h new file mode 100644 index 000000000..79a6c7f9f --- /dev/null +++ b/components/driver/include/driver/ledc.h @@ -0,0 +1,406 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _DRIVER_LEDC_H_ +#define _DRIVER_LEDC_H_ +#include "esp_err.h" +#include "soc/soc.h" +#include "soc/ledc_reg.h" +#include "soc/ledc_reg.h" +#include "soc/ledc_struct.h" +#include "driver/gpio.h" +#include "driver/periph_ctrl.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define LEDC_APB_CLK_HZ (APB_CLK_FREQ) +#define LEDC_REF_CLK_HZ (1*1000000) + +typedef enum { + LEDC_HIGH_SPEED_MODE = 0, /*LEDC high speed speed_mode */ + //in this version, we only support high speed speed_mode. We will access low speed speed_mode later + //LEDC_LOW_SPEED_MODE, /*LEDC low speed speed_mode */ + LEDC_SPEED_MODE_MAX, +} ledc_mode_t; + +typedef enum { + LEDC_INTR_DISABLE = 0, /*Disable LEDC interrupt */ + LEDC_INTR_FADE_END, /*Enable LEDC interrupt */ +} ledc_intr_type_t; + +typedef enum { + LEDC_DUTY_DIR_DECREASE = 0, /*LEDC duty decrease direction */ + LEDC_DUTY_DIR_INCREASE = 1, /*LEDC duty increase direction */ +} ledc_duty_direction_t; + +typedef enum { + LEDC_REF_TICK = 0, /*LEDC timer clock divided from reference tick(1Mhz) */ + LEDC_APB_CLK, /*LEDC timer clock divided from APB clock(80Mhz)*/ +} ledc_clk_src_t; + +typedef enum { + LEDC_TIMER_0 = 0, /*LEDC source timer TIMER0 */ + LEDC_TIMER_1, /*LEDC source timer TIMER1 */ + LEDC_TIMER_2, /*LEDC source timer TIMER2 */ + LEDC_TIMER_3, /*LEDC source timer TIMER3 */ +} ledc_timer_t; + +typedef enum { + LEDC_CHANNEL_0 = 0, /*LEDC channel 0 */ + LEDC_CHANNEL_1, /*LEDC channel 1 */ + LEDC_CHANNEL_2, /*LEDC channel 2 */ + LEDC_CHANNEL_3, /*LEDC channel 3 */ + LEDC_CHANNEL_4, /*LEDC channel 4 */ + LEDC_CHANNEL_5, /*LEDC channel 5 */ + LEDC_CHANNEL_6, /*LEDC channel 6 */ + LEDC_CHANNEL_7, /*LEDC channel 7 */ +} ledc_channel_t; + +typedef enum { + LEDC_TIMER_10_BIT = 10, /*LEDC PWM depth 10Bit */ + LEDC_TIMER_11_BIT = 11, /*LEDC PWM depth 11Bit */ + LEDC_TIMER_12_BIT = 12, /*LEDC PWM depth 12Bit */ + LEDC_TIMER_13_BIT = 13, /*LEDC PWM depth 13Bit */ + LEDC_TIMER_14_BIT = 14, /*LEDC PWM depth 14Bit */ + LEDC_TIMER_15_BIT = 15, /*LEDC PWM depth 15Bit */ +} ledc_timer_bit_t; + +typedef struct { + int gpio_num; /*the LEDC output gpio_num, if you want to use gpio16, gpio_num = 16*/ + ledc_mode_t speed_mode; /*LEDC speed speed_mode, high-speed mode or low-speed mode*/ + ledc_channel_t channel; /*LEDC channel(0 - 7)*/ + ledc_intr_type_t intr_type; /*configure interrupt, Fade interrupt enable or Fade interrupt disable*/ + ledc_timer_t timer_sel; /*Select the timer source of channel (0 - 3)*/ + uint32_t duty; /*LEDC channel duty, the duty range is [0, (2**bit_num) - 1], */ +} ledc_channel_config_t; + +typedef struct { + ledc_mode_t speed_mode; /*LEDC speed speed_mode, high-speed mode or low-speed mode*/ + ledc_timer_bit_t bit_num; /*LEDC channel duty depth*/ + ledc_timer_t timer_num; /*The timer source of channel (0 - 3)*/ + uint32_t freq_hz; /*LEDC timer frequency(Hz)*/ +} ledc_timer_config_t; + + +/** + * @brief LEDC channel configuration + * + * User this Function, configure LEDC channel with the given channel/output gpio_num/interrupt/source timer/frequency(Hz)/LEDC depth + * + * @param[in] ledc_channel_config_t + * ledc_channel_config_t.speed_mode : LEDC speed speed_mode + * ledc_channel_config_t.gpio_num : LEDC output gpio_num, if you want to use gpio16, ledc_channel_config_t.gpio_num = 16 + * ledc_channel_config_t.channel : LEDC channel(0 - 7) + * ledc_channel_config_t.intr_type : configure interrupt, Fade interrupt enable or Fade interrupt disable + * ledc_channel_config_t.timer_sel : Select the timer source of channel (0 - 3), high speed channel must bind with high speed timer. + * ledc_channel_config_t.duty : LEDC channel duty, the duty range is [0, (2**timer_bit_num) - 1], + * @return ESP_OK: success + * ESP_ERR_INVALID_ARG: parameter error + * + */ +esp_err_t ledc_channel_config(ledc_channel_config_t* ledc_conf); + +/** + * @brief LEDC timer configuration + * + * User this Function, configure LEDC timer with the given source timer/frequency(Hz)/bit_num + * + * @param[in] ledc_timer_config_t + * ledc_timer_config_t.speed_mode : LEDC speed speed_mode + * ledc_timer_config_t.timer_num : Select the timer source of channel (0 - 3) + * ledc_timer_config_t.freq_hz : LEDC channel frequency(Hz), + * ledc_timer_config_t.bit_num : LEDC channel duty depth + * @return ESP_OK: success + * ESP_ERR_INVALID_ARG: parameter error + * ESP_FAIL: Can not find a proper pre-divider number base on the given frequency and the current bit_num. + * + */ +esp_err_t ledc_timer_config(ledc_timer_config_t* timer_conf); + +/** + * @brief LEDC update channel parameters + * + * Call this function to activate the LEDC updated parameters. + * After ledc_set_duty, ledc_set_fade, we need to call this function to update the settings. + * + * @param[in] speed_mode : select the LEDC speed_mode, high-speed mode and low-speed mode, now we only support high-speed mode. We will access low-speed mode in next version + * + * @param[in] channel : LEDC channel(0-7), select from ledc_channel_t + * + * @return ESP_OK: success + * ESP_ERR_INVALID_ARG: parameter error + * + */ +esp_err_t ledc_update_duty(ledc_mode_t speed_mode, ledc_channel_t channel); + +/** + * @brief LEDC stop + * + * Disable LEDC output, and set idle level + * + * @param[in] speed_mode : select the LEDC speed_mode, high-speed mode and low-speed mode, now we only support high-speed mode. We will access low-speed mode in next version + * + * @param[in] channel : LEDC channel(0-7), select from ledc_channel_t + * + * @return ESP_OK: success + * ESP_ERR_INVALID_ARG: parameter error + */ +esp_err_t ledc_stop(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t idle_level); + +/** + * @brief LEDC set channel frequency(Hz) + * + * Set LEDC frequency(Hz) + * + * @param[in] speed_mode : select the LEDC speed_mode, high-speed mode and low-speed mode, now we only support high-speed mode. We will access low-speed mode in next version + * + * @param[in] timer_num : LEDC timer index(0-3), select from ledc_timer_t + * + * @param[in] freq_hz : set the LEDC frequency + * + * @return ESP_OK: success + * ESP_ERR_INVALID_ARG: parameter error + * ESP_FAIL: Can not find a proper pre-divider number base on the given frequency and the current bit_num. + */ +esp_err_t ledc_set_freq(ledc_mode_t speed_mode, ledc_timer_t timer_num, uint32_t freq_hz); + +/** + * @brief LEDC get channel frequency(Hz) + * + * @param[in] speed_mode : select the LEDC speed_mode, high-speed mode and low-speed mode, now we only support high-speed mode. We will access low-speed mode in next version + * + * @param[in] timer_num : LEDC timer index(0-3), select from ledc_timer_t + * + * @return 0 : error + * others : current LEDC frequency + * + */ +uint32_t ledc_get_freq(ledc_mode_t speed_mode, ledc_timer_t timer_num); + +/** + * @brief LEDC set duty + * + * Set LEDC duty, After the function calls the ledc_update_duty function, the function can take effect. + * + * @param[in] speed_mode : select the LEDC speed_mode, high-speed mode and low-speed mode, now we only support high-speed mode. We will access low-speed mode in next version + * + * @param[in] channel : LEDC channel(0-7), select from ledc_channel_t + * + * @param[in] duty : set the LEDC duty, the duty range is [0, (2**bit_num) - 1] + * + * @return ESP_OK: success + * ESP_ERR_INVALID_ARG: parameter error + */ +esp_err_t ledc_set_duty(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t duty); + +/** + * @brief LEDC get duty + * + * @param[in] speed_mode : select the LEDC speed_mode, high-speed mode and low-speed mode, now we only support high-speed mode. We will access low-speed mode in next version + * + * @param[in] channel : LEDC channel(0-7), select from ledc_channel_t + * + * + * @return -1: parameter error + * other value: current LEDC duty + * + */ +int ledc_get_duty(ledc_mode_t speed_mode, ledc_channel_t channel); + +/** + * @brief LEDC set gradient + * + * Set LEDC gradient, After the function calls the ledc_update_duty function, the function can take effect. + * + * @param[in] speed_mode : select the LEDC speed_mode, high-speed mode and low-speed mode, now we only support high-speed mode. We will access low-speed mode in next version + * + * @param[in] channel : LEDC channel(0-7), select from ledc_channel_t + * + * @param[in] duty : set the start of the gradient duty, the duty range is [0, (2**bit_num) - 1] + * + * @param[in] gradule_direction : set the direction of the gradient + * + * @param[in] step_num : set the number of the gradient + * + * @param[in] duty_cyle_num : set how many LEDC tick each time the gradient lasts + * + * @param[in] duty_scale : set gradient change amplitude + * + * @return ESP_OK : success + * ESP_ERR_INVALID_ARG : parameter error + */ +esp_err_t ledc_set_fade(ledc_mode_t speed_mode, uint32_t channel, uint32_t duty, ledc_duty_direction_t gradule_direction, + uint32_t step_num, uint32_t duty_cyle_num, uint32_t duty_scale); + +/** + * @brief register LEDC interrupt handler, the handler is an ISR. + * The handler will be attached to the same CPU core that this function is running on. + * Users should know that which CPU is running and then pick a INUM that is not used by system. + * We can find the information of INUM and interrupt level in soc.h. + * TODO: to move INUM options to menu_config + * @param[in] uint32_t ledc_intr_num : LEDC interrupt number, check the info in soc.h, and please see the core-isa.h for more details + * @param[in] void (* fn)(void* ) : interrupt handler function. + * Note that the handler function MUST be defined with attribution of "IRAM_ATTR". + * @param[in] void * arg : parameter for handler function + * + * @return ESP_OK : success ; + * ESP_ERR_INVALID_ARG : function ptr error. + */ +esp_err_t ledc_isr_register(uint32_t ledc_intr_num, void (*fn)(void*), void * arg); + +/** + * @brief configure LEDC settings + * + * @param[in] speed_mode : select the LEDC speed_mode, high-speed mode and low-speed mode, now we only support high-speed mode. We will access low-speed mode in next version + * + * @param[in] timer_sel : timer index(0-3), there are 4 timers in LEDC module + * + * @param[in] div_num : timer clock divide number, the timer clock is divided from the selected clock source + * + * @param[in] bit_num : the count number of one period, counter range is 0 ~ ((2 ** bit_num) - 1) + * + * @param[in] clk_src : select LEDC source clock. + * + * @return -1: parameter error + * other value: current LEDC duty + * + */ +esp_err_t ledc_timer_set(ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t div_num, uint32_t bit_num, ledc_clk_src_t clk_src); + +/** + * @brief reset LEDC timer + * + * @param[in] speed_mode : select the LEDC speed_mode, high-speed mode and low-speed mode, now we only support high-speed mode. We will access low-speed mode in next version + * + * @param[in] timer_sel : LEDC timer index(0-3), select from ledc_timer_t + * + * + * @return ESP_ERR_INVALID_ARG: parameter error + * ESP_OK: success + * + */ +esp_err_t ledc_timer_rst(ledc_mode_t speed_mode, uint32_t timer_sel); + +/** + * @brief pause LEDC timer counter + * + * @param[in] speed_mode : select the LEDC speed_mode, high-speed mode and low-speed mode, now we only support high-speed mode. We will access low-speed mode in next version + * + * @param[in] timer_sel : LEDC timer index(0-3), select from ledc_timer_t + * + * + * @return ESP_ERR_INVALID_ARG: parameter error + * ESP_OK: success + * + */ +esp_err_t ledc_timer_pause(ledc_mode_t speed_mode, uint32_t timer_sel); + +/** + * @brief pause LEDC timer resume + * + * @param[in] speed_mode : select the LEDC speed_mode, high-speed mode and low-speed mode, now we only support high-speed mode. We will access low-speed mode in next version + * + * @param[in] timer_sel : LEDC timer index(0-3), select from ledc_timer_t + * + * + * @return ESP_ERR_INVALID_ARG: parameter error + * ESP_OK: success + * + */ +esp_err_t ledc_timer_resume(ledc_mode_t speed_mode, uint32_t timer_sel); + +/** + * @brief bind LEDC channel with the selected timer + * + * @param[in] speed_mode : select the LEDC speed_mode, high-speed mode and low-speed mode, now we only support high-speed mode. We will access low-speed mode in next version + * + * @param[in] channel : LEDC channel index(0-7), select from ledc_channel_t + * + * @param[in] timer_idx : LEDC timer index(0-3), select from ledc_timer_t + * + * + * @return ESP_ERR_INVALID_ARG: parameter error + * ESP_OK: success + * + */ +esp_err_t ledc_bind_channel_timer(ledc_mode_t speed_mode, uint32_t channel, uint32_t timer_idx); + +/***************************EXAMPLE********************************** + * + * + * ----------------EXAMPLE OF LEDC SETTING --------------------- + * //1. enable LEDC + * periph_module_enable(PERIPH_LEDC_MODULE); //enable LEDC module, or you can not set any register of it. + * + * //2. set LEDC timer + * ledc_timer_config_t timer_conf = { + * .bit_num = LEDC_TIMER_12_BIT, //set timer counter bit number + * .freq_hz = 1000, //set frequency of pwm, here, 1000Hz + * .speed_mode = LEDC_HIGH_SPEED_MODE //timer mode, + * .timer_num = LEDC_TIMER_0, //timer number + * }; + * ledc_timer_config(&timer_conf); //setup timer. + * + * //3. set LEDC channel + * ledc_channel_config_t ledc_conf = { + * .channel = LEDC_CHANNEL_0; //set LEDC channel 0 + * .duty = 1000; //set the duty for initialization.(duty range is 0 ~ ((2**bit_num)-1) + * .gpio_num = 16; //GPIO number + * .intr_type = LEDC_INTR_FADE_END; //GPIO INTR TYPE, as an example, we enable fade_end interrupt here. + * .speed_mode = LEDC_HIGH_SPEED_MODE; //set LEDC mode, from ledc_mode_t + * .timer_sel = LEDC_TIMER_0; //set LEDC timer source, if different channel use one timer, the frequency and bit_num of these channels should be the same + * } + * ledc_channel_config(&ledc_conf); //setup the configuration + * + * ----------------EXAMPLE OF SETTING DUTY --- ----------------- + * uint32_t ledc_channel = LEDC_CHANNEL_0; //LEDC channel(0-73) + * uint32_t duty = 2000; //duty range is 0 ~ ((2**bit_num)-1) + * LEDC_set_duty(LEDC_HIGH_SPEED_MODE, ledc_channel, duty); //set speed mode, channel, and duty. + * ledc_update_duty(LEDC_HIGH_SPEED_MODE, ledc_channel); //after set duty, we need to call ledc_update_duty to update the settings. + * + * + * ----------------EXAMPLE OF LEDC INTERRUPT ------------------ + * //we have fade_end interrupt and counter overflow interrupt. we just give an example of fade_end interrupt here. + * ledc_isr_register(18, ledc_isr_handler, NULL); //hook the isr handler for LEDC interrupt + * //the first parameter is INUM, you can pick one form interrupt level 1/2 which is not used by the system. + * //NOTE1:user should arrange the INUMs that used, better not to use a same INUM for different interrupt source. + * //NOTE2:do not pick the INUM that already occupied by the system. + * //NOTE3:refer to soc.h to check which INUMs that can be used. + * ----------------EXAMPLE OF INTERRUPT HANDLER --------------- + * #include "esp_attr.h" + * void IRAM_ATTR ledc_isr_handler(void* arg) //we should add 'IRAM_ATTR' attribution when we declare the isr function + * { + * uint32_t intr_st = LEDC.int_st.val; //read LEDC interrupt status. + * + * //you will find which channels have triggered fade_end interrupt here, + * //then, you can post some event to RTOS queue to process the event. + * //later we will add a queue in the driver code. + * + * LEDC.int_clr.val = intr_st; //clear LEDC interrupt status. + * } + * + * + *--------------------------END OF EXAMPLE -------------------------- + */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_LEDC_H_ */ diff --git a/components/driver/include/driver/periph_ctrl.h b/components/driver/include/driver/periph_ctrl.h new file mode 100644 index 000000000..3faa347b5 --- /dev/null +++ b/components/driver/include/driver/periph_ctrl.h @@ -0,0 +1,70 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _DRIVER_PERIPH_CTRL_H_ +#define _DRIVER_PERIPH_CTRL_H_ +#include "esp_err.h" +#include "soc/soc.h" +#include "soc/dport_reg.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PERIPH_LEDC_MODULE = 0, + PERIPH_UART0_MODULE, + PERIPH_UART1_MODULE, + PERIPH_UART2_MODULE, + PERIPH_I2C0_MODULE, + PERIPH_I2C1_MODULE, + PERIPH_I2S0_MODULE, + PERIPH_I2S1_MODULE, + PERIPH_TIMG0_MODULE, + PERIPH_TIMG1_MODULE, + PERIPH_PWM0_MODULE, + PERIPH_PWM1_MODULE, + PERIPH_PWM2_MODULE, + PERIPH_PWM3_MODULE, + PERIPH_UHCI0_MODULE, + PERIPH_UHCI1_MODULE, +} periph_module_t; + +/** + * @brief enable peripheral module + * + * @param[in] periph : Peripheral module name + * + * + * @return NULL + * + */ +void periph_module_enable(periph_module_t periph); + +/** + * @brief disable peripheral module + * + * @param[in] periph : Peripheral module name + * + * + * @return NULL + * + */ +void periph_module_disable(periph_module_t periph); + +#ifdef __cplusplus +} +#endif + +#endif /* _DRIVER_PERIPH_CTRL_H_ */ diff --git a/components/driver/ledc.c b/components/driver/ledc.c new file mode 100644 index 000000000..386c93dfa --- /dev/null +++ b/components/driver/ledc.c @@ -0,0 +1,432 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#include +#include "esp_intr.h" +#include "freertos/FreeRTOS.h" +#include "freertos/semphr.h" +#include "freertos/xtensa_api.h" +#include "soc/gpio_sig_map.h" +#include "driver/ledc.h" + +//TODO: to use APIs in esp_log.h. +#define LEDC_DBG_WARING_ENABLE (0) +#define LEDC_DBG_ERROR_ENABLE (0) +#define LEDC_INFO_ENABLE (0) +#define LEDC_DBG_ENABLE (0) + +//DBG INFOR +#if LEDC_DBG_ENABLE +#define LEDC_DBG(format,...) do{\ + ets_printf("[dbg][%s#%u]",__FUNCTION__,__LINE__);\ + ets_printf(format,##__VA_ARGS__);\ +}while(0) +#else +#define LEDC_DBG(...) +#endif + +#if LEDC_INFO_ENABLE +#define LEDC_INFO(format,...) do{\ + ets_printf("[info][%s#%u]",__FUNCTION__,__LINE__);\ + ets_printf(format,##__VA_ARGS__);\ +}while(0) +#else +#define LEDC_INFO(...) +#endif + +#if LEDC_DBG_WARING_ENABLE +#define LEDC_WARING(format,...) do{\ + ets_printf("[waring][%s#%u]",__FUNCTION__,__LINE__);\ + ets_printf(format,##__VA_ARGS__);\ +}while(0) +#else +#define LEDC_WARING(...) +#endif +#if LEDC_DBG_ERROR_ENABLE +#define LEDC_ERROR(format,...) do{\ + ets_printf("[error][%s#%u]",__FUNCTION__,__LINE__);\ + ets_printf(format,##__VA_ARGS__);\ +}while(0) +#else +#define LEDC_ERROR(...) +#endif + +static portMUX_TYPE ledc_spinlock = portMUX_INITIALIZER_UNLOCKED; + +static bool ledc_is_valid_channel(uint32_t channel) +{ + if(channel > LEDC_CHANNEL_7) { + LEDC_ERROR("LEDC CHANNEL ERR: %d\n",channel); + return false; + } + return true; +} + +static bool ledc_is_valid_mode(uint32_t mode) +{ + if(mode >= LEDC_SPEED_MODE_MAX) { + LEDC_ERROR("LEDC MODE ERR: %d\n",mode); + return false; + } + return true; +} + +static bool ledc_is_valid_timer(int timer) +{ + if(timer > LEDC_TIMER_3) { + LEDC_ERROR("LEDC TIMER ERR: %d\n", timer); + return false; + } + return true; +} + +esp_err_t ledc_timer_set(ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t div_num, uint32_t bit_num, ledc_clk_src_t clk_src) +{ + if(!ledc_is_valid_mode(speed_mode)) { + return ESP_ERR_INVALID_ARG; + } + if(!ledc_is_valid_timer(timer_sel)) { + return ESP_ERR_INVALID_ARG; + } + portENTER_CRITICAL(&ledc_spinlock); + LEDC.timer_group[speed_mode].timer[timer_sel].conf.div_num = div_num; + LEDC.timer_group[speed_mode].timer[timer_sel].conf.tick_sel = clk_src; + LEDC.timer_group[speed_mode].timer[timer_sel].conf.bit_num = bit_num; + if(speed_mode != LEDC_HIGH_SPEED_MODE) { + LEDC.timer_group[speed_mode].timer[timer_sel].conf.low_speed_update = 1; + } + portEXIT_CRITICAL(&ledc_spinlock); + return ESP_OK; +} + +static esp_err_t ledc_duty_config(ledc_mode_t speed_mode, uint32_t channel_num, uint32_t hpoint_val, uint32_t duty_val, + uint32_t duty_direction, uint32_t duty_num, uint32_t duty_cycle, uint32_t duty_scale) +{ + portENTER_CRITICAL(&ledc_spinlock); + LEDC.channel_group[speed_mode].channel[channel_num].hpoint.hpoint = hpoint_val; + LEDC.channel_group[speed_mode].channel[channel_num].duty.duty = duty_val; + LEDC.channel_group[speed_mode].channel[channel_num].conf1.val = ((duty_direction & LEDC_DUTY_INC_HSCH0_V) << LEDC_DUTY_INC_HSCH0_S) | + ((duty_num & LEDC_DUTY_NUM_HSCH0_V) << LEDC_DUTY_NUM_HSCH0_S) | + ((duty_cycle & LEDC_DUTY_CYCLE_HSCH0_V) << LEDC_DUTY_CYCLE_HSCH0_S) | + ((duty_scale & LEDC_DUTY_SCALE_HSCH0_V) << LEDC_DUTY_SCALE_HSCH0_S); + portEXIT_CRITICAL(&ledc_spinlock); + return ESP_OK; +} + +esp_err_t ledc_bind_channel_timer(ledc_mode_t speed_mode, uint32_t channel, uint32_t timer_idx) +{ + if(!ledc_is_valid_mode(speed_mode)) { + return ESP_ERR_INVALID_ARG; + } + if(!ledc_is_valid_timer(timer_idx)) { + return ESP_ERR_INVALID_ARG; + } + portENTER_CRITICAL(&ledc_spinlock); + LEDC.channel_group[speed_mode].channel[channel].conf0.timer_sel = timer_idx; + portEXIT_CRITICAL(&ledc_spinlock); + return ESP_OK; +} + +esp_err_t ledc_timer_rst(ledc_mode_t speed_mode, uint32_t timer_sel) +{ + if(!ledc_is_valid_mode(speed_mode)) { + return ESP_ERR_INVALID_ARG; + } + if(!ledc_is_valid_timer(timer_sel)) { + return ESP_ERR_INVALID_ARG; + } + portENTER_CRITICAL(&ledc_spinlock); + LEDC.timer_group[speed_mode].timer[timer_sel].conf.rst = 1; + LEDC.timer_group[speed_mode].timer[timer_sel].conf.rst = 0; + portEXIT_CRITICAL(&ledc_spinlock); + return ESP_OK; +} + +esp_err_t ledc_timer_pause(ledc_mode_t speed_mode, uint32_t timer_sel) +{ + if(!ledc_is_valid_mode(speed_mode)) { + return ESP_ERR_INVALID_ARG; + } + if(!ledc_is_valid_timer(timer_sel)) { + return ESP_ERR_INVALID_ARG; + } + portENTER_CRITICAL(&ledc_spinlock); + LEDC.timer_group[speed_mode].timer[timer_sel].conf.pause = 1; + portEXIT_CRITICAL(&ledc_spinlock); + return ESP_OK; +} + +esp_err_t ledc_timer_resume(ledc_mode_t speed_mode, uint32_t timer_sel) +{ + if(!ledc_is_valid_mode(speed_mode)) { + return ESP_ERR_INVALID_ARG; + } + if(!ledc_is_valid_timer(timer_sel)) { + return ESP_ERR_INVALID_ARG; + } + portENTER_CRITICAL(&ledc_spinlock); + LEDC.timer_group[speed_mode].timer[timer_sel].conf.pause = 0; + portEXIT_CRITICAL(&ledc_spinlock); + return ESP_OK; +} + +static esp_err_t ledc_enable_intr_type(ledc_mode_t speed_mode, uint32_t channel, ledc_intr_type_t type) +{ + if(!ledc_is_valid_mode(speed_mode)) { + return ESP_ERR_INVALID_ARG; + } + uint32_t value; + uint32_t intr_type = type; + portENTER_CRITICAL(&ledc_spinlock); + value = LEDC.int_ena.val; + if(intr_type == LEDC_INTR_FADE_END) { + LEDC.int_ena.val = value | BIT(LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_S + channel); + } else { + LEDC.int_ena.val = (value & (~(BIT(LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_S + channel)))); + } + portEXIT_CRITICAL(&ledc_spinlock); + return ESP_OK; +} + +esp_err_t ledc_isr_register(uint32_t ledc_intr_num, void (*fn)(void*), void * arg) +{ + if(fn == NULL) { + return ESP_ERR_INVALID_ARG; + } + portENTER_CRITICAL(&ledc_spinlock); + ESP_INTR_DISABLE(ledc_intr_num); + intr_matrix_set(xPortGetCoreID(), ETS_LEDC_INTR_SOURCE, ledc_intr_num); + xt_set_interrupt_handler(ledc_intr_num, fn, arg); + ESP_INTR_ENABLE(ledc_intr_num); + portEXIT_CRITICAL(&ledc_spinlock); + return ESP_OK; +} + +esp_err_t ledc_timer_config(ledc_timer_config_t* timer_conf) +{ + int freq_hz = timer_conf->freq_hz; + int bit_num = timer_conf->bit_num; + int timer_num = timer_conf->timer_num; + int speed_mode = timer_conf->speed_mode; + + if(!ledc_is_valid_mode(speed_mode)) { + return ESP_ERR_INVALID_ARG; + } + if(freq_hz == 0 || bit_num == 0 || bit_num > LEDC_TIMER_15_BIT) { + LEDC_ERROR("freq_hz=%u bit_num=%u\n", freq_hz, bit_num); + return ESP_ERR_INVALID_ARG; + } + if(timer_num > LEDC_TIMER_3) { + LEDC_ERROR("Time Select %u\n", timer_num); + return ESP_ERR_INVALID_ARG; + } + esp_err_t ret = ESP_OK; + uint32_t precision = (0x1 << bit_num); //2**depth + uint64_t div_param = ((uint64_t) LEDC_APB_CLK_HZ << 8) / freq_hz / precision; //8bit fragment + int timer_clk_src; + /*Fail ,because the div_num overflow or too small*/ + if(div_param <= 256 || div_param > LEDC_DIV_NUM_HSTIMER0_V) { //REF TICK + /*Selet the reference tick*/ + div_param = ((uint64_t) LEDC_REF_CLK_HZ << 8) / freq_hz / precision; + if(div_param <= 256 || div_param > LEDC_DIV_NUM_HSTIMER0_V) { + LEDC_ERROR("div param err,div_param=%u\n", div_param); + ret = ESP_FAIL; + } + timer_clk_src = LEDC_REF_TICK; + } else { //APB TICK + timer_clk_src = LEDC_APB_CLK; + } + /*set timer parameters*/ + /*timer settings decide the clk of counter and the period of PWM*/ + ledc_timer_set(speed_mode, timer_num, div_param, bit_num, timer_clk_src); + /* reset timer.*/ + ledc_timer_rst(speed_mode, timer_num); + return ret; +} + +esp_err_t ledc_channel_config(ledc_channel_config_t* ledc_conf) +{ + uint32_t speed_mode = ledc_conf->speed_mode; + uint32_t gpio_num = ledc_conf->gpio_num; + uint32_t ledc_channel = ledc_conf->channel; + uint32_t timer_select = ledc_conf->timer_sel; + uint32_t intr_type = ledc_conf->intr_type; + uint32_t duty = ledc_conf->duty; + + if(!ledc_is_valid_channel(ledc_channel)) { + return ESP_ERR_INVALID_ARG; + } + if(!ledc_is_valid_mode(speed_mode)) { + return ESP_ERR_INVALID_ARG; + } + if(!GPIO_IS_VALID_OUTPUT_GPIO(gpio_num)) { + LEDC_ERROR("GPIO number error: IO%d\n ", gpio_num); + return ESP_ERR_INVALID_ARG; + } + if(timer_select > LEDC_TIMER_3) { + LEDC_ERROR("Time Select %u\n", timer_select); + return ESP_ERR_INVALID_ARG; + } + esp_err_t ret = ESP_OK; + /*set channel parameters*/ + /* channel parameters decide how the waveform looks like in one period*/ + /* set channel duty, duty range is (0 ~ ((2 ** bit_num) - 1))*/ + ledc_set_duty(speed_mode, ledc_channel, duty); + /*update duty settings*/ + ledc_update_duty(speed_mode, ledc_channel); + /*bind the channel with the timer*/ + ledc_bind_channel_timer(speed_mode, ledc_channel, timer_select); + /*set interrupt type*/ + ledc_enable_intr_type(speed_mode, ledc_channel, intr_type); + LEDC_INFO("LEDC_PWM CHANNEL %1u|GPIO %02u|Duty %04u|Time %01u\n", + ledc_channel, gpio_num, duty, timer_select + ); + /*set LEDC signal in gpio matrix*/ + PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO); + gpio_set_direction(gpio_num, GPIO_MODE_OUTPUT); + gpio_matrix_out(gpio_num, LEDC_HS_SIG_OUT0_IDX + ledc_channel, 0, 0); + return ret; +} + +esp_err_t ledc_update_duty(ledc_mode_t speed_mode, ledc_channel_t channel) +{ + if(!ledc_is_valid_mode(speed_mode)) { + return ESP_ERR_INVALID_ARG; + } + if(!ledc_is_valid_channel(channel)) { + return ESP_ERR_INVALID_ARG; + } + portENTER_CRITICAL(&ledc_spinlock); + LEDC.channel_group[speed_mode].channel[channel].conf0.sig_out_en = 1; + LEDC.channel_group[speed_mode].channel[channel].conf1.duty_start = 1; + portEXIT_CRITICAL(&ledc_spinlock); + return ESP_OK; +} + +esp_err_t ledc_stop(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t idle_level) +{ + if(!ledc_is_valid_mode(speed_mode)) { + return ESP_ERR_INVALID_ARG; + } + if(!ledc_is_valid_channel(channel)) { + return ESP_ERR_INVALID_ARG; + } + portENTER_CRITICAL(&ledc_spinlock); + LEDC.channel_group[speed_mode].channel[channel].conf0.idle_lv = idle_level & 0x1; + LEDC.channel_group[speed_mode].channel[channel].conf0.sig_out_en = 0; + LEDC.channel_group[speed_mode].channel[channel].conf1.duty_start = 0; + portEXIT_CRITICAL(&ledc_spinlock); + return ESP_OK; +} +esp_err_t ledc_set_fade(ledc_mode_t speed_mode, uint32_t channel, uint32_t duty, ledc_duty_direction_t fade_direction, + uint32_t step_num, uint32_t duty_cyle_num, uint32_t duty_scale) +{ + if(!ledc_is_valid_mode(speed_mode)) { + return ESP_ERR_INVALID_ARG; + } + if(!ledc_is_valid_channel(channel)) { + return ESP_ERR_INVALID_ARG; + } + if(fade_direction > LEDC_DUTY_DIR_INCREASE) { + LEDC_ERROR("Duty direction err\n"); + return ESP_ERR_INVALID_ARG; + } + if(step_num > LEDC_DUTY_NUM_HSCH0_V || duty_cyle_num > LEDC_DUTY_CYCLE_HSCH0_V || duty_scale > LEDC_DUTY_SCALE_HSCH0_V) { + LEDC_ERROR("step_num=%u duty_cyle_num=%u duty_scale=%u\n", step_num, duty_cyle_num, duty_scale); + return ESP_ERR_INVALID_ARG; + } + ledc_duty_config(speed_mode, + channel, //uint32_t chan_num, + 0, //uint32_t hpoint_val, + duty << 4, //uint32_t duty_val,the least 4 bits are decimal part + fade_direction, //uint32_t increase, + step_num, //uint32_t duty_num, + duty_cyle_num, //uint32_t duty_cycle, + duty_scale //uint32_t duty_scale + ); + return ESP_OK; +} + +esp_err_t ledc_set_duty(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t duty) +{ + if(!ledc_is_valid_mode(speed_mode)) { + return ESP_ERR_INVALID_ARG; + } + if(!ledc_is_valid_channel(channel)) { + return ESP_ERR_INVALID_ARG; + } + ledc_duty_config(speed_mode, + channel, //uint32_t chan_num, + 0, //uint32_t hpoint_val, + duty << 4, //uint32_t duty_val,the least 4 bits are decimal part + 1, //uint32_t increase, + 1, //uint32_t duty_num, + 1, //uint32_t duty_cycle, + 0 //uint32_t duty_scale + ); + return ESP_OK; +} + +int ledc_get_duty(ledc_mode_t speed_mode, ledc_channel_t channel) +{ + if(!ledc_is_valid_mode(speed_mode)) { + return -1; + } + uint32_t duty = (LEDC.channel_group[speed_mode].channel[channel].duty_rd.duty_read >> 4); + return duty; +} + +esp_err_t ledc_set_freq(ledc_mode_t speed_mode, ledc_timer_t timer_num, uint32_t freq_hz) +{ + if(!ledc_is_valid_mode(speed_mode)) { + return ESP_ERR_INVALID_ARG; + } + portENTER_CRITICAL(&ledc_spinlock); + esp_err_t ret = ESP_OK; + uint32_t div_num = 0; + uint32_t bit_num = LEDC.timer_group[speed_mode].timer[timer_num].conf.bit_num; + uint32_t timer_source_clk = LEDC.timer_group[speed_mode].timer[timer_num].conf.tick_sel; + uint32_t precision = (0x1 << bit_num); + if(timer_source_clk == LEDC_APB_CLK) { + div_num = ((uint64_t) LEDC_APB_CLK_HZ << 8) / freq_hz / precision; + } else { + div_num = ((uint64_t) LEDC_REF_CLK_HZ << 8) / freq_hz / precision; + } + if(div_num <= 256 || div_num > LEDC_DIV_NUM_HSTIMER0) { + LEDC_ERROR("div param err,div_param=%u\n", div_num); + ret = ESP_FAIL; + } + LEDC.timer_group[speed_mode].timer[timer_num].conf.div_num = div_num; + portEXIT_CRITICAL(&ledc_spinlock); + return ret; +} + +uint32_t ledc_get_freq(ledc_mode_t speed_mode, ledc_timer_t timer_num) +{ + if(!ledc_is_valid_mode(speed_mode)) { + return 0; + } + portENTER_CRITICAL(&ledc_spinlock); + uint32_t freq = 0; + uint32_t timer_source_clk = LEDC.timer_group[speed_mode].timer[timer_num].conf.tick_sel; + uint32_t bit_num = LEDC.timer_group[speed_mode].timer[timer_num].conf.bit_num; + uint32_t div_num = LEDC.timer_group[speed_mode].timer[timer_num].conf.div_num; + uint32_t precision = (0x1 << bit_num); + if(timer_source_clk == LEDC_APB_CLK) { + freq = ((uint64_t) LEDC_APB_CLK_HZ << 8) / precision / div_num; + } else { + freq = ((uint64_t) LEDC_REF_CLK_HZ << 8) / precision / div_num; + } + portEXIT_CRITICAL(&ledc_spinlock); + return freq; +} diff --git a/components/driver/periph_ctrl.c b/components/driver/periph_ctrl.c new file mode 100644 index 000000000..3a671abad --- /dev/null +++ b/components/driver/periph_ctrl.c @@ -0,0 +1,170 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#include +#include "esp_intr.h" +#include "freertos/FreeRTOS.h" +#include "freertos/semphr.h" +#include "freertos/xtensa_api.h" +#include "soc/dport_reg.h" +#include "driver/periph_ctrl.h" + +static portMUX_TYPE periph_spinlock = portMUX_INITIALIZER_UNLOCKED; + +void periph_module_enable(periph_module_t periph) +{ + portENTER_CRITICAL(&periph_spinlock); + switch(periph) { + case PERIPH_LEDC_MODULE: + SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_LEDC_CLK_EN); + CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_LEDC_RST); + break; + case PERIPH_UART0_MODULE: + SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UART_CLK_EN); + CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART_RST); + break; + case PERIPH_UART1_MODULE: + SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UART1_CLK_EN); + CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART1_RST); + break; + case PERIPH_UART2_MODULE: + SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UART2_CLK_EN); + CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART2_RST); + break; + case PERIPH_I2C0_MODULE: + SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2C_EXT0_CLK_EN); + CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2C_EXT0_RST); + break; + case PERIPH_I2C1_MODULE: + SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2C_EXT1_CLK_EN); + CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2C_EXT1_RST); + break; + case PERIPH_I2S0_MODULE: + SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN); + CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST); + break; + case PERIPH_I2S1_MODULE: + SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S1_CLK_EN); + CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S1_RST); + break; + case PERIPH_TIMG0_MODULE: + SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_TIMERGROUP_CLK_EN); + CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_TIMERGROUP_RST); + break; + case PERIPH_TIMG1_MODULE: + SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_TIMERGROUP1_CLK_EN); + CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_TIMERGROUP1_RST); + break; + case PERIPH_PWM0_MODULE: + SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PWM0_CLK_EN); + CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PWM0_RST); + break; + case PERIPH_PWM1_MODULE: + SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PWM1_CLK_EN); + CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PWM1_RST); + break; + case PERIPH_PWM2_MODULE: + SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PWM2_CLK_EN); + CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PWM2_RST); + break; + case PERIPH_PWM3_MODULE: + SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PWM3_CLK_EN); + CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PWM3_RST); + break; + case PERIPH_UHCI0_MODULE: + SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UHCI0_CLK_EN); + CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UHCI0_RST); + break; + case PERIPH_UHCI1_MODULE: + SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UHCI1_CLK_EN); + CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UHCI1_RST); + break; + default: + break; + } + portEXIT_CRITICAL(&periph_spinlock); +} + +void periph_module_disable(periph_module_t periph) +{ + portENTER_CRITICAL(&periph_spinlock); + switch(periph) { + case PERIPH_LEDC_MODULE: + CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_LEDC_CLK_EN); + SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_LEDC_RST); + break; + case PERIPH_UART0_MODULE: + CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UART_CLK_EN); + SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART_RST); + break; + case PERIPH_UART1_MODULE: + CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UART1_CLK_EN); + SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART1_RST); + break; + case PERIPH_UART2_MODULE: + CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UART2_CLK_EN); + SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART2_RST); + break; + case PERIPH_I2C0_MODULE: + CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2C_EXT0_CLK_EN); + SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2C_EXT0_RST); + break; + case PERIPH_I2C1_MODULE: + CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2C_EXT0_CLK_EN); + SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2C_EXT1_RST); + break; + case PERIPH_I2S0_MODULE: + CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN); + SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST); + break; + case PERIPH_I2S1_MODULE: + CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S1_CLK_EN); + SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S1_RST); + break; + case PERIPH_TIMG0_MODULE: + CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_TIMERGROUP_CLK_EN); + SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_TIMERGROUP_RST); + break; + case PERIPH_TIMG1_MODULE: + CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_TIMERGROUP1_CLK_EN); + SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_TIMERGROUP1_RST); + break; + case PERIPH_PWM0_MODULE: + CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PWM0_CLK_EN); + SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PWM0_RST); + break; + case PERIPH_PWM1_MODULE: + CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PWM1_CLK_EN); + SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PWM1_RST); + break; + case PERIPH_PWM2_MODULE: + CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PWM2_CLK_EN); + SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PWM2_RST); + break; + case PERIPH_PWM3_MODULE: + CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_PWM3_CLK_EN); + SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_PWM3_RST); + break; + case PERIPH_UHCI0_MODULE: + CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UHCI0_CLK_EN); + SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UHCI0_RST); + break; + case PERIPH_UHCI1_MODULE: + CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UHCI1_CLK_EN); + SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UHCI1_RST); + break; + default: + break; + } + portEXIT_CRITICAL(&periph_spinlock); +} diff --git a/components/esp32/include/soc/io_mux_reg.h b/components/esp32/include/soc/io_mux_reg.h index f6ec4e520..208a60703 100644 --- a/components/esp32/include/soc/io_mux_reg.h +++ b/components/esp32/include/soc/io_mux_reg.h @@ -40,6 +40,8 @@ #define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD) #define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC) +#define PIN_FUNC_GPIO 2 + #define PIN_CTRL (DR_REG_IO_MUX_BASE +0x00) #define CLK_OUT3 0xf #define CLK_OUT3_S 8 @@ -48,84 +50,17 @@ #define CLK_OUT1 0xf #define CLK_OUT1_S 0 -#define PERIPHS_IO_MUX_GPIO36_U (DR_REG_IO_MUX_BASE +0x04) -#define FUNC_GPIO36_GPIO36 2 -#define FUNC_GPIO36_GPIO36_0 0 +#define PERIPHS_IO_MUX_GPIO0_U (DR_REG_IO_MUX_BASE +0x44) +#define FUNC_GPIO0_EMAC_TX_CLK 5 +#define FUNC_GPIO0_GPIO0 2 +#define FUNC_GPIO0_CLK_OUT1 1 +#define FUNC_GPIO0_GPIO0_0 0 -#define PERIPHS_IO_MUX_GPIO37_U (DR_REG_IO_MUX_BASE +0x08) -#define FUNC_GPIO37_GPIO37 2 -#define FUNC_GPIO37_GPIO37_0 0 - -#define PERIPHS_IO_MUX_GPIO38_U (DR_REG_IO_MUX_BASE +0x0c) -#define FUNC_GPIO38_GPIO38 2 -#define FUNC_GPIO38_GPIO38_0 0 - -#define PERIPHS_IO_MUX_GPIO39_U (DR_REG_IO_MUX_BASE +0x10) -#define FUNC_GPIO39_GPIO39 2 -#define FUNC_GPIO39_GPIO39_0 0 - -#define PERIPHS_IO_MUX_GPIO34_U (DR_REG_IO_MUX_BASE +0x14) -#define FUNC_GPIO34_GPIO34 2 -#define FUNC_GPIO34_GPIO34_0 0 - -#define PERIPHS_IO_MUX_GPIO35_U (DR_REG_IO_MUX_BASE +0x18) -#define FUNC_GPIO35_GPIO35 2 -#define FUNC_GPIO35_GPIO35_0 0 - -#define PERIPHS_IO_MUX_GPIO32_U (DR_REG_IO_MUX_BASE +0x1c) -#define FUNC_GPIO32_GPIO32 2 -#define FUNC_GPIO32_GPIO32_0 0 - -#define PERIPHS_IO_MUX_GPIO33_U (DR_REG_IO_MUX_BASE +0x20) -#define FUNC_GPIO33_GPIO33 2 -#define FUNC_GPIO33_GPIO33_0 0 - -#define PERIPHS_IO_MUX_GPIO25_U (DR_REG_IO_MUX_BASE +0x24) -#define FUNC_GPIO25_EMAC_RXD0 5 -#define FUNC_GPIO25_GPIO25 2 -#define FUNC_GPIO25_GPIO25_0 0 - -#define PERIPHS_IO_MUX_GPIO26_U (DR_REG_IO_MUX_BASE +0x28) -#define FUNC_GPIO26_EMAC_RXD1 5 -#define FUNC_GPIO26_GPIO26 2 -#define FUNC_GPIO26_GPIO26_0 0 - -#define PERIPHS_IO_MUX_GPIO27_U (DR_REG_IO_MUX_BASE +0x2c) -#define FUNC_GPIO27_EMAC_RX_DV 5 -#define FUNC_GPIO27_GPIO27 2 -#define FUNC_GPIO27_GPIO27_0 0 - -#define PERIPHS_IO_MUX_MTMS_U (DR_REG_IO_MUX_BASE +0x30) -#define FUNC_MTMS_EMAC_TXD2 5 -#define FUNC_MTMS_SD_CLK 4 -#define FUNC_MTMS_HS2_CLk 3 -#define FUNC_MTMS_GPIO14 2 -#define FUNC_MTMS_HSPICLK 1 -#define FUNC_MTMS_MTMS 0 - -#define PERIPHS_IO_MUX_MTDI_U (DR_REG_IO_MUX_BASE +0x34) -#define FUNC_MTDI_EMAC_TXD3 5 -#define FUNC_MTDI_SD_DATA2 4 -#define FUNC_MTDI_HS2_DATA2 3 -#define FUNC_MTDI_GPIO12 2 -#define FUNC_MTDI_HSPIQ 1 -#define FUNC_MTDI_MTDI 0 - -#define PERIPHS_IO_MUX_MTCK_U (DR_REG_IO_MUX_BASE +0x38) -#define FUNC_MTCK_EMAC_RX_ER 5 -#define FUNC_MTCK_SD_DATA3 4 -#define FUNC_MTCK_HS2_DATA3 3 -#define FUNC_MTCK_GPIO13 2 -#define FUNC_MTCK_HSPID 1 -#define FUNC_MTCK_MTCK 0 - -#define PERIPHS_IO_MUX_MTDO_U (DR_REG_IO_MUX_BASE +0x3c) -#define FUNC_MTDO_EMAC_RXD3 5 -#define FUNC_MTDO_SD_CMD 4 -#define FUNC_MTDO_HS2_CMD 3 -#define FUNC_MTDO_GPIO15 2 -#define FUNC_MTDO_HSPICS0 1 -#define FUNC_MTDO_MTDO 0 +#define PERIPHS_IO_MUX_U0TXD_U (DR_REG_IO_MUX_BASE +0x88) +#define FUNC_U0TXD_EMAC_RXD2 3 +#define FUNC_U0TXD_GPIO1 2 +#define FUNC_U0TXD_CLK_OUT3 1 +#define FUNC_U0TXD_U0TXD 0 #define PERIPHS_IO_MUX_GPIO2_U (DR_REG_IO_MUX_BASE +0x40) #define FUNC_GPIO2_SD_DATA0 4 @@ -134,11 +69,10 @@ #define FUNC_GPIO2_HSPIWP 1 #define FUNC_GPIO2_GPIO2_0 0 -#define PERIPHS_IO_MUX_GPIO0_U (DR_REG_IO_MUX_BASE +0x44) -#define FUNC_GPIO0_EMAC_TX_CLK 5 -#define FUNC_GPIO0_GPIO0 2 -#define FUNC_GPIO0_CLK_OUT1 1 -#define FUNC_GPIO0_GPIO0_0 0 +#define PERIPHS_IO_MUX_U0RXD_U (DR_REG_IO_MUX_BASE +0x84) +#define FUNC_U0RXD_GPIO3 2 +#define FUNC_U0RXD_CLK_OUT2 1 +#define FUNC_U0RXD_U0RXD 0 #define PERIPHS_IO_MUX_GPIO4_U (DR_REG_IO_MUX_BASE +0x48) #define FUNC_GPIO4_EMAC_TX_ER 5 @@ -148,40 +82,12 @@ #define FUNC_GPIO4_HSPIHD 1 #define FUNC_GPIO4_GPIO4_0 0 -#define PERIPHS_IO_MUX_GPIO16_U (DR_REG_IO_MUX_BASE +0x4c) -#define FUNC_GPIO16_EMAC_CLK_OUT 5 -#define FUNC_GPIO16_U2RXD 4 -#define FUNC_GPIO16_HS1_DATA4 3 -#define FUNC_GPIO16_GPIO16 2 -#define FUNC_GPIO16_GPIO16_0 0 - -#define PERIPHS_IO_MUX_GPIO17_U (DR_REG_IO_MUX_BASE +0x50) -#define FUNC_GPIO17_EMAC_CLK_OUT_180 5 -#define FUNC_GPIO17_U2TXD 4 -#define FUNC_GPIO17_HS1_DATA5 3 -#define FUNC_GPIO17_GPIO17 2 -#define FUNC_GPIO17_GPIO17_0 0 - -#define PERIPHS_IO_MUX_SD_DATA2_U (DR_REG_IO_MUX_BASE +0x54) -#define FUNC_SD_DATA2_U1RXD 4 -#define FUNC_SD_DATA2_HS1_DATA2 3 -#define FUNC_SD_DATA2_GPIO9 2 -#define FUNC_SD_DATA2_SPIHD 1 -#define FUNC_SD_DATA2_SD_DATA2 0 - -#define PERIPHS_IO_MUX_SD_DATA3_U (DR_REG_IO_MUX_BASE +0x58) -#define FUNC_SD_DATA3_U1TXD 4 -#define FUNC_SD_DATA3_HS1_DATA3 3 -#define FUNC_SD_DATA3_GPIO10 2 -#define FUNC_SD_DATA3_SPIWP 1 -#define FUNC_SD_DATA3_SD_DATA3 0 - -#define PERIPHS_IO_MUX_SD_CMD_U (DR_REG_IO_MUX_BASE +0x5c) -#define FUNC_SD_CMD_U1RTS 4 -#define FUNC_SD_CMD_HS1_CMD 3 -#define FUNC_SD_CMD_GPIO11 2 -#define FUNC_SD_CMD_SPICS0 1 -#define FUNC_SD_CMD_SD_CMD 0 +#define PERIPHS_IO_MUX_GPIO5_U (DR_REG_IO_MUX_BASE +0x6c) +#define FUNC_GPIO5_EMAC_RX_CLK 5 +#define FUNC_GPIO5_HS1_DATA6 3 +#define FUNC_GPIO5_GPIO5 2 +#define FUNC_GPIO5_VSPICS0 1 +#define FUNC_GPIO5_GPIO5_0 0 #define PERIPHS_IO_MUX_SD_CLK_U (DR_REG_IO_MUX_BASE +0x60) #define FUNC_SD_CLK_U1CTS 4 @@ -204,12 +110,72 @@ #define FUNC_SD_DATA1_SPID 1 #define FUNC_SD_DATA1_SD_DATA1 0 -#define PERIPHS_IO_MUX_GPIO5_U (DR_REG_IO_MUX_BASE +0x6c) -#define FUNC_GPIO5_EMAC_RX_CLK 5 -#define FUNC_GPIO5_HS1_DATA6 3 -#define FUNC_GPIO5_GPIO5 2 -#define FUNC_GPIO5_VSPICS0 1 -#define FUNC_GPIO5_GPIO5_0 0 +#define PERIPHS_IO_MUX_SD_DATA2_U (DR_REG_IO_MUX_BASE +0x54) +#define FUNC_SD_DATA2_U1RXD 4 +#define FUNC_SD_DATA2_HS1_DATA2 3 +#define FUNC_SD_DATA2_GPIO9 2 +#define FUNC_SD_DATA2_SPIHD 1 +#define FUNC_SD_DATA2_SD_DATA2 0 + +#define PERIPHS_IO_MUX_SD_DATA3_U (DR_REG_IO_MUX_BASE +0x58) +#define FUNC_SD_DATA3_U1TXD 4 +#define FUNC_SD_DATA3_HS1_DATA3 3 +#define FUNC_SD_DATA3_GPIO10 2 +#define FUNC_SD_DATA3_SPIWP 1 +#define FUNC_SD_DATA3_SD_DATA3 0 + +#define PERIPHS_IO_MUX_SD_CMD_U (DR_REG_IO_MUX_BASE +0x5c) +#define FUNC_SD_CMD_U1RTS 4 +#define FUNC_SD_CMD_HS1_CMD 3 +#define FUNC_SD_CMD_GPIO11 2 +#define FUNC_SD_CMD_SPICS0 1 +#define FUNC_SD_CMD_SD_CMD 0 + +#define PERIPHS_IO_MUX_MTDI_U (DR_REG_IO_MUX_BASE +0x34) +#define FUNC_MTDI_EMAC_TXD3 5 +#define FUNC_MTDI_SD_DATA2 4 +#define FUNC_MTDI_HS2_DATA2 3 +#define FUNC_MTDI_GPIO12 2 +#define FUNC_MTDI_HSPIQ 1 +#define FUNC_MTDI_MTDI 0 + +#define PERIPHS_IO_MUX_MTCK_U (DR_REG_IO_MUX_BASE +0x38) +#define FUNC_MTCK_EMAC_RX_ER 5 +#define FUNC_MTCK_SD_DATA3 4 +#define FUNC_MTCK_HS2_DATA3 3 +#define FUNC_MTCK_GPIO13 2 +#define FUNC_MTCK_HSPID 1 +#define FUNC_MTCK_MTCK 0 + +#define PERIPHS_IO_MUX_MTMS_U (DR_REG_IO_MUX_BASE +0x30) +#define FUNC_MTMS_EMAC_TXD2 5 +#define FUNC_MTMS_SD_CLK 4 +#define FUNC_MTMS_HS2_CLk 3 +#define FUNC_MTMS_GPIO14 2 +#define FUNC_MTMS_HSPICLK 1 +#define FUNC_MTMS_MTMS 0 + +#define PERIPHS_IO_MUX_MTDO_U (DR_REG_IO_MUX_BASE +0x3c) +#define FUNC_MTDO_EMAC_RXD3 5 +#define FUNC_MTDO_SD_CMD 4 +#define FUNC_MTDO_HS2_CMD 3 +#define FUNC_MTDO_GPIO15 2 +#define FUNC_MTDO_HSPICS0 1 +#define FUNC_MTDO_MTDO 0 + +#define PERIPHS_IO_MUX_GPIO16_U (DR_REG_IO_MUX_BASE +0x4c) +#define FUNC_GPIO16_EMAC_CLK_OUT 5 +#define FUNC_GPIO16_U2RXD 4 +#define FUNC_GPIO16_HS1_DATA4 3 +#define FUNC_GPIO16_GPIO16 2 +#define FUNC_GPIO16_GPIO16_0 0 + +#define PERIPHS_IO_MUX_GPIO17_U (DR_REG_IO_MUX_BASE +0x50) +#define FUNC_GPIO17_EMAC_CLK_OUT_180 5 +#define FUNC_GPIO17_U2TXD 4 +#define FUNC_GPIO17_HS1_DATA5 3 +#define FUNC_GPIO17_GPIO17 2 +#define FUNC_GPIO17_GPIO17_0 0 #define PERIPHS_IO_MUX_GPIO18_U (DR_REG_IO_MUX_BASE +0x70) #define FUNC_GPIO18_HS1_DATA7 3 @@ -241,17 +207,6 @@ #define FUNC_GPIO22_VSPIWP 1 #define FUNC_GPIO22_GPIO22_0 0 -#define PERIPHS_IO_MUX_U0RXD_U (DR_REG_IO_MUX_BASE +0x84) -#define FUNC_U0RXD_GPIO3 2 -#define FUNC_U0RXD_CLK_OUT2 1 -#define FUNC_U0RXD_U0RXD 0 - -#define PERIPHS_IO_MUX_U0TXD_U (DR_REG_IO_MUX_BASE +0x88) -#define FUNC_U0TXD_EMAC_RXD2 3 -#define FUNC_U0TXD_GPIO1 2 -#define FUNC_U0TXD_CLK_OUT3 1 -#define FUNC_U0TXD_U0TXD 0 - #define PERIPHS_IO_MUX_GPIO23_U (DR_REG_IO_MUX_BASE +0x8c) #define FUNC_GPIO23_HS1_STROBE 3 #define FUNC_GPIO23_GPIO23 2 @@ -262,4 +217,51 @@ #define FUNC_GPIO24_GPIO24 2 #define FUNC_GPIO24_GPIO24_0 0 +#define PERIPHS_IO_MUX_GPIO25_U (DR_REG_IO_MUX_BASE +0x24) +#define FUNC_GPIO25_EMAC_RXD0 5 +#define FUNC_GPIO25_GPIO25 2 +#define FUNC_GPIO25_GPIO25_0 0 + +#define PERIPHS_IO_MUX_GPIO26_U (DR_REG_IO_MUX_BASE +0x28) +#define FUNC_GPIO26_EMAC_RXD1 5 +#define FUNC_GPIO26_GPIO26 2 +#define FUNC_GPIO26_GPIO26_0 0 + +#define PERIPHS_IO_MUX_GPIO27_U (DR_REG_IO_MUX_BASE +0x2c) +#define FUNC_GPIO27_EMAC_RX_DV 5 +#define FUNC_GPIO27_GPIO27 2 +#define FUNC_GPIO27_GPIO27_0 0 + +#define PERIPHS_IO_MUX_GPIO32_U (DR_REG_IO_MUX_BASE +0x1c) +#define FUNC_GPIO32_GPIO32 2 +#define FUNC_GPIO32_GPIO32_0 0 + +#define PERIPHS_IO_MUX_GPIO33_U (DR_REG_IO_MUX_BASE +0x20) +#define FUNC_GPIO33_GPIO33 2 +#define FUNC_GPIO33_GPIO33_0 0 + +#define PERIPHS_IO_MUX_GPIO34_U (DR_REG_IO_MUX_BASE +0x14) +#define FUNC_GPIO34_GPIO34 2 +#define FUNC_GPIO34_GPIO34_0 0 + +#define PERIPHS_IO_MUX_GPIO35_U (DR_REG_IO_MUX_BASE +0x18) +#define FUNC_GPIO35_GPIO35 2 +#define FUNC_GPIO35_GPIO35_0 0 + +#define PERIPHS_IO_MUX_GPIO36_U (DR_REG_IO_MUX_BASE +0x04) +#define FUNC_GPIO36_GPIO36 2 +#define FUNC_GPIO36_GPIO36_0 0 + +#define PERIPHS_IO_MUX_GPIO37_U (DR_REG_IO_MUX_BASE +0x08) +#define FUNC_GPIO37_GPIO37 2 +#define FUNC_GPIO37_GPIO37_0 0 + +#define PERIPHS_IO_MUX_GPIO38_U (DR_REG_IO_MUX_BASE +0x0c) +#define FUNC_GPIO38_GPIO38 2 +#define FUNC_GPIO38_GPIO38_0 0 + +#define PERIPHS_IO_MUX_GPIO39_U (DR_REG_IO_MUX_BASE +0x10) +#define FUNC_GPIO39_GPIO39 2 +#define FUNC_GPIO39_GPIO39_0 0 + #endif /* _SOC_IO_MUX_REG_H_ */ diff --git a/components/esp32/include/soc/ledc_struct.h b/components/esp32/include/soc/ledc_struct.h index d44720a14..d119289ac 100644 --- a/components/esp32/include/soc/ledc_struct.h +++ b/components/esp32/include/soc/ledc_struct.h @@ -14,133 +14,74 @@ #ifndef _SOC_LEDC_STRUCT_H_ #define _SOC_LEDC_STRUCT_H_ typedef volatile struct { - struct{ - union { - struct { - uint32_t timer_sel: 2; /*There are four high speed timers the two bits are used to select one of them for high speed channel. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ - uint32_t sig_out_en: 1; /*This is the output enable control bit for high speed channel*/ - uint32_t idle_lv: 1; /*This bit is used to control the output value when high speed channel is off.*/ - uint32_t reserved4: 27; - uint32_t clk_en: 1; /*This bit is clock gating control signal. when software configure LED_PWM internal registers it controls the register clock.*/ - }; - uint32_t val; - } conf0; - union { - struct { - uint32_t hpoint: 20; /*The output value changes to high when htimerx(x=[0 3]) selected by high speed channel has reached reg_hpoint_hsch0[19:0]*/ - uint32_t reserved20: 12; - }; - uint32_t val; - } hpoint; - union { - struct { - uint32_t duty: 25; /*The register is used to control output duty. When hstimerx(x=[0 3]) chosen by high speed channel has reached reg_lpoint_hsch0 the output signal changes to low. reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4]) (1) reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ - uint32_t reserved25: 7; - }; - uint32_t val; - } duty; - union { - struct { - uint32_t duty_scale:10; /*This register controls the increase or decrease step scale for high speed channel.*/ - uint32_t duty_cycle:10; /*This register is used to increase or decrease the duty every reg_duty_cycle_hsch0 cycles for high speed channel.*/ - uint32_t duty_num: 10; /*This register is used to control the number of increased or decreased times for high speed channel.*/ - uint32_t duty_inc: 1; /*This register is used to increase the duty of output signal or decrease the duty of output signal for high speed channel.*/ - uint32_t duty_start: 1; /*When reg_duty_num_hsch0 reg_duty_cycle_hsch0 and reg_duty_scale_hsch0 has been configured. these register won't take effect until set reg_duty_start_hsch0. this bit is automatically cleared by hardware.*/ - }; - uint32_t val; - } conf1; - union { - struct { - uint32_t duty_read: 25; /*This register represents the current duty of the output signal for high speed channel.*/ - uint32_t reserved25: 7; - }; - uint32_t val; - } duty_rd; - } high_speed_channel[8]; - struct{ - union { - struct { - uint32_t timer_sel: 2; /*There are four low speed timers the two bits are used to select one of them for low speed channel. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ - uint32_t sig_out_en: 1; /*This is the output enable control bit for low speed channel.*/ - uint32_t idle_lv: 1; /*This bit is used to control the output value when low speed channel is off.*/ - uint32_t para_up: 1; /*This bit is used to update register LEDC_LSCH0_HPOINT and LEDC_LSCH0_DUTY for low speed channel.*/ - uint32_t reserved5: 27; - }; - uint32_t val; - } conf0; - union { - struct { - uint32_t hpoint: 20; /*The output value changes to high when lstimerx(x=[0 3]) selected by low speed channel has reached reg_hpoint_lsch0[19:0]*/ - uint32_t reserved20: 12; - }; - uint32_t val; - } hpoint; - union { - struct { - uint32_t duty: 25; /*The register is used to control output duty. When lstimerx(x=[0 3]) choosed by low speed channel has reached reg_lpoint_lsch0 the output signal changes to low. reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4]) (1) reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ - uint32_t reserved25: 7; - }; - uint32_t val; - } duty; - union { - struct { - uint32_t duty_scale:10; /*This register controls the increase or decrease step scale for low speed channel.*/ - uint32_t duty_cycle:10; /*This register is used to increase or decrease the duty every reg_duty_cycle_lsch0 cycles for low speed channel.*/ - uint32_t duty_num: 10; /*This register is used to control the num of increased or decreased times for low speed channel6.*/ - uint32_t duty_inc: 1; /*This register is used to increase the duty of output signal or decrease the duty of output signal for low speed channel6.*/ - uint32_t duty_start: 1; /*When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ - }; - uint32_t val; - } conf1; - union { - struct { - uint32_t duty_read: 25; /*This register represents the current duty of the output signal for low speed channel.*/ - uint32_t reserved25: 7; - }; - uint32_t val; - } duty_r; - } low_speed_channel[8]; - struct{ - union { - struct { - uint32_t timer_lim: 5; /*This register controls the range of the counter in high speed timer. the counter range is [0 2**reg_hstimer0_lim] the max bit width for counter is 20.*/ - uint32_t div_num: 18; /*This register is used to configure parameter for divider in high speed timer the least significant eight bits represent the decimal part.*/ - uint32_t pause: 1; /*This bit is used to pause the counter in high speed timer*/ - uint32_t rst: 1; /*This bit is used to reset high speed timer the counter will be 0 after reset.*/ - uint32_t tick_sel: 1; /*This bit is used to choose apb_clk or ref_tick for high speed timer. 1'b1:apb_clk 0:ref_tick*/ - uint32_t reserved26: 6; - }; - uint32_t val; - } conf; - union { - struct { - uint32_t timer_cnt: 20; /*software can read this register to get the current counter value in high speed timer*/ - uint32_t reserved20: 12; - }; - uint32_t val; - } value; - } high_speed_timer[4]; - struct{ - union { - struct { - uint32_t timer_lim: 5; /*This register controls the range of the counter in low speed timer. the counter range is [0 2**reg_lstimer0_lim] the max bit width for counter is 20.*/ - uint32_t div_num: 18; /*This register is used to configure parameter for divider in low speed timer the least significant eight bits represent the decimal part.*/ - uint32_t pause: 1; /*This bit is used to pause the counter in low speed timer.*/ - uint32_t rst: 1; /*This bit is used to reset low speed timer the counter will be 0 after reset.*/ - uint32_t tick_sel: 1; /*This bit is used to choose slow_clk or ref_tick for low speed timer. 1'b1:slow_clk 0:ref_tick*/ - uint32_t param_update: 1; /*Set this bit to update reg_div_num_lstime0 and reg_lstimer0_lim.*/ - uint32_t reserved27: 5; - }; - uint32_t val; - } conf; - union { - struct { - uint32_t timer_cnt: 20; /*software can read this register to get the current counter value in low speed timer.*/ - uint32_t reserved20: 12; - }; - uint32_t val; - } value; - } low_speed_timer[4]; + struct { + struct { + union { + struct { + uint32_t timer_sel: 2; /*There are four high speed timers the two bits are used to select one of them for high speed channel. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ + uint32_t sig_out_en: 1; /*This is the output enable control bit for high speed channel*/ + uint32_t idle_lv: 1; /*This bit is used to control the output value when high speed channel is off.*/ + uint32_t reserved4: 27; + uint32_t clk_en: 1; /*This bit is clock gating control signal. when software configure LED_PWM internal registers it controls the register clock.*/ + }; + uint32_t val; + } conf0; + union { + struct { + uint32_t hpoint: 20; /*The output value changes to high when htimerx(x=[0 3]) selected by high speed channel has reached reg_hpoint_hsch0[19:0]*/ + uint32_t reserved20: 12; + }; + uint32_t val; + } hpoint; + union { + struct { + uint32_t duty: 25; /*The register is used to control output duty. When hstimerx(x=[0 3]) chosen by high speed channel has reached reg_lpoint_hsch0 the output signal changes to low. reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4]) (1) reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ + uint32_t reserved25: 7; + }; + uint32_t val; + } duty; + union { + struct { + uint32_t duty_scale:10; /*This register controls the increase or decrease step scale for high speed channel.*/ + uint32_t duty_cycle:10; /*This register is used to increase or decrease the duty every reg_duty_cycle_hsch0 cycles for high speed channel.*/ + uint32_t duty_num: 10; /*This register is used to control the number of increased or decreased times for high speed channel.*/ + uint32_t duty_inc: 1; /*This register is used to increase the duty of output signal or decrease the duty of output signal for high speed channel.*/ + uint32_t duty_start: 1; /*When reg_duty_num_hsch0 reg_duty_cycle_hsch0 and reg_duty_scale_hsch0 has been configured. these register won't take effect until set reg_duty_start_hsch0. this bit is automatically cleared by hardware.*/ + }; + uint32_t val; + } conf1; + union { + struct { + uint32_t duty_read: 25; /*This register represents the current duty of the output signal for high speed channel.*/ + uint32_t reserved25: 7; + }; + uint32_t val; + } duty_rd; + } channel[8]; + } channel_group[2]; /*two channel groups : 0: high-speed channels; 1: low-speed channels*/ + struct { + struct { + union { + struct { + uint32_t bit_num: 5; /*This register controls the range of the counter in high speed timer. the counter range is [0 2**reg_hstimer0_lim] the max bit width for counter is 20.*/ + uint32_t div_num: 18; /*This register is used to configure parameter for divider in high speed timer the least significant eight bits represent the decimal part.*/ + uint32_t pause: 1; /*This bit is used to pause the counter in high speed timer*/ + uint32_t rst: 1; /*This bit is used to reset high speed timer the counter will be 0 after reset.*/ + uint32_t tick_sel: 1; /*This bit is used to choose apb_clk or ref_tick for high speed timer. 1'b1:apb_clk 0:ref_tick*/ + uint32_t low_speed_update: 1; /*This bit is only useful for low speed timer channels, reserved for high speed timers*/ + uint32_t reserved26: 5; + }; + uint32_t val; + } conf; + union { + struct { + uint32_t timer_cnt: 20; /*software can read this register to get the current counter value in high speed timer*/ + uint32_t reserved20: 12; + }; + uint32_t val; + } value; + } timer[4]; + } timer_group[2]; /*two channel groups : 0: high-speed channels; 1: low-speed channels*/ union { struct { uint32_t hstimer0_ovf: 1; /*The interrupt raw bit for high speed channel0 counter overflow.*/