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Merge branch 'bugfix/timer_group_intr_enable_v3.3' into 'release/v3.3'

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Fix timer group intr enable (backport v3.3)

See merge request espressif/esp-idf!8531
This commit is contained in:
Michael (XIAO Xufeng) 2020-05-08 15:00:16 +08:00
parent 2c1c87b37d 67131b7d78
commit 44d1c90d25
4 changed files with 38 additions and 19 deletions
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4
components/driver/include/driver/sigmadelta.h
View file

@ -19,7 +19,7 @@
#include "soc/gpio_sd_reg.h"
#include "driver/gpio.h"
#ifdef _cplusplus
#ifdef __cplusplus
extern "C" {
#endif
@ -102,7 +102,7 @@ esp_err_t sigmadelta_set_prescale(sigmadelta_channel_t channel, uint8_t prescale
*/
esp_err_t sigmadelta_set_pin(sigmadelta_channel_t channel, gpio_num_t gpio_num);
#ifdef _cplusplus
#ifdef __cplusplus
}
#endif

26
components/driver/timer.c
View file

@ -259,7 +259,12 @@ esp_err_t timer_group_intr_enable(timer_group_t group_num, uint32_t en_mask)
{
TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
portENTER_CRITICAL(&timer_spinlock[group_num]);
TG[group_num]->int_ena.val |= en_mask;
for (int i = 0; i < 2; i++) {
if (en_mask & (1 << i)) {
TG[group_num]->hw_timer[i].config.level_int_en = 1;
TG[group_num]->int_ena.val |= (1 << i);
}
}
portEXIT_CRITICAL(&timer_spinlock[group_num]);
return ESP_OK;
}
@ -268,7 +273,12 @@ esp_err_t timer_group_intr_disable(timer_group_t group_num, uint32_t disable_mas
{
TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
portENTER_CRITICAL(&timer_spinlock[group_num]);
TG[group_num]->int_ena.val &= (~disable_mask);
for (int i = 0; i < 2; i++) {
if (disable_mask & (1 << i)) {
TG[group_num]->hw_timer[i].config.level_int_en = 0;
TG[group_num]->int_ena.val &= ~(1 << i);
}
}
portEXIT_CRITICAL(&timer_spinlock[group_num]);
return ESP_OK;
}
@ -277,14 +287,22 @@ esp_err_t timer_enable_intr(timer_group_t group_num, timer_idx_t timer_num)
{
TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
return timer_group_intr_enable(group_num, BIT(timer_num));
portENTER_CRITICAL(&timer_spinlock[group_num]);
TG[group_num]->hw_timer[timer_num].config.level_int_en = 1;
TG[group_num]->int_ena.val |= (1 << timer_num);
portEXIT_CRITICAL(&timer_spinlock[group_num]);
return ESP_OK;
}
esp_err_t timer_disable_intr(timer_group_t group_num, timer_idx_t timer_num)
{
TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
return timer_group_intr_disable(group_num, BIT(timer_num));
portENTER_CRITICAL(&timer_spinlock[group_num]);
TG[group_num]->hw_timer[timer_num].config.level_int_en = 0;
TG[group_num]->int_ena.val &= ~(1 << timer_num);
portEXIT_CRITICAL(&timer_spinlock[group_num]);
return ESP_OK;
}

1
components/freertos/test/test_suspend_scheduler.c
View file

@ -108,6 +108,7 @@ TEST_CASE("Scheduler disabled can handle a pending context switch on resume", "[
// When we resume scheduler, we expect the counter task
// will preempt and count at least one more item
esp_intr_noniram_enable();
timer_enable_intr(TIMER_GROUP_0, TIMER_0);
xTaskResumeAll();
TEST_ASSERT_NOT_EQUAL(count_config.counter, no_sched_task);

14
examples/peripherals/timer_group/main/timer_group_example_main.c
View file

@ -108,13 +108,13 @@ static void example_tg0_timer_init(int timer_idx,
bool auto_reload, double timer_interval_sec)
{
/* Select and initialize basic parameters of the timer */
timer_config_t config;
config.divider = TIMER_DIVIDER;
config.counter_dir = TIMER_COUNT_UP;
config.counter_en = TIMER_PAUSE;
config.alarm_en = TIMER_ALARM_EN;
config.intr_type = TIMER_INTR_LEVEL;
config.auto_reload = auto_reload;
timer_config_t config = {
.divider = TIMER_DIVIDER,
.counter_dir = TIMER_COUNT_UP,
.counter_en = TIMER_PAUSE,
.alarm_en = TIMER_ALARM_EN,
.auto_reload = auto_reload,
}; // default clock source is APB
timer_init(TIMER_GROUP_0, timer_idx, &config);
/* Timer's counter will initially start from value below.