Remove superfluous example
This commit is contained in:
Jeroen Domburg
parent
fe3082fa98
commit
43c0758b8d
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@ -1,9 +0,0 @@
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#
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# This is a project Makefile. It is assumed the directory this Makefile resides in is a
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# project subdirectory.
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#
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PROJECT_NAME := psram_demo
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include $(IDF_PATH)/make/project.mk
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@ -1,31 +0,0 @@
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简介：
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本工程主要演示psram的初始化以及读写操作
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注意事项：
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psram进行读写操作软件应用层面需要做原子保护
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###Brief:
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This example shows how to
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* init psram: call psram_enable() API
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* PSRAM_CACHE_F40M_S40M mean flash cache 40Mhz and sram cache 40Mhz, which is the recommended option in current version.
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* read & write psram: Must add lock for read/write operations in this version.
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* We need to initialize mmu in set_cache_and_start_app() of bootloader_start.c, refer to bootloader_start.c in the demo folder.
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```
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//32KBytes for each page, totally 128 pages, that is 4MBytes.
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cache_sram_mmu_set( 0, 0, 0x3f800000, 0, 32, 128 );
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```
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###Restrictions:
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1. GPIO16, GPIO17 and GPIO20 are occupied, can not be used in app code.
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2. GPIO matrix signal 224 and 225 are occupied, can not be used in app code.
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3. SPI1 is used to initialize the psram chip.
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4. Must add lock for psram read/write operations in this version.
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5. ~~For now, we have some confilcts between spi flash read/write and psram driver, we will resolve it soon.~~
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###update on 161206: Item No.5 has been fixed
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@ -1,620 +0,0 @@
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <string.h>
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#include <stdint.h>
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#include <limits.h>
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#include "esp_attr.h"
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#include "esp_log.h"
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#include "rom/cache.h"
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#include "rom/ets_sys.h"
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#include "rom/spi_flash.h"
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#include "rom/crc.h"
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#include "rom/rtc.h"
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#include "soc/soc.h"
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#include "soc/cpu.h"
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#include "soc/dport_reg.h"
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#include "soc/io_mux_reg.h"
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#include "soc/efuse_reg.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/timer_group_reg.h"
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#include "sdkconfig.h"
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#include "esp_image_format.h"
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#include "esp_secure_boot.h"
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#include "bootloader_flash.h"
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#include "bootloader_config.h"
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extern int _bss_start;
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extern int _bss_end;
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static const char* TAG = "boot";
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/*
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We arrive here after the bootloader finished loading the program from flash. The hardware is mostly uninitialized,
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flash cache is down and the app CPU is in reset. We do have a stack, so we can do the initialization in C.
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*/
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// TODO: make a nice header file for ROM functions instead of adding externs all over the place
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extern void Cache_Flush(int);
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void bootloader_main();
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static void unpack_load_app(const esp_partition_pos_t *app_node);
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void print_flash_info(const esp_image_header_t* pfhdr);
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void set_cache_and_start_app(uint32_t drom_addr,
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uint32_t drom_load_addr,
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uint32_t drom_size,
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uint32_t irom_addr,
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uint32_t irom_load_addr,
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uint32_t irom_size,
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uint32_t entry_addr);
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static void update_flash_config(const esp_image_header_t* pfhdr);
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void IRAM_ATTR call_start_cpu0()
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{
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cpu_configure_region_protection();
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//Clear bss
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memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start));
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/* completely reset MMU for both CPUs
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(in case serial bootloader was running) */
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Cache_Read_Disable(0);
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Cache_Read_Disable(1);
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Cache_Flush(0);
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Cache_Flush(1);
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mmu_init(0);
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REG_SET_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
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mmu_init(1);
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REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
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/* (above steps probably unnecessary for most serial bootloader
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usage, all that's absolutely needed is that we unmask DROM0
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cache on the following two lines - normal ROM boot exits with
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DROM0 cache unmasked, but serial bootloader exits with it
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masked. However can't hurt to be thorough and reset
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everything.)
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The lines which manipulate DPORT_APP_CACHE_MMU_IA_CLR bit are
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necessary to work around a hardware bug.
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*/
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REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MASK_DROM0);
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REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DROM0);
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bootloader_main();
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}
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/**
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* @function : load_partition_table
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* @description: Parse partition table, get useful data such as location of
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* OTA info sector, factory app sector, and test app sector.
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*
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* @inputs: bs bootloader state structure used to save the data
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* @return: return true, if the partition table is loaded (and MD5 checksum is valid)
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*
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*/
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bool load_partition_table(bootloader_state_t* bs)
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{
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const esp_partition_info_t *partitions;
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const int ESP_PARTITION_TABLE_DATA_LEN = 0xC00; /* length of actual data (signature is appended to this) */
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const int MAX_PARTITIONS = ESP_PARTITION_TABLE_DATA_LEN / sizeof(esp_partition_info_t);
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char *partition_usage;
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ESP_LOGI(TAG, "Partition Table:");
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ESP_LOGI(TAG, "## Label Usage Type ST Offset Length");
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#ifdef CONFIG_SECURE_BOOTLOADER_ENABLED
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if(esp_secure_boot_enabled()) {
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ESP_LOGI(TAG, "Verifying partition table signature...");
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esp_err_t err = esp_secure_boot_verify_signature(ESP_PARTITION_TABLE_ADDR, ESP_PARTITION_TABLE_DATA_LEN);
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if (err != ESP_OK) {
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ESP_LOGE(TAG, "Failed to verify partition table signature.");
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return false;
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}
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ESP_LOGD(TAG, "Partition table signature verified");
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}
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#endif
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partitions = bootloader_mmap(ESP_PARTITION_TABLE_ADDR, ESP_PARTITION_TABLE_DATA_LEN);
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if (!partitions) {
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ESP_LOGE(TAG, "bootloader_mmap(0x%x, 0x%x) failed", ESP_PARTITION_TABLE_ADDR, ESP_PARTITION_TABLE_DATA_LEN);
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return false;
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}
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ESP_LOGD(TAG, "mapped partition table 0x%x at 0x%x", ESP_PARTITION_TABLE_ADDR, (intptr_t)partitions);
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for(int i = 0; i < MAX_PARTITIONS; i++) {
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const esp_partition_info_t *partition = &partitions[i];
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ESP_LOGD(TAG, "load partition table entry 0x%x", (intptr_t)partition);
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ESP_LOGD(TAG, "type=%x subtype=%x", partition->type, partition->subtype);
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partition_usage = "unknown";
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if (partition->magic != ESP_PARTITION_MAGIC) {
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/* invalid partition definition indicates end-of-table */
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break;
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}
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/* valid partition table */
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switch(partition->type) {
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case PART_TYPE_APP: /* app partition */
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switch(partition->subtype) {
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case PART_SUBTYPE_FACTORY: /* factory binary */
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bs->factory = partition->pos;
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partition_usage = "factory app";
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break;
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case PART_SUBTYPE_TEST: /* test binary */
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bs->test = partition->pos;
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partition_usage = "test app";
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break;
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default:
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/* OTA binary */
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if ((partition->subtype & ~PART_SUBTYPE_OTA_MASK) == PART_SUBTYPE_OTA_FLAG) {
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bs->ota[partition->subtype & PART_SUBTYPE_OTA_MASK] = partition->pos;
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++bs->app_count;
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partition_usage = "OTA app";
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}
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else {
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partition_usage = "Unknown app";
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}
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break;
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}
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break; /* PART_TYPE_APP */
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case PART_TYPE_DATA: /* data partition */
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switch(partition->subtype) {
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case PART_SUBTYPE_DATA_OTA: /* ota data */
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bs->ota_info = partition->pos;
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partition_usage = "OTA data";
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break;
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case PART_SUBTYPE_DATA_RF:
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partition_usage = "RF data";
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break;
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case PART_SUBTYPE_DATA_WIFI:
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partition_usage = "WiFi data";
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break;
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default:
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partition_usage = "Unknown data";
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break;
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}
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break; /* PARTITION_USAGE_DATA */
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default: /* other partition type */
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break;
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}
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/* print partition type info */
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ESP_LOGI(TAG, "%2d %-16s %-16s %02x %02x %08x %08x", i, partition->label, partition_usage,
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partition->type, partition->subtype,
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partition->pos.offset, partition->pos.size);
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}
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bootloader_munmap(partitions);
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ESP_LOGI(TAG,"End of partition table");
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return true;
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}
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static uint32_t ota_select_crc(const esp_ota_select_entry_t *s)
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{
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return crc32_le(UINT32_MAX, (uint8_t*)&s->ota_seq, 4);
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}
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static bool ota_select_valid(const esp_ota_select_entry_t *s)
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{
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return s->ota_seq != UINT32_MAX && s->crc == ota_select_crc(s);
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}
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/**
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* @function : bootloader_main
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* @description: entry function of 2nd bootloader
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*
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* @inputs: void
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*/
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void bootloader_main()
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{
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ESP_LOGI(TAG, "Espressif ESP32 2nd stage bootloader v. %s", BOOT_VERSION);
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esp_image_header_t fhdr;
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bootloader_state_t bs;
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SpiFlashOpResult spiRet1,spiRet2;
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esp_ota_select_entry_t sa,sb;
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const esp_ota_select_entry_t *ota_select_map;
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memset(&bs, 0, sizeof(bs));
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ESP_LOGI(TAG, "compile time " __TIME__ );
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/* disable watch dog here */
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REG_CLR_BIT( RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_FLASHBOOT_MOD_EN );
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REG_CLR_BIT( TIMG_WDTCONFIG0_REG(0), TIMG_WDT_FLASHBOOT_MOD_EN );
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SPIUnlock();
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if(esp_image_load_header(0x1000, &fhdr) != ESP_OK) {
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ESP_LOGE(TAG, "failed to load bootloader header!");
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return;
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}
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print_flash_info(&fhdr);
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update_flash_config(&fhdr);
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if (!load_partition_table(&bs)) {
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ESP_LOGE(TAG, "load partition table error!");
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return;
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}
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esp_partition_pos_t load_part_pos;
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if (bs.ota_info.offset != 0) { // check if partition table has OTA info partition
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//ESP_LOGE("OTA info sector handling is not implemented");
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if (bs.ota_info.size < 2 * sizeof(esp_ota_select_entry_t)) {
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ESP_LOGE(TAG, "ERROR: ota_info partition size %d is too small (minimum %d bytes)", bs.ota_info.size, sizeof(esp_ota_select_entry_t));
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return;
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}
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ota_select_map = bootloader_mmap(bs.ota_info.offset, bs.ota_info.size);
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if (!ota_select_map) {
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ESP_LOGE(TAG, "bootloader_mmap(0x%x, 0x%x) failed", bs.ota_info.offset, bs.ota_info.size);
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return;
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}
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sa = ota_select_map[0];
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sb = ota_select_map[1];
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bootloader_munmap(ota_select_map);
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if(sa.ota_seq == 0xFFFFFFFF && sb.ota_seq == 0xFFFFFFFF) {
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// init status flash
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if (bs.factory.offset != 0) { // if have factory bin,boot factory bin
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load_part_pos = bs.factory;
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} else {
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load_part_pos = bs.ota[0];
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sa.ota_seq = 0x01;
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sa.crc = ota_select_crc(&sa);
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sb.ota_seq = 0x00;
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sb.crc = ota_select_crc(&sb);
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Cache_Read_Disable(0);
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spiRet1 = SPIEraseSector(bs.ota_info.offset/0x1000);
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spiRet2 = SPIEraseSector(bs.ota_info.offset/0x1000+1);
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if (spiRet1 != SPI_FLASH_RESULT_OK || spiRet2 != SPI_FLASH_RESULT_OK ) {
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ESP_LOGE(TAG, SPI_ERROR_LOG);
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return;
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}
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spiRet1 = SPIWrite(bs.ota_info.offset,(uint32_t *)&sa,sizeof(esp_ota_select_entry_t));
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spiRet2 = SPIWrite(bs.ota_info.offset + 0x1000,(uint32_t *)&sb,sizeof(esp_ota_select_entry_t));
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if (spiRet1 != SPI_FLASH_RESULT_OK || spiRet2 != SPI_FLASH_RESULT_OK ) {
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ESP_LOGE(TAG, SPI_ERROR_LOG);
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return;
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}
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Cache_Read_Enable(0);
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}
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//TODO:write data in ota info
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} else {
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if(ota_select_valid(&sa) && ota_select_valid(&sb)) {
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load_part_pos = bs.ota[(((sa.ota_seq > sb.ota_seq)?sa.ota_seq:sb.ota_seq) - 1)%bs.app_count];
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}else if(ota_select_valid(&sa)) {
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load_part_pos = bs.ota[(sa.ota_seq - 1) % bs.app_count];
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}else if(ota_select_valid(&sb)) {
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load_part_pos = bs.ota[(sb.ota_seq - 1) % bs.app_count];
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}else {
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ESP_LOGE(TAG, "ota data partition info error");
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return;
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}
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}
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} else if (bs.factory.offset != 0) { // otherwise, look for factory app partition
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load_part_pos = bs.factory;
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} else if (bs.test.offset != 0) { // otherwise, look for test app parition
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load_part_pos = bs.test;
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} else { // nothing to load, bail out
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ESP_LOGE(TAG, "nothing to load");
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return;
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}
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ESP_LOGI(TAG, "Loading app partition at offset %08x", load_part_pos);
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#ifdef CONFIG_SECURE_BOOTLOADER_ENABLED
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/* Generate secure digest from this bootloader to protect future
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modifications */
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esp_err_t err = esp_secure_boot_permanently_enable();
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if (err != ESP_OK) {
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ESP_LOGE(TAG, "Bootloader digest generation failed (%d). SECURE BOOT IS NOT ENABLED.", err);
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/* Allow booting to continue, as the failure is probably
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due to user-configured EFUSEs for testing...
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*/
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}
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#endif
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if(fhdr.encrypt_flag == 0x01) {
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/* encrypt flash */
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if (false == flash_encrypt(&bs)) {
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ESP_LOGE(TAG, "flash encrypt failed");
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return;
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}
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}
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// copy loaded segments to RAM, set up caches for mapped segments, and start application
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unpack_load_app(&load_part_pos);
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}
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static void unpack_load_app(const esp_partition_pos_t* partition)
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{
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esp_err_t err;
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esp_image_header_t image_header;
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uint32_t image_length;
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/* TODO: verify the app image as part of OTA boot decision, so can have fallbacks */
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err = esp_image_basic_verify(partition->offset, &image_length);
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if (err != ESP_OK) {
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ESP_LOGE(TAG, "Failed to verify app image @ 0x%x (%d)", partition->offset, err);
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return;
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}
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#ifdef CONFIG_SECURE_BOOTLOADER_ENABLED
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if (esp_secure_boot_enabled()) {
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ESP_LOGI(TAG, "Verifying app signature @ 0x%x (length 0x%x)", partition->offset, image_length);
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err = esp_secure_boot_verify_signature(partition->offset, image_length);
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if (err != ESP_OK) {
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ESP_LOGE(TAG, "App image @ 0x%x failed signature verification (%d)", partition->offset, err);
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return;
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}
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ESP_LOGD(TAG, "App signature is valid");
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}
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#endif
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if (esp_image_load_header(partition->offset, &image_header) != ESP_OK) {
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ESP_LOGE(TAG, "Failed to load app image header @ 0x%x", partition->offset);
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return;
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}
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uint32_t drom_addr = 0;
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uint32_t drom_load_addr = 0;
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uint32_t drom_size = 0;
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uint32_t irom_addr = 0;
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uint32_t irom_load_addr = 0;
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uint32_t irom_size = 0;
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/* Reload the RTC memory segments whenever a non-deepsleep reset
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is occurring */
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bool load_rtc_memory = rtc_get_reset_reason(0) != DEEPSLEEP_RESET;
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ESP_LOGD(TAG, "bin_header: %u %u %u %u %08x", image_header.magic,
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image_header.segment_count,
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image_header.spi_mode,
|
||||
image_header.spi_size,
|
||||
(unsigned)image_header.entry_addr);
|
||||
|
||||
for (int segment = 0; segment < image_header.segment_count; segment++) {
|
||||
esp_image_segment_header_t segment_header;
|
||||
uint32_t data_offs;
|
||||
if(esp_image_load_segment_header(segment, partition->offset,
|
||||
&image_header, &segment_header,
|
||||
&data_offs) != ESP_OK) {
|
||||
ESP_LOGE(TAG, "failed to load segment header #%d", segment);
|
||||
return;
|
||||
}
|
||||
|
||||
const uint32_t address = segment_header.load_addr;
|
||||
bool load = true;
|
||||
bool map = false;
|
||||
if (address == 0x00000000) { // padding, ignore block
|
||||
load = false;
|
||||
}
|
||||
if (address == 0x00000004) {
|
||||
load = false; // md5 checksum block
|
||||
// TODO: actually check md5
|
||||
}
|
||||
|
||||
if (address >= DROM_LOW && address < DROM_HIGH) {
|
||||
ESP_LOGD(TAG, "found drom segment, map from %08x to %08x", data_offs,
|
||||
segment_header.load_addr);
|
||||
drom_addr = data_offs;
|
||||
drom_load_addr = segment_header.load_addr;
|
||||
drom_size = segment_header.data_len + sizeof(segment_header);
|
||||
load = false;
|
||||
map = true;
|
||||
}
|
||||
|
||||
if (address >= IROM_LOW && address < IROM_HIGH) {
|
||||
ESP_LOGD(TAG, "found irom segment, map from %08x to %08x", data_offs,
|
||||
segment_header.load_addr);
|
||||
irom_addr = data_offs;
|
||||
irom_load_addr = segment_header.load_addr;
|
||||
irom_size = segment_header.data_len + sizeof(segment_header);
|
||||
load = false;
|
||||
map = true;
|
||||
}
|
||||
|
||||
if (!load_rtc_memory && address >= RTC_IRAM_LOW && address < RTC_IRAM_HIGH) {
|
||||
ESP_LOGD(TAG, "Skipping RTC code segment at %08x\n", data_offs);
|
||||
load = false;
|
||||
}
|
||||
|
||||
if (!load_rtc_memory && address >= RTC_DATA_LOW && address < RTC_DATA_HIGH) {
|
||||
ESP_LOGD(TAG, "Skipping RTC data segment at %08x\n", data_offs);
|
||||
load = false;
|
||||
}
|
||||
|
||||
ESP_LOGI(TAG, "segment %d: paddr=0x%08x vaddr=0x%08x size=0x%05x (%6d) %s", segment, data_offs - sizeof(esp_image_segment_header_t),
|
||||
segment_header.load_addr, segment_header.data_len, segment_header.data_len, (load)?"load":(map)?"map":"");
|
||||
|
||||
if (load) {
|
||||
const void *data = bootloader_mmap(data_offs, segment_header.data_len);
|
||||
if(!data) {
|
||||
ESP_LOGE(TAG, "bootloader_mmap(0x%xc, 0x%x) failed",
|
||||
data_offs, segment_header.data_len);
|
||||
return;
|
||||
}
|
||||
memcpy((void *)segment_header.load_addr, data, segment_header.data_len);
|
||||
bootloader_munmap(data);
|
||||
}
|
||||
}
|
||||
|
||||
set_cache_and_start_app(drom_addr,
|
||||
drom_load_addr,
|
||||
drom_size,
|
||||
irom_addr,
|
||||
irom_load_addr,
|
||||
irom_size,
|
||||
image_header.entry_addr);
|
||||
}
|
||||
|
||||
void set_cache_and_start_app(
|
||||
uint32_t drom_addr,
|
||||
uint32_t drom_load_addr,
|
||||
uint32_t drom_size,
|
||||
uint32_t irom_addr,
|
||||
uint32_t irom_load_addr,
|
||||
uint32_t irom_size,
|
||||
uint32_t entry_addr)
|
||||
{
|
||||
ESP_LOGD(TAG, "configure drom and irom and start");
|
||||
Cache_Read_Disable( 0 );
|
||||
Cache_Flush( 0 );
|
||||
cache_sram_mmu_set( 0, 0, 0x3f800000, 0, 32, 128 );
|
||||
|
||||
uint32_t drom_page_count = (drom_size + 64*1024 - 1) / (64*1024); // round up to 64k
|
||||
ESP_LOGV(TAG, "d mmu set paddr=%08x vaddr=%08x size=%d n=%d", drom_addr & 0xffff0000, drom_load_addr & 0xffff0000, drom_size, drom_page_count );
|
||||
int rc = cache_flash_mmu_set( 0, 0, drom_load_addr & 0xffff0000, drom_addr & 0xffff0000, 64, drom_page_count );
|
||||
ESP_LOGV(TAG, "rc=%d", rc );
|
||||
rc = cache_flash_mmu_set( 1, 0, drom_load_addr & 0xffff0000, drom_addr & 0xffff0000, 64, drom_page_count );
|
||||
ESP_LOGV(TAG, "rc=%d", rc );
|
||||
uint32_t irom_page_count = (irom_size + 64*1024 - 1) / (64*1024); // round up to 64k
|
||||
ESP_LOGV(TAG, "i mmu set paddr=%08x vaddr=%08x size=%d n=%d", irom_addr & 0xffff0000, irom_load_addr & 0xffff0000, irom_size, irom_page_count );
|
||||
rc = cache_flash_mmu_set( 0, 0, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count );
|
||||
ESP_LOGV(TAG, "rc=%d", rc );
|
||||
rc = cache_flash_mmu_set( 1, 0, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count );
|
||||
ESP_LOGV(TAG, "rc=%d", rc );
|
||||
REG_CLR_BIT( DPORT_PRO_CACHE_CTRL1_REG, (DPORT_PRO_CACHE_MASK_IRAM0) | (DPORT_PRO_CACHE_MASK_IRAM1 & 0) | (DPORT_PRO_CACHE_MASK_IROM0 & 0) | DPORT_PRO_CACHE_MASK_DROM0 | DPORT_PRO_CACHE_MASK_DRAM1 );
|
||||
REG_CLR_BIT( DPORT_APP_CACHE_CTRL1_REG, (DPORT_APP_CACHE_MASK_IRAM0) | (DPORT_APP_CACHE_MASK_IRAM1 & 0) | (DPORT_APP_CACHE_MASK_IROM0 & 0) | DPORT_APP_CACHE_MASK_DROM0 | DPORT_APP_CACHE_MASK_DRAM1 );
|
||||
Cache_Read_Enable( 0 );
|
||||
|
||||
// Application will need to do Cache_Flush(1) and Cache_Read_Enable(1)
|
||||
|
||||
ESP_LOGD(TAG, "start: 0x%08x", entry_addr);
|
||||
typedef void (*entry_t)(void);
|
||||
entry_t entry = ((entry_t) entry_addr);
|
||||
|
||||
// TODO: we have used quite a bit of stack at this point.
|
||||
// use "movsp" instruction to reset stack back to where ROM stack starts.
|
||||
(*entry)();
|
||||
}
|
||||
|
||||
static void update_flash_config(const esp_image_header_t* pfhdr)
|
||||
{
|
||||
uint32_t size;
|
||||
switch(pfhdr->spi_size) {
|
||||
case ESP_IMAGE_FLASH_SIZE_1MB:
|
||||
size = 1;
|
||||
break;
|
||||
case ESP_IMAGE_FLASH_SIZE_2MB:
|
||||
size = 2;
|
||||
break;
|
||||
case ESP_IMAGE_FLASH_SIZE_4MB:
|
||||
size = 4;
|
||||
break;
|
||||
case ESP_IMAGE_FLASH_SIZE_8MB:
|
||||
size = 8;
|
||||
break;
|
||||
case ESP_IMAGE_FLASH_SIZE_16MB:
|
||||
size = 16;
|
||||
break;
|
||||
default:
|
||||
size = 2;
|
||||
}
|
||||
Cache_Read_Disable( 0 );
|
||||
// Set flash chip size
|
||||
SPIParamCfg(g_rom_flashchip.deviceId, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff);
|
||||
// TODO: set mode
|
||||
// TODO: set frequency
|
||||
Cache_Flush(0);
|
||||
Cache_Read_Enable( 0 );
|
||||
}
|
||||
|
||||
void print_flash_info(const esp_image_header_t* phdr)
|
||||
{
|
||||
#if (BOOT_LOG_LEVEL >= BOOT_LOG_LEVEL_NOTICE)
|
||||
|
||||
ESP_LOGD(TAG, "magic %02x", phdr->magic );
|
||||
ESP_LOGD(TAG, "segments %02x", phdr->segment_count );
|
||||
ESP_LOGD(TAG, "spi_mode %02x", phdr->spi_mode );
|
||||
ESP_LOGD(TAG, "spi_speed %02x", phdr->spi_speed );
|
||||
ESP_LOGD(TAG, "spi_size %02x", phdr->spi_size );
|
||||
|
||||
const char* str;
|
||||
switch ( phdr->spi_speed ) {
|
||||
case ESP_IMAGE_SPI_SPEED_40M:
|
||||
str = "40MHz";
|
||||
break;
|
||||
case ESP_IMAGE_SPI_SPEED_26M:
|
||||
str = "26.7MHz";
|
||||
break;
|
||||
case ESP_IMAGE_SPI_SPEED_20M:
|
||||
str = "20MHz";
|
||||
break;
|
||||
case ESP_IMAGE_SPI_SPEED_80M:
|
||||
str = "80MHz";
|
||||
break;
|
||||
default:
|
||||
str = "20MHz";
|
||||
break;
|
||||
}
|
||||
ESP_LOGI(TAG, "SPI Speed : %s", str );
|
||||
|
||||
switch ( phdr->spi_mode ) {
|
||||
case ESP_IMAGE_SPI_MODE_QIO:
|
||||
str = "QIO";
|
||||
break;
|
||||
case ESP_IMAGE_SPI_MODE_QOUT:
|
||||
str = "QOUT";
|
||||
break;
|
||||
case ESP_IMAGE_SPI_MODE_DIO:
|
||||
str = "DIO";
|
||||
break;
|
||||
case ESP_IMAGE_SPI_MODE_DOUT:
|
||||
str = "DOUT";
|
||||
break;
|
||||
case ESP_IMAGE_SPI_MODE_FAST_READ:
|
||||
str = "FAST READ";
|
||||
break;
|
||||
case ESP_IMAGE_SPI_MODE_SLOW_READ:
|
||||
str = "SLOW READ";
|
||||
break;
|
||||
default:
|
||||
str = "DIO";
|
||||
break;
|
||||
}
|
||||
ESP_LOGI(TAG, "SPI Mode : %s", str );
|
||||
|
||||
switch ( phdr->spi_size ) {
|
||||
case ESP_IMAGE_FLASH_SIZE_1MB:
|
||||
str = "1MB";
|
||||
break;
|
||||
case ESP_IMAGE_FLASH_SIZE_2MB:
|
||||
str = "2MB";
|
||||
break;
|
||||
case ESP_IMAGE_FLASH_SIZE_4MB:
|
||||
str = "4MB";
|
||||
break;
|
||||
case ESP_IMAGE_FLASH_SIZE_8MB:
|
||||
str = "8MB";
|
||||
break;
|
||||
case ESP_IMAGE_FLASH_SIZE_16MB:
|
||||
str = "16MB";
|
||||
break;
|
||||
default:
|
||||
str = "2MB";
|
||||
break;
|
||||
}
|
||||
ESP_LOGI(TAG, "SPI Flash Size : %s", str );
|
||||
#endif
|
||||
}
|
||||
|
|
@ -1,5 +0,0 @@
|
|||
#
|
||||
# "main" pseudo-component makefile.
|
||||
#
|
||||
# (Uses default behaviour of compiling all source files in directory, adding 'include' to include path.)
|
||||
|
||||
|
|
@ -1,143 +0,0 @@
|
|||
/* Timer group-hardware timer example
|
||||
|
||||
This example code is in the Public Domain (or CC0 licensed, at your option.)
|
||||
|
||||
Unless required by applicable law or agreed to in writing, this
|
||||
software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
|
||||
CONDITIONS OF ANY KIND, either express or implied.
|
||||
*/
|
||||
#include "esp_types.h"
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "freertos/task.h"
|
||||
#include "freertos/queue.h"
|
||||
#include "freertos/semphr.h"
|
||||
#include <string.h>
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include "psram.h"
|
||||
|
||||
#define TEST_DATA_LEN 1024
|
||||
#define PSRAM_START_ADR (0x3F800000) //0x3F800000 is psram start address
|
||||
|
||||
#define mutex_t xSemaphoreHandle
|
||||
mutex_t psram_mem_mutex = NULL;
|
||||
|
||||
uint8_t inRam0[TEST_DATA_LEN] = {0};
|
||||
uint8_t inRam1[TEST_DATA_LEN] = {0};
|
||||
|
||||
int mutex_init(mutex_t *pxMutex);
|
||||
void mutex_lock(mutex_t *pxMutex);
|
||||
void mutex_unlock(mutex_t *pxMutex);
|
||||
|
||||
/** Create a new mutex
|
||||
* @param mutex pointer to the mutex to create
|
||||
* @return 0: successed;1:failed;
|
||||
*/
|
||||
int mutex_init(mutex_t *pxMutex)
|
||||
{
|
||||
int xReturn = -1;
|
||||
*pxMutex = xSemaphoreCreateMutex();
|
||||
if (*pxMutex != NULL) {
|
||||
xReturn = 0;
|
||||
}
|
||||
return xReturn;
|
||||
}
|
||||
|
||||
/** Lock a mutex
|
||||
* @param mutex the mutex to lock
|
||||
*/
|
||||
void mutex_lock(mutex_t *pxMutex)
|
||||
{
|
||||
while (xSemaphoreTake(*pxMutex, portMAX_DELAY) != pdPASS);
|
||||
}
|
||||
|
||||
/** Unlock a mutex
|
||||
* @param mutex the mutex to unlock
|
||||
*/
|
||||
void mutex_unlock(mutex_t *pxMutex)
|
||||
{
|
||||
xSemaphoreGive(*pxMutex);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Memcpy with a cache, atomic protected, speaking, reading and writing
|
||||
*/
|
||||
void psram_cache_memcpy(uint8_t *dst, uint8_t *src, uint16_t len)
|
||||
{
|
||||
if(psram_mem_mutex == NULL)
|
||||
{
|
||||
mutex_init(&psram_mem_mutex);
|
||||
}
|
||||
mutex_lock(&psram_mem_mutex);
|
||||
memcpy(dst, src, len);
|
||||
mutex_unlock(&psram_mem_mutex);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Memset with a cache, atomic protected, speaking, reading and writing
|
||||
*/
|
||||
void psram_cache_memset(uint8_t *addr, uint8_t c, uint32_t len)
|
||||
{
|
||||
if(psram_mem_mutex == NULL)
|
||||
{
|
||||
mutex_init(&psram_mem_mutex);
|
||||
}
|
||||
mutex_lock(&psram_mem_mutex);
|
||||
memset(addr, c, len);
|
||||
mutex_unlock(&psram_mem_mutex);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Print multiple bytes
|
||||
*/
|
||||
void printfByteS(uint8_t *indata, uint16_t len)
|
||||
{
|
||||
int i = 0;
|
||||
for(; i < len ; i++)
|
||||
{
|
||||
printf("%02X", indata[i]);
|
||||
}
|
||||
printf("\n");
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief psram test task
|
||||
*/
|
||||
void psram_test_task()
|
||||
{
|
||||
uint8_t *psram_buf_ptr = (uint8_t*) PSRAM_START_ADR;
|
||||
printf("*****************psram demo start*****************\n");
|
||||
psram_enable(PSRAM_CACHE_F40M_S40M);
|
||||
|
||||
psram_cache_memset(psram_buf_ptr, 0x00, TEST_DATA_LEN); //clear zero
|
||||
|
||||
memset(inRam0, 0x5A, TEST_DATA_LEN);
|
||||
memset(inRam1, 0xA5, TEST_DATA_LEN);
|
||||
|
||||
printf("1.write psram data\n");
|
||||
psram_cache_memcpy(psram_buf_ptr, inRam0, TEST_DATA_LEN);
|
||||
|
||||
printf("2.read psram data (expect 0x5A)\n");
|
||||
printfByteS(psram_buf_ptr, TEST_DATA_LEN);
|
||||
|
||||
printf("3.write psram data\n");
|
||||
psram_cache_memcpy(psram_buf_ptr, inRam1, TEST_DATA_LEN);
|
||||
|
||||
printf("4.read psram data (expect 0xA5)\n");
|
||||
printfByteS(psram_buf_ptr, TEST_DATA_LEN);
|
||||
printf("*****************psram demo end******************\n");
|
||||
|
||||
while(1)
|
||||
{
|
||||
vTaskDelay(100);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief In this test
|
||||
*/
|
||||
void app_main()
|
||||
{
|
||||
xTaskCreate(psram_test_task, "psram_test_task", 1024 * 5, NULL, 5, NULL);
|
||||
}
|
||||
|
||||
Loading…
Reference in a new issue