soc/rtc: fix switching between 80/160 and 240MHz
Previous code contained a check for PLL frequency to be 240MHz, while in fact 240MHz was a CPU frequency; corresponding PLL frequency is 480MHz. Fixed the comparison and replaced integer MHz values with an enum.
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@ -98,9 +98,17 @@ static const char* TAG = "rtc_clk";
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#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10
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#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10
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#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00
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#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00
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/* PLL currently enabled, if any */
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typedef enum {
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RTC_PLL_NONE,
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RTC_PLL_320M,
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RTC_PLL_480M
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} rtc_pll_t;
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static rtc_pll_t s_cur_pll = RTC_PLL_NONE;
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/* Current CPU frequency; saved in a variable for faster freq. switching */
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static rtc_cpu_freq_t s_cur_freq = RTC_CPU_FREQ_XTAL;
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static rtc_cpu_freq_t s_cur_freq = RTC_CPU_FREQ_XTAL;
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static int s_pll_freq = 0;
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static void rtc_clk_32k_enable_internal(int dac, int dres, int dbias)
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static void rtc_clk_32k_enable_internal(int dac, int dres, int dbias)
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{
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{
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@ -392,8 +400,9 @@ static void rtc_clk_cpu_freq_to_xtal()
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static void rtc_clk_cpu_freq_to_pll(rtc_cpu_freq_t cpu_freq)
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static void rtc_clk_cpu_freq_to_pll(rtc_cpu_freq_t cpu_freq)
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{
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{
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int freq = 0;
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int freq = 0;
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if ((cpu_freq == RTC_CPU_FREQ_240M && s_pll_freq == 320) ||
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if (s_cur_pll == RTC_PLL_NONE ||
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(cpu_freq != RTC_CPU_FREQ_240M && s_pll_freq == 240)) {
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(cpu_freq == RTC_CPU_FREQ_240M && s_cur_pll == RTC_PLL_320M) ||
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(cpu_freq != RTC_CPU_FREQ_240M && s_cur_pll == RTC_PLL_480M)) {
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/* need to switch PLLs, fall back to full implementation */
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/* need to switch PLLs, fall back to full implementation */
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rtc_clk_cpu_freq_set(cpu_freq);
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rtc_clk_cpu_freq_set(cpu_freq);
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return;
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return;
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@ -451,7 +460,7 @@ void rtc_clk_cpu_freq_set(rtc_cpu_freq_t cpu_freq)
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SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
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SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
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RTC_CNTL_BB_I2C_FORCE_PD | RTC_CNTL_BBPLL_FORCE_PD |
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RTC_CNTL_BB_I2C_FORCE_PD | RTC_CNTL_BBPLL_FORCE_PD |
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RTC_CNTL_BBPLL_I2C_FORCE_PD);
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RTC_CNTL_BBPLL_I2C_FORCE_PD);
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s_pll_freq = 0;
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s_cur_pll = RTC_PLL_NONE;
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rtc_clk_apb_freq_update(xtal_freq * MHZ);
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rtc_clk_apb_freq_update(xtal_freq * MHZ);
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/* is APLL under force power down? */
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/* is APLL under force power down? */
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@ -479,15 +488,15 @@ void rtc_clk_cpu_freq_set(rtc_cpu_freq_t cpu_freq)
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if (cpu_freq == RTC_CPU_FREQ_80M) {
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if (cpu_freq == RTC_CPU_FREQ_80M) {
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DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 0);
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DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 0);
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ets_update_cpu_frequency(80);
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ets_update_cpu_frequency(80);
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s_pll_freq = 320;
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s_cur_pll = RTC_PLL_320M;
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} else if (cpu_freq == RTC_CPU_FREQ_160M) {
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} else if (cpu_freq == RTC_CPU_FREQ_160M) {
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DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 1);
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DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 1);
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ets_update_cpu_frequency(160);
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ets_update_cpu_frequency(160);
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s_pll_freq = 320;
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s_cur_pll = RTC_PLL_320M;
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} else if (cpu_freq == RTC_CPU_FREQ_240M) {
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} else if (cpu_freq == RTC_CPU_FREQ_240M) {
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DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 2);
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DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 2);
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ets_update_cpu_frequency(240);
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ets_update_cpu_frequency(240);
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s_pll_freq = 480;
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s_cur_pll = RTC_PLL_480M;
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}
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}
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REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_PLL);
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REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_PLL);
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rtc_clk_wait_for_slow_cycle();
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rtc_clk_wait_for_slow_cycle();
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