Merge branch 'feature/esp32s2beta_dport' into 'feature/esp32s2beta'
dport_access: simplify for esp32s2beta See merge request espressif/esp-idf!5417
This commit is contained in:
commit
413a98b151
9 changed files with 34 additions and 483 deletions
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@ -66,6 +66,5 @@ void esp_cache_err_int_init()
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int IRAM_ATTR esp_cache_err_get_cpuid()
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int IRAM_ATTR esp_cache_err_get_cpuid()
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{
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{
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esp_dport_access_int_pause();
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return PRO_CPU_NUM;
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return PRO_CPU_NUM;
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}
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}
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@ -395,9 +395,6 @@ void start_cpu0_default(void)
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#endif
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#endif
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//esp_cache_err_int_init();
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//esp_cache_err_int_init();
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esp_crosscore_int_init();
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esp_crosscore_int_init();
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#ifndef CONFIG_FREERTOS_UNICORE
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esp_dport_access_int_init();
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#endif
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spi_flash_init();
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spi_flash_init();
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/* init default OS-aware flash access critical section */
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/* init default OS-aware flash access critical section */
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spi_flash_guard_set(&g_flash_guard_default_ops);
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spi_flash_guard_set(&g_flash_guard_default_ops);
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@ -449,7 +446,6 @@ void start_cpu1_default(void)
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//has started, but it isn't active *on this CPU* yet.
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//has started, but it isn't active *on this CPU* yet.
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esp_cache_err_int_init();
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esp_cache_err_int_init();
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esp_crosscore_int_init();
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esp_crosscore_int_init();
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esp_dport_access_int_init();
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ESP_EARLY_LOGI(TAG, "Starting scheduler on APP CPU.");
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ESP_EARLY_LOGI(TAG, "Starting scheduler on APP CPU.");
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xPortStartScheduler();
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xPortStartScheduler();
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@ -12,302 +12,14 @@
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// See the License for the specific language governing permissions and
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// limitations under the License.
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/*
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* DPORT access is used for do protection when dual core access DPORT internal register and APB register via DPORT simultaneously
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* This function will be initialize after FreeRTOS startup.
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* When cpu0 want to access DPORT register, it should notify cpu1 enter in high-priority interrupt for be mute. When cpu1 already in high-priority interrupt,
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* cpu0 can access DPORT register. Currently, cpu1 will wait for cpu0 finish access and exit high-priority interrupt.
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*/
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#include <stdint.h>
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#include <stdint.h>
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#include <string.h>
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#include <string.h>
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#include "soc/dport_access.h"
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#include <sdkconfig.h>
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// Read a sequence of DPORT registers to the buffer.
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#include "esp_attr.h"
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void esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address, uint32_t num_words)
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#include "esp_err.h"
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#include "esp_intr_alloc.h"
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#include "esp32s2beta/rom/ets_sys.h"
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#include "esp32s2beta/rom/uart.h"
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#include "soc/cpu.h"
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#include "soc/dport_reg.h"
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#include "soc/spi_mem_reg.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/semphr.h"
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#include "freertos/queue.h"
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#include "freertos/portmacro.h"
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#include "xtensa/core-macros.h"
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// TODO: dport_access: simplify for esp32s2beta - IDF-755
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#ifndef CONFIG_FREERTOS_UNICORE
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static portMUX_TYPE g_dport_mux = portMUX_INITIALIZER_UNLOCKED;
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#define DPORT_CORE_STATE_IDLE 0
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#define DPORT_CORE_STATE_RUNNING 1
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static uint32_t volatile dport_core_state[portNUM_PROCESSORS]; //cpu is already run
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/* these global variables are accessed from interrupt vector, hence not declared as static */
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uint32_t volatile dport_access_start[portNUM_PROCESSORS]; //dport register could be accessed
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uint32_t volatile dport_access_end[portNUM_PROCESSORS]; //dport register is accessed over
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static uint32_t volatile dport_access_ref[portNUM_PROCESSORS]; //dport access reference
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#ifdef DPORT_ACCESS_BENCHMARK
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#define DPORT_ACCESS_BENCHMARK_STORE_NUM
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static uint32_t ccount_start[portNUM_PROCESSORS];
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static uint32_t ccount_end[portNUM_PROCESSORS];
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static uint32_t ccount_margin[portNUM_PROCESSORS][DPORT_ACCESS_BENCHMARK_STORE_NUM];
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static uint32_t ccount_margin_cnt;
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#endif
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static BaseType_t oldInterruptLevel[2];
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#endif // CONFIG_FREERTOS_UNICORE
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/* stall other cpu that this cpu is pending to access dport register start */
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void IRAM_ATTR esp_dport_access_stall_other_cpu_start(void)
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{
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{
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#ifndef CONFIG_FREERTOS_UNICORE
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if (dport_core_state[0] == DPORT_CORE_STATE_IDLE
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|| dport_core_state[1] == DPORT_CORE_STATE_IDLE) {
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return;
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}
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BaseType_t intLvl = portENTER_CRITICAL_NESTED();
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int cpu_id = xPortGetCoreID();
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#ifdef DPORT_ACCESS_BENCHMARK
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ccount_start[cpu_id] = XTHAL_GET_CCOUNT();
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#endif
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if (dport_access_ref[cpu_id] == 0) {
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portENTER_CRITICAL_ISR(&g_dport_mux);
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oldInterruptLevel[cpu_id]=intLvl;
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dport_access_start[cpu_id] = 0;
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dport_access_end[cpu_id] = 0;
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if (cpu_id == 0) {
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_DPORT_REG_WRITE(DPORT_CPU_INTR_FROM_CPU_3_REG, DPORT_CPU_INTR_FROM_CPU_3); //interrupt on cpu1
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} else {
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_DPORT_REG_WRITE(DPORT_CPU_INTR_FROM_CPU_2_REG, DPORT_CPU_INTR_FROM_CPU_2); //interrupt on cpu0
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}
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while (!dport_access_start[cpu_id]) {};
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REG_READ(SPI_DATE_REG(3)); //just read a APB register sure that the APB-bus is idle
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}
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dport_access_ref[cpu_id]++;
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if (dport_access_ref[cpu_id] > 1) {
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/* Interrupts are already disabled by the parent, we're nested here. */
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portEXIT_CRITICAL_NESTED(intLvl);
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}
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#endif /* CONFIG_FREERTOS_UNICORE */
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}
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/* stall other cpu that this cpu is pending to access dport register end */
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void IRAM_ATTR esp_dport_access_stall_other_cpu_end(void)
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{
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#ifndef CONFIG_FREERTOS_UNICORE
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int cpu_id = xPortGetCoreID();
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if (dport_core_state[0] == DPORT_CORE_STATE_IDLE
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|| dport_core_state[1] == DPORT_CORE_STATE_IDLE) {
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return;
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}
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if (dport_access_ref[cpu_id] == 0) {
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assert(0);
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}
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dport_access_ref[cpu_id]--;
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if (dport_access_ref[cpu_id] == 0) {
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dport_access_end[cpu_id] = 1;
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portEXIT_CRITICAL_ISR(&g_dport_mux);
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portEXIT_CRITICAL_NESTED(oldInterruptLevel[cpu_id]);
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}
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#ifdef DPORT_ACCESS_BENCHMARK
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ccount_end[cpu_id] = XTHAL_GET_CCOUNT();
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ccount_margin[cpu_id][ccount_margin_cnt] = ccount_end[cpu_id] - ccount_start[cpu_id];
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ccount_margin_cnt = (ccount_margin_cnt + 1)&(DPORT_ACCESS_BENCHMARK_STORE_NUM - 1);
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#endif
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#endif /* CONFIG_FREERTOS_UNICORE */
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}
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void IRAM_ATTR esp_dport_access_stall_other_cpu_start_wrap(void)
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{
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DPORT_STALL_OTHER_CPU_START();
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}
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void IRAM_ATTR esp_dport_access_stall_other_cpu_end_wrap(void)
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{
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DPORT_STALL_OTHER_CPU_END();
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}
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#ifndef CONFIG_FREERTOS_UNICORE
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static void dport_access_init_core(void *arg)
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{
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int core_id = 0;
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uint32_t intr_source = ETS_FROM_CPU_INTR2_SOURCE;
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core_id = xPortGetCoreID();
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if (core_id == 1) {
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intr_source = ETS_FROM_CPU_INTR3_SOURCE;
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}
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ESP_INTR_DISABLE(ETS_DPORT_INUM);
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intr_matrix_set(core_id, intr_source, ETS_DPORT_INUM);
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ESP_INTR_ENABLE(ETS_DPORT_INUM);
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dport_access_ref[core_id] = 0;
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dport_access_start[core_id] = 0;
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dport_access_end[core_id] = 0;
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dport_core_state[core_id] = DPORT_CORE_STATE_RUNNING;
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vTaskDelete(NULL);
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}
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#endif
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/* Defer initialisation until after scheduler is running */
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void esp_dport_access_int_init(void)
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{
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#ifndef CONFIG_FREERTOS_UNICORE
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portBASE_TYPE res = xTaskCreatePinnedToCore(&dport_access_init_core, "dport", configMINIMAL_STACK_SIZE, NULL, 5, NULL, xPortGetCoreID());
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assert(res == pdTRUE);
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#endif
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}
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void IRAM_ATTR esp_dport_access_int_pause(void)
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{
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#ifndef CONFIG_FREERTOS_UNICORE
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portENTER_CRITICAL_ISR(&g_dport_mux);
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dport_core_state[0] = DPORT_CORE_STATE_IDLE;
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dport_core_state[1] = DPORT_CORE_STATE_IDLE;
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portEXIT_CRITICAL_ISR(&g_dport_mux);
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#endif
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}
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//Used in panic code: the enter_critical stuff may be messed up so we just stop everything without checking the mux.
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void IRAM_ATTR esp_dport_access_int_abort(void)
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{
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#ifndef CONFIG_FREERTOS_UNICORE
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dport_core_state[0] = DPORT_CORE_STATE_IDLE;
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dport_core_state[1] = DPORT_CORE_STATE_IDLE;
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#endif
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}
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void IRAM_ATTR esp_dport_access_int_resume(void)
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{
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#ifndef CONFIG_FREERTOS_UNICORE
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portENTER_CRITICAL_ISR(&g_dport_mux);
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dport_core_state[0] = DPORT_CORE_STATE_RUNNING;
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dport_core_state[1] = DPORT_CORE_STATE_RUNNING;
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portEXIT_CRITICAL_ISR(&g_dport_mux);
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#endif
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}
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/**
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* @brief Read a sequence of DPORT registers to the buffer, SMP-safe version.
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*
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* This implementation uses a method of the pre-reading of the APB register
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* before reading the register of the DPORT, without stall other CPU.
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* There is disable/enable interrupt.
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*
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* @param[out] buff_out Contains the read data.
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* @param[in] address Initial address for reading registers.
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* @param[in] num_words The number of words.
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*/
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void IRAM_ATTR esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address, uint32_t num_words)
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{
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DPORT_INTERRUPT_DISABLE();
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for (uint32_t i = 0; i < num_words; ++i) {
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for (uint32_t i = 0; i < num_words; ++i) {
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buff_out[i] = DPORT_SEQUENCE_REG_READ(address + i * 4);
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buff_out[i] = DPORT_SEQUENCE_REG_READ(address + i * 4);
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}
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}
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DPORT_INTERRUPT_RESTORE();
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}
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/**
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* @brief Read value from register, SMP-safe version.
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*
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* This method uses the pre-reading of the APB register before reading the register of the DPORT.
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* This implementation is useful for reading DORT registers for single reading without stall other CPU.
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* There is disable/enable interrupt.
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*
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* @param reg Register address
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* @return Value
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*/
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uint32_t IRAM_ATTR esp_dport_access_reg_read(uint32_t reg)
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{
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#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !defined(ESP_PLATFORM)
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return _DPORT_REG_READ(reg);
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#else
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uint32_t apb;
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unsigned int intLvl;
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__asm__ __volatile__ (\
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"movi %[APB], "XTSTR(0x3f400078)"\n"\
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"rsil %[LVL], "XTSTR(3)"\n"\
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"l32i %[APB], %[APB], 0\n"\
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"l32i %[REG], %[REG], 0\n"\
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"wsr %[LVL], "XTSTR(PS)"\n"\
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"rsync\n"\
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: [APB]"=a"(apb), [REG]"+a"(reg), [LVL]"=a"(intLvl)\
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: \
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: "memory" \
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);
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return reg;
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#endif
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}
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/**
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* @brief Read value from register, NOT SMP-safe version.
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*
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* This method uses the pre-reading of the APB register before reading the register of the DPORT.
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* There is not disable/enable interrupt.
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* The difference from DPORT_REG_READ() is that the user himself must disable interrupts while DPORT reading.
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* This implementation is useful for reading DORT registers in loop without stall other CPU. Note the usage example.
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* The recommended way to read registers sequentially without stall other CPU
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* is to use the method esp_dport_read_buffer(buff_out, address, num_words). It allows you to read registers in the buffer.
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*
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* \code{c}
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* // This example shows how to use it.
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* { // Use curly brackets to limit the visibility of variables in macros DPORT_INTERRUPT_DISABLE/RESTORE.
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* DPORT_INTERRUPT_DISABLE(); // Disable interrupt only on current CPU.
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* for (i = 0; i < max; ++i) {
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* array[i] = esp_dport_access_sequence_reg_read(Address + i * 4); // reading DPORT registers
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* }
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* DPORT_INTERRUPT_RESTORE(); // restore the previous interrupt level
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* }
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* \endcode
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*
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* @param reg Register address
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* @return Value
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*/
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uint32_t IRAM_ATTR esp_dport_access_sequence_reg_read(uint32_t reg)
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{
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#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !defined(ESP_PLATFORM)
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return _DPORT_REG_READ(reg);
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#else
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uint32_t apb;
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__asm__ __volatile__ (\
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"movi %[APB], "XTSTR(0x3f400078)"\n"\
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"l32i %[APB], %[APB], 0\n"\
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"l32i %[REG], %[REG], 0\n"\
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: [APB]"=a"(apb), [REG]"+a"(reg)\
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: \
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: "memory" \
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);
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return reg;
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#endif
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}
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}
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@ -25,32 +25,17 @@
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/*
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/*
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Interrupt , a high-priority interrupt, is used for several things:
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Interrupt , a high-priority interrupt, is used for several things:
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- Dport access mediation
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- Cache error panic handler
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- Cache error panic handler
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- Interrupt watchdog panic handler
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- Interrupt watchdog panic handler
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*/
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*/
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||||||
|
|
||||||
#define L4_INTR_STACK_SIZE 8
|
|
||||||
#define L4_INTR_A2_OFFSET 0
|
|
||||||
#define L4_INTR_A3_OFFSET 4
|
|
||||||
.data
|
|
||||||
_l4_intr_stack:
|
|
||||||
.space L4_INTR_STACK_SIZE
|
|
||||||
|
|
||||||
.section .iram1,"ax"
|
.section .iram1,"ax"
|
||||||
.global xt_highint4
|
.global xt_highint4
|
||||||
.type xt_highint4,@function
|
.type xt_highint4,@function
|
||||||
.align 4
|
.align 4
|
||||||
xt_highint4:
|
xt_highint4:
|
||||||
|
|
||||||
#ifndef CONFIG_FREERTOS_UNICORE
|
|
||||||
/* See if we're here for the dport access interrupt */
|
|
||||||
rsr a0, INTERRUPT
|
|
||||||
extui a0, a0, ETS_DPORT_INUM, 1
|
|
||||||
bnez a0, .handle_dport_access_int
|
|
||||||
#endif // CONFIG_FREERTOS_UNICORE
|
|
||||||
|
|
||||||
/* Allocate exception frame and save minimal context. */
|
/* Allocate exception frame and save minimal context. */
|
||||||
mov a0, sp
|
mov a0, sp
|
||||||
addi sp, sp, -XT_STK_FRMSZ
|
addi sp, sp, -XT_STK_FRMSZ
|
||||||
|
@ -127,77 +112,9 @@ xt_highint4:
|
||||||
rsr a0, EXCSAVE_4 /* restore a0 */
|
rsr a0, EXCSAVE_4 /* restore a0 */
|
||||||
rfi 4
|
rfi 4
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
#ifndef CONFIG_FREERTOS_UNICORE
|
|
||||||
|
|
||||||
.align 4
|
|
||||||
.handle_dport_access_int:
|
|
||||||
/* This section is for dport access register protection */
|
|
||||||
/* Allocate exception frame and save minimal context. */
|
|
||||||
/* Because the interrupt cause code has protection that only
|
|
||||||
allows one cpu to enter in the dport section of the L4
|
|
||||||
interrupt at one time, there's no need to have two
|
|
||||||
_l4_intr_stack for each cpu */
|
|
||||||
|
|
||||||
/* This int is edge-triggered and needs clearing. */
|
|
||||||
movi a0, (1<<ETS_DPORT_INUM)
|
|
||||||
wsr a0, INTCLEAR
|
|
||||||
|
|
||||||
/* Save A2, A3 so we can use those registers */
|
|
||||||
movi a0, _l4_intr_stack
|
|
||||||
s32i a2, a0, L4_INTR_A2_OFFSET
|
|
||||||
s32i a3, a0, L4_INTR_A3_OFFSET
|
|
||||||
|
|
||||||
/* handle dport interrupt */
|
|
||||||
/* get CORE_ID */
|
|
||||||
getcoreid a0
|
|
||||||
beqz a0, 2f
|
|
||||||
|
|
||||||
/* current cpu is 1 */
|
|
||||||
movi a0, DPORT_CPU_INTR_FROM_CPU_3_REG
|
|
||||||
movi a2, 0
|
|
||||||
s32i a2, a0, 0 /* clear intr */
|
|
||||||
movi a0, 0 /* other cpu id */
|
|
||||||
j 3f
|
|
||||||
2:
|
|
||||||
/* current cpu is 0 */
|
|
||||||
movi a0, DPORT_CPU_INTR_FROM_CPU_2_REG
|
|
||||||
movi a2, 0
|
|
||||||
s32i a2, a0, 0 /* clear intr */
|
|
||||||
movi a0, 1 /* other cpu id */
|
|
||||||
3:
|
|
||||||
/* set and wait flag */
|
|
||||||
movi a2, dport_access_start
|
|
||||||
addx4 a2, a0, a2
|
|
||||||
movi a3, 1
|
|
||||||
s32i a3, a2, 0
|
|
||||||
memw
|
|
||||||
movi a2, dport_access_end
|
|
||||||
addx4 a2, a0, a2
|
|
||||||
.check_dport_access_end:
|
|
||||||
l32i a3, a2, 0
|
|
||||||
beqz a3, .check_dport_access_end
|
|
||||||
|
|
||||||
/* Done. Restore registers and return. */
|
|
||||||
movi a0, _l4_intr_stack
|
|
||||||
l32i a2, a0, L4_INTR_A2_OFFSET
|
|
||||||
l32i a3, a0, L4_INTR_A3_OFFSET
|
|
||||||
rsync /* ensure register restored */
|
|
||||||
|
|
||||||
rsr a0, EXCSAVE_4 /* restore a0 */
|
|
||||||
rfi 4
|
|
||||||
|
|
||||||
#endif // CONFIG_FREERTOS_UNICORE
|
|
||||||
|
|
||||||
/* The linker has no reason to link in this file; all symbols it exports are already defined
|
/* The linker has no reason to link in this file; all symbols it exports are already defined
|
||||||
(weakly!) in the default int handler. Define a symbol here so we can use it to have the
|
(weakly!) in the default int handler. Define a symbol here so we can use it to have the
|
||||||
linker inspect this anyway. */
|
linker inspect this anyway. */
|
||||||
|
|
||||||
.global ld_include_panic_highint_hdl
|
.global ld_include_panic_highint_hdl
|
||||||
ld_include_panic_highint_hdl:
|
ld_include_panic_highint_hdl:
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
|
@ -53,10 +53,6 @@
|
||||||
#include "esp32s2beta/clk.h"
|
#include "esp32s2beta/clk.h"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
||||||
extern void esp_dport_access_stall_other_cpu_start_wrap(void);
|
|
||||||
extern void esp_dport_access_stall_other_cpu_end_wrap(void);
|
|
||||||
|
|
||||||
#define TAG "esp_adapter"
|
#define TAG "esp_adapter"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -505,6 +501,11 @@ void IRAM_ATTR coex_bb_reset_unlock_wrapper(uint32_t restore)
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static void IRAM_ATTR esp_empty_wrapper(void)
|
||||||
|
{
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
wifi_osi_funcs_t g_wifi_osi_funcs = {
|
wifi_osi_funcs_t g_wifi_osi_funcs = {
|
||||||
._version = ESP_WIFI_OS_ADAPTER_VERSION,
|
._version = ESP_WIFI_OS_ADAPTER_VERSION,
|
||||||
._set_isr = set_isr_wrapper,
|
._set_isr = set_isr_wrapper,
|
||||||
|
@ -549,8 +550,8 @@ wifi_osi_funcs_t g_wifi_osi_funcs = {
|
||||||
._free = free,
|
._free = free,
|
||||||
._get_free_heap_size = esp_get_free_heap_size,
|
._get_free_heap_size = esp_get_free_heap_size,
|
||||||
._rand = esp_random,
|
._rand = esp_random,
|
||||||
._dport_access_stall_other_cpu_start_wrap = esp_dport_access_stall_other_cpu_start_wrap,
|
._dport_access_stall_other_cpu_start_wrap = esp_empty_wrapper,
|
||||||
._dport_access_stall_other_cpu_end_wrap = esp_dport_access_stall_other_cpu_end_wrap,
|
._dport_access_stall_other_cpu_end_wrap = esp_empty_wrapper,
|
||||||
._phy_rf_deinit = esp_phy_rf_deinit,
|
._phy_rf_deinit = esp_phy_rf_deinit,
|
||||||
._phy_load_cal_and_init = esp_phy_load_cal_and_init,
|
._phy_load_cal_and_init = esp_phy_load_cal_and_init,
|
||||||
._read_mac = esp_read_mac,
|
._read_mac = esp_read_mac,
|
||||||
|
|
|
@ -12,8 +12,6 @@
|
||||||
// See the License for the specific language governing permissions and
|
// See the License for the specific language governing permissions and
|
||||||
// limitations under the License.
|
// limitations under the License.
|
||||||
|
|
||||||
#include <sdkconfig.h>
|
|
||||||
|
|
||||||
#ifndef _ESP_DPORT_ACCESS_H_
|
#ifndef _ESP_DPORT_ACCESS_H_
|
||||||
#define _ESP_DPORT_ACCESS_H_
|
#define _ESP_DPORT_ACCESS_H_
|
||||||
|
|
||||||
|
@ -21,29 +19,19 @@
|
||||||
extern "C" {
|
extern "C" {
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
void esp_dport_access_stall_other_cpu_start(void);
|
/**
|
||||||
void esp_dport_access_stall_other_cpu_end(void);
|
* @brief Read a sequence of DPORT registers to the buffer.
|
||||||
void esp_dport_access_int_init(void);
|
*
|
||||||
void esp_dport_access_int_pause(void);
|
* @param[out] buff_out Contains the read data.
|
||||||
void esp_dport_access_int_resume(void);
|
* @param[in] address Initial address for reading registers.
|
||||||
|
* @param[in] num_words The number of words.
|
||||||
|
*/
|
||||||
void esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address, uint32_t num_words);
|
void esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address, uint32_t num_words);
|
||||||
uint32_t esp_dport_access_reg_read(uint32_t reg);
|
|
||||||
uint32_t esp_dport_access_sequence_reg_read(uint32_t reg);
|
|
||||||
//This routine does not stop the dport routines in any way that is recoverable. Please
|
|
||||||
//only call in case of panic().
|
|
||||||
void esp_dport_access_int_abort(void);
|
|
||||||
|
|
||||||
#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !defined(ESP_PLATFORM) || !defined(CONFIG_CHIP_IS_ESP32)
|
|
||||||
#define DPORT_STALL_OTHER_CPU_START()
|
#define DPORT_STALL_OTHER_CPU_START()
|
||||||
#define DPORT_STALL_OTHER_CPU_END()
|
#define DPORT_STALL_OTHER_CPU_END()
|
||||||
#define DPORT_INTERRUPT_DISABLE()
|
#define DPORT_INTERRUPT_DISABLE()
|
||||||
#define DPORT_INTERRUPT_RESTORE()
|
#define DPORT_INTERRUPT_RESTORE()
|
||||||
#else
|
|
||||||
#define DPORT_STALL_OTHER_CPU_START() esp_dport_access_stall_other_cpu_start()
|
|
||||||
#define DPORT_STALL_OTHER_CPU_END() esp_dport_access_stall_other_cpu_end()
|
|
||||||
#define DPORT_INTERRUPT_DISABLE() unsigned int intLvl = XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL)
|
|
||||||
#define DPORT_INTERRUPT_RESTORE() XTOS_RESTORE_JUST_INTLEVEL(intLvl)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
|
|
|
@ -236,7 +236,6 @@ void panicHandler(XtExcFrame *frame)
|
||||||
#endif //!CONFIG_FREERTOS_UNICORE
|
#endif //!CONFIG_FREERTOS_UNICORE
|
||||||
|
|
||||||
haltOtherCore();
|
haltOtherCore();
|
||||||
esp_dport_access_int_abort();
|
|
||||||
panicPutStr("Guru Meditation Error: Core ");
|
panicPutStr("Guru Meditation Error: Core ");
|
||||||
panicPutDec(core_id);
|
panicPutDec(core_id);
|
||||||
panicPutStr(" panic'ed (");
|
panicPutStr(" panic'ed (");
|
||||||
|
@ -306,7 +305,6 @@ void panicHandler(XtExcFrame *frame)
|
||||||
void xt_unhandled_exception(XtExcFrame *frame)
|
void xt_unhandled_exception(XtExcFrame *frame)
|
||||||
{
|
{
|
||||||
haltOtherCore();
|
haltOtherCore();
|
||||||
esp_dport_access_int_abort();
|
|
||||||
if (!abort_called) {
|
if (!abort_called) {
|
||||||
panicPutStr("Guru Meditation Error: Core ");
|
panicPutStr("Guru Meditation Error: Core ");
|
||||||
panicPutDec(xPortGetCoreID());
|
panicPutDec(xPortGetCoreID());
|
||||||
|
|
|
@ -274,9 +274,6 @@ void IRAM_ATTR esp_restart_noos()
|
||||||
esp_cpu_stall(other_core_id);
|
esp_cpu_stall(other_core_id);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
// Other core is now stalled, can access DPORT registers directly
|
|
||||||
esp_dport_access_int_abort();
|
|
||||||
|
|
||||||
// Disable TG0/TG1 watchdogs
|
// Disable TG0/TG1 watchdogs
|
||||||
TIMERG0.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
|
TIMERG0.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
|
||||||
TIMERG0.wdt_config0.en = 0;
|
TIMERG0.wdt_config0.en = 0;
|
||||||
|
|
|
@ -95,61 +95,29 @@
|
||||||
|
|
||||||
#ifndef __ASSEMBLER__
|
#ifndef __ASSEMBLER__
|
||||||
|
|
||||||
#define IS_DPORT_REG(_r) (((_r) >= DR_REG_DPORT_BASE) && (_r) <= DR_REG_DPORT_END)
|
|
||||||
|
|
||||||
#if !defined( BOOTLOADER_BUILD ) && !defined( CONFIG_FREERTOS_UNICORE ) && defined( ESP_PLATFORM )
|
|
||||||
#define ASSERT_IF_DPORT_REG(_r, OP) TRY_STATIC_ASSERT(!IS_DPORT_REG(_r), (Cannot use OP for DPORT registers use DPORT_##OP));
|
|
||||||
#else
|
|
||||||
#define ASSERT_IF_DPORT_REG(_r, OP)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
//write value to register
|
//write value to register
|
||||||
#define REG_WRITE(_r, _v) ({ \
|
#define REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v)
|
||||||
ASSERT_IF_DPORT_REG((_r), REG_WRITE); \
|
|
||||||
(*(volatile uint32_t *)(_r)) = (_v); \
|
|
||||||
})
|
|
||||||
|
|
||||||
//read value from register
|
//read value from register
|
||||||
#define REG_READ(_r) ({ \
|
#define REG_READ(_r) (*(volatile uint32_t *)(_r))
|
||||||
ASSERT_IF_DPORT_REG((_r), REG_READ); \
|
|
||||||
(*(volatile uint32_t *)(_r)); \
|
|
||||||
})
|
|
||||||
|
|
||||||
//get bit or get bits from register
|
//get bit or get bits from register
|
||||||
#define REG_GET_BIT(_r, _b) ({ \
|
#define REG_GET_BIT(_r, _b) (*(volatile uint32_t*)(_r) & (_b))
|
||||||
ASSERT_IF_DPORT_REG((_r), REG_GET_BIT); \
|
|
||||||
(*(volatile uint32_t*)(_r) & (_b)); \
|
|
||||||
})
|
|
||||||
|
|
||||||
//set bit or set bits to register
|
//set bit or set bits to register
|
||||||
#define REG_SET_BIT(_r, _b) ({ \
|
#define REG_SET_BIT(_r, _b) (*(volatile uint32_t*)(_r) |= (_b))
|
||||||
ASSERT_IF_DPORT_REG((_r), REG_SET_BIT); \
|
|
||||||
(*(volatile uint32_t*)(_r) |= (_b)); \
|
|
||||||
})
|
|
||||||
|
|
||||||
//clear bit or clear bits of register
|
//clear bit or clear bits of register
|
||||||
#define REG_CLR_BIT(_r, _b) ({ \
|
#define REG_CLR_BIT(_r, _b) (*(volatile uint32_t*)(_r) &= ~(_b))
|
||||||
ASSERT_IF_DPORT_REG((_r), REG_CLR_BIT); \
|
|
||||||
(*(volatile uint32_t*)(_r) &= ~(_b)); \
|
|
||||||
})
|
|
||||||
|
|
||||||
//set bits of register controlled by mask
|
//set bits of register controlled by mask
|
||||||
#define REG_SET_BITS(_r, _b, _m) ({ \
|
#define REG_SET_BITS(_r, _b, _m) (*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)))
|
||||||
ASSERT_IF_DPORT_REG((_r), REG_SET_BITS); \
|
|
||||||
(*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m))); \
|
|
||||||
})
|
|
||||||
|
|
||||||
//get field from register, uses field _S & _V to determine mask
|
//get field from register, uses field _S & _V to determine mask
|
||||||
#define REG_GET_FIELD(_r, _f) ({ \
|
#define REG_GET_FIELD(_r, _f) ((REG_READ(_r) >> (_f##_S)) & (_f##_V))
|
||||||
ASSERT_IF_DPORT_REG((_r), REG_GET_FIELD); \
|
|
||||||
((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \
|
|
||||||
})
|
|
||||||
|
|
||||||
//set field of a register from variable, uses field _S & _V to determine mask
|
//set field of a register from variable, uses field _S & _V to determine mask
|
||||||
#define REG_SET_FIELD(_r, _f, _v) ({ \
|
#define REG_SET_FIELD(_r, _f, _v) (REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S)))))
|
||||||
ASSERT_IF_DPORT_REG((_r), REG_SET_FIELD); \
|
|
||||||
(REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S))))); \
|
|
||||||
})
|
|
||||||
|
|
||||||
//get field value from a variable, used when _f is not left shifted by _f##_S
|
//get field value from a variable, used when _f is not left shifted by _f##_S
|
||||||
#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
|
#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
|
||||||
|
@ -170,52 +138,28 @@
|
||||||
#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
|
#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
|
||||||
|
|
||||||
//read value from register
|
//read value from register
|
||||||
#define READ_PERI_REG(addr) ({ \
|
#define READ_PERI_REG(addr) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr)))
|
||||||
ASSERT_IF_DPORT_REG((addr), READ_PERI_REG); \
|
|
||||||
(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); \
|
|
||||||
})
|
|
||||||
|
|
||||||
//write value to register
|
//write value to register
|
||||||
#define WRITE_PERI_REG(addr, val) ({ \
|
#define WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val)
|
||||||
ASSERT_IF_DPORT_REG((addr), WRITE_PERI_REG); \
|
|
||||||
(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \
|
|
||||||
})
|
|
||||||
|
|
||||||
//clear bits of register controlled by mask
|
//clear bits of register controlled by mask
|
||||||
#define CLEAR_PERI_REG_MASK(reg, mask) ({ \
|
#define CLEAR_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask))))
|
||||||
ASSERT_IF_DPORT_REG((reg), CLEAR_PERI_REG_MASK); \
|
|
||||||
WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \
|
|
||||||
})
|
|
||||||
|
|
||||||
//set bits of register controlled by mask
|
//set bits of register controlled by mask
|
||||||
#define SET_PERI_REG_MASK(reg, mask) ({ \
|
#define SET_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask)))
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||||||
ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_MASK); \
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||||||
WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \
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||||||
})
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||||||
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||||||
//get bits of register controlled by mask
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//get bits of register controlled by mask
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||||||
#define GET_PERI_REG_MASK(reg, mask) ({ \
|
#define GET_PERI_REG_MASK(reg, mask) (READ_PERI_REG(reg) & (mask))
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||||||
ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_MASK); \
|
|
||||||
(READ_PERI_REG(reg) & (mask)); \
|
|
||||||
})
|
|
||||||
|
|
||||||
//get bits of register controlled by highest bit and lowest bit
|
//get bits of register controlled by highest bit and lowest bit
|
||||||
#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({ \
|
#define GET_PERI_REG_BITS(reg, hipos,lowpos) ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
|
||||||
ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS); \
|
|
||||||
((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); \
|
|
||||||
})
|
|
||||||
|
|
||||||
//set bits of register controlled by mask and shift
|
//set bits of register controlled by mask and shift
|
||||||
#define SET_PERI_REG_BITS(reg,bit_map,value,shift) ({ \
|
#define SET_PERI_REG_BITS(reg,bit_map,value,shift) (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) ))
|
||||||
ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_BITS); \
|
|
||||||
(WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) )); \
|
|
||||||
})
|
|
||||||
|
|
||||||
//get field of register
|
//get field of register
|
||||||
#define GET_PERI_REG_BITS2(reg, mask,shift) ({ \
|
#define GET_PERI_REG_BITS2(reg, mask,shift) ((READ_PERI_REG(reg)>>(shift))&(mask))
|
||||||
ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS2); \
|
|
||||||
((READ_PERI_REG(reg)>>(shift))&(mask)); \
|
|
||||||
})
|
|
||||||
|
|
||||||
#endif /* !__ASSEMBLER__ */
|
#endif /* !__ASSEMBLER__ */
|
||||||
//}}
|
//}}
|
||||||
|
@ -305,7 +249,7 @@
|
||||||
* 25 4 extern level CACHEERR
|
* 25 4 extern level CACHEERR
|
||||||
* 26 5 extern level
|
* 26 5 extern level
|
||||||
* 27 3 extern level Reserved Reserved
|
* 27 3 extern level Reserved Reserved
|
||||||
* 28 4 extern edge DPORT ACCESS DPORT ACCESS
|
* 28 4 extern edge
|
||||||
* 29 3 software Reserved Reserved
|
* 29 3 software Reserved Reserved
|
||||||
* 30 4 extern edge Reserved Reserved
|
* 30 4 extern edge Reserved Reserved
|
||||||
* 31 5 extern level
|
* 31 5 extern level
|
||||||
|
@ -320,7 +264,6 @@
|
||||||
#define ETS_FRC1_INUM 22
|
#define ETS_FRC1_INUM 22
|
||||||
#define ETS_T1_WDT_INUM 24
|
#define ETS_T1_WDT_INUM 24
|
||||||
#define ETS_CACHEERR_INUM 25
|
#define ETS_CACHEERR_INUM 25
|
||||||
#define ETS_DPORT_INUM 28
|
|
||||||
|
|
||||||
//CPU0 Interrupt number used in ROM, should be cancelled in SDK
|
//CPU0 Interrupt number used in ROM, should be cancelled in SDK
|
||||||
#define ETS_SLC_INUM 1
|
#define ETS_SLC_INUM 1
|
||||||
|
|
Loading…
Reference in a new issue