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Merge branch 'bugfix/ulp_doc_insn_time' into 'master'

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docs/ulp: fix instruction fetch and execution times

See merge request idf/esp-idf!1979
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Angus Gratton 2018-06-15 11:50:14 +08:00
parent 4056d1e2bf b1b1257476
commit 41095f8466
1 changed files with 32 additions and 27 deletions
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59
docs/en/api-guides/ulp_instruction_set.rst
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@ -73,7 +73,12 @@ ULP coprocessor is clocked from RTC_FAST_CLK, which is normally derived from the
uint32_t rtc_8md256_period = rtc_clk_cal(RTC_CAL_8MD256, 100);
uint32_t rtc_fast_freq_hz = 1000000ULL * (1 << RTC_CLK_CAL_FRACT) * 256 / rtc_8md256_period;
ULP coprocessor needs 2 clock cycle to fetch each instuction (fetching is not pipelined), plus certain number of cycles to execute, depending on the instruction. See description of each instruction for details on the execution time.
ULP coprocessor needs certain number of clock cycles to fetch each instuction, plus certain number of cycles to execute it, depending on the instruction. See description of each instruction below for details on the execution time.
Instruction fetch time is:
- 2 clock cycles — for instructions following ALU and branch instructions.
- 4 clock cycles — in other cases.
Note that when accessing RTC memories and RTC registers, ULP coprocessor has lower priority than the main CPUs. This means that ULP coprocessor execution may be suspended while the main CPUs access same memory region as the ULP.
@ -86,7 +91,7 @@ Note that when accessing RTC memories and RTC registers, ULP coprocessor has low
**Operands**
None
**Cycles**
2 (fetch) + 1 (execute)
2 cycle to execute, 4 cycles to fetch next instruction
**Description**
No operation is performed. Only the PC is incremented.
@ -111,7 +116,7 @@ Note that when accessing RTC memories and RTC registers, ULP coprocessor has low
- *Imm* - 16-bit signed value
**Cycles**
2 (fetch) + 2 (execute)
2 cycles to execute, 4 cycles to fetch next instruction
**Description**
The instruction adds source register to another source register or to a 16-bit signed value and stores result to the destination register.
@ -147,7 +152,7 @@ Note that when accessing RTC memories and RTC registers, ULP coprocessor has low
- *Imm* - 16-bit signed value
**Cycles**
2 (fetch) + 2 (execute)
2 cycles to execute, 4 cycles to fetch next instruction
**Description**
The instruction subtracts the source register from another source register or subtracts 16-bit signed value from a source register, and stores result to the destination register.
@ -181,7 +186,7 @@ Note that when accessing RTC memories and RTC registers, ULP coprocessor has low
- *Imm* - 16-bit signed value
**Cycles**
2 (fetch) + 2 (execute)
2 cycles to execute, 4 cycles to fetch next instruction
**Description**
The instruction does logical AND of a source register and another source register or 16-bit signed value and stores result to the destination register.
@ -216,7 +221,7 @@ Note that when accessing RTC memories and RTC registers, ULP coprocessor has low
- *Imm* - 16-bit signed value
**Cycles**
2 (fetch) + 2 (execute)
2 cycles to execute, 4 cycles to fetch next instruction
**Description**
The instruction does logical OR of a source register and another source register or 16-bit signed value and stores result to the destination register.
@ -252,7 +257,7 @@ Note that when accessing RTC memories and RTC registers, ULP coprocessor has low
- *Imm* - 16-bit signed value
**Cycles**
2 (fetch) + 2 (execute)
2 cycles to execute, 4 cycles to fetch next instruction
**Description**
The instruction does logical shift to left of source register to number of bits from another source register or 16-bit signed value and store result to the destination register.
@ -287,7 +292,7 @@ Note that when accessing RTC memories and RTC registers, ULP coprocessor has low
*Imm* - 16-bit signed value
**Cycles**
2 (fetch) + 2 (execute)
2 cycles to execute, 4 cycles to fetch next instruction
**Description**
The instruction does logical shift to right of source register to number of bits from another source register or 16-bit signed value and store result to the destination register.
@ -321,7 +326,7 @@ Note that when accessing RTC memories and RTC registers, ULP coprocessor has low
- *Imm* – 16-bit signed value
**Cycles**
2 (fetch) + 2 (execute)
2 cycles to execute, 4 cycles to fetch next instruction
**Description**
The instruction move to destination register value from source register or 16-bit signed value.
@ -356,7 +361,7 @@ Note that when accessing RTC memories and RTC registers, ULP coprocessor has low
- *Offset* – 10-bit signed value, offset in bytes
**Cycles**
2 (fetch) + 4 (execute)
4 cycles to execute, 4 cycles to fetch next instruction
**Description**
The instruction stores the 16-bit value of Rsrc to the lower half-word of memory with address Rdst+offset. The upper half-word is written with the current program counter (PC), expressed in words, shifted left by 5 bits::
@ -393,7 +398,7 @@ Note that when accessing RTC memories and RTC registers, ULP coprocessor has low
*Offset* – 10-bit signed value, offset in bytes
**Cycles**
2 (fetch) + 4 (execute)
4 cycles to execute, 4 cycles to fetch next instruction
**Description**
The instruction loads lower 16-bit half-word from memory with address Rsrc+offset into the destination register Rdst::
@ -439,7 +444,7 @@ Note that when accessing RTC memories and RTC registers, ULP coprocessor has low
- OV – jump if last ALU has set overflow flag
**Cycles**
2 (fetch) + 2 (execute)
2 cycles to execute, 2 cycles to fetch next instruction
**Description**
The instruction makes jump to the specified address. Jump can be either unconditional or based on an ALU flag.
@ -478,7 +483,7 @@ Note that when accessing RTC memories and RTC registers, ULP coprocessor has low
- *LT* (less than) – jump if value in R0 < threshold
**Cycles**
2 (fetch) + 2 (execute)
2 cycles to execute, 2 cycles to fetch next instruction
**Description**
The instruction makes a jump to a relative address if condition is true. Condition is the result of comparison of R0 register value and the threshold value.
@ -510,7 +515,7 @@ Note that when accessing RTC memories and RTC registers, ULP coprocessor has low
- *GT* (greater than) – jump if value in stage_cnt > threshold
**Cycles**
2 (fetch) + 2 (execute)
2 cycles to execute, 2 cycles to fetch next instruction
**Description**
The instruction makes a jump to a relative address if condition is true. Condition is the result of comparison of count register value and threshold value.
@ -539,7 +544,7 @@ Note that when accessing RTC memories and RTC registers, ULP coprocessor has low
The instruction sets the stage count register to 0
**Cycles**
2 (fetch) + 2 (execute)
2 cycles to execute, 4 cycles to fetch next instruction
**Examples**::
@ -557,7 +562,7 @@ Note that when accessing RTC memories and RTC registers, ULP coprocessor has low
- *Value* – 8 bits value
**Cycles**
2 (fetch) + 2 (execute)
2 cycles to execute, 4 cycles to fetch next instruction
**Description**
The instruction increments stage count register by given value.
@ -583,7 +588,7 @@ Note that when accessing RTC memories and RTC registers, ULP coprocessor has low
- *Value* – 8 bits value
**Cycles**
2 (fetch) + 2 (execute)
2 cycles to execute, 4 cycles to fetch next instruction
**Description**
The instruction decrements stage count register by given value.
@ -610,7 +615,7 @@ Note that when accessing RTC memories and RTC registers, ULP coprocessor has low
No operands
**Cycles**
2 (fetch) + 2 (execute)
2 cycles to execute
**Description**
The instruction halts the ULP coprocessor and restarts ULP wakeup timer, if it is enabled.
@ -631,7 +636,7 @@ Note that when accessing RTC memories and RTC registers, ULP coprocessor has low
No operands
**Cycles**
2 (fetch) + 2 (execute)
2 cycles to execute, 4 cycles to fetch next instruction
**Description**
The instruction sends an interrupt from ULP to RTC controller.
@ -666,7 +671,7 @@ Note that when accessing RTC memories and RTC registers, ULP coprocessor has low
- *sleep_reg* – 0..4, selects one of ``SENS_ULP_CP_SLEEP_CYCx_REG`` registers.
**Cycles**
2 (fetch) + 2 (execute)
2 cycles to execute, 4 cycles to fetch next instruction
**Description**
The instruction selects which of the ``SENS_ULP_CP_SLEEP_CYCx_REG`` (x = 0..4) register values is to be used by the ULP wakeup timer as wakeup period. By default, the value from ``SENS_ULP_CP_SLEEP_CYC0_REG`` is used.
@ -689,7 +694,7 @@ Note that when accessing RTC memories and RTC registers, ULP coprocessor has low
- *Cycles* – number of cycles for wait
**Cycles**
2 (fetch) + *Cycles* (execute)
2 + *Cycles* cycles to execute, 4 cycles to fetch next instruction
**Description**
The instruction delays for given number of cycles.
@ -715,7 +720,7 @@ Note that when accessing RTC memories and RTC registers, ULP coprocessor has low
- *Wait_Delay* – number of cycles used to perform the measurement
**Cycles**
2 (fetch) + *Wait_Delay* + 3 * TSENS_CLK
2 + *Wait_Delay* + 3 * TSENS_CLK to execute, 4 cycles to fetch next instruction
**Description**
The instruction performs measurement using TSENS and stores the result into a general purpose register.
@ -742,7 +747,7 @@ Note that when accessing RTC memories and RTC registers, ULP coprocessor has low
- *Mux* - selected PAD, SARADC Pad[Mux+1] is enabled
**Cycles**
2 (fetch) + 21 + max(1, SAR_AMP_WAIT1) + max(1, SAR_AMP_WAIT2) + max(1, SAR_AMP_WAIT3) + SARx_SAMPLE_CYCLE + SARx_SAMPLE_BIT
``23 + max(1, SAR_AMP_WAIT1) + max(1, SAR_AMP_WAIT2) + max(1, SAR_AMP_WAIT3) + SARx_SAMPLE_CYCLE + SARx_SAMPLE_BIT`` cycles to execute, 4 cycles to fetch next instruction
**Description**
The instruction makes measurements from ADC.
@ -763,7 +768,7 @@ Note that when accessing RTC memories and RTC registers, ULP coprocessor has low
- *Slave_sel* - Index of I2C slave address to use.
**Cycles**
2 (fetch) + I2C communication time
Execution time mostly depends on I2C communication time. 4 cycles to fetch next instruction.
**Description**
``I2C_RD`` instruction reads one byte from I2C slave with index ``Slave_sel``. Slave address (in 7-bit format) has to be set in advance into `SENS_I2C_SLAVE_ADDRx` register field, where ``x == Slave_sel``.
@ -787,7 +792,7 @@ Note that when accessing RTC memories and RTC registers, ULP coprocessor has low
- *Slave_sel* - Index of I2C slave address to use.
**Cycles**
2 (fetch) + I2C communication time
Execution time mostly depends on I2C communication time. 4 cycles to fetch next instruction.
**Description**
``I2C_WR`` instruction writes one byte to I2C slave with index ``Slave_sel``. Slave address (in 7-bit format) has to be set in advance into `SENS_I2C_SLAVE_ADDRx` register field, where ``x == Slave_sel``.
@ -809,7 +814,7 @@ Note that when accessing RTC memories and RTC registers, ULP coprocessor has low
- *Low* – Low part of R0
**Cycles**
2 (fetch) + 6 (execute)
4 cycles to execute, 4 cycles to fetch next instruction
**Description**
The instruction reads up to 16 bits from a peripheral register into a general purpose register: ``R0 = REG[Addr][High:Low]``.
@ -837,7 +842,7 @@ Note that when accessing RTC memories and RTC registers, ULP coprocessor has low
- *Data* – value to write, 8 bits
**Cycles**
2 (fetch) + 10 (execute)
8 cycles to execute, 4 cycles to fetch next instruction
**Description**
The instruction writes up to 8 bits from a general purpose register into a peripheral register. ``REG[Addr][High:Low] = data``