diff --git a/components/esp32s2beta/cpu_start.c b/components/esp32s2beta/cpu_start.c
index 63379a21b..568cc584c 100644
--- a/components/esp32s2beta/cpu_start.c
+++ b/components/esp32s2beta/cpu_start.c
@@ -311,9 +311,9 @@ void start_cpu0_default(void)
 
     do_global_ctors();
 #if CONFIG_ESP_INT_WDT
-    //esp_int_wdt_init();
-    //Initialize the interrupt watch dog for CPU0.
-    //esp_int_wdt_cpu_init();
+    esp_int_wdt_init();
+    //Initialize the interrupt watch dog
+    esp_int_wdt_cpu_init();
 #endif
     esp_cache_err_int_init();
     esp_crosscore_int_init();
diff --git a/components/esp32s2beta/int_wdt.c b/components/esp32s2beta/int_wdt.c
index 2515962db..bd46f3702 100644
--- a/components/esp32s2beta/int_wdt.c
+++ b/components/esp32s2beta/int_wdt.c
@@ -1,4 +1,4 @@
-// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -39,38 +39,18 @@
 
 
 //Take care: the tick hook can also be called before esp_int_wdt_init() is called.
-#if CONFIG_ESP_INT_WDT_CHECK_CPU1
-//Not static; the ISR assembly checks this.
-bool int_wdt_app_cpu_ticked=false;
 
-static void IRAM_ATTR tick_hook(void) {
-    if (xPortGetCoreID()!=0) {
-        int_wdt_app_cpu_ticked=true;
-    } else {
-        //Only feed wdt if app cpu also ticked.
-        if (int_wdt_app_cpu_ticked) {
-            TIMERG1.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
-            TIMERG1.wdt_config2=CONFIG_ESP_INT_WDT_TIMEOUT_MS*2;        //Set timeout before interrupt
-            TIMERG1.wdt_config3=CONFIG_ESP_INT_WDT_TIMEOUT_MS*4;        //Set timeout before reset
-            TIMERG1.wdt_feed=1;
-            TIMERG1.wdt_wprotect=0;
-            int_wdt_app_cpu_ticked=false;
-        }
-    }
-}
-#else
-static void IRAM_ATTR tick_hook(void) {
-    if (xPortGetCoreID()!=0) return;
+static void IRAM_ATTR tick_hook(void)
+{
     TIMERG1.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
     TIMERG1.wdt_config2=CONFIG_ESP_INT_WDT_TIMEOUT_MS*2;        //Set timeout before interrupt
     TIMERG1.wdt_config3=CONFIG_ESP_INT_WDT_TIMEOUT_MS*4;        //Set timeout before reset
     TIMERG1.wdt_feed=1;
     TIMERG1.wdt_wprotect=0;
 }
-#endif
 
-
-void esp_int_wdt_init(void) {
+void esp_int_wdt_init(void)
+{
     periph_module_enable(PERIPH_TIMG1_MODULE);
     TIMERG1.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
     TIMERG1.wdt_config0.sys_reset_length=7;                 //3.2uS
@@ -92,9 +72,9 @@ void esp_int_wdt_init(void) {
 
 void esp_int_wdt_cpu_init(void)
 {
-    esp_register_freertos_tick_hook_for_cpu(tick_hook, xPortGetCoreID());
+    esp_register_freertos_tick_hook_for_cpu(tick_hook, 0);
     ESP_INTR_DISABLE(WDT_INT_NUM);
-    intr_matrix_set(xPortGetCoreID(), ETS_TG1_WDT_LEVEL_INTR_SOURCE, WDT_INT_NUM);
+    intr_matrix_set(0, ETS_TG1_WDT_LEVEL_INTR_SOURCE, WDT_INT_NUM);
     //We do not register a handler for the interrupt because it is interrupt level 4 which
     //is not servicable from C. Instead, xtensa_vectors.S has a call to the panic handler for
     //this interrupt.
@@ -103,4 +83,4 @@ void esp_int_wdt_cpu_init(void)
 
 
 
-#endif
+#endif // CONFIG_ESP_INT_WDT